Stick Diagrams Layout Planning

Stick Diagrams
Stick Diagrams
by
Rita Jain Professor and Head

Department of Electronics and Communication Engineering Lakshmi Narain College of Technology, Bhopal
ritajain_bpl@yahoo.com
1 Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
Stick Diagrams
Layout
The Design Rules describe: Minimum width to avoid breaks in a line Minimum spacing to avoid shorts between lines Minimum overlap to ensure two layers completely overlap Unit Transistor Transistor dimensions are specified by their W/L ratio For 0.6 m process, W = 1.2 m and L = 0.6 m Such a minimum width contacted transistor is called UNIT TRANSISTOR
Stick Diagrams
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2, sometimes called 1 unit For 0.6 mm process, W=1.2 m, L=0.6 m
Stick Diagrams
Layout
A conservative but easy to use Design Rules for nwell process is as follows: Metal and diffusion have minimum width spacing of 4 Contacts are 2 X 2 and must be surrounded by 1 on the layers above and below Polysilicon uses a width of 2 Polysilicon overlaps diffusion by 2 where a transistor is desired and has a spacing of 1 away where no transistor is desired Polysilicon and contacts have a spacing of 3 from other polysilicon or contacts N-well surrounds PMOS transistors by 6 and avoids NMOS transistors by 6
Stick Diagrams
Simplified Design Rules

Conservative rules to get you started
Stick Diagrams
Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale Draw with color pencils or dry-erase markers
Stick Diagrams
Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing topography and layer information using simple diagrams. Stick diagrams convey layer information through colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout.
Stick Diagrams
Stick Diagrams
Does show all components/vias. It shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing
Does not show

Exact placement of components Transistor sizes Wire lengths, wire widths, tub boundaries. Any other low level details such as parasitics.
Stick Diagrams
Wiring Tracks
A wiring track is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track
Stick Diagrams
Well Spacing
Wells must surround transistors by 6
Implies 12 between opposite transistor flavors Leaves room for one wire track
Stick Diagrams
Area Estimation
Estimate area by counting wiring tracks
Multiply by 8 to express in
Stick Diagrams
Example: Inverter
Stick Diagrams
Example: NAND3
Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l
Stick Diagrams
Stick Diagrams Some rules

Rule 1. When two or more sticks of the same type cross or touch each other that represents electrical contact.
Stick Diagrams

Rule 2. When two or more sticks of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection
explicitly).
Stick Diagrams

Rule 3. When a poly crosses diffusion it represents a transistor.
Note: If a contact is shown then it is not a transistor.

Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
16
Stick Diagrams

Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.
Stick Diagrams
Stick Diagrams
N+
N+
Stick Diagrams
Stick Diagrams
VDD X X X VDD
Stick Diagram
X Gnd
Gnd
19
Stick Diagrams
Stick Diagrams
VDD X X X
VDD
X Gnd
Gnd
20
Stick Diagrams
Stick Diagrams Notations

Metal 1 poly ndiff pdiff
Can also draw in shades of gray/line style.
Similarly for contacts, via, tub etc..

Stick Diagrams
How to draw Stick Diagrams
Stick Diagrams
NOR Gate
Stick Diagrams
Stacked Layout
Power
Out
C B
Ground
Stick Diagrams
Methods for generating Stick Diagrams

Construct a Logic Graph of the Schematics Identify each transistor by a unique name of its gate signal (A, B, C, D ..) Identify each connection to the transistor by a unique name (1,2,3,4,5,..) Construct an Euler Path for both pull-up and pull-down network Euler Path is defined by a path that traverses each node in the path, such that each edge is visited only once Path is defined by the order of each transistor name Euler Path for the pull-up network must be same as the path of pulldown network Euler paths are not necessarily unique It may be necessary to redefined the function to find a Euler path
Stick Diagrams
Methods for generating Stick Diagrams

Once the Euler path is found it is time to layout the stick diagram Trace two lines horizontally to represent PMOS and NMOS Trace the number of Inputs vertically across each strip. These represent the gate contacts to the devices that are made of poly Surround NMOS and PMOS by P-well and N-well Trace a blue line horizontally above and below the PMOS and NMOS lines to represent the metal of VDD and VSS Label each poly line with the Euler path label, in order from left to right Place the connection label upon NMOS and PMOS devices
Stick Diagrams
Stick Diagrams
Sketch a stick diagram for O3AI and estimate area Y = ((A+B+C).D)
Stick Diagrams
Stick Diagrams
VDD
VDD
A B C Y D B
A Y D D
C Y
B C
VSS
C
VSS
Pull-up Network
Pull-down Network
Stick Diagrams
Stick Diagrams
Stick Diagrams
Area Estimation
Stick Diagrams
OAI21 Logic Graph

A j B X = !(C (A + B)) C A i i B B X A C X C
B j A C
GND A B C PDN
VDD PUN
Stick Diagrams
Home Work
1. Draw the stick diagram for two input CMOS NAND gate. 2. Draw the stick diagram for two input NAND gate using NMOS Logic. 3. Draw the stick diagram for 2:1 MUX using a) Pass transistors b) Transmission gates. 4. Draw Stick Diagrams for the following equations Y = ( A + B + C ).D : Y = A + ( B + C ).D
5. 6. For a process technology with L = 5 micron meter give the size of the layout for the following : (a) 4-input NOR gate and 4-Input NAND gate Draw Stick Diagram for the circuits given below and estimate its area (circuits given in next few slides) Identify the logic functions (stick diagrams given in next few slides)
7.
Drawing stick diagram is truly Fun !!! Enjoy it !!!

Stick Diagrams
Draw Stick Diagram for the circuit given below and estimate its area
B A C D OUT = !(D + A (B + C)) A D B C
Stick Diagrams
Draw Stick Diagram for the circuits given below and estimate its area
Stick Diagrams
Draw Stick Diagram for the circuits given below and estimate its area
A B
C D X = !((A+B)(C+D)) A B C D
C A
D B
Stick Diagrams
What logic function is this?

Routing channel VDD
signals
GND

Stick Diagrams
A VDD
C VDD
GND
GND
Stick Diagrams

A VDD B D C
GND

Stick Diagrams Layout Planning

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Stick Diagrams Layout Planning

Uploaded by

Copyright:

Available Formats

Stick Diagrams

Rita Jain Professor and Head

Simplified Design Rules

Does not show

Transistors also consume one wiring track

Stick Diagrams Some rules

Stick Diagrams Some rules

Stick Diagrams Some rules

Note: If a contact is shown then it is not a transistor.

Stick Diagrams Some rules

Stick Diagrams Notations

Similarly for contacts, via, tub etc..

How to draw Stick Diagrams

Methods for generating Stick Diagrams

Methods for generating Stick Diagrams

OAI21 Logic Graph

Drawing stick diagram is truly Fun !!! Enjoy it !!!

B A C D OUT = !(D + A (B + C)) A D B C

What logic function is this?

What logic function is this?

What logic function is this?

What logic function is this?

You might also like