UMC 180nm MM RF FDK CDN Userguide vB04 PB 3

UM180FDKMFC000000A_B
UMC 0.18um 1P6M Mixed-Mode/RF Thick Top Metal (20KA) Process Foundry Design Kit (PDK)
User Guide
Copyright UMC, 2005 All information contained herein is subject to change without prior notice. No liability shall be incurred from its use or application.
UMC Confidential
1 Ver. B04_PB
Contents
0. Release Notes .... 4 1. Overview ......... 7 .......... 8
2. Foundry Data
3. What makes up a PDK? .......... 9 4. Installation of the PDK ........... 10 ...... 11
5. PDK Install Directory Structure/Contents
6. Creation of a Design Project .................... 12 7. Techfile Methodology ................ 14
8. Customizing Layer Display Properties Using Display.drf File .. 15 9. Schematic Design .. 17
10. Library Device Setup 18 11. Supported Devices 20 12. Views provided .. 23 13. CDF parameters 24
14. Component Label Defaults . 37 15. Simulation Models 40
16. AddWire Utility 41 17. UpdateCDFs Utility . 42 18. Setting Environment Variables 19. Techfile Layers .. 43
45 46
20. Virtuoso XL ..
21. Dracula Support 48 22. Assura Decks . 49
23. DEVICE SPECIFICATIONS 59

UMC Confidential 2 Ver. B04_PB
24. DEVICE DATASHEETS 72 25. Known Problems and Solutions . 253
Appendix
A.1 Revision History .. 258 A.2. UMC Utilities 258
A.2.1. Callback Re-trigger Utility . 258 A.2.2. Alphabet Generator .... 259
UMC Confidential
3 Ver. B04_PB
0 Release Notes
0.1 Foundry Process Documents
The following documents were used to develop or verify this Design Kit.
Classification Design Support Manual Electrical Design Rule Topological Layout Rule Interconnect Capacitance SPICE Modeling Spec. No.
G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM-8C G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP
G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TRI_WELL/MMC-SPICE-8C G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TWIN_WELL/MMC-SPICE-8C
Version
2.0_P2 1.4_P1 2.8_P1 1.1_P2 1.4_P1 1.5_P1 B.B1PB 2.4_P1 2.8_P1 1.3_P3 1.1_P13 2.3_P1
Date
8/25/2005 11/29/2005 11/16/2005 5/9/2003 11/4/2005 11/4/2005 9/22/2003 11/2/2005 11/23/2005 10/24/2005 7/14/2005 11/4/2005
GT-DBT-030922-007 (MM salicide resistors and metal resistors)
Mask Tooling DRC Rule Deck LVS Rule Deck LPE Rule Deck Official Layer Mapping Table
G-06-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-MASKTOO L-8C
G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-DRC G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-LVS G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/XRC-LPE
G-DF-GENERATION18-VIRTUOSO-TF
NOTE: The model files and rule decks included in this release Design Kit were available at the time of this revision. The user should keep accessing the latest model files and rule decks. Please contact your Account Manager if you failed to access them.
0.2 EDA Tools Supported and Verified for Use with this FDK (PDK)
Classification Schematic Entry Simulation Interface Simulation Tool Layout Editor DRC Tool LVS Tool Parasitic RC Extractor EDA Tools Cadence Composer Cadence Analog Design Environment Cadence Spectre Synopsys Hspice Cadence Virtuoso Mentor Calibre Mentor Calibre Mentor XRC Version 5.10.41_USR1.7.43 5.10.41_USR1.7.43 5.10.41_USR1.7.43 2003.09 5.10.41_USR1.7.43 2005.1_10.20 2005.1_10.20 2005.1_10.20
NOTE: This Design Kit did not verify the other EDA tools not mentioned above.
UMC Confidential
4 Ver. B04_PB
0.3 Component List

Spectre Netlist Hspice Netlist Device Name Symbol View Device Type Spectre Sim. Layout View
Hspice Sim.
Model Type
DRC Check V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
CDL Netlist
SDL Check
MOS P_18_MM N_18_MM N_BPW_18_MM P_33_MM N_33_MM N_BPW_33_MM P_LV_18_MM N_LV_18_MM N_ZERO_18_MM P_LV_33_MM N_LV_33_MM N_ZERO_33_MM P_L18W500_18_RF P_PO7W500_18_RF N_L18W500_18_RF N_PO7W500_18_RF P_L34W500_33_RF P_PO7W500_33_RF N_L34W500_33_RF N_PO7W500_33_RF BJT PNP_V50X50_MM PNP_V100X100_MM Diode DION_MM DIONW_MM DIOP_MM RES RSND_MM RSPD_MM RNND_MM RNPD_MM RNNPO_MM RNPPO_MM RNHR1000_MM RSNWELL_MM RM1_MM RM2_MM RM3_MM RM4_MM RM5_MM RM6_MM RNNPO_RF
UMC Confidential
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 2 2 2 3 3 3 3 3 3 3 3 2 2 2 2 2 2 3
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
5
C* C* C* C* C* C* C* C* C* C* C* C* S* S* S* S* S* S* S* S* C* C* C* C* C* S* S* S* S* S* S* S* S* S* S* S* S* S* S* S*
Ver. B04_PB
LVS Check V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
Terminals
RNPPO_RF RNHR_RF CAP NCAP_MM PCAP_MM MIMCAPS_MM MIMCAPM_RF IND L_SLCR20K_RF VAR VARMIS_18_RF VARDIOP_RF PAD PAD_RF 3 3 3 3 2 3 3 3 2 2 V V V V V V V V V V S* S* C* C* S* S* S* S* S* S* V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
* C means compact model, and S means sub-circuit model.
0.4 Verification Notes

Calibre LVS: (1) Please let LVS setup options of LVS REDUCE PARALLEL CAPACITORS and LVS REDUCE SERIES CAPACITORS be NO when you run Calibre LVS rule eck on RF Capacitors (MIMCAPM_RF, VARDIOP_RF & VARMIS_18_RF). RF capacitors defined in Calibre LVS rule deck trace geometrical parameters (L, W, NX, NY, NF) instead of the capacitance.
UMC Confidential
6 Ver. B04_PB
1 Overview
The purpose of this User Guide is to describe the technical details of the UMC .18 MM/RF, 1P6M thick top metal (20KA) Process Design Kit (PDK) provided by Cadence Design Systems, Inc. (Cadence). NOTE: The RM6_MM resistor uses thick metal (20KA) values. This PDK requires the following environmental variables CDS_Netlisting_Mode to be set to Analog CDS_INST_DIR to be set to the Cadence DFII installation path Cadence DFII Tool Training is not provided as part of this PDK.
1.1 Software Releases
The following releases of software were used to develop and test this PDK: Cadence DFII Version: 5.0.33_USR3.16.35 (USR3) Cadence Assura DRC/LVS Versions: 3.1.3.USR1 Cadence Assura RCX Version: 3.1.3.USR1
UMC Confidential
7 Ver. B04_PB
2 Foundry Data
G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR 0.18 um Mixed Mode/RFCMOS Technology 1.8V/3.3V 1P6M Process Topological Layout Rule (With Metal/Metal Capacitor Module) (Rev. 2.8_P1) G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR 0.18um Mixed Mode/RFCMOS Technology 1.8V/3.3V 1P6M Electrical Design Rule (With Metal/Metal Capacitor Module) (Ver. 1.4_P1) G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP 0.18um 1P6M Mixed Mode with MMC Process Interconnect Capacitance Model (Ver. 1.1_P2)
UMC Confidential
8 Ver. B04_PB
3 What makes up a PDK?

PDK stands for Process Design Kit. A PDK contains the process technology and needed information to do device-level design in the Cadence DFII environment.
PDK
Cadence Tool
Schematic Symbols & CDF Analog Simulation & callbacks
Schematic (Composer) Analog Front-end Design
Simulation
Spectre
Foundry
Spectre Models
Analog Design Environment
Fixed Layouts Parameterized Cells
Device Generation/Cell Design

Virtuoso XL (Advanced Layout Editor)
Techfile: - Layer maps - Layer props - symbolics - Connectivity - VCR setup
Interconnect Wire Editor/Routing Virtuoso Custom Router (VCR)
VirtuosoXL Layout
Physical Verification - DRC - LVS - LPE
Interactive Physical Verification

Diva, Dracula, Assura
UMC Confidential
9 Ver. B04_PB
4 Installation of the PDK

Logon to the computer as the user who will own and maintain the PDK. Choose a disk and directory under which the PDK will be installed. This disk should be exported to all client machines and must be mounted consistently across all client machines. Connect to the directory where the PDK will be installed: cd <pdk_install_directory> Extract the PDK from the archive using the following commands: gzip -d <path_to_pdk_tar_file>/ xxx.tar.gz tar xvf xxx.tar The default permissions on the PDK have already been set to allow only the owner to have write, read and execute access. Other users will have only read and execute access.
UMC Confidential
10 Ver. B04_PB
5 PDK Install Directory Structure/Contents

REVISION - ASCII file containing the PDK revision history. cds.lib - file containing the Cadence initialization file. display.drf - ASCII version of display resources file icc.rules - Virtuoso Custom Router and Virtuoso Custom Placer rules file Models directory containing SPICE model files used to test the PDK umc18mmrf.tf - ASCII version of technology file umc18mmrf UMC .18 MM/RF Process PDK Cadence Library RuleDecks directory containing Calibre rule decks used to test the PDK celview.cellmap cell map file for Calibre view
UMC Confidential
11 Ver. B04_PB
6 Creation of a Design Project

A unique directory should be created for each circuit design project. The following command can be executed in UNIX: mkdir ~/circuit_design cd ~/circuit_design All work by the user should be performed in this circuit design directory. The following file should be copied from the PDK install directory to begin the circuit design process. The following command can be used: cp <pdk_install_directory>/display.drf .
Next the user should create a "cds.lib" file. Using any text editor the following entry should be put in the cds.lib file: INCLUDE <pdk_install_directory>/cds.lib Where "pdk_install_directory" is the path to where the UMC .18 MM/RF PDK was installed.
Because the UMC .18 MM and UMC .18 MM/RF PDK, differ in their top metal thicknesses, you can not use the same techfile for both PDKs. The UMC .18 MM PDK uses thin top metal, and the UMC .18 MM/RF PDK uses thick top metal. The symbolic contacts for M6_M5 and the path width for ME6 differ between these two PDKs. Both of these settings are defined in the techfile. This will require a techfile for each PDK. Given that two techfile are required, what follows is a step by step flow that can be executed to switch between PDK's. For example, If you would like to reuse an existing test library (developed for UMC .18 MM) for your UMC .18 MM/RF tests, please do the following: ***NOTE: Assuming that the test library that you want to change is named "umc18mm_test" 1) Rename the reference library: In the library manager select Edit->Rename Reference Library... Make sure that the following fields are entered:
UMC Confidential
12 Ver. B04_PB
UM180FDKMFC000000A_B In Library From Library To Library umc18mm_test umc18mm umc18mmrf
Then click on the "OK" button. 2)Attach the UMC .18 MM/RF technology file: In the CIW window, select Technology File->Attach To... Make sure that the "Design Library" field is set to "umc18mm_test". Make sure that the "Technology Library" is set to "umc18mmrf" Then click on the "OK" button. 3) Update CDFs: In the CIW window, enter the following command: umc18mmrf_updateCDFs("umc18mm_test") Once all 3 of these steps have been executed, you will then be able to reuse existing designs in the "umc18mm_test" library that was developed in "umc18mm" on the "umc18mmrf" PDK.
UMC Confidential
13 Ver. B04_PB
7 Techfile Methodology
The umc18mmrf Library techfile will be designated as the master techfile. This techfile will contain all required techfile information. There is an ASCII version of this techfile shipped with the PDK. This ASCII version represents the techfile currently compiled into the umc18mmrf library The attach method should be used for any design library that is created. This allows the design database techfile to be kept in sync with the techfile in the process PDK. To create a new library that uses an attached techfile, use the command File->New->Library from either the CIW or library manager and select the Attach to an existing techfile option. Select the umc18mmrf library when asked for the name of the Attach To Technology Library.
UMC Confidential
14 Ver. B04_PB
8 Customizing Layer Display Properties Using Display.drf File

The display.drf can be autoloaded at Cadence start-up time or manually loaded during the Cadence session. For the file to be autoloaded, the display.drf file must be located in the Cadence start-up directory. To manually load the display.drf file (or load a new version), choose Tools->Display Resources->Merge Files... from the CIW and enter the location of the display.drf file that you want to use. If the display.drf file is not autoloaded and you do not manually load it, you will get error messages about missing packets when you try to open a schematic or layout view and you will not be able to see any process specific layers. The UMC .18 MM/RF 1P6M process display.drf file can be found in the PDK install directory. Listed below are the packet, color, lineStyle, and stipplePattern definitions for a ME3 drawing layer. The packet info references predefined color, lineStyle, and stipplePattern definitions. Any of these can be changed to suit an individual users preferences in the project copy of the display.drf file. drDefinePacket( ;( DisplayName PacketName Fill Outline ) ( display ) drDefineColor( ;( DisplayName ( display ) drDefineLineStyle( ;( DisplayName ( display ) drDefineStipple( solid LineStyle 1 Size (1 1 1) ) Pattern ) green ColorName 0 Red 204 Green 102 nil ) Blue Blink ) m3 dots Stipple solid LineStyle green green )
UMC Confidential
15 Ver. B04_PB
UM180FDKMFC000000A_B ;( DisplayName ( display dots StippleName ( (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) Bitmap )
UMC Confidential
16 Ver. B04_PB
9 Schematic Design
The user should follow the guidelines listed below while building schematics using Composer: Project libraries should list the primitive PDK library as a reference library in the library properties form. Users can add instances from the PDK library to designs stored in the project libraries. When performing hierarchical copy of schematic designs care should be taken to preserve the references to the PDK libraries. These references should not be copied locally to the project directories and the references set to the local copy of PDK cells. This would prevent your designs from inheriting any fixes done to the PDK library from an upgrade. Users should exercise caution when querying an instance and changing the name of the cell and replacing it with a reference to another cell. While like parameters will inherit values, callbacks are not necessarily executed. This would cause dependent parameters to have incorrect values. Schematics should be designed with schematic driven layout methodology in mind. Partitioning of schematics, hierarchical design, input and output ports, should be done in a clean and consistent fashion. Usage of pPar and iPar in a schematic design context is discouraged. While this works fine in schematic design, this could lead to problems while performing schematic driven layout.
UMC Confidential
17 Ver. B04_PB
10 Library Device Setup

10.1 Resistors
The resistors in the library consist of two types; diffused and insulated. The diffused types include n+ and are 3 terminal resistors with diode backplates. The insulated resistors are those that are isolated from silicon by an insulator (oxide) such as poly resistors. The resistors in this PDK are 3 terminal devices. Serpentine resistor layouts are not allowed. Dog-bone configurations are allowed. Units: The width is specified in meters for schematic simulation. All parameters entered into the resistor form must be integers or floating-point numbers. No design variables are supported due to the calculations that must be performed on the entries. Calculation: The width and length are snapped to grid, and the resistances are recalculated and updated on the component form based on actual dimensions. Simulation: The UMC provided model definitions are used to model the resistors.
10.2 Capacitors
All capacitors in the PDK library are 2 and 3 terminals. The capacitors for this process are MIMCAPS_MM, MIMCAPM_RF, NCAP_MM and PCAP_MM. MIMCAPS_MM and MIMCAPM_RF are metal on metal capacitors and they have 2 and 3 terminals respectively. The NCAP_MM and PCAP_MM are MOSFET capacitors and they have 4 terminals. Units: The length and width are specified in meters for schematic simulation. All parameters entered into the capacitor form must be integers or floating-point numbers. Design variables are supported here. Calculation: The width and length are snapped to grid, and the capacitance is recalculated and updated on the component form based on actual dimensions. Simulation: The UMC provided model definitions are used to model the capacitors.
10.3 MOSFETS
All mosfets in the PDK library are 4 terminal, with the body terminal explicitly connected. To conform to electromigration rules, customer must choose proper finger width, finger number, or source/drain metal width according to device operating point.
UMC Confidential
18 Ver. B04_PB
UM180FDKMFC000000A_B Units: Length and width are in meters, with areas and perimeters in meters squared and meters, respectively. Design variables are allowed for Length and Width entries. Calculation: The area and perimeter parameters for the sources and drains are calculated from the width and the number of fingers used. This calculation assumes that the drain will always have the lesser capacitance (area) when there is an even number of fingers (odd number of diffusion areas). The Width per finger is calculated by dividing the width by the number of fingers. This parameter is for viewing by the designer. Simulation: The UMC provided model definitions are used to model the MOSFET devices.
10.4 Bipolar Transistors
This PDK contains 2 vertical PNP transistors that have a substrate collector. The device has fixed dimensions for its emitter size. Units: The emitter size is specified in meters for schematic entry. All parameters entered into the PNP_V50X50_MM and PNP_V100X100_MM forms must be integers or floating-point numbers. Simulation: The UMC provided model definitions are used to model the bipolar transistors.
UMC Confidential
19 Ver. B04_PB
11 Supported Devices
11.1 MOSFETS
N_18_MM 1.8 volt NMOS transistor P_18_MM 1.8 volt PMOS transistor N_33_MM 3.3 volt NMOS transistor P_33_MM 3.3 volt PMOS transistor N_LV_18_MM 1.8 volt low vt NMOS transistor P_LV_18_MM 1.8 volt low vt PMOS transistor N_LV_33_MM 3.3 volt low vt NMOS transistor P_LV_33_MM 3.3 volt low vt PMOS transistor N_ZERO_18_MM 1.8 volt zero vt NMOS transistor N_ZERO_33_MM 3.3 volt zero vt NMOS transistor N_BPW_18_MM 1.8 volt triple-well NMOS transistor N_BPW_33_MM 3.3 volt triple-well NMOS transistor N_L18W500_18_RF - 1.8 volt variable finger RF NMOS transistor N_L34W500_33_RF - 3.3 volt variable finger RF NMOS transistor N_PO7W500_18_RF - 1.8 volt variable length RF NMOS transistor N_PO7W500_33_RF - 3.3 volt variable length RF NMOS transistor P_L18W500_18_RF - 1.8 volt variable finger RF PMOS transistor P_L34W500_33_RF - 3.3 volt variable finger RF PMOS transistor P_PO7W500_18_RF -1.8 volt variable length RF PMOS transistor P_PO7W500_33_RF - 3.3 volt variable length RF PMOS transistor
11.2 RESISTORS
RSPD_MM P+ diffused resistor w/salicide RSND_MM N+ diffused resistor w/ salicide RNPPO_MM P+ poly resistor w/o salicide RNNPO_MM N+ poly resistor w/o salicide RSNWELL_MM N-Well resistor RNHR1000_MM High Resistive poly resistor RNND_MM N+ diffused resistor w/o salicide RNPD_MM P+ diffused resistor w/o salicide
UMC Confidential
20 Ver. B04_PB
UM180FDKMFC000000A_B RM1_MM Metal 1 resistor RM1_MM Metal 2 resistor RM3_MM Metal 3 resistor RM4_MM Metal 4 resistor RM5_MM Metal 5 resistor RM6_MM Metal 6 resistor RNHR_RF - RF High resistive poly resistor RNNPO_RF - RF N+ poly resistor w/o salicide RNPPO_RF - RF P+ poly resistor w/o salicide
11.3 CAPACITORS
MIMCAPS_MM Single-squared mixed-mode metal-to-metal capacitor - CapA = 0.001F/M^2 CapP = 7.5e-11F/M NCAP_MM - NMOS transistor configured as a capacitor PCAP_MM - PMOS transistor configured as a capacitor MIMCAPM_RF RF Metal Capacitor
11.4 BIPOLARS 11.5 DIODES
PNP_V50X50_MM - 5x5 CMOS vertical substrate PNP PNP_V100X100_MM - 10x10 CMOS vertical substrate PNP DION_MM N+/psub diode DIONW_MM Nwell/psub diode DIOP_MM P+/nwell diode
11.6 Inductors
L_SLCR20K_RF Circular spiral RF inductor PAD_RF RF Bond Pad VARDIOP_RF - P+/Nwell RF diode varactor VARMIS_18_RF - 1.8V N+/Nwell RF MIS varactor
11.7 Bond Pads 11.8 Varactors
UMC Confidential
21 Ver. B04_PB
11.9 PARASITICS
NOTE: These symbols are used for internal use only. They are placed in the extracted view of a layout to display parasitic values. They are not devices that designers should use in their designs. pcapacitor presistor
UMC Confidential
22 Ver. B04_PB
12 Views provided
12.1 MOSFETS
Four terminals (D, G, S, B) symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.2 RESISTORS
Two terminals (PLUS, MINUS) for RM1_MM, RM1_MM, RM3_MM, RM4_MM, RM5_MM, RM6_MM Three terminals (PLUS, MINUS, B) for RSPD_MM, RSND_MM, RNPPO_MM, RNNPO_MM, RSNWELL_MM, RNHR1000_MM, RNND_MM, RNPD_MM, RNHR_RF, RNNPO_RF, RNPPO_RF symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.3 CAPACITORS
Two terminals (PLUS, MINUS) for MIMCAPS_MM Three terminals (PLUS, MINUS, B) for NCAP_MM, PCAP_MM, MIMCAPM_RF symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.4 BIPOLARS 12.5 DIODES
Three terminals (C, B, E) symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Fixed) Two terminals (PLUS, MINUS) symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Fixed)
12.6 Inductors
Three terminals (PLUS, MINUS, B) symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
12.7 Bond Pads 12.8 Varactors
Two terminals (PLUS, MINUS) symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells) Two terminals (PLUS, MINUS) for VARDIOP_RF Three terminals (PLUS, MINUS, B) for VARMIS_18_RF symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)
UMC Confidential
23 Ver. B04_PB
13 CDF parameters
13.1 MOSFETS
l (M) - gate length in meters w (M) - gate width in meters Number of Fingers - Number of poly gate stripes used in layout (w/nf width) Source Drain Metal Width (M) Width of metal on Source and Drain in meters. Width Per Finger - Width of each gate stripe (non-editable) Multiplier - Number of Parallel MOS devices Calc Diff Params - cyclic which controls the calculation of area and periphery of the source/drain regions for simulation. Default is true which auto calculates the values. If nil, the user can enter the values. Source diffusion area - Calculated source diffusion area in square meters Drain diffusion area - Calculated drain diffusion area in square meters Source diffusion periphery - Calculated source diffusion periphery in meters Drain diffusion periphery - Calculated source diffusion periphery in meters
NOTE: To conform to electromigration rules, customer must choose proper finger width, finger number, or source/drain metal width according to device operating point.
13.2 RF MOSFETS
Width per Finger (M) - gate width in meters Length (M) - gate length in meters
Number of Fingers - Number of poly gate stripes used in layout (w/nf width)
UMC Confidential
24 Ver. B04_PB
MOSFET ADD INSTANCE FORM
UMC Confidential
25 Ver. B04_PB
13.3 RESISTORS
Resistance - Resistance value used for simulation w (M) - resistor width in meters l (M) - resistor length in meters (non-editable) Rho - resistor layer sheet rho (non-editable) Area (M^2) - resistor area for parasitics in meters squared(non-editable) Perim (M) - resistor perimeter for parasitics in meters (non-editable)
13.4 RF RESISTORS
Resistance - Resistance value used for simulation Width (M) - resistor width in meters Length (M) - resistor length in meters (non-editable) Rsh (ohm/sq) - resistor layer sheet rho (non-editable) Rend (ohm-um) resistor end sheet rho (non-editable) delta Width (um) resistor delta width (non-editable) delta Length (um) resistor delta length (non-editable)
UMC Confidential
26 Ver. B04_PB
RESISTOR ADD INSTANCE FORM
UMC Confidential
27 Ver. B04_PB
13.5 CAPACITORS MIMCAPS_MM

Total Capacitance (non-editable) -
Capacitance - capacitance value used in simulation (non-editable) Capacitance multiplied times Multiplier
w (M) - capacitor width in meters l (M) - capacitor length in meters CapA (F/M^2) - Plate Capacitance (non-editable, units are Farads per Meter Squared) CapP (F/M) - Fringe Capacitance (non-editable, units are Farads per Meter) Multiplier - Number of devices in layout (non-editable for mimcap)
13.6 CAPACITORS NCAP_MM, PCAP_MM
Capacitance capacitance value used in simulation ( based on rough calculation) Total Capacitance total capacitance value is Capacitance * Multiplier (non-editable) Spec cyclic used to choose capacitor entry method (Capacitance, Cap & l, l & w) l (M) capacitor length in meters w (M) capacitor width in meters Multiplier - Number of Parallel MOS devices CapA (F/M^2) Plate Capacitance (non-editable, units are Farads per Meter Squared) CapP (F/M) Fringe Capacitance (non-editable, units are Farads per Meter) Number of Fingers - Number of poly gate stripes used in layout (w/nf width)
Width Per Finger - Width of each gate stripe (non-editable using totalWidth) Calc Diff Params - cyclic which controls the calculation of area and periphery of the source/drain regions for simulation. Default is true which auto calculates the values. If nil, the user can enter the values. Source diffusion area - Calculated source diffusion area in square meters
UMC Confidential
28 Ver. B04_PB
UM180FDKMFC000000A_B Drain diffusion area - Calculated drain diffusion area in square meters Source diffusion periphery - Calculated source diffusion periphery in meters Drain diffusion periphery - Calculated source diffusion periphery in meters
13.7 CAPACITORS MIMCAPM_RF
Capacitance - capacitance value used in simulation Multi Square X - multiple square capacitors in x-direction Multi Square Y - multiple square capacitors in y-direction Width (X) - capacitor width in meters Length (Y) - capacitor length in meters
UMC Confidential
29 Ver. B04_PB
CAPACITOR ADD INSTANCE FORM
UMC Confidential
30 Ver. B04_PB
13.8 BIPOLARS
Model name - Spectre model name (non-editable) Multiplier - Number of Parallel Bipolar devices Width (M) Emitter Width in metres (non-editable) Length (M) Emitter Length in metres (non-editable) Emitter area Calculated emitter area in meters squared (non-editable) Device initially off bolean to turn device model off for simulation start-up. Estimated operating region Simulation operating region (off, fwd, rev, sat) Linearized Region Simulation operating region (yes, no)
UMC Confidential
31 Ver. B04_PB
BIPOLAR ADD INSTANCE FORM
UMC Confidential
32 Ver. B04_PB
13.9 DIODES
Device Area - Calculated junction area in meters squared (non-editable) Multiplier - Number of Parallel Diode devices Length (M) - diode length in meters
Width (M) - diode width in meters
DIODE ADD INSTANCE FORM
UMC Confidential
33 Ver. B04_PB
13.10
Inductance Inductance in Henries Inner Diameter (M) inner diameter in meters Width (M) width of inductor in meters Number of Turns number of inductor turns.
Inductors
INDUCTOR ADD INSTANCE FORM
UMC Confidential
34 Ver. B04_PB
13.11
Specified Index multi layer number of PAD metal (1, 2, 3, 4, 5)
Bond Pads
INDUCTOR ADD INSTANCE FORM
13.12
Capacitance (zero bias) zero bias capacitance value Number of Fingers number of finger stripes used in layout Parasitic Cap. (fF/um^2) area capacitance in fF/um2 Fringe Cap. (fF/um) fringe capacitance in fF/um
Varactors VARDIOP_RF
13.13
Capacitance (max) maximum capacitance value Number of Fingers number of finger stripes used in layout
Varactors VARMIS_18_RF
UMC Confidential
35 Ver. B04_PB
UM180FDKMFC000000A_B Parasitic Cap. (fF/um^2) area capacitance in fF/um2 Fringe Cap. (fF/um) fringe capacitance in fF/um
VARACTOR ADD INSTANCE FORM
UMC Confidential
36 Ver. B04_PB
14 Component Label Defaults

14.1 MOSFETS
component parameters: model, l, w, fingers, m operating point: ids, vgs, vds, vth, vdsat model: vtho, vsat instance name prefix: NM, NP
14.2 RF MOSFETS
component parameters: model, l, w, nf operating point: ids, vgs, vds, vth, vdsat model: vth, vsat instance name prefix: NM, NP
14.3 RESISTORS
model: -
component parameters: model, r, w, l operating point: v i res instance name prefix: R
14.4 RF RESISTORS
model: -
component parameters: model, r, w, l operating point: v, res instance name prefix: R
14.5 CAPACITORS MIMCAPS_MM

operating point: cap model: instance name prefix: C
component parameters: model, c, l, w, m
14.6 CAPACITORS NCAP_MM, PCAP_MM

operating point: cap model: vtho, tox, cj
UMC Confidential 37
component parameters: model, c, l, w, fingers, m
Ver. B04_PB
UM180FDKMFC000000A_B instance name prefix: C
14.7 CAPACITORS MIMCAPM_RF

operating point: cap model: instance name prefix: C
component parameters: model, nx, ny, w, l
14.8 BIPOLARS
component parameters: model, area, m operating point: betadc, ic, vce model: bf, is, vaf instance name prefix: Q
14.9 DIODES
component parameters: model, area, m operating point: id, vd, region model: is, rs, n instance name prefix: D
14.10
component parameters: model, nf, c operating point: model: instance name prefix: C
VARACTORS
14.11
component parameters: model, index operating point: - i model: instance name prefix: C
Bond Pads
14.12
component parameters: model, d, w, n operating point: - i, ind model: -
Inductors
UMC Confidential
38 Ver. B04_PB
UM180FDKMFC000000A_B instance name prefix: C
UMC Confidential
39 Ver. B04_PB
15 Simulation Models
The following simulators are supported in the PDK: Spectre hSpiceS UltraSim NOTE: MMSIM60 is recommended to run Spectre or UltraSim simulations. The following model library setup is done automatically when the user first opens the umc18mmrf library or uses a component from that library. The user may disable or modify this feature by editing the libInitCustomExit.il file found in the umc18mmrf library. Spectre: <pdkInstallDir>/Models/Spectre/018-rf-v2d4-control.scs <pdkInstallDir>/Models/Spectre/MM180_BJT_V112.mdl.scs <pdkInstallDir>/Models/Spectre/MM180_DIODE_V113.mdl.scs <pdkInstallDir>/Models/Spectre/MM180_LVT18_V113.lib.scs <pdkInstallDir>/Models/Spectre/MM180_LVT33_V113.lib.scs <pdkInstallDir>/Models/Spectre/MM180_MIMCAP_V101.lib.scs <pdkInstallDir>/Models/Spectre/MM180_REG18BPW_V123.lib.scs <pdkInstallDir>/Models/Spectre/MM180_REG18_V123.lib.scs <pdkInstallDir>/Models/Spectre/MM180_REG33BPW_V123.lib.scs <pdkInstallDir>/Models/Spectre/MM180_REG33_V113.lib.scs <pdkInstallDir>/Models/Spectre/MM180_RES_V111.lib.scs <pdkInstallDir>/Models/Spectre/MM180_RES_V132.lib.scs <pdkInstallDir>/Models/Spectre/MM180_ZVT18_V113.lib.scs <pdkInstallDir>/Models/Spectre/MM180_ZVT33_V113.lib.scs
tt tt mimcaps_typ tt tt tt tt res_typ res_typ tt tt
Where <pdkInstallDir> is the path where the UMC90nm PDK is installed and the second entry is the simulation corner that the user wants to simulate. The user should follow the instructions provided with the device models from UMC to ensure the proper selection of sections for simulation.
UMC Confidential
40 Ver. B04_PB
16 AddWire Utility
Certain devices in the library have bulk pins (i.e N_18_MM, P_18_MM, RSND_MM, etc..). A utility has been added to the PDK to automatically wire these bulk terminals to user specified signals (i.e. gnd!, vdd!, etc..). This will help reduce schematic clutter while maintaining required circuit hookup. The following picture shows the result of executing the "addWire" routine.
There are no arguments to run the program, the user must type umc18mmrf_addWire() in the CIW. If you dont have a schematic cellview open it will give you an error message. If the user has instances selected when they run addWire, it will prompt them for the label name for those specific instances and will only add the wires to those instances. It does nothing to the schematic hierarchy. If no instances are selected then the program will wire up all instances that have their bulk nodes unconnected. The user gets prompted for the label name for each type of instance, and they also have the option of running it down through the hierarchy or just at the current cellview. And, finally, if the user does not want to use gnd! or vdd! as the label name, there is an entry box for the user to type in an alternative net name. If another wire name is used, it will be added to the cyclic list of label name choices - but only for that DFII session. Once you exit the dfII session, the cyclic is reset to gnd! and vdd!
UMC Confidential
41 Ver. B04_PB
17 UpdateCDFs Utility
When changes are made to a device inside the PDK, these changes often affect circuit design, which have already been created. For example, a sheet rho value may change on a resistor, which affects the length of the device passed to the simulator and used to generate the layout. These parameters are not automatically updated in each of the designers circuit libraries. A function has been written and included as a part of the PDK to complete the update to an existing library such that all modifications made to a PDK since a previous release are reflected in each of the circuit designs inside a library. The name of the function for this PDK is called "umc18mmrf_updateCDFs". There is a single argument to this function, which represents the design library, which is to be updated with the new CDF information. Once this routine has been run, all design schematics in the designated library will be in sync with the latest release of the PDK. Please note, however, that possible LVS violations may arise as a result of running this routine depending upon what changes have been made to the PDK. For example, a sheet rho change as specified earlier could cause a resistor to shrink in length in the schematic thus causing a mismatch as far as LVS is concerned. Please be sure that you verify again each design in simulation, DRC, and LVS to insure that no unintended modifications have been overlooked. The syntax for this function is as follows:
In the CIW, type umc18mmrf_updateCDFs(libName) for the library which you wish to operate on. For example, given a library named designLib, the proper syntax for this routine would be: umc18mmrf_updateCDFs("designLib") Please be sure that the library name you choose to pass as an argument is present in the library manager window (i.e. - be sure that it is visible and located in your cds.lib file)
UMC Confidential
42 Ver. B04_PB
18
Setting Environment Variables
Environment variables control how various DFII commands work by default. These variables can be stored in the Library .cdsenv file which is located in the umc18mmrf directory. This library .cdsenv file is loaded by default in the PDK libinit.il file. The .cdsenv file, which is provided with the UMC .18 MM/RF PDK, contains five environment variables; setPPConn, xSnapSpacing, ySnapSpacing, updatePCellIncrement, and InitIOPinLayer. 1. setPPConn is a boolean layoutXL editor environment variable which recognizes pseudo-parallel nets. These nets can be connected, or not connected as in the schematic, to produce an electrically equivalent layout. If set to nil, pseudo-parallel nets are ignored. These nets then require interconnect that matches the schematic exactly. In this PDK the setPPConn environment variable has been set to nil. The designer can change the value of the setPPConn environment variable by editing the following line in the .cdsenv file: layoutXL setPPConn boolean nil The valid values for setPPConn are nil and t. 2. xSnapSpacing is a floating-point layout editor environment variable which controls the minimum distance the cursor moves in the X direction. In this PDK the xSnapSpacing environment variable has been set to 0.01. The designer can change the value of the xSnapSpacing environment variable by editing the following line in the .cdsenv file: layout xSnapSpacing float 0.01 The valid values for xSnapSpacing are 0.01 to the desired value. 3. ySnapSpacing is a floating-point layout editor environment variable which controls the minimum distance the cursor moves in the Y direction. In this PDK the ySnapSpacing environment variable has been set to 0.01. The designer can change the value of the ySnapSpacing environment variable by editing the following line in the .cdsenv file: layout ySnapSpacing float 0.01
The valid values for ySnapSpacing are 0.01 to the desired value. 4. updatePCellIncrement is a floating-point layout editor environment variable specifying how often the system updates pcell parameters and regenerates the pcell during a stretch operation. The designer can change the value of the updatePCellIncrement environment variable by editing the following line in the .cdsenv file: layout updatePCellIncrement float 0.01 The valid values for updatePCellIncrement are 0.01 to the desired value. 5. initIOPinLayer is a string layoutXL editor environment variable specifying the default layer to use in the Gen From Source Form for I/O Pin creation. The designer can change the value of the initIOPinLayer environment variable by editing the following line in the .cdsenv file: layoutXL initIOPinLayer string ME1 drawing The valid values for initIOPinLayer are any layer defined in the techfile.
UMC Confidential
44 Ver. B04_PB
19 Techfile Layers
Cadence will provide a standard display setup, and will not support desired changes to the display. The customer is free to modify the display.drf file used on-site to achieve any desired display. Techfile layers defined in this PDK are done in accordance with UMC document G-06LMT-GENERATION18-LAYER_MAPPING_TABLE, Revision 2.3_P1 (UMC Official Layer Mapping Table). The user is referred to this UMC document for a complete listing of all layer/levels of the process technology.
UMC Confidential
45 Ver. B04_PB
20 Virtuoso XL
The standard Cadence Virtuoso XL design flow will be implemented. This includes basic connectivity of connection layers, wells, and substrate, and symbolic contacts. The M factor will be used for device instance multiplier - there will be no conflict with the parameter used in cell operation. Names will be displayed on the layout views to aid in schematic-layout instance correlation. Auto-abutment of MOSFET devices is supported. Pin permuting of MOSFET and Resistor device is also supported. The skill pcell layouts are compiled into the PDK. The users should follow the guidelines listed below for layout design: The VirtuosoXL tool requires a separate license for operation. Users obtain maximum leverage from the PDK by doing schematic driven layout in the Virtuoso XL environment. This flow will produce a correct design layout. The Virtuoso Custom Router (IC Craftsman) can be used to finish the interconnects in the layout. The VCR rules file for the target process is provided with the PDK. Abutment is currently supported only for MOS transistors. Note, abutment will work only on schematic driven layouts. Schematic Driven Layout is recommended over Netlist Driven Layout. NOTE: Skill pcell source code is not included in the PDK kit.
UMC Confidential
46 Ver. B04_PB
20.1 SYMBOLIC CONTACTS
M1_NACTIVE Metal 1 to NPLUS DIFF contact M1_NWELL Metal 1 to NWEL contact M1_PACTIVE Metal 1 to PPLUS DIFF contact M1_POLY Metal 1 to PO1 contact M1_PSUB - Metal1 to Substrate contact M2_M1 Metal 2 to Metal 1 via contact M3_M2 Metal 3 to Metal 2 via contact M4_M3 Metal 4 to Metal 3 via contact M5_M4 Metal 5 to Metal 4 via contact M6_M5 Metal 6 to Metal 5 via contact
ADD CONTACT FORM
UMC Confidential
47 Ver. B04_PB
21 Dracula Support
CDL OUT FORM
No Dracula support will be provided with the exception of creating an auCdl netlist. Listed below is an example of the CDL netlist for each device.
UMC Confidential
48 Ver. B04_PB
22 Assura Decks
NOTE: This PDK revision B04_PB does not incorporate Assura Decks. The following descriptions are for reference only The user needs to do the following in order to implement and use the Assura Verification decks: 1) Create a directory named: assura_umc18mmrf_tech 2) Place all Assura decks in the directory created above ( assura_umc18mmrf_tech). 3) Create a file named: assura_tech.lib 4) In this file ( assura_tech.lib ), the user needs to enter only one line: DEFINE umc18mmrf_rcx ./assura_umc18mmrf_tech Once these four steps have been completed, the user will then be able to run Assura Verification on this PDK. The user needs the licenses for these tools to perform verification. When performing verification you have to provide the library name to the verification deck. Select the desired switches before starting the verification run. Refrain from working on the target layout being verified while the run is in progress. Following are the tar files for the description of Assura verification setup only: Assura RCX tar file name: G-DF-MIXED_MODE_RFCMOS18-1.8V_3.3V-1P6M-MMC-ASSURA-LPE-1.1-P3 Files Included: Topm_20k.tar g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p5-extract.rul g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p5compare.rul bind.Model Version: 1.2_p5 Date: 05/12/03
Assura DRC tar file name: G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.2-p5 Files Included: g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul
UMC Confidential
49 Ver. B04_PB
UM180FDKMFC000000A_B g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rsf umc_ant_assura_all.0.rul umc_ant_assura_all-.0.rsf Version: DRC version: 2.2-p5 ANT version: 0 Date: DRC date: 04/11/03 ANT date: 04/21/03
UMC Confidential
50 Ver. B04_PB
22.1 Assura DRC
The following 3 Assura DRC files were tested with the PDK and were placed in the assura_umc18mmrf_tech directory: g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p 5.rul. umc_ant_assura_all.0.rul assuraESD.rul The following switches are available in the
g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul: Technology Switches: BDSP_rule checks rules for the bordered SP SRAM core regions BLSP1_rule checks the rules for the borderless SP SRAM core regions BLSP_rule checks the rules for the Virage SP SRAM core regions DP1_rule checks the rules for the DP1 SRAM core regions DP2_rule checks the rules for the DP2 SRAM core regions DP_rule checks the rules for the DP SRAM core regions ROM_rule checks the rules for the ROM regions metal2_is_top specifies 2-Metal Technology metal3_is_top specifies 3-Metal Technology metal4_is_top specifies 4-Metal Technology metal5_is_top specifies 5-Metal Technology top_metal_is_thick specifies Thick Top Metal Chip-Level Switches: SR Seal ring rules are checked Run-Time Intensive Switches: check_max_metal_space Maximum Metal spacing rules are checked check_density Metal coverage rules are checked check_slots Slot rules are checked
UMC Confidential
51 Ver. B04_PB
UM180FDKMFC000000A_B By default, if none of the switches are set, the file will assume the following: The design incorporates 6-metal technology Off-grid checks will be performed The chip-level checks will NOT be performed The run-time intensive checks will NOT be performed.
22.2 Assura Antenna
The following Assura Antenna file was tested with the PDK and was placed in the assura_umc18mmrf_tech directory: umc_ant_assura_all.0.rul The following switches are available in the assuraANT.rul file: Technology Switches: metal1_is_top specifies 1-Metal Technology metal2_is_top specifies 2-Metal Technology metal3_is_top specifies 3-Metal Technology metal4_is_top specifies 4-Metal Technology metal5_is_top specifies 5-Metal Technology metal6_is_top specifies 6-Metal Technology By default, if none of the switches are set, the file will assume 6-metal process.
Antenna Check Format Switches: Check_All_Top_Antenna Performs one level area and perimeter antenna checks. For example, checks m3 area/gate area and m3 perimeter/gate perimeter check. Check_Cumulative_Area_Antenna Performs antenna checks. cumulative area
Check_Cumulative_Perimeter_Antenna Performs perimeter antenna checks.
cumulative
UMC Confidential
52 Ver. B04_PB
22.3 Assura ESD
The Assura Antenna files tested with the PDK were placed in the assura_umc18mmrf_tech directory and are named: assuraESD.rul No switches are available in the assuraESD.rul file.
ASSURA DRC FORM
UMC Confidential
53 Ver. B04_PB
22.4 Assura LVS
The Assura LVS files tested with assura_umc18mmrf_tech directory:
the
PDK
were
placed
in
the
g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p 3-extract.rul g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p 3-compare.rul bind.Model for use with any devices from VST or Artisan libraries. Please see usage notes in extract.rul for more information. The following switches are available in the extract.rul file: Artisan_Lib for extraction of devices from Artisan libraries Skip_Soft-Connect_Checks - Select the switch to skip the reporting of multStamp, floating, and multConnect errors. By default, this switch is not set. Top_Metal_Thickness--20K Sets Metal Resistor Coefficients for 20KA thick Top Metal. To avoid RCX run-time errors, use the switches below to skip the extraction statements of the devices without IVPCELL view. Skip_Logic_Device_ExtractionSkips extraction of logic devices. Skip_Mixed_Mode_Device_ExtractionSkips extraction Mode ( _MM) devices. of Mixed
Skip_RF_Device_ExtractionSkips extraction of RF ( _RF) devices. DO NOT SELECT ANY OF THE FOLLOWING SWITCHES: Top_MetalME4 This is not supported in this PDK. Top_MetalME5 This is not supported in this PDK.
UMC Confidential
54 Ver. B04_PB
UM180FDKMFC000000A_B The default switch is for the 8KA 1P6M process.
ASSURA LVS FORM
22.5 Assura RCX

The Assura RCX files tested with the PDK were placed in the following directory: assura_umc18mmrf_tech - Directory where Assura RCX files are provided
UMC Confidential
55 Ver. B04_PB
UM180FDKMFC000000A_B Please consult the Assura RCX users manual for available RCX options.
NOTE: The av_extracted view is not supported in these Assura rules. To enable av_extracted views please follow the instructions below: 1) Convert the extract rules with the Skip_Logic_Device_Extraction switch set for capgen input The following files should be found in your assura_umc18mmrf_tech directory: cap_coeff.dat compare.rul extract.rul lvsfile p2lvsfile procfile Additional files - assura 3.0 binary file output from capgen -S run - compare rules for LVS - extract rules file for LVS - converted Assura extract file for RCX - layer mapping file for procfile & extract.rul - Process description file (SEE NOTE BELOW) - RCXdspfINIT, RCXspiceINIT, RCXutilities - cap.so, s2d.log, caps2d - paxfile_coeff, rcxfs.dat The capgen lvsfile is created from the Assura extract rules file. A sample RSF file, lvsfile.rsf is shown below to do this. The Cadence PDK compatible Assura extract rules file, extract.rul is included. You may use this or your own file. Change the lvsfile.rsf file as needed. Within the assura_umc18mmrf_tech directory, run Assura from Unix: Sample lvsfile.rsf: /**********************************************************************
umc18mm_20k_rcx.rsf - sample RSF to run Assura RCX
UMC Confidential
56 Ver. B04_PB
UM180FDKMFC000000A_B Assura RCX sample RSF for capgen lvsfile creation Use this file to create the capgen "lvsfile" from extract.rul ***********************************************************************/ avParameters( ?rulesFile "extract.rul" ?rcxFile "lvsfile" ?inputLayout ("df2" "dummyLayoutName" ) ?cellName "dummyCellname" ?viewName dummyviewName ?cdslib ./cds.lib ?set Skip_Logic_Device_Extraction ?runName "lvs_convert" ?compileOnly t )
Note: Set ?inputLayout, ?cellName and ?viewName to point to data. 2) Run assura lvsfile.rsf > lvs_convert.log from the Unix prompt The output will be the file "lvsfile" which will be used as an input to capgen. The other files from the run (lvs_convert.???) can be deleted.
3) Execute the second capgen command from Unix prompt within the assura_umc18mmrf_tech. % capgen -C -lvs lvsfile -p2lvs p2lvsfile -mos_diff_ap -cap_unit 1 . Note: The period . at the end of the command stands for current directory.
ASSURA RCX FORM
UMC Confidential
58 Ver. B04_PB
23 DEVICE SPECIFICATIONS
Model and Layout Source
Spectre Model received HspiceS Model received GDS or DFII Sample Layout Received Fixed Layout or Variable Layout (Pcell)
Device Mos N_18_MM N_BPW_18_MM N_33_MM N_BPW_33_MM N_LV_18_MM N_LV_33_MM N_ZERO_18_MM N_ZERO_33_MM P_18_MM P_33_MM P_LV_18_MM P_LV_33_MM RF Mos
Description
1.8 volt NMOS transistor 1.8 volt triple-well NMOS transistor 3.3 volt NMOS transistor 3.3 volt triple-well NMOS transistor 1.8 volt low vt NMOS transistor 3.3 volt low vt NMOS transistor 1.8 volt zero vt NMOS transistor 3.3 volt zero vt NMOS transistor 1.8 volt PMOS transistor 3.3 volt PMOS transistor 1.8 volt low vt PMOS transistor 3.3 volt low vt PMOS transistor
y y y y y y y y y y y y
Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell
N_L18W500_18_RF 1.8 volt variable finger RF NMOS transistor N_L34W500_33_RF 3.3 volt variable finger RF NMOS transistor N_PO7W500_18_RF 1.8 volt variable length RF NMOS transistor N_PO7W500_33_RF 3.3 volt variable length RF NMOS transistor P_L18W500_18_RF 1.8 volt variable finger RF PMOS transistor P_L34W500_33_RF 3.3 volt variable finger RF PMOS transistor P_PO7W500_18_RF 1.8 volt variable length RF PMOS transistor P_PO7W500_33_RF 3.3 volt variable length RF PMOS transistor Resistor RSND_MM RSPD_MM RNPPO_MM N+ diffused resistor w/ salicide P+ diffused resistor w/ salicide P+ poly resistor w/o salicide
y y y y y y y y
y y y y y y y y
y y y y y y y y
Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell
y y y
y y y
y y y
Pcell Pcell Pcell
UMC Confidential
59 Ver. B04_PB
RNNPO_MM RSNWELL_MM RNHR1000_MM RNND_MM RNPD_MM RM1_MM RM2_MM RM3_MM RM4_MM RM5_MM RM6_MM RF Resistor RNHR_RF RNNPO_RF RNPPO_RF Capacitor MIMCAPS_MM NCAP_MM PCAP_MM RF Capacitor MIMCAPM_RF Diode DION_MM DIONW_MM DIOP_MM BJT PNP_V50X50_MM Vertical substrate PNP ( 5x5 ) y y y y y y Fixed Fixed PNP_V100X100_MM Vertical substrate PNP ( 10x10 ) Inductor L_SLCR20K_RF Bond Pad PAD_RF N+/psub diode Nwell/psub diode P+/nwell diode y y y y y y y y y Fixed Fixed Fixed RF Metal capacitor y y y Pcell Single-squared MM Metal capacitor NMOS gate capacitor PMOS gate capacitor y y y y y y y y y Pcell Pcell Pcell RF High resistive poly resistor RF N+ poly resistor w/o salicide RF P+ poly resistor w/o salicide y y y y y y y y y Pcell Pcell Pcell N+ poly resistor w/o salicide N-well resistor High resistive poly resistor N+ diffused resistor w/o salicide P+ diffused resistor w/o salicide Metal 1 resistor Metal 2 resistor Metal 3 resistor Metal 4 resistor Metal 5 resistor Metal 6 resistor y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell Pcell
Circular spiral RF inductor
Pcell
Bond Pad
Fixed
UMC Confidential
60 Ver. B04_PB
Varactor VARDIOP_RF VARMIS_18_RF
P+/Nwell RF diode varactor 1.8V N+/Nwell RF MIS varactor
y y
y y
y y
Pcell Pcell
23.1 MOS FORMAL PARAMETERS

l (gate length in microns)
Device
N_18_MM N_BPW_18_MM N_33_MM N_BPW_33_MM N_LV_18_MM N_LV_33_MM N_ZERO_18_MM N_ZERO_33_MM P_18_MM P_33_MM P_LV_18_MM P_LV_33_MM
min 180n 180n 340n 340n 240n 500n 300n 500n 180n 340n 240n 500n
Value Got from Design Rule # Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules 4.14Aa 4.14Aa 4.14Ab 4.14Ab 4.7Aa 4.9A 4.8A 4.7Ab 4.14Ba 4.14Bb 4.4A 4.5A
max 50u 50u 50u 50u 50u 50u 50u 50u 50u 50u 50u 50u
Value Got from Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
w (gate width in microns)
Device
min 240n 240n 240n 240n 240n 800n 240n 800n 240n 240n 240n 800n
max 100u 100u 100u 100u 100u 100u 100u 100u 100u 100u 100u 100u
UMC Confidential
61 Ver. B04_PB
Fingers (number of fingers)
Device
min 1 1 1 1 1 1 1 1 1 1 1 1
Value Got from Default Default Default Default Default Default Default Default Default Default Default Default
max 100 100 100 100 100 100 100 100 100 100 100 100
Value Got from PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard PDK standard
UMC Confidential
62 Ver. B04_PB
23.2 RF MOS FORMAL PARAMETERS

Device Name Formal Parameters l (Length) min 180.0n 340.0n 200n 340.0n 180.0n 340.0n 200n 340.0n Value Got from Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model max 180.0n 340.0n 500n 800n 180.0n 340.0n 500n 800n Value Got from Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
N_L18W500_18_RF N_L34W500_33_RF N_PO7W500_18_RF N_PO7W500_33_RF P_L18W500_18_RF P_L34W500_33_RF P_PO7W500_18_RF P_PO7W500_33_RF Device Name
w (Finger Width) min N_L18W500_18_RF N_L34W500_33_RF N_PO7W500_18_RF N_PO7W500_33_RF P_L18W500_18_RF P_L34W500_33_RF P_PO7W500_18_RF P_PO7W500_33_RF Device Name nf (Finger Number) min N_L18W500_18_RF N_L34W500_33_RF N_PO7W500_18_RF N_PO7W500_33_RF P_L18W500_18_RF P_L34W500_33_RF P_PO7W500_18_RF P_PO7W500_33_RF 5 5 7 7 5 5 7 7 5u 5u 5u 5u 5u 5u 5u 5u
Value Got from Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model Spectre model
max 5u 5u 5u 5u 5u 5u 5u 5u
max 21 21 7 7 21 21 7 7
UMC Confidential
63 Ver. B04_PB
23.3 RESISTOR FORMAL PARAMETERS

r (resistance in Ohms)
Device
RSND_MM RSPD_MM RNPPO_MM RNNPO_MM RSNWELL_MM RNHR1000_MM RNND_MM RNPD_MM RM1_MM RM1_MM RM3_MM RM4_MM RM5_MM RM6_MM
min 168.000m 168.000m 21.1085 5.11481 31.376 43.263 2.39596 4.73918 2.82975m 2.1545m 2.1545m 2.1545m 2.1545m 2.16275m
Value Got from Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation
Design Rule # Calc.1 Calc.1 Calc.1 Calc.1 Calc.1 Calc.5 Calc.1 Calc.1 Calc.2 Calc.2 Calc.2 Calc.2 Calc.2 Calc.2
max 33.3107K 33.3107K 2.62455M 1.35984M 6.19403K 7.56992M 291.817K 484.5K 6.41667 4.42857 4.42857 4.42857 4.42857 1.86364
Value Got from Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation Calculation
Design Rule # Calc. 3 Calc. 3 Calc. 3 Calc. 3 Calc. 3 Calc. 6 Calc. 3 Calc. 3 Calc.4 Calc.4 Calc.4 Calc.4 Calc.4 Calc.4
w (width In microns)
Device
RSND_MM RSPD_MM RNPPO_MM RNNPO_MM RSNWELL_MM RNHR1000_MM RNND_MM RNPD_MM RM1_MM RM1_MM RM3_MM RM4_MM RM5_MM RM6_MM
min 240n 240n 180n 180n 1.5u 180n 240n 240n 240n 280n 280n 280n 280n 440n
Value Got from Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules Design Rules
Design Rule # 4.1Aa 4.1Ab 4.14Aa 4.14Ba 4.2Ab 4.14Aa 4.1Aa 4.1Ab 4.20A 4.22A 4.24A 4.26A 4.28A 4.31A
max 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u 20u
Value Got from PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard PDK Standard
UMC Confidential
64 Ver. B04_PB
Note: Calc.1 ( Salicided sheet resistance ) * ( minL + deltaL ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW ) ( Salicided sheet resistance ) * ( minL ) / ( maxW ) ( Salicided sheet resistance ) * ( maxL + deltaL ) / ( minW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( minW + deltaW) ( Salicided sheet resistance ) * ( maxL ) / ( minW ) ( Salicided sheet resistance ) * ( minL -0.4um ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW ) ( Salicided sheet resistance ) * ( maxL -0.4um ) / ( minW + deltaW ) + 2 * ( non-salicided sheet resistance ) / ( minW + deltaW )
Calc.2 Calc.3
Calc.4 Calc.5
Calc.6
UMC Confidential
65 Ver. B04_PB
23.4 RF RESISTOR FORMAL PARAMETERS

Device Name Formal Parameters r
(Resistance)
min RNHR_RF RNNPO_RF RNPPO_RF Device Name w (Width) min RNHR_RF RNNPO_RF RNPPO_RF Device Name l (Length) min RNHR_RF RNNPO_RF RNPPO_RF 2u 2u 2u 2u 2u 2u 972.1002 136.6264 467.7584
Value Got from

Calculation Calculation Calculation
max 10.52856K 1.205465K 3.710338K
Value Got from

Calculation Calculation Calculation
Value Got from

Spectre model Spectre model Spectre model
max 10u 10u 10u
Value Got from

Value Got from

max 100u 100u 100u
Value Got from

UMC Confidential
66 Ver. B04_PB
23.5 CAPACITOR FORMAL PARAMETERS

c (capacitance In Farads)
Device
MIMCAPS_MM NCAP_MM PCAP_MM
min N/E 1.8618f 1.8618f
Value Got from Design Rule #
max N/E 3.3011p 3.3011p
Value Got from
Design Rule #
Design Rules Design Rules
Dim.1 Dim.1
Design Rules Design Rules
Dim.2 Dim.2
l (length in Metres)
Device
min 1.84u 180n 180n
Value Got from Design Rule # Design Rules Design Rules Design Rules Dim.3 4.14Aa 4.14Ba
max 100u 20u 20u
Value Got from Spectre model Spectre model Spectre model
W (width in Metres)
Device
min 1.84u 440n 440n
Value Got from Dim.3 Dim.4 Dim.5 100u 20u 20u
max
Value Got from Spectre model Spectre model Spectre model
Fingers
(number of Fingers)
Value Got from max Value Got from
Device
min
1 1
Default Default
50 PDK Standard 50 PDK Standard
UMC Confidential
67 Ver. B04_PB
Note: Dim.1 Dim.2 Dim.3 minW * minL * ( Area Capacitance ) + 2 * ( minW + minL ) * ( Fringe Capacitance ) maxW * maxL * ( Area Capacitance ) + 2 * ( maxW + maxL ) * ( Fringe Capacitance ) ( minWidth of VI5 ) + 2 * ( MMC enclosure of VI5 ) 4.30A
4.29D
Dim.4
( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact ) 4.19A 4.19G ( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact ) 4.19A 4.19F
Dim.5
UMC Confidential
68 Ver. B04_PB
23.6 RF CAPACITOR FORMAL PARAMETERS

Device Name Formal Parameters c (Capacitance) min 103.00f
Value Got from Calculation
max 5.047p
MIMCAPM_RF Device Name
l (Length(Y)) min MIMCAPM_RF Device Name w (Width(X)) min MIMCAPM_RF 10u 10u
Value Got from Spectre model
max 70u
max 70u
Device Name nx (Multi Square X) min MIMCAPM_RF Device Name ny (Multi Square Y) min MIMCAPM_RF 1 1
max 7
max 7
UMC Confidential
69 Ver. B04_PB
23.7 INDUCTOR FORMAL PARAMETERS

Device Name Formal Parameters l (Inductance) min 567.9646p
max 14.27438n
L_SLCR20K_RF Device Name
d (Diameter) min L_SLCR20K_RF Device Name w (Width) min L_SLCR20K_RF Device Name n (Turn Number) min L_SLCR20K_RF 1.5 6u 126u
max 238u
max 20u
max 5.5
23.8 BOND PAD FORMAL PARAMETERS

Device Name index min PAD_RF 1 Value Got from Spectre model max 5 Value Got from Spectre model
UMC Confidential
70 Ver. B04_PB
23.9 VARACTOR FORMAL PARAMETERS

Device Name Formal Parameters c (C(zero bias)) min 406.32f N/A
max 1.62528p N/A
VARDIOP_RF VARMIS_18_RF
Device Name c (Cmax) min VARDIOP_RF VARMIS_18_RF N/A 1.030819p Value Got from max N/A 5.154096p Value Got from
Calculation
Calculation
Device Name nf (Finger Number) min VARDIOP_RF VARMIS_18_RF 30 24
Value Got from Spectre model Spectre model
max 120 120
Value Got from Spectre model Spectre model
23.10 23.11
BIPOLAR FORMAL PARAMETERS DIODES FORMAL PARAMETERS
The bipolar devices have fixed layouts and do not have any formal editable parameters.
The diode devices have fixed layouts and do not have any formal editable parameters.
UMC Confidential
71 Ver. B04_PB
24 DEVICE DATASHEETS
24.1 N_18_MM 1.8 volt NMOS Transistor
Spectre Netlist Spectre Model Name = n_18_mm NM0 (D G S B) n_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_18_MM MNM0 D G S B N_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 +PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_18_MM ; N_18_MM Instance /NM0 = auLvs device M0 d N_18_MM D G S B (p D S) i 0 N_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_18_MM MMN0 D G S B N_18_MM W=2u L=180.0n M=1
UMC Confidential
72 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_18_MM C N_18_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_18_MM D G S B ; L 1.8e-07 W 2e-06 effW 2e-06 ; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
73 Ver. B04_PB
N_18_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS PO1 CONT ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS CONTAINS PO1 PO1 DIFF AND NPLUS NOT PO1 DIFF AND NPLUS NOT PO1 Substrate
LVS Comparison Parameter Length Width Calculation PO1 intersecting DIFF (illustrated above) PO1 inside DIFF (illustrated above)
UMC Confidential
74 Ver. B04_PB
UM180FDKMFC000000A_B * S and D are PERMUTABLE
UMC Confidential
75 Ver. B04_PB
24.2 P_18_MM 1.8 volt PMOS Transistor
Spectre Netlist Spectre Model Name = p_18_mm PM0 (D G S B) p_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = P_18_MM MPM0 D G S B P_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 +PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = P_18_MM ; P_18_MM Instance /PM0 = auLvs device M0 d P_18_MM D G S B (p D S) i 0 P_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = P_18_MM MPM0 D G S B P_18_MM W=2u L=180.0n M=1
UMC Confidential
76 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = P_18_MM c P_18_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MP0 P_18_MM D G S B ; W 2e-06 effW 2e-06 L 1.8e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
77 Ver. B04_PB
P_18_MM (diagrammatic layout)

Width
Length
Device Layers Layer NWEL DIFF PPLUS PO1 CONT ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation NWEL AND DIFF AND PPLUS CONTAINS PO1 PO1 NWEL AND DIFF AND PPLUS NOT PO1 NWEL AND DIFF AND PPLUS NOT PO1 NWEL
UMC Confidential
78 Ver. B04_PB
UMC Confidential
79 Ver. B04_PB
24.3 N_33_MM 3.3 volt NMOS Transistor
Spectre Netlist Spectre Model Name = n_33_mm NM0 (D G S B) n_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_33_MM MNM0 D G S B N_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 +PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_33_MM ; N_33_MM Instance /NM0 = auLvs device M0 d N_33_MM D G S B (p D S) i 0 N_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_33_MM MMN0 D G S B N_33_MM W=2u L=340.0n M=1
UMC Confidential
80 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_33_MM C N_33_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_33_MM D G S B ; W 2e-06 effW 2e-06 L 3.4e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
81 Ver. B04_PB
N_33_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS PO1 CONT TG ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND TG CONTAINS PO1 PO1 DIFF AND NPLUS AND TG NOT PO1 DIFF AND NPLUS AND TG NOT PO1 Substrate
UMC Confidential
82 Ver. B04_PB
UMC Confidential
83 Ver. B04_PB
24.4 P_33_MM 3.3 volt PMOS Transistor
Spectre Netlist Spectre Model Name = p_33_mm PM0 (D G S B) p_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = P_33_MM MPM0 D G S B P_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 +PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = P_33_MM ; P_33_MM Instance /PM0 = auLvs device M0 d P_33_MM D G S B (p D S) I 0 P_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = P_33_MM MPM0 D G S B P_33_MM W=2u L=340.0n M=1
UMC Confidential
84 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = P_33_MM c P_33_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MP0 P_33_MM D G S B ; effW 2e-06 L 3.4e-07 W 2e-06; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
85 Ver. B04_PB
P_33_MM (diagrammatic layout)

Width
Length
Device Layers Layer NWEL DIFF PPLUS TG PO1 CONT ME1 SYMBOL ( MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation NWEL AND DIFF AND PPLUS AND TG CONTAINS PO1 PO1 NWEL AND DIFF AND PPLUS AND TG NOT PO1 NWEL AND DIFF AND PPLUS AND TG NOT PO1 NWEL
UMC Confidential
86 Ver. B04_PB
LVS Comparison Parameter Length Width Calculation PO1 intersecting DIFF (illustrated above) PO1 inside DIFF (illustrated above) * S and D are PERMUTABLE
UMC Confidential
87 Ver. B04_PB
24.5 N_LV_18_MM 1.8 volt low vt NMOS Transistor
Spectre Netlist Spectre Model Name = n_lv_18_mm NM0 (D G S B) n_lv_18_mm w=2u l=240.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_LV_18_MM MNM0 D G S B N_LV_18_MM L=240E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_LV_18_MM ; N_LV_18_MM Instance /NM0 = auLvs device M0 d N_LV_18_MM D G S B (p D S) i 0 N_LV_18_MM D G S B " L 240e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_LV_18_MM MMN0 D G S B N_LV_18_MM W=2u L=240.0n M=1
UMC Confidential
88 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_LV_18_MM C N_LV_18_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_LV_18_MM D G S B ; W 2e-06 effW 2e-06 L 2.4e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
89 Ver. B04_PB
N_LV_18_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS PO1 CONT VT (VTNL) ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND VTNL CONTAINS PO1 PO1 DIFF AND NPLUS AND VTNL NOT PO1 DIFF AND NPLUS AND VTNL NOT PO1 Substrate
UMC Confidential
90 Ver. B04_PB
UM180FDKMFC000000A_B * PLUS and MINUS are PERMUTABLE
UMC Confidential
91 Ver. B04_PB
24.6 P_LV_18_MM 1.8 volt low vt PMOS Transistor
Spectre Netlist Spectre Model Name = p_lv_18_mm PM0 (D G S B) p_lv_18_mm w=2u l=240.0n as=980e-15 ad=980e-15 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = P_LV_18_MM MPM0 D G S B P_LV_18_MM L=240E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = P_LV_18_MM ; P_LV_18_MM Instance /PM0 = auLvs device M0 d P_LV_18_MM D G S B (p D S) i 0 P_LV_18_MM D G S B " L 240e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = P_LV_18_MM MPM0 D G S B P_LV_18_MM W=2u L=240.0n M=1
UMC Confidential
92 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = P_LV_18_MM c P_LV_18_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MP0 P_LV_18_MM D G S B ; W 2e-06 effW 2e-06 L 2.4e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
93 Ver. B04_PB
P_LV_18_MM (diagrammatic layout)

Width
Length
Device Layers Layer NWEL DIFF PPLUS VT (VTPL) PO1 CONT ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation NWEL AND DIFF AND PPLUS AND VTPL CONTAINS PO1 PO1 NWEL AND DIFF AND PPLUS AND VTPL NOT PO1 NWEL AND DIFF AND PPLUS AND VTPL NOT PO1 NWEL
UMC Confidential
94 Ver. B04_PB
LVS Comparison Parameter Length Width Calculation PO1 intersecting DIFF (illustrated above) PO1 inside DIFF (illustrated above) * PLUS and MINUS are PERMUTABLE
UMC Confidential
95 Ver. B04_PB
24.7 N_LV_33_MM 3.3 volt low vt NMOS Transistor
Spectre Netlist Spectre Model Name = n_lv_33_mm NM0 (D G S B) n_lv_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_LV_33_MM MNM0 D G S B N_LV_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_LV_33_MM ; N_LV_33_MM Instance /NM0 = auLvs device M0 d N_LV_33_MM D G S B (p D S) i 0 N_LV_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_LV_33_MM MMN0 D G S B N_LV_33_MM W=2u L=500.0n M=1
UMC Confidential
96 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_LV_33_MM C N_LV_33_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_LV_33_MM D G S B ; W 2e-06 effW 2e-06 L 5e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
97 Ver. B04_PB
N_LV_33_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS PO1 CONT VTNHL TG ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND TG AND VTNHL CONTAINS PO1 PO1 DIFF AND NPLUS AND TG AND VTNHL NOT PO1 DIFF AND NPLUS AND TG AND VTNHL NOT PO1 Substrate
UMC Confidential
98 Ver. B04_PB
UMC Confidential
99 Ver. B04_PB
24.8 P_LV_33_MM 3.3 volt low vt PMOS Transistor
Spectre Netlist Spectre Model Name = p_lv_33_mm PM0 (D G S B) p_lv_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = P_LV_33_MM MPM0 D G S B P_LV_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = P_LV_33_MM ; P_LV_33_MM Instance /PM0 = auLvs device M0 d P_LV_33_MM D G S B (p D S) I 0 P_LV_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = P_LV_33_MM MPM0 D G S B P_LV_33_MM W=2u L=500.0n M=1
UMC Confidential
100 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = P_LV_33_MM c P_LV_33_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MP0 P_LV_33_MM D G S B ; effW 2e-06 L 5e-07 W 2e-06; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
101 Ver. B04_PB
P_LV_33_MM (diagrammatic layout)

Width
Length
Device Layers Layer NWEL DIFF PPLUS VTPHL TG PO1 CONT ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation NWEL AND DIFF AND PPLUS AND TG AND VTPHL CONTAINS PO1 PO1 NWEL AND DIFF AND PPLUS AND TG AND VTPHL NOT PO1 NWEL AND DIFF AND PPLUS AND TG AND VTPHL NOT PO1 NWEL
UMC Confidential
102 Ver. B04_PB
UMC Confidential
103 Ver. B04_PB
24.9 N_ZERO_18_MM 1.8 volt zero vt NMOS transistor
Spectre Netlist Spectre Model Name = n_zero_18_mm NM0 (D G S B) n_zero_18_mm w=2u l=300.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_ZERO_18_MM MNM0 D G S B N_ZERO_18_MM L=300E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_ZERO_18_MM ; N_ZERO_18_MM Instance /NM0 = auLvs device M0 d N_ZERO_18_MM D G S B (p D S) i 0 N_ZERO_18_MM D G S B " L 300e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_ZERO_18_MM MMN0 D G S B N_ZERO_18_MM W=2u L=300.0n M=1
UMC Confidential
104 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_ZERO_18_MM C N_ZERO_18_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_ZERO_18_MM D G S B ; W 2e-06 effW 2e-06 L 3e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
105 Ver. B04_PB
N_ZERO_18_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS PO1 CONT VTNI ME1 SYMBOL ( MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND VTNI CONTAINS PO1 PO1 DIFF AND NPLUS AND VTNI NOT PO1 DIFF AND NPLUS AND VTNI NOT PO1 Substrate
UMC Confidential
106 Ver. B04_PB
UM180FDKMFC000000A_B PLUS and MINUS are PERMUTABLE
24.10
N_ZERO_33_MM 3.3 volt zero vt NMOS Transistor
Spectre Netlist Spectre Model Name = n_zero_33_mm NM0 (D G S B) n_zero_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_ZERO_33_MM MNM0 D G S B N_ZERO_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_ZERO_33_MM ; N_ZERO_33_MM Instance /NM0 = auLvs device M0 d N_ZERO_33_MM D G S B (p D S) i 0 N_ZERO_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_ZERO_33_MM MMN0 D G S B N_ZERO_33_MM W=2u L=500.0n M=1
UMC Confidential
107 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_ZERO_33_MM C N_ZERO_33_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_ZERO_33_MM D G S B ; W 2e-06 effW 2e-06 L 5e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
108 Ver. B04_PB
N_ZERO_33_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS PO1 CONT VT (VTNL) TG ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND TG AND VTNL CONTAINS PO1 PO1 DIFF AND NPLUS AND TG AND VTNL NOT PO1 DIFF AND NPLUS AND TG AND VTNL NOT PO1 Substrate
UMC Confidential
109 Ver. B04_PB
UMC Confidential
110 Ver. B04_PB
24.11 N_BPW_18_MM 1.8 volt triple-well NMOS Transistor
Spectre Netlist Spectre Model Name = n_bpw_18_mm NM0 (D G S B) n_bpw_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \ pd=4.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_BPW_18_MM MNM0 D G S B N_BPW_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_BPW_18_MM ; N_BPW_18_MM Instance /NM0 = auLvs device M0 d N_BPW_18_MM D G S B (p D S) i 0 N_BPW_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_BPW_18_MM MMN0 D G S B N_BPW_18_MM W=2u L=180.0n M=1
UMC Confidential
111 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_BPW_18_MM C N_BPW_18_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_BPW_18_MM D G S B ; W 2e-06 effW 2e-06 L 1.8e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
112 Ver. B04_PB
N_BPW_18_MM (diagrammatic layout)

Width
Length
Device Layers Layer NWEL DIFF NPLUS PO1 CONT TWEL ME1 SYMBOL ( MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND TWEL CONTAINS PO1 PO1 DIFF AND NPLUS AND TWEL NOT PO1 DIFF AND NPLUS AND TWEL NOT PO1 TWEL
UMC Confidential
113 Ver. B04_PB
* PLUS and MINUS are PERMUTABLE
UMC Confidential
114 Ver. B04_PB
24.12 N_BPW_33_MM 3.3 volt triple-well NMOS Transistor
Spectre Netlist Spectre Model Name = n_bpw_33_mm NM0 (D G S B) n_bpw_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \ pd=5.28u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_BPW_33_MM MNM0 D G S B N_BPW_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00
DIVA LVS Netlist DIVA Device Name = N_BPW_33_MM ; N_BPW_33_MM Instance /NM0 = auLvs device M0 d N_BPW_33_MM D G S B (p D S) i 0 N_BPW_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "
CDL Netlist CDL Device Name = N_BPW_33_MM MMN0 D G S B N_BPW_33_MM W=2u L=340.0n M=1
UMC Confidential
115 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_BPW_33_MM C N_BPW_33_MM MOS DRAIN B * 4 pins * 4 nets * 0 instances i MN0 N_BPW_33_MM D G S B ; W 2e-06 effW 2e-06 L 3.4e-07; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
116 Ver. B04_PB
N_BPW_33_MM (diagrammatic layout)

Width
Length
Device Layers Layer NWEL DIFF NPLUS PO1 CONT TWEL TG ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND TG AND TWEL CONTAINS PO1 PO1 DIFF AND NPLUS AND TG AND TWEL NOT PO1 DIFF AND NPLUS AND TG AND TWEL NOT PO1 TWEL
UMC Confidential
117 Ver. B04_PB
UMC Confidential
118 Ver. B04_PB
24.13
RSPD_MM P+ diffused resistor w/ salicide
NOTE: Dog-bone configurations are permitted. NOTE: If: 0.24um <= width <= 0.43um then 0.48um <= length <=1000um Else if: 0.43um < width <=20um then 0.42um <= length <=1000um Spectre Netlist Spectre Model Name = rspd_mm R0 (PLUS MINUS B) rspd_mm lr=9.32u wr=440.0n
HspiceS Netlist HspiceS Model Name = RSPD_MM XR0 PLUS MINUS B RSPD_MM LR=9.32E-6 WR=440E-9
DIVA LVS Netlist DIVA Device Name = RSPD_MM ; RSPD_MM Instance /R0 = auLvs device R0 d RSPD_MM PLUS MINUS B (p PLUS MINUS)
UMC Confidential
119 Ver. B04_PB
UM180FDKMFC000000A_B i 0 RSPD_MM PLUS MINUS B " R 169.455 L 9.32e-6 W 440e-9 "
CDL Netlist CDL Device Name = RSPD_MM RR0 PLUS MINUS 169.455 $SUB=B $[RSPD_MM] $W=440.0n $L=9.32u Assura Netlist Assura auLvs Device Name = RSPD_MM c RSPD_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RSPD_MM PLUS MINUS B; L 9.32e-06 lSim 9.32e-06 lTot 9.32e-06 W 4.4e-07 wSim 4.4e-07 R 169.455; OUT B SUBSTRATE B ;;
UMC Confidential
120 Ver. B04_PB
RSPD_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF PPLUS RSYMBOL CONT ME1 SYMBOL (MMSYMBOL) NWEL Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation DIFF AND PPLUS AND RSYMBOL DIFF NOT RSYMBOL DIFF NOT RSYMBOL NWEL
LVS Comparison Parameter Length Width Calculation CONT to CONT (illustrated above) DIFF Width (illustrated above) * PLUS and MINUS are PERMUTABLE
UMC Confidential
121 Ver. B04_PB
24.14
RSND_MM N+ diffused resistor w/ salicide
NOTE: Dog-bone configurations are permitted. NOTE: If: 0.24um <= width <= 0.43um then 0.48um <= length <=1000um Else if: 0.43um < width <=20um then 0.42um <= length <=1000um
Spectre Netlist Spectre Model Name = rsnd_mm R0 (PLUS MINUS B) rsnd_mm lr=9.32u wr=440.0n
HspiceS Netlist HspiceS Model Name = RSND_MM XR0 PLUS MINUS B RSND_MM LR=9.32E-6 WR=440E-9
DIVA LVS Netlist DIVA Device Name = RSND_MM ; RSND_MM Instance /R0 = auLvs device R0 d RSND PLUS MINUS B (p PLUS MINUS)
UMC Confidential
122 Ver. B04_PB
UM180FDKMFC000000A_B i 0 RSND_MM PLUS MINUS B " R 169.455 L 9.32e-6 W 440e-9 "
CDL Netlist CDL Device Name = RSND_MM RR0 PLUS MINUS 169.455 $SUB=B $[RSND_MM] $W=440.0n $L=9.32u
Assura Netlist Assura auLvs Device Name = RSND_MM c RSND_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RSND_MM PLUS MINUS B; R 169.455 L 9.32e-06 lSim 9.32e-06 lTot 9.32e-06 W 4.4e-07 wSim 4.4e-07 ; OUT B SUBSTRATE B ;;
UMC Confidential
123 Ver. B04_PB
RSND_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS RSYMBOL CONT ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation DIFF AND NPLUS AND RSYMBOL DIFF NOT RSYMBOL DIFF NOT RSYMBOL Substrate
LVS Comparison Parameter Length Width Calculation CONT to CONT (illustrated above) DIFF Width (illustrated above) * PLUS and MINUS are PERMUTABLE
UMC Confidential
124 Ver. B04_PB
24.15
RNPPO_MM P+ Poly resistor w/o salicide
Spectre Netlist Spectre Model Name = rnppo_mm R0 (PLUS MINUS B) rnppo_mm lr=8.32u wr=440.0n
HspiceS Netlist HspiceS Model Name = RNPPO_MM XR0 PLUS MINUS B RNPPO_MM LR=8.32E-6 WR=440E-9
DIVA LVS Netlist DIVA Device Name = RNPPO_MM ; RNPPO_MM Instance /R0 = auLvs device R0 d RNPPO_MM PLUS MINUS B (p PLUS MINUS) i 0 RNPPO_MM PLUS MINUS B " R 7.96609e3 L 8.32e-6 W 440e-9 "
CDL Netlist CDL Device Name = RNPPO_MM
UMC Confidential
125 Ver. B04_PB
UM180FDKMFC000000A_B RR0 PLUS MINUS 7.96609K $SUB=B $[RNPPO_MM] $W=440.0n $L=8.32u
Assura Netlist Assura auLvs Device Name = RNPPO_MM c RNPPO_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RNPPO_MM PLUS MINUS B; R 7.96609e3 L 8.32e-06 lSim 8.32e-06 lTot 8.32e-06 W 4.4e-07 wSim 4.4e-07 ; OUT B SUBSTRATE B ;;
UMC Confidential
126 Ver. B04_PB
RNPPO_MM (diagrammatic layout)

Width
Length
Device Layers Layer PO1 PPLUS PSYMBOL CONT ME1 SYMBOL (MMSYMBOL) NWEL SAB Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation PO1 AND PPLUS AND PSYMBOL AND SAB PO1 NOT PSYMBOL PO1 NOT PSYMBOL NWEL
LVS Comparison Parameter Length Width Calculation SAB length (illustrated above) PO1 Width (illustrated above)
UMC Confidential
127 Ver. B04_PB
24.16
RNNPO_MM N+ Poly resistor w/o salicide
Spectre Netlist Spectre Model Name = rnnpo_mm R0 (PLUS MINUS B) rnnpo_mm lr=8.32u wr=440.0n
HspiceS Netlist HspiceS Model Name = RNNPO_MM XR0 PLUS MINUS B RNNPO_MM LR=8.32E-6 WR=440E-9
DIVA LVS Netlist DIVA Device Name = RNNPO_MM ; RNNPO_MM Instance /R0 = auLvs device R0 d RNNPO_MM PLUS MINUS B (p PLUS MINUS) i 0 RNNPO_MM PLUS MINUS B " R 2.84012e3 L 8.32e-6 W 440e-9 "
CDL Netlist CDL Device Name = RNNPO_MM
UMC Confidential
128 Ver. B04_PB
UM180FDKMFC000000A_B RR0 PLUS MINUS 2.84012K $SUB=B $[RNNPO_MM] $W=440.0n $L=8.32u
Assura Netlist Assura auLvs Device Name = RNNPO_MM c RNNPO_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RNNPO_MM PLUS MINUS B; R 2.84012e3 L 8.32e-06 lSim 8.32e-06 lTot 8.32e-06 W 4.4e-07 wSim 4.4e-07 ; OUT B SUBSTRATE B ;;
UMC Confidential
129 Ver. B04_PB
RNNPO_MM (diagrammatic layout)

Width
Length
Device Layers Layer PO1 NPLUS PSYMBOL CONT ME1 SYMBOL (MMSYMBOL) SAB Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation PO1 AND NPLUS AND PSYMBOL AND SAB PO1 NOT PSYMBOL PO1 NOT PSYMBOL Substrate
LVS Comparison Parameter Length Width Calculation SAB length (illustrated above) PO1 Width (illustrated above)

24.17
RSNWELL_MM N-Well Resistor
Spectre Netlist Spectre Model Name = rsnwell_mm R0 (PLUS MINUS B) rsnwell_mm lr=8.64u wr=1.5u
HspiceS Netlist HspiceS Model Name = RSNWELL_MM XR0 PLUS MINUS B RSNWELL_MM LR=8.64E-6 WR=1.5E-6
DIVA LVS Netlist DIVA Device Name = RSNWELL_MM ; RSNWELL_MM Instance /R0 = auLvs device R0 d RSNWELL_MM PLUS MINUS B (p PLUS MINUS) i 0 RSNWELL_MM PLUS MINUS B " R 3.03864e3 L 8.64e-6 W 1.5e-6 "
CDL Netlist CDL Device Name = RSNWELL_MM
UMC Confidential
131 Ver. B04_PB
UM180FDKMFC000000A_B RR0 PLUS MINUS 3.03864K $SUB=B $[RSNWELL_MM] $W=1.5u $L=8.64u
Assura Netlist Assura auLvs Device Name = RSNWELL_MM c RSNWELL_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RSNWELL_MM PLUS MINUS B; R 3.03864e3 L 8.64e-06 lSim 8.16e-06 lTot 8.64e-06 W 1.5e-06 wSim 1.5e-06 ; OUT B SUBSTRATE B ;;
UMC Confidential
132 Ver. B04_PB
RSNWELL_MM (diagrammatic layout)

Width
Length
Device Layers Layer DIFF NPLUS NWR CONT ME1 SYMBOL (MMSYMBOL) NWEL Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation NWEL AND NPLUS AND NWR NWEL NOT NWR NWEL NOT NWR Substrate
LVS Comparison Parameter Length Width Calculation DIFF to DIFF (illustrated above) NWEL Width (illustrated above)
UMC Confidential
133 Ver. B04_PB
24.18
RNHR1000_MM High Resistive Poly Resistor
Spectre Netlist Spectre Model Name = rnhr1000_mm R0 (PLUS MINUS B) rnhr1000_mm lr=8.32u wr=440.0n
HspiceS Netlist HspiceS Model Name = RNHR1000_MM XR0 PLUS MINUS B RNHR1000_MM LR=8.32E-6 WR=440E-9
DIVA LVS Netlist DIVA Device Name = RNHR1000_MM ; RNHR1000_MM Instance /R0 = auLvs device R0 d RNHR1000_MM PLUS MINUS B (p PLUS MINUS) i 0 RNHR1000_MM PLUS MINUS B " R 21.3322e3 L 8.32e-6 W 440e-9 "
CDL Netlist CDL Device Name = RNHR1000_MM RR0 PLUS MINUS 21.3322K $SUB=B $[RNHR1000_MM] $W=440e-9 $L=8.32u
UMC Confidential
134 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = RNHR1000_MM c RNHR1000_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RNHR1000_MM PLUS MINUS B; R 21.3322e3 L 8.32e-06 lSim 8.32e-06 lTot 8.32e-06 W 4.4e-07 wSim 4.4e-09 ; OUT B SUBSTRATE B ;;
UMC Confidential
135 Ver. B04_PB
RNHR1000_MM (diagrammatic layout)

Width
Length
Device Layers Layer PPLUS HR PSYMBOL CONT ME1 SYMBOL (MMSYMBOL) PO1 NWEL SAB Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation PO1 AND HR AND PSYMBOL AND SAB PO1 NOT PSYMBOL PO1 NOT PSYMBOL NWEL
LVS Comparison Parameter Length Calculation SAB length (illustrated above)
PO1 Width (illustrated above) Width * PLUS and MINUS are PERMUTABLE
24.19
RNND_MM N+ diffused Resistor w/o salicide
Spectre Netlist Spectre Model Name = rnnd_mm R0 (PLUS MINUS B) rnnd_mm lr=8.56u wr=440.0n
HspiceS Netlist HspiceS Model Name = RNND_MM XR0 PLUS MINUS B RNND_MM LR=8.56E-6 WR=440E-9
DIVA LVS Netlist DIVA Device Name = RNND_MM ; RNND_MM Instance /R0 = auLvs device R0 d RNND_MM PLUS MINUS B (p PLUS MINUS) i 0 RNND_MM PLUS MINUS B " R 1.34936e3 L 8.56e-6 W 440e-9 "
CDL Netlist CDL Device Name = RNND_MM RR0 PLUS MINUS 1.34936K $SUB=B $[RNND_MM] $W=440e-9 $L=8.56u
UMC Confidential
137 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = RNND_MM c RNND_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RNND_MM PLUS MINUS B; R 1.34936e3 L 8.56e-06 lSim 8.56e-06 lTot 8.56e-06 W 4.4e-07 wSim 4.4e-09 ; OUT B SUBSTRATE B ;;
UMC Confidential
138 Ver. B04_PB
RNND_MM (diagrammatic layout)

Width
Length
Device Layers Layer SAB NPLUS DIFF CONT ME1 SYMBOL (MMSYMBOL) RSYMBOL Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation NPLUS AND DIFF AND RSYMBOL AND SAB DIFF NOT RSYMBOL DIFF NOT RSYMBOL Substrate
LVS Comparison Parameter Length Width Calculation SAB length (illustrated above) DIFF Width (illustrated above)

24.20
RNPD_MM P+ diffused Resistor w/o salicide
Spectre Netlist Spectre Model Name = rnpd_mm R0 (PLUS MINUS B) rnpd_mm lr=8.56u wr=440.0n
HspiceS Netlist HspiceS Model Name = RNPD_MM XR0 PLUS MINUS B RNPD_MM LR=8.56E-6 WR=440E-9
DIVA LVS Netlist DIVA Device Name = RNPD_MM ; RNPD_MM Instance /R0 = auLvs device R0 d RNPD_MM PLUS MINUS B (p PLUS MINUS) i 0 RNPD_MM PLUS MINUS B " R 2.5771e3 L 8.56e-6 W 440e-9 "
CDL Netlist CDL Device Name = RNPD_MM RR0 PLUS MINUS 2.5771K $SUB=B $[RNPD_MM] $W=440e-9 $L=8.56u
Assura Netlist Assura auLvs Device Name = RNPD_MM c RNPD_MM RES IN B * 3 pins * 3 nets * 0 instances i R0 RNPD_MM PLUS MINUS B; R 2.5771e3 L 8.56e-06 lSim 8.56e-06 lTot 8.56e-06 W 4.4e-07 wSim 4.4e-09 ; OUT B SUBSTRATE B ;;
UMC Confidential
141 Ver. B04_PB
RNPD_MM (diagrammatic layout)

Width
Length
Device Layers Layer SAB PPLUS DIFF NWEL CONT ME1 SYMBOL (MMSYMBOL) RSYMBOL Color and Fill
Device Derivation Device Recognition PLUS MINUS B Layer Derivation PPLUS AND DIFF AND RSYMBOL AND SAB DIFF NOT RSYMBOL DIFF NOT RSYMBOL NWEL
LVS Comparison Parameter Length Width Calculation SAB length (illustrated above) DIFF Width (illustrated above)
UMC Confidential
142 Ver. B04_PB
24.21
RM1_MM Metal 1 Resistor
Spectre Netlist Spectre Model Name = rm1_mm R0 (PLUS MINUS) rm1_mm lr=740.0n wr=420.0n
HspiceS Netlist HspiceS Model Name = RM1_MM XR0 PLUS MINUS RM1_MM LR=740E-9 WR=420E-9
DIVA LVS Netlist DIVA Device Name = RM1_MM ; RM1_MM Instance /R0 = auLvs device R0 d RM1_MM PLUS MINUS (p PLUS MINUS) i 0 RM1_MM PLUS MINUS " R 135.667e-3 L 740e-9 W 420e-9 "
CDL Netlist CDL Device Name = RM1_ MM RR0 PLUS MINUS 135.667m $[RM1_MM] $W=420.0n $L=740.0n
UMC Confidential
143 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = RM1_MM c RM1_MM RES IN B * 2 pins * 2 nets * 0 instances i R0 RM1_ MM PLUS MINUS; L 7.40e-07 W 4.2e-07 R 0.135667; OUT B;;
UMC Confidential
144 Ver. B04_PB
RM1_MM (diagrammatic layout)

width length
Device Layers Layer ME1 M1_CAD (Resistor_Mark) Color and Fill
Device Derivation Device Recognition PLUS MINUS Layer Derivation ME1 AND M1_CAD (Resistor_Mark) ME1 ME1
LVS Comparison Parameter Length Width Calculation M1_CAD (Resistor_Mark) length (illustrated above) M1_CAD (Resistor_Mark) Width (illustrated above)
UMC Confidential
145 Ver. B04_PB
24.22
CDL Netlist CDL Device Name = RM2_MM RR0 PLUS MINUS 98.6363m $[RM2_MM] $W=440.0n $L=700.0n
UMC Confidential
146 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = RM2_MM c RM2_MM RES IN B * 2 pins * 2 nets * 0 instances i R0 RM2_MM PLUS MINUS; L 7.00e-07 W 4.4e-07 R 0.00986363; OUT B;;
UMC Confidential
147 Ver. B04_PB

width length
UMC Confidential
148 Ver. B04_PB
24.23
UMC Confidential
149 Ver. B04_PB
UMC Confidential
150 Ver. B04_PB

width length
UMC Confidential
151 Ver. B04_PB
24.24
DIVA LVS Netlist DIVA Device Name = RM4_MM ; RM4_MM Instance /R0 = auLvs device R0 d RM4_MM PLUS MINUS (p PLUS MINUS) i 0 RM4_MM PLUS MINUS " R 98.6363m L 700e-9 W 440e-9 "
UMC Confidential
152 Ver. B04_PB
UMC Confidential
153 Ver. B04_PB

width length
UMC Confidential
154 Ver. B04_PB
24.25
UMC Confidential
155 Ver. B04_PB
UMC Confidential
156 Ver. B04_PB

width length
LVS Comparison Parameter Length Width Calculation M5_CAD (Resistor_Mark) length (illustrated above) M5_CAD (Resistor_Mark) (illustrated above)
UMC Confidential
157 Ver. B04_PB
24.26
RM6_MM Metal 6 Resistor (20KA)
Spectre Netlist Spectre Model Name = rm6_mm R0 (PLUS MINUS) rm6_mm lr=7.5u wr=1.2u
HspiceS Netlist HspiceS Model Name = RM6_MM XR0 PLUS MINUS RM6_MM LR=7.5E-6 WR=1.2E-6
DIVA LVS Netlist DIVA Device Name = RM6_MM ; RM6_MM Instance /R0 = auLvs device R0 d RM6_MM PLUS MINUS (p PLUS MINUS) i 0 RM6_MM PLUS MINUS " R 125.000e-3 L 7.5e-6 W 1.2e-6 "
CDL Netlist CDL Device Name = RM6_MM RR0 PLUS MINUS 125.000m $[RM6_MM] $W=1.2u $L=7.5u
UMC Confidential
158 Ver. B04_PB
UMC Confidential
159 Ver. B04_PB

width length
UMC Confidential
160 Ver. B04_PB
24.27 NCAP_MM NMOS Transistor configured as a Capacitor
Spectre Netlist Spectre Model Name = n_18_mm C0 (D G S B) n_18_mm w=10u l=10u as=4.9e-12 ad=4.9e-12 ps=20.98u pd=20.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = N_18_MM MC0 D G S B N_18_MM W=10E-6 L=10E-6 AS=4.9E-12 PD=20.98E-6 +PS=20.98E-6 M=+1.000000000E+00
DIVA LVS Netlist DIVA Device Name = NCAP_MM ; NCAP_MM Instance /C0 = auLvs device C0 d N_18_MM D G S B i 0 N_18_MM D G S B" M 1.0 L 10e-6 W 10e-6 "
CDL Netlist CDL Device Name = N_18_MM
UMC Confidential
161 Ver. B04_PB
UM180FDKMFC000000A_B MC0 D G S B N_18_MM W=10u L=10u M=1
Assura Netlist Assura auLvs Device Name = NCAP_MM c NCAP_MM CAP DRAIN B * 3 pins * 3 nets * 0 instances i C0 N_18_MM D G S B ; np 4e-05 W 1e-05 effW 1e-05 c 8.28336e-13 L 1e-05 na 1e-10; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
162 Ver. B04_PB
NCAP_MM (diagrammatic layout)

Width
Length
Device Layers Layer SYMBOL (CSYMBOL) DIFF NPLUS PO1 CONT ME1 SYMBOL (MMSYMBOL) Color and Fill
Device Derivation Device Recognition TOP BOT B Layer Derivation CSYMBOL AND DIFF AND NPLUS CONTAINS PO1 PO1 CSYMBOL AND DIFF AND NPLUS NOT PO1 Substrate
UMC Confidential
163 Ver. B04_PB
24.28 PCAP_MM PMOS Transistor configured as a Capacitor
Spectre Netlist Spectre Model Name = p_18_mm C0 (D G S B) p_18_mm w=10u l=10u as=4.9e-12 ad=4.9e-12 ps=20.98u pd=20.98u m=(1)*(1)
HspiceS Netlist HspiceS Model Name = P_18_MM MC0 D G S B P_18_MM W=10E-6 L=10E-6 AS=4.9E-12 PD=20.98E-6 +PS=20.98E-6 M=+1.000000000E+00
DIVA LVS Netlist DIVA Device Name = PCAP_MM ; PCAP_MM Instance /C0 = auLvs device C0 d P_18_MM D G S B i 0 P_18_MM D G S B" M 1.0 L 10e-6 W 10e-6 "
CDL Netlist CDL Device Name = P_18_MM
UMC Confidential
164 Ver. B04_PB
UM180FDKMFC000000A_B MC0 D G S B P_18_MM W=10u L=10u M=1
Assura Netlist Assura auLvs Device Name = PCAP_MM c PCAP_MM CAP DRAIN B * 3 pins * 3 nets * 0 instances i C0 P_18_MM D G S B ; np 4e-05 W 1e-05 effW 1e-05 c 8.28336e-13 L 1e-05 na 1e-10; GATE B SOURCE B SUBSTRATE B ;;
UMC Confidential
165 Ver. B04_PB
PCAP_MM (diagrammatic layout)

Width
Length
Device Layers Layer SYMBOL (CSYMBOL) DIFF PPLUS PO1 CONT ME1 SYMBOL (MMSYMBOL) NWEL Color and Fill
Device Derivation Device Recognition TOP BOT B Layer Derivation CSYMBOL AND DIFF AND PPLUS CONTAINS PO1 PO1 CSYMBOL AND DIFF AND PPLUS NOT PO1 NWEL
UMC Confidential
166 Ver. B04_PB
24.29 MIMCAPS_MM Single-squared Mixed-Mode Metal Capacitor
Spectre Netlist Spectre Model Name = mimcaps_mm C0 (PLUS MINUS) mimcaps_mm w=10u l=10u m=1
HspiceS Netlist HspiceS Model Name = MIMCAPS_MM XC0 PLUS MINUS MIMCAPS_MM W=10E-6 L=10E-6 M=1.0
DIVA LVS Netlist DIVA Device Name = MIMCAPS_MM ; MIMCAPS_MM Instance /C0 = auLvs device C0 d MIMCAPS_MM PLUS MINUS i 0 MIMCAPS_MM PLUS MINUS" l 10e-6 w 10e-6 M 1.0 C 103e-15 "
CDL Netlist CDL Device Name = MIMCAPS_MM CC0 PLUS MINUS 103.00f $[MIMCAPS_MM]
UMC Confidential
167 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = MIMCAPS_MM c MIMCAPS_MM CAP POS B * 2 pins * 2 nets * 0 instances i C0 MIMCAPS_MM PLUS MINUS ; w 1e-05 C 1.03e-13 l 1e-05; MINUS B;;
UMC Confidential
168 Ver. B04_PB
MIMCAPS_MM (diagrammatic layout)

Length Width Device Layers Layer MMC SYMBOL (CSYMBOL) VI5 ME6 SYMBOL (MMSYMBOL) ME5 Color and Fill Device Derivation Device Recognition PLUS MINUS Layer Derivation CSYMBOL AND MMC ME6 AND ME5 AND MMC ME6 AND ME5 NOT MMC LVS Comparison Parameter Length Width Calculation MMC Length (illustrated above) MMC Width (illustrated above)
169 Ver. B04_PB
UMC Confidential
24.30 PNP_V50X50_MM CMOS vertical substrate PNP (5x5)
Spectre Netlist Spectre Model Name = pnp_v50x50_mm Q0 (C B E) pnp_v50x50_mm m=1
HspiceS Netlist HspiceS Model Name = PNP_V50X50_MM Q0 C B E PNP_V50X50_MM M=1.0
DIVA LVS Netlist DIVA Device Name = PNP_V50X50_MM ; PNP_V50X50_MM Instance /Q0 = auLvs device Q0 d PNP_V50X50_MM C B E i 0 PNP_V50X50_MM C B E" M 1.0 EA 25e-12"
CDL Netlist CDL Device Name = PNP_V50X50_MM QQ0 C B E PNP_V50X50_MM M=1 $EA=2.5e-11
UMC Confidential
170 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = PNP_V50X50_MM c PNP_V50X50_MM BJT COLLECTOR B * 3 pins * 3 nets * 0 instances i Q0 PNP_V50X50_MM C B E ; model PNP_V50X50_MM EA 2.5e-11; BASE B EMITTER B ;;
UMC Confidential
171 Ver. B04_PB
PNP_V50X50_MM (diagrammatic layout)
C E Area B
Device Layers Layer DIFF ME1 CONT NPLUS PPLUS NWEL SYMBOL (MMSYMBOL) SIZE (SIZE1) SYMBOL (BJTSYMBOL) Color and Fill
UMC Confidential
172 Ver. B04_PB
Device Derivation Device Recognition C B E Layer Derivation BJTSYMBOL AND SIZE1 BJTSYMBOL AND PPLUS AND DIFF NOT NWEL BJTSYMBOL AND NPLUS AND DIFF AND NWEL BJTSYMBOL AND PPLUS AND DIFF AND NWEL
LVS Comparison Parameter Area Calculation Area of DIFF emitter (illustrated above)
UMC Confidential
173 Ver. B04_PB
24.31 PNP_V100X100_MM CMOS vertical substrate PNP (10x10)
Spectre Netlist Spectre Model Name = pnp_v100x100_mm Q0 (C B E) pnp_v100x100_mm m=1
HspiceS Netlist HspiceS Model Name = PNP_V100X100_MM Q0 C B E PNP_V100X100_MM M=1.0
DIVA LVS Netlist DIVA Device Name = PNP_V100X100_MM ; PNP_V100X100_MM Instance /Q0 = auLvs device Q0 d PNP_V100X100_MM C B E i 0 PNP_V100X100_MM C B E" M 1.0 EA 100e-12"
CDL Netlist CDL Device Name = PNP_V100X100_MM QQ0 C B E PNP_V100X100_MM M=1 $EA=10e-11
UMC Confidential
174 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = PNP_V100X100_MM c PNP_V100X100_MM BJT COLLECTOR B * 3 pins * 3 nets * 0 instances i Q0 PNP_V100X100_MM C B E ; model PNP_V100X100_MM EA 10e-11 BASE B EMITTER B ;;
UMC Confidential
175 Ver. B04_PB
PNP_V100X100_MM (diagrammatic layout)
C E Area B
Device Layers Layer DIFF ME1 CONT NPLUS PPLUS NWEL SYMBOL (MMSYMBOL) SIZE (SIZE2) SYMBOL (BJTSYMBOL) Color and Fill
UMC Confidential
176 Ver. B04_PB
Device Derivation Device Recognition C B E Layer Derivation BJTSYMBOL AND SIZE2 BJTSYMBOL AND PPLUS AND DIFF NOT NWEL BJTSYMBOL AND NPLUS AND DIFF AND NWEL BJTSYMBOL AND PPLUS AND DIFF AND NWEL
LVS Comparison Parameter Area Calculation Area of DIFF emitter (illustrated above)
UMC Confidential
177 Ver. B04_PB
24.32
DION_MM N+/psub diode
Spectre Netlist Spectre Model Name = dion_mm D0 (PLUS MINUS) dion_mm area=8e-09 pj=0.00036 m=1
HspiceS Netlist HspiceS Model Name = DION_MM D0 PLUS MINUS DION_MM AREA=8E-9 PJ=360E-6 W=80E-6 L=100E-6 M=1.0
DIVA LVS Netlist DIVA Device Name = DION_MM ; DION_MM Instance /D0 = auLvs device D0 d DION_MM PLUS MINUS i 0 DION_MM PLUS MINUS" AREA 8e-9 PJ 360e-6 M 1.0"
CDL Netlist CDL Device Name = DION_MM DD0 PLUS MINUS DION_MM 8e-09 0.00036
UMC Confidential
178 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = DION_MM c DION_MM DIO POS B * 2 pins * 2 nets * 0 instances i D0 DION_MM PLUS MINUS ; PJ 0.00036 AREA 8e-09; MINUS B ;;
UMC Confidential
179 Ver. B04_PB
DION_MM (diagrammatic layout)

plus minus
Area
Device Layers Layer DIFF ME1 CONT NPLUS PPLUS SYMBOL (MMSYMBOL) SYMBOL (DIOBLK) Color and Fill
Device Derivation Device Recognition Layer Derivation (NPLUS AND DIFF) INTERACT MMSYMBOL NOT INTERACT (PO1 OR RSYMBOL) NOT BJTSYMBOL PPLUS AND DIFF NPLUS AND DIFF
PLUS MINUS
UMC Confidential
180 Ver. B04_PB
LVS Comparison Parameter Area Calculation Area of DIFF MINUS (illustrated above)
UMC Confidential
181 Ver. B04_PB
24.33
DIONW_MM Nwell/psub diode
Spectre Netlist Spectre Model Name = dionw_mm D0 (PLUS MINUS) dionw_mm area=9.72e-08 pj=0.00234 m=1
HspiceS Netlist HspiceS Model Name = DIONW_MM D0 PLUS MINUS DIONW_MM AREA=9.72E-8 PJ=234E-5 W=90E-6 L=1080E-6 M=1.0
DIVA LVS Netlist DIVA Device Name = DIONW_MM ; DIONW_MM Instance /D0 = auLvs device D0 d DIONW_MM PLUS MINUS i 0 DIONW_MM PLUS MINUS" AREA 9.72e-8 PJ 234e-5 M 1.0"
CDL Netlist CDL Device Name = DIONW_MM DD0 PLUS MINUS DIONW_MM 9.72e-08 0.00234
UMC Confidential
182 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = DIONW_MM c DIONW_MM DIO POS B * 2 pins * 2 nets * 0 instances i D0 DIONW_MM PLUS MINUS ; PJ 0.00234 AREA 9.72e-08; MINUS B ;;
UMC Confidential
183 Ver. B04_PB
DIONW_MM (diagrammatic layout)

plus minus
Area
Device Layers Layer DIFF ME1 CONT NWELL NPLUS PPLUS SYMBOL (MMSYMBOL) SYMBOL (DIOBLK & DSYMBOL) Color and Fill
Device Derivation Device Recognition Layer Derivation (NPLUS AND DIFF) INTERACT (NWELL AND MMSYMBOL) NOT INTERACT (PO1 OR RSYMBOL) NOT BJTSYMBOL PPLUS AND DIFF
184 Ver. B04_PB
PLUS
UMC Confidential
UM180FDKMFC000000A_B MINUS NWELL AND NPLUS AND DIFF
LVS Comparison Parameter Area Calculation Area of NWELL MINUS (illustrated above)
UMC Confidential
185 Ver. B04_PB
24.34
DIOP_MM P+/nwell diode
Spectre Netlist Spectre Model Name = diop_mm D0 (PLUS MINUS) diop_mm area=8e-09 pj=0.00036 m=1
HspiceS Netlist HspiceS Model Name = DIOP_MM D0 PLUS MINUS DIOP_MM AREA=8E-9 PJ=360E-6 W=80E-6 L=100E-6 M=1.0
DIVA LVS Netlist DIVA Device Name = DIOP_MM ; DIOP_MM Instance /D0 = auLvs device D0 d DIOP_MM PLUS MINUS i 0 DIOP_MM PLUS MINUS" AREA 8e-9 PJ 360e-6 M 1.0"
CDL Netlist CDL Device Name = DIOP_MM DD0 PLUS MINUS DIOP_MM 8e-09 0.00036
UMC Confidential
186 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = DIOP_MM c DIOP_MM DIO POS B * 2 pins * 2 nets * 0 instances i D0 DIOP_MM PLUS MINUS ; PJ 0.00036 AREA 8e-09; MINUS B ;;
UMC Confidential
187 Ver. B04_PB
DIOP_MM (diagrammatic layout)

minus plus
Area
Device Layers Layer DIFF ME1 CONT NPLUS PPLUS NWEL SYMBOL (MMSYMBOL) SYMBOL (DIOBLK) Color and Fill
Device Derivation Device Recognition Layer Derivation (PPLUS AND DIFF AND NWEL) INTERACT MMSYMBOL NOT INTERACT (PO1 OR RSYMBOL) NOT (BJTSYMBOL OR CSYMBOL) PPLUS AND DIFF NPLUS AND DIFF
PLUS MINUS
UMC Confidential
188 Ver. B04_PB
LVS Comparison Parameter Area Calculation Area of DIFF PLUS (illustrated above)
UMC Confidential
189 Ver. B04_PB
24.35 N_L18W500_18_RF 1.8 volt variable finger RF NMOS transistor
Spectre Netlist Spectre Model Name = n_l18w500_18_rf NM0 (D G S B) n_l18w500_18_rf nf=5
HspiceS Netlist HspiceS Model Name = N_L18W500_18_RF XNM0 D G S B N_L18W500_18_RF NF=5.0
DIVA LVS Netlist DIVA Device Name = N_L18W500_18_RF ; N_L18W500_18_RF Instance /NM0 = auLvs device M0 d N_L18W500_18_RF D G S B (p D S) i 0 N_L18W500_18_RF D G S B " nf 5.0 L 180e-9 W 5e-6 M 5.0"
CDL Netlist CDL Device Name = N_L18W500_18_RF MMN0 D G S B N_L18W500_18_RF W=5u L=180.0n M=5
UMC Confidential
190 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_L18W500_18_RF C N_L18W500_18_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MN0 N_L18W500_18_RF D G S B ; L 1.8e-07 W 5e-06 Nf 5 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
191 Ver. B04_PB
N_L18W500_18_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF NPLUS PPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 ME6 SYMBOL (RFMOS_S) Color and Fill
192 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B SYMBOL (RFSYMBOL), SIZE(SIZE2)
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND RFSYMBOL AND SIZE2 CONTAINS PO1 PO1 DIFF AND NPLUS NOT (PO1 OR RFMOS_S) DIFF AND NPLUS AND RFMOS_S NOT PO1 Substrate
UMC Confidential
193 Ver. B04_PB
24.36 N_L34W500_33_RF 3.3 volt variable finger RF NMOS transistor
Spectre Netlist Spectre Model Name = n_l34w500_33_rf NM0 (D G S B) n_l34w500_33_rf nf=5
HspiceS Netlist HspiceS Model Name = N_L34W500_33_RF XNM0 D G S B N_L34W500_33_RF NF=5.0
DIVA LVS Netlist DIVA Device Name = N_L34W500_33_RF ; N_L34W500_33_RF Instance /NM0 = auLvs device M0 d N_L34W500_33_RF D G S B (p D S) i 0 N_L34W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 5.0"
CDL Netlist CDL Device Name = N_L34W500_33_RF MMN0 D G S B N_L34W500_33_RF W=5u L=340.0n M=5
UMC Confidential
194 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_L34W500_33_RF C N_L34W500_33_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MN0 N_L34W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 5 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
195 Ver. B04_PB
N_L34W500_33_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF NPLUS PPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 ME6 Color and Fill
196 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B TG SYMBOL (RFMOS_S) SYMBOL (RFSYMBOL), SIZE(SIZE2)
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND RFSYMBOL AND TG AND SIZE2 CONTAINS PO1 PO1 DIFF AND NPLUS NOT (PO1 OR RFMOS_S) DIFF AND NPLUS AND RFMOS_S NOT PO1 Substrate
UMC Confidential
197 Ver. B04_PB
24.37 N_PO7W500_18_RF 1.8 volt variable length RF NMOS transistor
Spectre Netlist Spectre Model Name = n_po7w500_18_rf NM0 (D G S B) n_po7w500_18_rf l=200n
HspiceS Netlist HspiceS Model Name = N_PO7W500_18_RF XNM0 D G S B N_PO7W500_18_RF L=200E-9
DIVA LVS Netlist DIVA Device Name = N_PO7W500_18_RF ; N_PO7W500_18_RF Instance /NM0 = auLvs device M0 d N_PO7W500_18_RF D G S B (p D S) i 0 N_PO7W500_18_RF D G S B " nf 5.0 L 200e-9 W 5e-6 M 7.0"
CDL Netlist CDL Device Name = N_PO7W500_18_RF MMN0 D G S B N_PO7W500_18_RF W=5u L=200.0n M=7
UMC Confidential
198 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = N_PO7W500_18_RF C N_PO7W500_18_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MN0 N_PO7W500_18_RF D G S B ; L 2.0e-07 W 5e-06 Nf 7 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
199 Ver. B04_PB
N_PO7W500_18_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF NPLUS PPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 ME6 SYMBOL (RFMOS_S) Color and Fill
200 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B SYMBOL (RFSYMBOL), SIZE(SIZE1)
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND RFSYMBOL AND SIZE1 CONTAINS PO1 PO1 DIFF AND NPLUS NOT (PO1 OR RFMOS_S) DIFF AND NPLUS AND RFMOS_S NOT PO1 Substrate
UMC Confidential
201 Ver. B04_PB
24.38 N_PO7W500_33_RF 3.3 volt variable length RF NMOS transistor
Spectre Netlist Spectre Model Name = n_po7w500_33_rf NM0 (D G S B) n_po7w500_33_rf l=340n
HspiceS Netlist HspiceS Model Name = N_PO7W500_33_RF XNM0 D G S B N_PO7W500_33_RF L=340E-9
DIVA LVS Netlist DIVA Device Name = N_PO7W500_33_RF ; N_PO7W500_33_RF Instance /NM0 = auLvs device M0 d N_PO7W500_33_RF D G S B (p D S) i 0 N_PO7W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 7.0"
CDL Netlist CDL Device Name = N_PO7W500_33_RF
UMC Confidential
202 Ver. B04_PB
UM180FDKMFC000000A_B MMN0 D G S B N_PO7W500_33_RF W=5u L=340.0n M=7
Assura Netlist Assura auLvs Device Name = N_PO7W500_33_RF C N_PO7W500_33_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MN0 N_PO7W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 7 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
203 Ver. B04_PB
N_PO7W500_33_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF NPLUS PPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 ME6 TG Color and Fill
204 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B SYMBOL (RFMOS_S) SYMBOL (RFSYMBOL), SIZE(SIZE1)
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND NPLUS AND RFSYMBOL AND TG AND SIZE1 CONTAINS PO1 PO1 DIFF AND NPLUS NOT (PO1 OR RFMOS_S) DIFF AND NPLUS AND RFMOS_S NOT PO1 Substrate
UMC Confidential
205 Ver. B04_PB
24.39 P_L18W500_18_RF 1.8 volt variable finger RF PMOS transistor
Spectre Netlist Spectre Model Name = p_l18w500_18_rf PM0 (D G S B) p_l18w500_18_rf nf=5
HspiceS Netlist HspiceS Model Name = P_L18W500_18_RF XPM0 D G S B P_L18W500_18_RF NF=5.0
DIVA LVS Netlist DIVA Device Name = P_L18W500_18_RF ; P_L18W500_18_RF Instance /PM0 = auLvs device M0 d P_L18W500_18_RF D G S B (p D S) i 0 P_L18W500_18_RF D G S B " nf 5.0 L 180e-9 W 5e-6 M 5.0"
CDL Netlist CDL Device Name = P_L18W500_18_RF
UMC Confidential
206 Ver. B04_PB
UM180FDKMFC000000A_B MMP0 D G S B P_L18W500_18_RF W=5u L=180.0n M=5
Assura Netlist Assura auLvs Device Name = P_L18W500_18_RF C P_L18W500_18_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MP0 P_L18W500_18_RF D G S B ; L 1.8e-07 W 5e-06 Nf 5 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
207 Ver. B04_PB
P_L18W500_18_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF PPLUS NPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 Color and Fill
208 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B ME6 SYMBOL(RFMOS_S) SYMBOL(RFSYMBOL), SIZE(SIZE2), NWEL
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND PPLUS AND RFSYMBOL AND SIZE2 CONTAINS PO1 PO1 DIFF AND PPLUS NOT (PO1 OR RFMOS_S) DIFF AND PPLUS AND RFMOS_S NOT PO1 NWEL
UMC Confidential
209 Ver. B04_PB
24.40 P_L34W500_33_RF 3.3 volt variable finger RF PMOS transistor
Spectre Netlist Spectre Model Name = p_l34w500_33_rf PM0 (D G S B) p_l34w500_33_rf nf=5
HspiceS Netlist HspiceS Model Name = P_L34W500_33_RF XPM0 D G S B P_L34W500_33_RF NF=5.0
DIVA LVS Netlist DIVA Device Name = P_L34W500_33_RF ; P_L34W500_33_RF Instance /PM0 = auLvs device M0 d P_L34W500_33_RF D G S B (p D S) i 0 P_L34W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 5.0"
CDL Netlist CDL Device Name = P_L34W500_33_RF MMP0 D G S B P_L34W500_33_RF W=5u L=340.0n M=5
UMC Confidential
210 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = P_L34W500_33_RF C P_L34W500_33_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MN0 P_L34W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 5 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
211 Ver. B04_PB
P_L34W500_33_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF PPLUS NPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 ME6 Color and Fill
212 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B TG SYMBOL(RFMOS_S) SYMBOL(RFSYMBOL), SIZE(SIZE2), NWEL
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND PPLUS AND RFSYMBOL AND TG AND SIZE2 CONTAINS PO1 PO1 DIFF AND PPLUS NOT (PO1 OR RFMOS_S) DIFF AND PPLUS AND RFMOS_S NOT PO1 NWEL
UMC Confidential
213 Ver. B04_PB
24.41 P_PO7W500_18_RF 1.8 volt variable length RF PMOS transistor
Spectre Netlist Spectre Model Name = p_po7w500_18_rf PM0 (D G S B) p_po7w500_18_rf l=200n
HspiceS Netlist HspiceS Model Name = P_PO7W500_18_RF XPM0 D G S B P_PO7W500_18_RF L=200E-9
DIVA LVS Netlist DIVA Device Name = P_PO7W500_18_RF ; P_PO7W500_18_RF Instance /PM0 = auLvs device M0 d P_PO7W500_18_RF D G S B (p D S) i 0 P_PO7W500_18_RF D G S B " nf 5.0 L 200e-9 W 5e-6 M 7.0"
CDL Netlist CDL Device Name = P_PO7W500_18_RF MMP0 D G S B P_PO7W500_18_RF W=5u L=200.0n M=7
UMC Confidential
214 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = P_PO7W500_18_RF C P_PO7W500_18_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MP0 P_PO7W500_18_RF D G S B ; L 2.0e-07 W 5e-06 Nf 7 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
215 Ver. B04_PB
P_PO7W500_18_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF PPLUS NPLUS, ME1, DIFF,CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 ME6 Color and Fill
216 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B SYMBOL(RFMOS_S) SYMBOL (RFSYMBOL), SIZE(SIZE1), NWEL
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND PPLUS AND RFSYMBOL AND TG AND SIZE1 CONTAINS PO1 PO1 DIFF AND PPLUS NOT (PO1 OR RFMOS_S) DIFF AND PPLUS AND RFMOS_S NOT PO1 NWEL
UMC Confidential
217 Ver. B04_PB
24.42 P_PO7W500_33_RF 3.3 volt variable length RF PMOS transistor
Spectre Netlist Spectre Model Name = p_po7w500_33_rf PM0 (D G S B) p_po7w500_33_rf l=340n
HspiceS Netlist HspiceS Model Name = P_PO7W500_33_RF XPM0 D G S B P_PO7W500_33_RF L=340E-9
DIVA LVS Netlist DIVA Device Name = P_PO7W500_33_RF ; P_PO7W500_33_RF Instance /PM0 = auLvs device M0 d P_PO7W500_33_RF D G S B (p D S) i 0 P_PO7W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 7.0"
CDL Netlist CDL Device Name = P_PO7W500_33_RF MMP0 D G S B P_PO7W500_33_RF W=5u L=340.0n M=7
UMC Confidential
218 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = P_PO7W500_33_RF C P_PO7W500_33_RF MOS DRAIN B B ;; * 4 pins * 4 nets * 0 instances i MP0 P_PO7W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 7 ; GATE B SOURCE B SUBSTRATE
UMC Confidential
219 Ver. B04_PB
P_PO7W500_33_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF PPLUS NPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME4 ME4-ME5 ME5-ME6 ME6 Color and Fill
220 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B TG SYMBOL (RFMOS_S) SYMBOL (RFSYMBOL), SIZE (SIZE1), NWEL
Device Derivation Device Recognition G D S B Layer Derivation DIFF AND PPLUS AND RFSYMBOL AND TG AND SIZE1 CONTAINS PO1 PO1 DIFF AND PPLUS NOT (PO1 OR CONT) DIFF AND PPLUS AND RFMOS_S NOT PO1 NWEL
UMC Confidential
221 Ver. B04_PB
24.43
MIMCAPM_RF RF Metal Capacitor
Spectre Netlist Spectre Model Name = mimcapm_rf C0 (PLUS MINUS B) mimcapm_rf nx=1 ny=1 l=10.0u w=10.0u
HspiceS Netlist HspiceS Model Name = MIMCAPM_RF XC0 PLUS MINUS B MIMCAPM_RF NX=1.0 NY=1.0 L=10E-6 W=10E-6
DIVA LVS Netlist DIVA Device Name = MIMCAPM_RF ; MIMCAPM_RF Instance /C0 = auLvs device C0 d MIMCAPM_RF PLUS MINUS B i 0 MIMCAPM_RF PLUS MINUS B " nx 1.0 ny 1.0 l 10e-6 w 10e-6 C 103e-15"
CDL Netlist CDL Device Name = MIMCAPM_RF CC0 PLUS MINUS 103f $[MIMCAPM_RF] $SUB=B
UMC Confidential
222 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = MIMCAPM_RF c MIMCAPM_RF CAP POS B * 3 pins * 3 nets * 0 instances i C0 MIMCAPM_RF PLUS MINUS B; w 1e-05 C 1.03e-13 l 1e-05 nx 1.0 ny 1.0; MINUS B SUBSTRATE B;;
UMC Confidential
223 Ver. B04_PB
MIMCAPM_RF (diagrammatic layout)
Device Layers Layer MMC DIFF PPLUS CONT ME1, M1_CAD (Slot_Mark) ME6 ME5 VI5 SYMBOL (CSYMBOL) SYMBOL (RFSYMBOL) Color and Fill
Device Derivation
UMC Confidential
224 Ver. B04_PB
UM180FDKMFC000000A_B Device Recognition PLUS MINUS B Layer Derivation MMC AND CSYMBOL AND RFSYMBOL MMC ME5 NOT MMC Substrate
LVS Comparison Parameter Length Width Nx Ny Calculation MMC Area / Width MMC coincident CSYMBOL Number of MMC enclosed by CSYMBOL Fingers/nx
UMC Confidential
225 Ver. B04_PB
24.44
L_SLCR20K_RF Circular spiral Inductor
Spectre Netlist Spectre Model Name = l_slcr20k_rf L0 (PLUS MINUS B) l_slcr20k_rf d=126u w=6u n=1.5
HspiceS Netlist HspiceS Model Name = P_PO7W500_33_RF XL0 PLUS MINUS B L_SLCR20K_RF D=126E-6 W=6E-6 N=1.5
DIVA LVS Netlist DIVA Device Name = L_SLCR20K_RF ; L_SLCR20K_RF Instance /L0 = auLvs device L0 d L_SLCR20K_RF PLUS MINUS B i 0 L_SLCR20K_RF PLUS MINUS B " d 126e-6 w 6e-6 n 1.5 L 585.824e-12"
CDL Netlist CDL Device Name = L_SLCR20K_RF LL0 PLUS MINUS 585.824p $[L_SLCR20K_RF] $SUB=B
UMC Confidential
226 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = L_SLCR20K_RF c L_SLCR20K_RF IND POS B * 3 pins * 3 nets * 0 instances i C0 L_SLCR20K_RF PLUS MINUS B; w 6e-06 d 126e-6 n 1.5; MINUS B SUBSTRATE B;;
UMC Confidential
227 Ver. B04_PB
L_SLCR20K_RF (diagrammatic layout)
Device Layers Layer ME6 ME5 VI5 DIFF PPLUS CONT ME1
Color and Fill
UM180FDKMFC000000A_B SYMBOL (RFSYMBOL), SYMBOL (LSYMBOL)
Device Derivation Device Recognition PLUS MINUS B Layer Derivation LSYMBOL AND ME6 AND RFSYMBOL ME6 ME6 Substrate
LVS Comparison Parameter Width Calculation ME6 Width
UMC Confidential
229 Ver. B04_PB
24.45
PAD_RF Bond Pad
Spectre Netlist Spectre Model Name = pad_rf C0 (PLUS MINUS) pad_rf index=1
HspiceS Netlist HspiceS Model Name = PAD_RF XC0 PLUS MINUS PAD_RF INDEX=1.0
DIVA LVS Netlist DIVA Device Name = PAD_RF ; PAD_RF Instance /C0 = auLvs device C0 d PAD_RF PLUS MINUS i 0 PAD_RF PLUS MINUS " index 1.0"
CDL Netlist CDL Device Name = PAD_RF CC0 PLUS MINUS $[PAD_RF]
UMC Confidential
230 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = PAD_RF c PAD_RF CAP POS B * 2 pins * 2 nets * 0 instances i C0 PAD_RF PLUS MINUS ; index 1.0; MINUS B ;;
UMC Confidential
231 Ver. B04_PB
PAD_RF (diagrammatic layout)
Device Layers Layer PAD ME6 ME1 SYMBOL (RFSYMBOL) Color and Fill
Device Derivation Device Recognition PLUS MINUS Layer Derivation RFSYMBOL AND ME6 AND PAD AND ME1 ME6 ME1
LVS Comparison Parameter Index Calculation RFSYMBOL AND ME6 AND PAD AND ME1 Overlapping particular metal layer.
UMC Confidential
232 Ver. B04_PB
24.46
RNHR_RF RF High resistive poly resistor
Spectre Netlist Spectre Model Name = rnhr_rf R0 (PLUS MINUS B) rnhr_rf w=2u l=2u
HspiceS Netlist HspiceS Model Name = RNHR_RF XR0 PLUS MINUS B RNHR_RF L=2E-6 W=2E-6
DIVA LVS Netlist DIVA Device Name = RNHR_RF ; RNHR_RF Instance /R0 = auLvs device R0 d RNHR_RF PLUS MINUS B (p PLUS MINUS) i 0 RNHR_RF PLUS MINUS B" R 972.1 L 2e-6 W 2e-6"
CDL Netlist CDL Device Name = RNHR_RF RR0 PLUS MINUS 972.1 $SUB=B $[RNHR_RF] $W=2u $L=2u
UMC Confidential
233 Ver. B04_PB
UM180FDKMFC000000A_B Assura Netlist Assura auLvs Device Name = RNHR_RF c RNHR_RF RES IN B * 3 pins * 3 nets * 0 instances i R0 RNHR_RF PLUS MINUS B; L 2e-06 W 2e-06 R 972.1; OUT B SUBSTRATE B ;;
UMC Confidential
234 Ver. B04_PB
RNHR_RF (diagrammatic layout)
Device Layers Layer PPLUS PO1 SAB PSYMBOL ME1-ME6 ME1 CONT SYMBOL (RFSYMBOL) HR NWEL Color and Fill
Device Derivation
UMC Confidential
235 Ver. B04_PB
UM180FDKMFC000000A_B Device Recognition PLUS MINUS B Layer Derivation PO1 AND HR AND SAB AND PSYMBOL AND RFSYMBOL AND NWEL PO1 PO1 NWEL
LVS Comparison Parameter Length Width Calculation SAB length PO1 width PLUS and MINUS are PERMUTABLE
UMC Confidential
236 Ver. B04_PB
24.47
RNNPO_RF RF N+ poly resistor w/o salicide
Spectre Netlist Spectre Model Name = rnnpo_rf R0 (PLUS MINUS B) rnnpo_rf w=2u l=2u
HspiceS Netlist HspiceS Model Name = RNNPO_RF XR0 PLUS MINUS B RNNPO_RF L=2E-6 W=2E-6
DIVA LVS Netlist DIVA Device Name = RNNPO_RF ; RNNPO_RF Instance /R0 = auLvs device R0 d RNNPO_RF PLUS MINUS B (p PLUS MINUS) i 0 RNNPO_RF PLUS MINUS B" R 136.626 L 2e-6 W 2e-6"
CDL Netlist CDL Device Name = RNNPO_RF RR0 PLUS MINUS 136.626 $SUB=B $[RNNPO_RF] $W=2u $L=2u
UMC Confidential
237 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = RNNPO_RF c RNNPO_RF RES IN B * 3 pins * 3 nets * 0 instances i R0 RNNPO_RF PLUS MINUS B; L 2e-06 W 2e-06 R 136.626; OUT B SUBSTRATE B ;;
UMC Confidential
238 Ver. B04_PB
RNNPO_RF (diagrammatic layout)
Device Layers Layer NPLUS PO1 SAB PSYMBOL ME1-ME6 ME1 CONT SYMBOL (RFSYMBOL) SUBSTRATE Color and Fill
Device Derivation
UMC Confidential
239 Ver. B04_PB
UM180FDKMFC000000A_B Device Recognition PLUS MINUS B Layer Derivation PO1 AND SAB AND PSYMBOL AND NPLUS AND RFSYMBOL PO1 PO1 Substrate
UMC Confidential
240 Ver. B04_PB
24.48
RNPPO_RF RF P+ poly resistor w/o salicide
Spectre Netlist Spectre Model Name = rnppo_rf R0 (PLUS MINUS B) rnppo_rf w=2u l=2u
HspiceS Netlist HspiceS Model Name = RNPPO_RF XR0 PLUS MINUS B RNPPO_RF L=2E-6 W=2E-6
DIVA LVS Netlist DIVA Device Name = RNPPO_RF ; RNPPO_RF Instance /R0 = auLvs device R0 d RNPPO_RF PLUS MINUS B (p PLUS MINUS) i 0 RNPPO_RF PLUS MINUS B" R 467.758 L 2e-6 W 2e-6"
CDL Netlist CDL Device Name = RNPPO_RF RR0 PLUS MINUS 467.758 $SUB=B $[RNPPO_RF] $W=2u $L=2u
UMC Confidential
241 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = RNPPO_RF c RNPPO_RF RES IN B * 3 pins * 3 nets * 0 instances i R0 RNPPO_RF PLUS MINUS B; L 2e-06 W 2e-06 R 467.758; OUT B SUBSTRATE B ;;
UMC Confidential
242 Ver. B04_PB
RNPPO_RF (diagrammatic layout)
Device Layers Layer PPLUS PO1 SAB PSYMBOL ME1-ME6 ME1 CONT SYMBOL (RFSYMBOL) NWEL Color and Fill
Device Derivation
UMC Confidential
243 Ver. B04_PB
UM180FDKMFC000000A_B Device Recognition PLUS MINUS B Layer Derivation PO1 AND SAB AND PSYMBOL AND PPLUS AND RFSYMBOL PO1 PO1 Substrate
UMC Confidential
244 Ver. B04_PB
24.49
VARMIS_18_RF 1.8V N+/Nwell RF MIS varactor
Spectre Netlist Spectre Model Name = varmis_18_rf C0 (PLUS MINUS B) varmis_18_rf nf=24
HspiceS Netlist HspiceS Model Name = VARMIS_18_RF XC0 PLUS MINUS B VARMIS_18_RF NF=24.0
DIVA LVS Netlist DIVA Device Name = VARMIS_18_RF ; VARMIS_18_RF Instance /C0 = auLvs device C0 d VARMIS_18_RF PLUS MINUS B i 0 VARMIS_18_RF PLUS MINUS B" nf 24.0 C 1.03082e-12"
CDL Netlist CDL Device Name = VARMIS_18_RF CC0 PLUS MINUS 1.03082p $[VARMIS_18_RF] $SUB=B
UMC Confidential
245 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = VARMIS_18_RF c VARMIS_18_RF CAP POS B * 3 pins * 3 nets * 0 instances i C0 VARMIS_18_RF PLUS MINUS B; nf 24.0 c 1.030828e-12; MINUS B SUBSTRATE B;;
UMC Confidential
246 Ver. B04_PB
VARMIS_18_RF (diagrammatic layout)
Width Length Device Layers Layer DIFF NWEL NPLUS PPLUS, ME1, DIFF, CONT PO1, ME4-ME5 CONT ME1-ME2 ME3-ME6 ME4-ME5 Color and Fill
247 Ver. B04_PB
UMC Confidential
UM180FDKMFC000000A_B ME5-ME6 ME6 SYMBOL (RFSYMBOL)
Device Derivation Device Recognition PLUS MINUS B Layer Derivation DIFF AND NWEL AND RFSYMBOL CONTAINS PO1 PO1 DIFF AND NPLUS NOT PO1 Substrate
LVS Comparison Parameter Nf Calculation PO1 intersecting DIFF
UMC Confidential
248 Ver. B04_PB
24.50
VARDIOP_RF P+/Nwell RF diode varactor
Spectre Netlist Spectre Model Name = vardiop_rf C0 (PLUS MINUS) vardiop_rf nf=30
HspiceS Netlist HspiceS Model Name = VARDIOP_RF XC0 PLUS MINUS VARDIOP_RF NF=30.0
DIVA LVS Netlist DIVA Device Name = VARDIOP_RF ; VARDIOP_RF Instance /C0 = auLvs device C0 d VARDIOP_RF PLUS MINUS i 0 VARDIOP_RF PLUS MINUS " nf 30.0 C 406.32e-15"
CDL Netlist CDL Device Name = VARDIOP_RF CC0 PLUS MINUS 406.32f $[VARDIOP_RF]
UMC Confidential
249 Ver. B04_PB
Assura Netlist Assura auLvs Device Name = VARDIOP_RF c VARDIOP_RF CAP POS B * 2 pins * 2 nets * 0 instances i C0 VARDIOP_RF PLUS MINUS; nf 30.0 c 406.32e-15; MINUS B;;
UMC Confidential
250 Ver. B04_PB
VARDIOP_RF (diagrammatic layout)
Device Layers Layer DIFF PPLUS NPLUS, ME1, DIFF, CONT CONT ME1 ME1-ME6 NWEL SYMBOL (RFSYMBOL), SYMBOL (CSYMBOL) Color and Fill
Device Derivation Device Recognition PLUS Layer Derivation DIFF AND CSYMBOL AND RFSYMBOL AND NWEL DIFF AND PPLUS
UMC Confidential
251 Ver. B04_PB
UM180FDKMFC000000A_B MINUS DIFF AND NPLUS
LVS Comparison Parameter Nf Calculation DIFF AND PPLUS
UMC Confidential
252 Ver. B04_PB
25 Known Problems and Solutions

Metal Resistors violate minimum area DRC Issue: The metal resistors ( RM1_MM RM6_MM ) when set to their minimum length and width violate the minimum area Design rule. Solution: When the metal resistors are set to minimum, the designer needs to hook up the rest of the circuit to the metal resistors. When the minimum metal area metal resistors are hooked up, and DRC is run, this error will go away. Assura LVS reports parameter mismatches when using a CDL netlist Issue: Assura LVS reports parameter mismatches when comparing a CDL netlist against the layout. The SKILL routines may have problems dealing with CDL netlists that include *.SCALE METER in the file. Solution: The user needs to manually edit the ASCII CDL netlist to change the SCALE being used. Currently, the CDL netlist outputs the following as the SCALE: *.SCALE METER The user needs to edit this line, so it reads: *.SCALE MICRON A solution will be created so that the user does not have to manually edit the ASCII CDL netlist, which will be provided in a future release. Parasitic devices in Pcells maybe double counted during Assura RCX Issue: Currently, parasitic devices in the Pcell maybe double counted during the Assura RCX process. Solution: A solution will be created so that this issue is avoided, which will be provided in a future release. Assura aborts when run on a GDS stream file Issue: When streaming out a GDS file, and then running Assura on it, Assura aborts prematurely. Solution: This is a GDS problem with regards to device name and model names. This problem can be avoided when streaming out a layout. In the Stream Out form, when selecting the Options button, a Stream Out Options form will appear. One needs to
UMC Confidential
253 Ver. B04_PB
UM180FDKMFC000000A_B ensure that the Case Sensitivity radio button is set to upper. An example of the Stream Out Options form is given below:
Assura DRC does not check for off grid errors Issue: Assura DRC does not check for off grid errors in layouts. Solution: To check for off grid errors in Assura DRC, the user needs to specify the grid size in the Assura Run DRC form. To do this, the user needs to select Assura -> Run DRCThis will bring up the Assura Run DRC form. In this form, the user needs to select the Modify avParameters button in the bottom left-hand corner of the form. This will bring up the DRC Options form illustrated below. The user then needs to select the ?flagOffGrid option, and then enter the desired Grid Size. The user then needs to select the Use in Run option so that this change in avParameters is applied.
UMC Confidential
254 Ver. B04_PB
Metal Resistors may not route properly using VCR Issue: The metal resistors ( RM1_MM RM6_MM ) may not route properly when using VCR. Solution: Manual adjustment may be necessary to fix routing problems encountered with metal resistors using VCR. Devices fail to redraw in layout view, when Properties are edited Issue: Some devices fail to redraw in the layout view, when properties are edited in the Edit Object Properties form. Solution: The user may see these problems, if using Cadence ICFB 4.4.6.100.99 software. If this is the case, the user should use Cadence 4.4.6.100.70 instead, and this problem will be resolved.
UMC Confidential
255 Ver. B04_PB
The entire purpose name can not be read in the LSW window. Issue: Only the first and last letters of the purpose name can be viewed in the LSW window. Solution: The user can edit their "~/.Xdefaults" file and add the following lines to it; ! *********************************************************** ! * These resources allow you to set the LSW size * ! *********************************************************** Opus.LSWGeometry:300x760+770+0 Once these lines have been entered and saved in the "~/.Xdefaults" file, the user then needs to type the following command in their terminal window so that their LSW window will be resized during their next ICFB session: xrdb ~/.Xdefaults Once this has been done, and a new ICFB session is executed, the LSW window will be large enough so that the entire purpose name will be visible. L_SLCR20K_RF flags DRC error 4.31H Issue: When DRC is run on the L_SLCR20K_RF pcell layout, the following error is flagged: 4.31H: The minimum overlap of IND to inductor layer is 10um Solution: The designer must connect to the PLUS and MINUS terminal with ME6. The width of the ME6 layer needs to be coincident with the width of the PLUS and MINUS terminals ( 6um, for example ). Please refer to the diagram below:
UMC Confidential
256 Ver. B04_PB
6um 6um
NCAP_MM and PCAP_MM will not route in VCR Issue: NCAP_MM and PCAP_MM will not completely route in VCR. Solution: The user may need to manually route the NCAP_MM and PCAP_MM devices.
UMC Confidential
257 Ver. B04_PB
Appendix
A.1 Revision History
Approved Author/ Version Date B03_PA May/2005 Reviser Yueh Guey Chiou Event (Purpose) Remark
UIP official release
Doc No:
G-9FD-MIXED_MODE/RFCMOS18-1.8V/3.3V1P6M-MMC/UM180FDKMFC000000A-FDK-8C 1. Included SPICE model files 1. One-single packaged FDK for Spectre and Hspice 2. Included rule decks for 2. One-single packaged FDK Calibre 3. Updated Virtuoso techfile in 3. By G-DF-GENERATION18-VIRTUOSO-TF 2.3_P1 FDK 4. Added RFMMCMK layer to 4. By TLR 4.29M and Calibre DRC rule deck 2.7_P1 MIMCAPM_RF Pcell 5. Modified RM1_MM ~RM6_MM mark layers to be 5. By Calibre LVS rule deck 1.3_P1 MxRESMK layers 6. Removed VARACT layer 6. Null layer from VARMIS_18_RF Pcell 7. Additional CDL parameters were added to the following 7. By Calibre LVS deck 1.3_P1 devices NF -> VARMIS_18_RF NF -> VARDIOP_RF NX,NY,W,L->MIMCAPM_RF W,D,N -> L_SLCR20K_RF INDEX -> PAD_RF 8. Added DIONW_MM cell 8. Requested by Q&RA/DSQA views 9. Changed MIMCAPS_MM 9. To form 2x2 VIA5 array at least inside minimum width / length from Metal_CAP layer 1.5um to 1.84um 10. Replaced two BJT layouts 10. By officially released SPICE twinwell 1.5_P1
B04_PB Dec/9/2005 Yueh Guey Chiou
A.2. UMC Utilities

Below utilities are provided in this design kit, and can be accessed from the UMC Utils pull-down menu, A.2.1. Callback Re-trigger Utility
UMC Confidential
258 Ver. B04_PB
A.2.2. Alphabet Generator
Fig. The Alphabet Generator Usage- Generate alphabetical logo by physical layers in a layout view Text Input Text content Coordinate Location of the logo (X:Y) Text Layer Name Physical layer used Text Magnification Ratio Text logo size
UMC Confidential
259 Ver. B04_PB
UM180FDKMFC000000A_B Note: DRC errors might happen with small text magnification ratio.
UMC Confidential
260 Ver. B04_PB

UMC 180nm MM RF FDK CDN Userguide vB04 PB 3

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

UMC 180nm MM RF FDK CDN Userguide vB04 PB 3

Uploaded by

Copyright:

Available Formats

UM180FDKMFC000000A_B

3. What makes up a PDK? .......... 9 4. Installation of the PDK ........... 10 ...... 11

5. PDK Install Directory Structure/Contents

6. Creation of a Design Project .................... 12 7. Techfile Methodology ................ 14

8. Customizing Layer Display Properties Using Display.drf File .. 15 9. Schematic Design .. 17

14. Component Label Defaults . 37 15. Simulation Models 40

21. Dracula Support 48 22. Assura Decks . 49

23. DEVICE SPECIFICATIONS 59

24. DEVICE DATASHEETS 72 25. Known Problems and Solutions . 253

GT-DBT-030922-007 (MM salicide resistors and metal resistors)

0.3 Component List

* C means compact model, and S means sub-circuit model.

0.4 Verification Notes

1.1 Software Releases

3 What makes up a PDK?

Schematic Symbols & CDF Analog Simulation & callbacks

Schematic (Composer) Analog Front-end Design

Analog Design Environment

Fixed Layouts Parameterized Cells

Device Generation/Cell Design

Techfile: - Layer maps - Layer props - symbolics - Connectivity - VCR setup

Interconnect Wire Editor/Routing Virtuoso Custom Router (VCR)

Physical Verification - DRC - LVS - LPE

Interactive Physical Verification

4 Installation of the PDK

5 PDK Install Directory Structure/Contents

6 Creation of a Design Project

UM180FDKMFC000000A_B In Library From Library To Library umc18mm_test umc18mm umc18mmrf

8 Customizing Layer Display Properties Using Display.drf File

10 Library Device Setup

10.4 Bipolar Transistors

11.4 BIPOLARS 11.5 DIODES

11.7 Bond Pads 11.8 Varactors

12.4 BIPOLARS 12.5 DIODES

12.7 Bond Pads 12.8 Varactors

MOSFET ADD INSTANCE FORM

RESISTOR ADD INSTANCE FORM

13.5 CAPACITORS MIMCAPS_MM

13.6 CAPACITORS NCAP_MM, PCAP_MM

13.7 CAPACITORS MIMCAPM_RF

CAPACITOR ADD INSTANCE FORM

BIPOLAR ADD INSTANCE FORM

Width (M) - diode width in meters

DIODE ADD INSTANCE FORM

INDUCTOR ADD INSTANCE FORM

Specified Index multi layer number of PAD metal (1, 2, 3, 4, 5)

INDUCTOR ADD INSTANCE FORM

VARACTOR ADD INSTANCE FORM

14 Component Label Defaults

component parameters: model, r, w, l operating point: v i res instance name prefix: R

component parameters: model, r, w, l operating point: v, res instance name prefix: R

14.5 CAPACITORS MIMCAPS_MM

component parameters: model, c, l, w, m

14.6 CAPACITORS NCAP_MM, PCAP_MM

component parameters: model, c, l, w, fingers, m

UM180FDKMFC000000A_B instance name prefix: C

14.7 CAPACITORS MIMCAPM_RF

component parameters: model, nx, ny, w, l

component parameters: model, d, w, n operating point: - i, ind model: -

UM180FDKMFC000000A_B instance name prefix: C

tt tt mimcaps_typ tt tt tt tt res_typ res_typ tt tt

Setting Environment Variables