1 DIGIT (4 BITS) BCD COUNTER:

module bcdcount (clk,rstm,entm,count); //4 bit bcd counter

input clk,rstm,entm;
output [3:0]count;
reg [3:0]count;
parameter
s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b0100,s5=4'b0101,s6=4'b0110,s7=4'b0111,
s8=4'b1000,s9=4'b1001;
reg [3:0]state;

always @(posedge clk or rstm ) //rstm is asynchronous reset input

begin
if(rstm)
begin
state=s0;
count=s0;
end
else if(entm==1)
begin
case(state)
s0: state = s1;
s1: state = s2;
s2: state = s3;
s3: state = s4;
s4: state = s5;
s5: state = s6;

s6: state = s7;

s7: state = s8;
s8: state = s9;
s9: state = s0;
default: state = s0;
endcase
count=state;
end
else
begin
state=state;
count=count;
end
end
endmodule
if this is ok with you , you can have it. I tried in another way. But change the module names.
4 DIGIT BCD COUNTER:
//module bcd16_beh (clk,rstm,entm,count); //4 digit bcd counter
/*input clk,rstm,entm;
output [15:0]count;
reg [15:0]count;
parameter
s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b0100,s5=4'b0101,s6=4'b0110,s7=4'b0111,
s8=4'b1000,s9=4'b1001;
reg [3:0]state=s0;
reg [3:0]state1=s0;

reg [3:0] state2=s0;

reg [3:0]state3=s0;
reg clk1,clk2,clk3;

always @(posedge clk or rstm ) //rstm is asynchronous reset input

begin
if(rstm)
begin
state=s0;
count=16'b0;
end
else if(entm==1) //if entm=1 then counting should be proceeded
begin

//otherwise the present count value should be hold to display

case(state)
s0: state = s1;
s1: state = s2;
s2: state = s3;
s3: state = s4;
s4: state = s5;
s5: state = s6;
s6: state = s7;
s7: state = s8;
s8: state = s9;
s9: state = s0; //BCD counter should count upto 9 only after that it has to be reset
default: state = s0;

endcase
end
else
begin
state=state;
count=count;
end
count={state3,state2,state1,state};
clk1= state[0]&state[3];

end

always @(negedge clk1 )

begin
if(rstm)
begin
state1=s0;
count=16'b0;
end
else
begin
case(state1)
s0: state1 = s1;
s1: state1 = s2;
s2: state1 = s3;

s3: state1 = s4;

s4: state1 = s5;
s5: state1 = s6;
s6: state1 = s7;
s7: state1 = s8;
s8: state1 = s9;
s9: state1 = s0; //BCD counter should count upto 9 only after that it has to be reset
default: state1 = s0;
endcase
end
/*else
begin
state1=state1;
count=count;
end*/
/* count={state3,state2,state1,state};
clk2= state1[0]&state1[3];
end
always @(negedge clk2 )
begin
if(rstm)
begin
state2=s0;
count=16'b0;
end

else
begin
case(state2)
s0: state2 = s1;
s1: state2 = s2;
s2: state2 = s3;
s3: state2 = s4;
s4: state2 = s5;
s5: state2 = s6;
s6: state2 = s7;
s7: state2 = s8;
s8: state2 = s9;
s9: state2 = s0; //BCD counter should count upto 9 only after that it has to be reset
default: state2 = s0;
endcase
end
/*else
begin
state2=state2;
count=count;
end*/
/*count={state3,state2,state1,state};
clk3= state2[0]&state2[3];
end
always @(negedge clk3 )

begin
if(rstm)
begin
state3=s0;
count=16'b0;
end
else
begin

case(state3)
s0: state3 = s1;
s1: state3 = s2;
s2: state3 = s3;
s3: state3 = s4;
s4: state3 = s5;
s5: state3 = s6;
s6: state3 = s7;
s7: state3 = s8;
s8: state3 = s9;
s9: state3 = s0;
default: state3 = s0;
endcase
end
/* else
begin

state3=state3;
count=count;
end*/
//count={state3,state2,state1,state};

//end

I tried it with structural level modeling. If the above is good, you can have it.
BCD TO 7 SEGMENT ENCODER:
module bcdto7seg(dis,op);
input [15:0]dis;
output [27:0]op;
reg [27:0]op=28'b0;

always @(dis)
begin
case(dis[3:0])
4'b0000: op[6:0]=7'b0000001;
4'b0010: op[6:0]=7'b1111001;
4'b0011: op[6:0]=7'b0010010;
4'b0100: op[6:0]=7'b0000110;
4'b0101: op[6:0]=7'b1001100;
4'b0110: op[6:0]=7'b0100000;
4'b0111: op[6:0]=7'b0001111;
4'b1000: op[6:0]=7'b0000000;

4'b1001: op[6:0]=7'b0000100;
endcase
case(dis[7:4])
4'b0000: op[13:7]=7'b0000001;
4'b0010: op[13:7]=7'b1111001;
4'b0011: op[13:7]=7'b0010010;
4'b0100: op[13:7]=7'b0000110;
4'b0101: op[13:7]=7'b1001100;
4'b0110: op[13:7]=7'b0100000;
4'b0111: op[13:7]=7'b0001111;
4'b1000: op[13:7]=7'b0000000;
4'b1001: op[13:7]=7'b0000100;
endcase
case(dis[11:8])
4'b0000: op[20:14]=7'b0000001;
4'b0010: op[20:14]=7'b1111001;
4'b0011: op[20:14]=7'b0010010;
4'b0100: op[20:14]=7'b0000110;
4'b0101: op[20:14]=7'b1001100;
4'b0110: op[20:14]=7'b0100000;
4'b0111: op[20:14]=7'b0001111;
4'b1000: op[20:14]=7'b0000000;
4'b1001: op[20:14]=7'b0000100;
endcase
case(dis[15:12])

4'b0000: op[27:21]=7'b0000001;
4'b0010: op[27:21]=7'b1111001;
4'b0011: op[27:21]=7'b0010010;
4'b0100: op[27:21]=7'b0000110;
4'b0101: op[27:21]=7'b1001100;
4'b0110: op[27:21]=7'b0100000;
4'b0111: op[27:21]=7'b0001111;
4'b1000: op[27:21]=7'b0000000;
4'b1001: op[27:21]=7'b0000100;
endcase

end
endmodule

THIS IS MY CODE. YOU CAN WRITE ONE MODULE FOR ONE DIGIT AND THEN CALL IT FOR 4 TIMES, TO
DISPLAY 4 DIGITS.
COMPARATOR
module comp16(a,b,altb);
input [15:0]a,b;
output altb;
reg altb;
wire altb0,altb1,altb2,altb3,altb4,altb5,altb6,altb7;

comp c0 (a[1:0],b[1:0],altb0);
comp c1 (a[3:2],b[3:2],altb1);
comp c2 (a[5:4],b[5:4],altb2);

comp c3 (a[7:6],b[7:6],altb3);
comp c4 (a[9:8],b[9:8],altb4);
comp c5 (a[11:10],b[11:10],altb5);
comp c6 (a[13:12],b[13:12],altb6);
comp c7 (a[15:14],b[15:14],altb7);

always @(*)
begin
if(altb7)
altb=1'b1;
else if (altb6)
altb=1'b1;
else if (altb5)
altb=1'b1;
else if (altb4)
altb=1'b1;
else if (altb3)
altb=1'b1;
else if (altb2)
altb=1'b1;
else if (altb1)
altb=1'b1;
else if (altb0)
altb=1'b1;
else

altb=1'b0;
end
endmodule

module comp(a,b,altb);
input [1:0]a,b;
output altb;
wire altb;
wire a1bar,a0bar,w1,w2,w3;

not (a1bar,a[1]);
not (a0bar,a[0]);
and (w1,a1bar,a0bar,b[0]);
and (w2,a0bar,b[0],b[1]);
and (w3,b[1],a1bar);
or (altb,w1,w2,w3);

endmodule
YOU HAVE TO CHANGE THIS CODE ALSO, MAY BE TO BEHAVIOURAL
MUX:
module mux16x1(d1,d0,update,d);
input [15:0]d1,d0;
input update;
output [15:0]d;

reg [15:0]d;

always @(*)
begin
if(update)
d<=d1;
else
d<=d0;
end
endmodule

REGISTER:
module reg16(clk,lsr,reset,d,a);
input clk,lsr,reset;
input [15:0]d;
output [15:0]a;
reg [15:0]a,buff=16'b0;

always @(posedge clk or reset)

begin
if(reset)
a=16'b0;
else if(lsr)
begin
buff=d;

a=buff;
end
else
a=buff;
end
endmodule

STOPWATCH:
module stopwatch(clk,entm,rstm,lsr,reset,update,ds,altb,op);
input clk,entm,rstm,lsr,reset,update,ds;
output altb;
output [27:0]op;
wire [27:0]op;
wire altb;
wire [15:0] a;
wire [15:0] b;
wire [15:0] d;
wire [15:0] dis;
wire [15:0]d0=16'b1001_1001_1001_1001;

bcd16_beh b5 (clk,rstm,entm,b);
comp16 c5 (a,b,altb);
mux16x1 m5 (b,d0,update,d);
reg16 r5 (clk,lsr,reset,d,a);

bcdto7seg b6 (dis,op);
mux16x1 m6 (a,b,ds,dis);

endmodule