Instruction Set of 8051 Microcontroller Mnemonics, Arranged Alphabetically

MNEMONIC
ACALL addr11 ADD A, direct ADD A, @Ri ADD A, #data ADD A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data ADDC A, Rn AJMP addr11 ANL A, direct ANL A, @Ri ANL A, #data ANL A, Rn ANL direct, A ANL direct, #data ANL C, bit ANL C, /bit CJNE A, direct, rel CJNE A, #data, rel CJNE @Ri, #data, rel CJNE Rn, #data, rel CLR A CLR bit CLR C CPL A CPL bit CPL C DA A DEC A DEC direct DEC @Ri DEC Rn DIV AB DJNZ direct, rel DJNZ Rn, rel INC A INC direct INC DPTR INC @Ri INC Rn JB bit, rel JBC bit, rel JC rel JMP @A + DPTR JNB bit, rel JNC rel JNZ rel JZ rel LCALL addr16 LJMP addr16 MOV A, direct MOV A, @Ri MOV A, #data MOV A, Rn MOV direct, A MOV direct, direct MOV direct, @Ri MOV direct, #data MOV direct, Rn MOV bit, C MOV C, bit MOV @Ri, A MOV @Ri, direct MOV @Ri, #data

DESCRIPTION
PC + 2 (SP); addr11 PC A + (direct) A A + (Ri) A A + #data A A + Rn A A + (direct) + C A A + (Ri) + C A A + #data + C A A + Rn + C A Addr11 PC A AND (direct) A A AND (Ri) A A AND #data A A AND Rn A (direct) AND A (direct) (direct) AND #data (direct) C AND bit C C AND bit C [A <> (direct)]: PC + 3 + rel PC [A <> data]: PC + 3 + rel PC [(Ri) <> data]: PC + 3 + rel PC [Rn <> data]: PC + 3 + rel PC 0A 0 bit 0C AA bit bit CC Abin Adec A1A (direct) 1 (direct) (Ri) 1 (Ri) Rn 1 Rn A/B AB [(direct) 1 <> 00]: PC + 3 + rel PC [Rn 1 <> 00]: PC + 2 + rel PC A+1A (direct) + 1 (direct) DPTR + 1 DPTR (Ri) + 1 (Ri) Rn + 1 Rn [b=1]: PC + 3 + rel PC [b=1]: PC + 3 + rel PC; 0 bit [C=1]: PC + 2 + rel PC DPTR + A PC [b=0]: PC + 3 + rel PC [C=0]: PC + 2 + rel PC [A>00]: PC + 2 + rel PC [A=00]: PC + 2 + rel PC PC + 3 (SP); addr16 PC Addr16 PC (direct) A (Ri) A #data A Rn A A (direct) (direct) (direct) (Ri) (direct) #data (direct) Rn (direct) C bit bit C A (Ri) (direct) (Ri) #data (Ri)

BYTES
2 2 1 2 1 2 1 2 1 2 2 1 2 1 2 3 2 2 3 3 3 3 1 2 1 1 2 1 1 1 2 1 1 1 3 2 1 2 1 1 1 3 3 2 1 3 2 2 2 3 3 2 1 2 1 2 3 2 3 2 2 2 1 2 2

CYCLES
2 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 4 2 2 1 1 2 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 2 2 2 2 2 1 1 2 1

FLAGS
C C C C C C C C OV OV OV OV OV OV OV OV AC AC AC AC AC AC AC AC

C C C C C C

C C

OV

MOV DPTR, #data16 MOV Rn, A MOV Rn, direct MOV Rn, #data MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @DPTR MOVX A, @Ri MOVX @DPTR, A MOVX @Ri, A NOP MUL AB ORL A, direct ORL A, @Ri ORL A, #data ORL A, Rn ORL direct, A ORL direct, #data ORL C, bit ORL C, /bit POP direct PUSH direct RET RETI RL A RLC A RR A RRC A SETB bit SETB C SJMP rel SUBB A, direct SUBB A, @Ri SUBB A, #data SUBB A, Rn SWAP A XCH A, direct XCH A, @Ri XCH A, Rn XCHD A, @Ri XRL A, direct XRL A, @Ri XRL A #data XRL A, Rn XRL direct, A XRL direct, #data

#data DPTR A Rn (direct) Rn #data Rn (A+DPTR) A (A+PC) A (DPTR)^ A (Ri)^ A A (DPTR)^ A (Ri)^ PC + 1 PC A x B AB A OR (direct) A A OR (Ri) A A OR #data A A OR Rn A (direct) OR A (direct) (direct) OR #data (direct) C OR bit C C OR bit C (SP) (direct) (direct) (SP) (SP) PC (SP) PC; EI A0A7A6..A1A0 CA7A6..A0C A0A7A6..A1A0 CA7A6..A0C 1 bit 1C PC + 2 + rel PC A (direct) C A A (Ri) C A A #data C A A Rn C A Alsn Amsn A (direct) A (Ri) A Rn Alsn (Ri)lsn A XOR (direct) A A XOR (Ri) A A XOR #data A A XOR Rn A (direct) XOR A (direct) (direct) XOR #data (direct)

3 1 2 2 1 1 1 1 1 1 1 1 2 1 2 1 2 3 2 2 2 2 1 1 1 1 1 1 2 1 2 2 1 2 1 1 2 1 1 1 2 1 2 1 2 3

2 1 2 1 2 2 2 2 2 2 1 4 1 1 1 1 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2

OV

C C

C C 1 C C C C OV OV OV OV AC AC AC AC

ACRONYMS
addr11 addr16 bit C #data #data16 direct lsn msn rel Rn @Ri [ ]: ^ () Page address of 11 bits, which is in the same 2K page as the address of the following instruction. Address for any location in the 64K memory space. The address of a bit in the internal RAM bit address area or a bit in an SFR. The carry flag. An 8-bit binary number from 00 to FFh. A 16-bit binary number from 0000 to FFFFh. An internal RAM address or an SFR byte address. Least significant nibble. Most significant nibble. Number that is added to the address of the next instruction to form an address +127d to 128d from the address of the next instruction. Any of registers R0 to R7 of the current register bank. Indirect address using the contents of R0 or R1. IF the condition inside the brackets is true, THEN the action listed will occur; ELSE go to the next instruction. EXTERNAL memory location. Contents of the location inside the parentheses.

Note that flags affected each instruction are shown where appropriate; any operations which affect the PSW address may also affect the flags.