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[Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
= (W/Lp)/(W/Ln)
tpLH tpHL
4.5
tp
of 2.4 (= 31 k/13 k) gives symmetrical response of 1.6 to 1 9 gi es 1 6 1.9 gives optimal performance
3.5 3
3 1 2 3 4 5
= (W/Lp)/(W/Ln)
Out
Heads up
This lecture
Logical Effort
- Reading assignment textbook pp251-257, and handout
Next lecture
Designing energy efficient logic
- R di assignment R b Reading i Rabaey, et al, 5.5 & 6 2 1 l 6.2.1
History
First proposed by Ivan Sutherland and Bob Sproull in 1991
Logical Effort: Designing for Speed on the back of an Envelope, IEEE Advanced Research in VLSI, 1991 Both authors are vice president and fellow at Sun Microsystems
Inverter Delay
Divide capacitive load CL, into load,
Cint : intrinsic - diffusion and Miller effect (Cg) Cext : extrinsic - wiring and fanout
Split delay of logic gate into three components Delay = Logical Effort x Electrical Effort + Parasitic Delay Logical Effort Complexity of logic function (Invert, NAND, NOR, etc) Define inverter has logical effort = 1 Depends only on topology not transistor sizing Electrical Effort Ratio of output capacitance to input capacitance Cout/Cin Parasitic Delay Intrinsic delay Independent of transistor sizes and output load
Sp11 CMPEN 411 L12 S.8
Example
Estimate th d l E ti t the delay of an inverter driving 4 identical f i t di i id ti l inverter: (FO4)
g=
h=
p=
d=
Example
CL
CL
Questions
d = gh+p How to derive the model from Elmore delay model? Why logical effort g is independent of transistor sizing? How to calculate parasitic delay p ? Why it is independent of transistor sizing? How to calculate single delay parameter: What if the ratio of p-type to n-type transistor widths changes?
g
Sp11 CMPEN 411 L12 S.20
Parasitic Delay
CgateP
Main cause is drain capacitances These scale with t Th l ith transistor width i t idth so it is independent of transistor sizes For inverter:
RonP
CdrainP
RonN
CgateN
~= 15 ps for 0.18um
For each stage: Delay = Logical Effort x Electrical Effort + Parasitic Delay = 1.0 (definition) x 1.0 (in = out) + 1.0 (drain caps) = 2.0 units
Path logical effort, G = gi Path electrical effort, H = Cout/Cin Parasitic d l P iti delay, P = pi Path effort, F= fi = gi hi D= D F+P
G H GH h1 h2 F
= = = = = = GH?
5
15
90
15
90
G H GH h1 h2 F
15
90
15
90
Multistage Networks
Path electrical effort: H= Cout/Cin Path logical effort: G = g1g2gN g Branching effort: B = b1b2bN Path ff t F= P th effort: F GBH Path delay D = F+P=GBH+P
f 64
tp 65
18
15
2.8
15.3
Summary