COGNITION TECH LABS

FPGA

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Implementation of image reconstruction algorithm using compressive sensing in Implementation of algorithm for detection and correction of defective pixels in FPGA
1.

Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder

FPGA implementation of graph cut based image thresholding Efficient FPGA implementation of steerable Gaussian smoothers Background subtraction algorithm for moving object detection in FPGA Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA High speed FPGA implementation of hough transform for real-time applications Real time hardware co-simulation of Edge Detection for video processing system An FPGA embedded system architecture for handwritten symbol recognition 2D/3D FPGA array for brain process and numerical computation A moving window architecture for a HW/SW codesign based Canny edge detection for FPGA A low computing power frame rate converter An FPGA-based accelerator for cortical object classification New digital Pulse-Mode Neural Network based image denoising FPGA design of H.264/AVC intra-frame prediction architecture for high resolution video encoding FPGA implementation of chaotic state sequence generator for secure communication An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion FPGA based real time face detection using Adaboost and histogram equalization

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FPGA

Mobile no.: +91-9043451654, +91-9786866345

Implementation of image reconstruction algorithm using compressive sensing in Multichannel Pulse-Coupled-Neural-Network-Based Color Image Segmentation for Object Detection VLSI Implementation of a Bio-Inspired Olfactory Spiking Neural Network VLSI Implementation of Advanced Encryption Standard A novel architecture for VLSI implementation of RSA cryptosystem Analysis and VLSI Implementation of EWA Rendering for Real-time HD Video Applications Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm Implementation of VLSI-oriented FELICS algorithm using Pseudo Dual-Port RAM VLSI design and implementation of reconfigurable OFDM transceivers for software defined radio An adaptive, linear-line approximation method and its VLSI implementation for maximum power control of photovoltaic system VLSI implementation with double cipher and media processing for ad-hoc network Modified Redundant Representation for Designing Arithmetic Circuits with Small Complexity Design and implementation of high-performance high-valency ling adders Fast two-pick n2n round-robin arbiter circuit A Scalable Architecture for Dual Basis GF(2m) Multiplications Design and implementation of low power FFT/IFFT processor for wireless communication Hardware Efficient Architecture for Generating Sine/Cosine Waves

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Presence of Multiple Transient Errors

Mobile no.: +91-9043451654, +91-9786866345

Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing Low-power Logarithmic Number System Addition/Subtraction and their Impact on Digital Filters A novel VLSI architecture for generation of Six Phase pulse compression sequences VLSI signal processing oriented segmentation based serial parallel multiplier VLSI Based Robust Router Architecture A fault tolerant parallel-prefix adder for VLSI and FPGA design Highly secured high throughput VLSI architecture for AES algorithm A Novel Interpolation Chip for Real-Time Multimedia Applications A Nonbinary LDPC Decoder Architecture With Adaptive Message Control Design of Low Power TPG Using LP-LFSR A high throughput sort free VLSI architecture for wireless applications A non linear equation based cryptosystem for image encryption and decryption Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes Hardware Implementation of Nakagami and Weibull Variate Generators Dual-Layer Adaptive Error Control for Network-on-Chip Links Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip CORDIC Designs for Fixed Angle of Rotation

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Routing-efficient architecture implementation of an

Mobile no.: +91-9043451654, +91-9786866345

internal-response-based

BIST

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT Hardware Implementation of a Digital Watermarking System for Video Authentication VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform Implementation of random walk algorithm by parallel computing Scalable Packet Classification on FPGA Throughput/Resource-Efficient Applications Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA Hardware Implementation of a Digital Watermarking System for Video Authentication Techniques for Compensating Memory Errors in JPEG2000 Derating based hardware optimizations in soft error tolerant designs High-Speed Low-Power Viterbi Decoder Design for TCM Decoders Construction of Optimum Composite Field Architecture for Compact HighThroughput AES S-Boxes A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories Design and implementation of an optical OFDM baseband receiver in FPGA An FPGA Chip Identification Generator Using Configurable Ring Oscillators VLSI Architecture of Arithmetic Coder Used in SPIHT Reconfigurable Processor for Multimedia

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A Network-on-Chip-based turbo/LDPC decoder architecture
2.

Mobile no.: +91-9043451654, +91-9786866345

Reconfigurable Accelerator for the Word-Matching Stage of BLASTN Real-time multi-view rendering based on FPGA Performance Using FPGA Correlator The design and implementation of fire smoke detection system based on FPGA Real-Time Vehicle Identification Hardware A multifunctional, reconfigurable pulse generator for high-frequency ultrasound imaging Gesture recognition using field programmable gate arrays A hardware acceleration of a real time video processing Lossy Compression of Discrete Sources via the Viterbi Algorithm FPGA implementation of IEEE 802.15.3c receiver