MOORE MACHINES

In the theory of computation, a Moore machine is a finite-state machine, whose output values are determined solely by its current state. A Moore machine can be defined as a 6-tuple ( S, S0, , , T, G ) consisting of the following:

a finite set of states ( S ) a start state (also called initial state) S0 which is an element of (S) a finite set called the input alphabet ( ) a finite set called the output alphabet ( ) a transition function (T : S S) mapping a state and the input alphabet to the next state an output function (G : S ) mapping each state to the output alphabet

The Moore machine is a finite state transducer.

MEALY MACHINES
In the theory of computation, a Mealy machine is a finite-state machine whose output values are determined both by its current state and by the values of its inputs. The outputs change asynchronously with respect to the clock, meaning that the outputs change at unpredictable times, making timing analysis harder. (This is in contrast to a Moore machine, whose output values are determined solely by its current state.) A Mealy machine is a 6-tuple, (S, S0, , , T, G), consisting of the following:

a finite set of states (S) a start state (also called initial state) S0 which is an element of (S) a finite set called the input alphabet () a finite set called the output alphabet () a transition function (T : S S) mapping pairs of a state and an input symbol to the corresponding next state. an output function (G : S ) mapping pairs of a state and an input symbol to the corresponding output symbol.

In some formulations, the transition and output functions are coalesced into a single function (T : S S ).

BEHAVIOURAL MODELING
The behavioral modeling of the sequence 1011000 for moore and mealy is given below: 1) Moore FSM
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY moore IS port(x,clk:in BIT; z:out std_logic); END ENTITY moore; ARCHITECTURE moore_beh OF moore IS type moore_type is(s0,s1,s2,s3,s4,s5,s6,s7); signal p_state,n_state:moore_type; begin process(clk) begin if (clk='0' and clk'event)then p_state<=n_state; end if; end process; process (p_state,x) begin case p_state is when s0=>z<='0';

if (x='1')then n_state<=s1; elsif (x='0')then n_state<=s0; end if; when s1=>z<='0'; if (x='1')then n_state<=s1; elsif (x='0')then n_state<=s1; end if; when s2=>z<='0'; if (x='1')then n_state<=s3; elsif (x='0')then n_state<=s2; end if; when s3=>z<='0'; if (x='1')then n_state<=s4; elsif (x='0')then n_state<=s3; end if; when s4=>z<='0'; if (x='1')then n_state<=s4; elsif (x='0')then n_state<=s4; end if; when s5=>z<='0'; if (x='1')then n_state<=s3; elsif (x='0')then n_state<=s5; end if; when s6=>z<='0'; if (x='1')then n_state<=s7; elsif (x='0')then n_state<=s6; end if; when s7=>z<='1';

if (x='1')then n_state<=s0; elsif (x='0')then n_state<=s7; end if; end case; end process;

END ARCHITECTURE moore_beh; OUTPUT:

2. Mealy FSM
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mealy IS port(x,clk:in BIT; z:out std_logic); END ENTITY moore; ARCHITECTURE mealy_beh OF mealy IS type mealy_type is(s0,s1,s2,s3,s4,s5,s6,s7); signal p_state,n_state:mealy_type; begin process(clk) begin if (clk='0' and clk'event)then p_state<=n_state; end if; end process; process(p_state,x) begin case p_state is when s0=> if (x='1')then n_state<=s1;z<='0'; elsif (x='0')then n_state<=s0;z<='1'; end if; when s1=> if (x='1')then n_state<=s1;z<='0'; elsif (x='0')then n_state<=s1;z<='1';

end if; when s2=> if (x='1')then n_state<=s3;z<='0'; elsif (x='0')then n_state<=s2;z<='1'; end if; when s3=> if (x='1')then n_state<=s4;z<='0'; elsif (x='0')then n_state<=s3;z<='1'; end if; when s4=> if (x='1')then n_state<=s4;z<='0'; elsif (x='0')then n_state<=s4;z<='0'; end if; when s5=> if (x='1')then n_state<=s3;z<='0'; elsif (x='0')then n_state<=s5;z<='0'; end if; when s6=> if (x='1')then n_state<=s7;z<='0'; elsif (x='0')then n_state<=s6;z<='1'; end if; when s7=> if (x='1')then n_state<=s0;z<='1'; elsif (x='0')then n_state<=s7;z<='1'; end if; end case; end process;

END ARCHITECTURE mealy_beh; OUTPUT:

STRUCTURAL MODELING
File1.vhd Entity and3 is Port(B,B0,C:in std_logic; D:out std_logic); End entity and3; Architecture one_line of and3 is Begin D<= (B and B0) and C; End one_line; File2.vhd Entity and4 is Port(E,F,G,H:in std_logic;I:out std_logic); End entity and4; Architecture one_line of and4 is Begin I<= (E and F) and (G and H); End one_line; File3.vhd Entity and2 is Port(J,K:in std_logic;L:out std_logic); End entity and2; Architecture one_line of and2 is Begin L<=J and K; End one_line; File4.vhd Entity or3 is Port(M,N,O:in std_logic;P:out std_logic); End entity or3; Architecture one_line of or3 is Begin P<= (M or N) or O; End one_line; File5.vhd Entity or4 is Port(Q,R,S,T:in std_logic;U:out std_logic); End entity or4; Architecture one_line of or4 is Begin U<= (Q or R) or (S or T); End one_line;

File6.vhd Entity or5 is Port(V,W,X,Y1,Z:in std_logic;Y0:out std_logic); End entity or5; Architecture one_line of or5 is Begin Y0<= (V or W) or (X or Y1) or Z; End one_line; File7.vhd Entity inv is Port(A0:in std_logic;A1:out std_logic); End entity inv; Architecture one_line of inv is Begin A1<=not(A0); End one_line; File8.vhd Entity dff is Port(pr,cr,D0,clk:in std_logic;Q0,Qbar:out std_logic); End entity dff; Architecture one_line of dff is Begin Process(clk) Begin If (cr=0)then Q0<=0; Qbar<=1; Elsif(pr=0)then Q0<=1; Qbar<=0; Elsif(clk=1 and clkevent)then Q0<=D0; Qbar<=not(D0); End if; End process; End one_line;

Entity sequence_detector is Port(Q0,Q1,Q2,A:in std_logic;Y:out std_logic); End sequence_detector; Architecture sequence_struct of sequence_detector is Component inv Port(A0:in std_logic;A1:out std_logic); End component;

Component and3 Port(B,B0,C:in std_logic; D:out std_logic); End component; Component and4 Port(E,F,G,H:in std_logic;I:out std_logic); End component; Component and2 Port(J,K:in std_logic;L:out std_logic); End component; Component or3 Port(M,N,O:in std_logic;P:out std_logic); End component; Component or4 Port(Q,R,S,T:in std_logic;U:out std_logic); End component; Component or5 Port(V,W,X,Y1,Z:in std_logic;Y0:out std_logic); End component; Component dff Port(pr,cr,D0,clk:in std_logic;Q0,Qbar:out std_logic); End component; Signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22:std_logic; Begin I1:inv port map(A,s1); A1:and3 port map(s1,s2,s17,s5); A2:and4 port map(s1,s2,s17,s20,s6); A3:and4 port map(A,s3,s17,s19,s7); A4:and3 port map(s1,s3,s19,s8); A5:and3 port map(s2,s18,s19,s9); A6:and4 port map(s1,s2,s17,s20,s10); A7:and4 port map(A,s19,s17,s3,s11); A8:and2 port map(A,s2,s12); A9:and3 port map(s2,s18,s20,s13); A10:and3 port map(s2,s17,s20,s14); A11:and3 port map(A,s18,s3,s15); A12:and3 port map(A,s20,s17,s16); A13:and3 port map(s2,s17,s19,Y); Dff1:dff port map(s4,s2,s3); Dff2:dff port map(s21,s17,s18); Dff3:dff port map(s22,s19,s20); O1:or3 port map(s5,s6,s7,s4);

O2:or4 port map(s8,s9,s10,s11,s21); O3:or5 port map(s12,s13,s14,s15,s16,s22); End Architecture sequence_struct;