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Code No: RR321202 Set No.

1
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
VLSI SYSTEMS DESIGN
(Information Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. Implement the following gates with n-MOS transistors only and explain its working

(a) 3 ? Input NAND gate.


(b) Inverter. [8+8]

2. An p-MOS transistor is operating in the triode region with the following parameters
µn Cox = 95 µ A/V 2 W/L ( ratio) = 90 V gs = −4V, Vtn = −1.1V, Vds = −2V .
Find its drain current & drain -Source resistance. [16]

3. Explain about different spice - parameters of MOS transistor and their significance.
[16]

4. Design a layout for CMOS 3-input NOR gate. [16]

5. What do you mean by transistor sizing? With suitable example explain, how
transistor sizing can improve the speed of a combinational logic. [16]

6. Design a logic gate network for full adder

(a) Using Two-level logic


(b) Using multi-level logic [8+8]

7. Explain how sequential ASM states are implemented as data path and controller.
[16]

8. Clearly explain about the generic integrated circuit design flow. [16]

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Code No: RR321202 Set No. 2
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
VLSI SYSTEMS DESIGN
(Information Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with p-MOS transistors only and explain its working

(a) 2 ? Input NAND gate.


(b) 3 ? Input NOR gate. [8+8]

2. An p-MOS transistor is operating in the triode region with the following parameters
µn Cox = 95 µ A/V 2 W/L ( ratio) = 90 V gs = −4V, Vtn = −1.1V, Vds = −2V .
Find its drain current & drain -Source resistance. [16]

3. Design a stick diagram for two-input N-MOS NAND and NOR gates. [16]

4. (a) What do you mean by layout of a component?


(b) Draw neat layout diagram for NMOS transistor [8+8]

5. Explain with suitable example the details of single - Row layout design method.
[16]

6. With neat circuit diagram explain working principle of transistor DRAM cell with
two bit lines and one word line. [16]

7. Explain clearly block placement phase of the Floor planning of the chip with suit-
able examples. [16]

8. Write a register-transfer description of one four-digit timer. [16]

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Code No: RR321202 Set No. 3
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
VLSI SYSTEMS DESIGN
(Information Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with n-MOS transistors only and explain its working

(a) 2 ? Input NAND gate.


(b) 3 ? Input NOR gate. [8+8]

2. Explain about different computer aided design tools used in designing Integrated
Circuits. [16]

3. Design a stick diagram for CMOS logic shown below.


Y = (AB + CD)1 [16]

4. Design a layout for CMOS 2-input AND gate. [16]

5. How cross-talk appears in ICs and explain how this cross-talk can be minimized in
ICs. [16]

6. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]

7. Explain about different packaging technologies used in IC packaging. [16]

8. Clearly explain about the generic integrated circuit design flow. [16]

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Code No: RR321202 Set No. 4
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
VLSI SYSTEMS DESIGN
(Information Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with n-MOS transistors only and explain its working

(a) 2 ? Input OR gate.


(b) 4 ? Input NAND gate. [8+8]

2. What are the key advantages of ICs? And explain how these advantages of ICs
translate in to advantages at the system level. [16]

3. Design a stick diagram for CMOS logic shown below.


Y = (A + B + C + D)1 [16]

4. Compute the high-to-low delay of a two-input static complementary NOR gate with
minimum-sized transistor driving these loads.

(a) An inverter with minimum-sized pull up and pull down.


(b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ.
[8+8]

5. Explain in detail the path - delay measurement of the combinational logic circuits.
[16]

6. Draw the structure of a carry look ahead adder and explain its working principle.
[16]

7. Explain how Architecture driven voltage scaling technique reduces the power con-
sumption of the design. [16]

8. Explain about design methodology for 1BM ASICS. [16]

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