Code No: RR210203 Set No.

1
II B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Write the following binary numbers in signed 1’s complement form and signed
2’s complement form using 16 bit registers.
i. +1001010
ii. -11110000
iii. -11001100.1
iv. +100000011.111
(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2’s
complement representation. Verify your answers by using decimal addition
and subtraction
i. N1=00110010, N2=11111101
ii. N1=10001110, N2=00001101. [10+6]

2. (a) Simplify the function

P using Karnaugh
Pmap method
F (A,B,C,D) = (4,5,7,12,14,15)+ d(3,8,10).
(b) Give three possible ways to express the function
F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8]

3. (a) Derive Boolean expression for a 2input Ex-OR gate to realize with 2 input
NAND gates without using complemented variables and draw the circuit.
(b) Redraw the given circuit in (figure3b)after simplification. [8+8]

Figure 3b
4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.
(b) Implement Full adder circuit using ROM and Verify the working. [8+8]

5. (a) Give the transition tables for the following flip-flops

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Code No: RR210203 Set No. 1
i. T-Flip-Flop
ii. R-S flip-flop
(b) Draw the schematic circuit of J-K-Flip-Flop with negative edge triggering.
Convert this flip-flop to Toggle flip-flop (T). Give its truth-table, Justify the
entries in the truth-table [6+10]

6. Design a 4-bit universal shift register and draw the circuit with the given mode of
operation table. [16]
S1 S0 Operation
0 0 Parallel
0 1 Shift right
1 0 Shift left
1 1 Inhibit clock
7. What are the conditions for the two machines are to be equivalent? For the machine
given below, find the equivalence partition and a corresponding reduced machine
in standard form: [16]

PS NS,Z
X=0 X=1
A F,0 B,1
B G,0 A,1
C B,0 C,1
D C,0 B,1
E D,0 A,1
F E,1 F,1
G E,1 G,1

8. (a) Draw the state diagram and the state table of the control unit conditions given
below. Draw the equivalent ASM chart leaving the state box empty.
i. from 00 state, if x = 1 , it goes to 01 state and if x = 0, it remains in the
same state 00.
ii. from 01 state, if y = 1, it goes to 11 state and if y = 0, it goes to 10 state.
iii. from 10 stae, if x = 1 and y = 0, it remains in the same state 10 and if x
= 1 and y = 1, it goes to 11 state, and if x = 0, it goes to 00 state.
iv. from 11 state, if x = 1, y = 0, it goes to 10 state and if x = 1, and y =
1, it remains in the same state, and if x = 0, it goes to 00 state.
(b) Design the control using PLA and registers for the above problem. [8+8]

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Code No: RR210203 Set No. 2
II B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Write the following binary numbers in signed 1’s complement form and signed
2’s complement form using 16 bit registers.
i. +1001010
ii. -11110000
iii. -11001100.1
iv. +100000011.111
(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2’s
complement representation. Verify your answers by using decimal addition
and subtraction
i. N1=00110010, N2=11111101
ii. N1=10001110, N2=00001101. [10+6]

2. (a) Simplify the function

P using Karnaugh
Pmap method
F (A,B,C,D) = (4,5,7,12,14,15)+ d(3,8,10).
(b) Give three possible ways to express the function
F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8]

3. Implement the function F with the following two level forms

(a) NAND-AND,
(b) AND-NOR,
(c) OR-NAND and
(d) NOR-OR P
F (A, B, C, D) = (0,1,2,3,4,8,9,12) [16]

4. (a) Design a combinational circuit that accepts a 3-bit number and generates an
output binary number equal to the square of the input number.
(b) Realize a 3-bit odd-parity generator circuit using only two-input ex-or gate
[8+8]

5. (a) Compare synchronous logic system with asynchronous logic system.

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Code No: RR210203 Set No. 2
(b) Draw the schematic circuit of J-K-flip-flop with positive edge triggering, active
low preset and clear, using NAND gates. Give its truth-table and justify the
entries is the truth-table. [6+10]

6. Design a clocked sequential circuit to detect 1111 or 0000 and it will produce an
output z=1 at the end of sequence. Overlapping is allowed. Draw the circuit using
D flip flops. [16]

7. (a) Convert the following Mealy machine into a corresponding Moore machine:

PS NS,Z
X=0 X=1
A C,0 B,0
B A,1 D,0
C B,1 A,1
D D,1 C,0

(b) Design the circuit for the above table. [8+8]

8. (a) Explain in detail the block diagram of ASM chart.

(b) Draw the portion of an ASM chart that specifies the conditional operation to
increment register R during state T1 and transfer to state T2, if control inputs
z and y are = 1 and 0 respectively. [8+8]

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Code No: RR210203 Set No. 3
II B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Write the following binary numbers in signed 1’s complement form and signed
2’s complement form using 16 bit registers.
i. +1001010
ii. -11110000
iii. -11001100.1
iv. +100000011.111
(b) Perform N1+N2,N1+(-N2) for the following 8 bit numbers expressed in a 2’s
complement representation. Verify your answers by using decimal addition
and subtraction
i. N1=00110010, N2=11111101
ii. N1=10001110, N2=00001101. [10+6]

2. (a) Obtain the simplified expressions in sum of products for the following Boolean
functions using Karnaugh-Map.
P
i. F(A, B,C,D) = (7,13, 14, 15)
P
ii. F(w,x,y,z) = (2,3,12,13,14,15)
(b) Minimize the following Boolean expressions to the required no. of literals
i. BC +AC +AB+BCD to four literals
ii. ABC+ A BC + ABC+ABC+A B C to five literals
(c) Obtain complement and dual for the given expression (AB+BC+AC) (EF)
[6+6+4]

3. (a) Implement the following Boolen function F together with the don?t care con-
ditions D using not more than two NOR gates. Assume that both normal and
complement inputs are available.
P
F (A, B, C, D) = P(0.1.2.9,11)
D(A, B, C, D) = (8,10,14,15)
(b) What are universal gates. Why they are so called. Give their truth tables.
[12+4]

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Code No: RR210203 Set No. 3
4. (a) Give the schematic circuit of a 2-to-4 binary decoder with an active-low enable
input. Give the truth - table for the same.
(b) Give the gate-level realization for 8:1 mux with active-low enable input. Show
how several 8:1 muxes can be combined to make a 32-to-1 mux. [6+10]

5. (a) Give the transition tables for the following flip-flops

i. T-Flip-Flop
ii. R-S flip-flop
(b) Draw the schematic circuit of J-K-Flip-Flop with negative edge triggering.
Convert this flip-flop to Toggle flip-flop (T). Give its truth-table, Justify the
entries in the truth-table [6+10]

6. Design a 4-bit universal shift register and draw the circuit with the given mode of
operation table. [16]
S1 S0 Operation
0 0 Parallel
0 1 Shift right
1 0 Shift left
1 1 Inhibit clock

7. (a) Convert the following Mealy machine into a corresponding Moore machine:

PS NS,Z
X=0 X=1
A C,0 B,0
B A,1 D,0
C B,1 A,1
D D,1 C,0

(b) Design the circuit for the above table. [8+8]

8. (a) Design a digital system with three 4-bit registers, A, B and C to perform the
following operations by drawing the ASM chart.
i. Transfer two binary numbers to A and B when a start signal is enabled.
ii. If A<B, shift left the contents of A and transfer the result to register C.
iii. If A>B, shift right the contents of B and transfer the result to register C.
iv. If A+B, transfer the number to register C unchanged.
(b) Realize the above using JK flipflops and D flip flops. [8+8]

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Code No: RR210203 Set No. 4
II B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Why are complements used in binary arithmetic.

(b) What are the advantages and disadvantages of using 2‘s complement notation
in binary arithmetic
(c) Carry out the following computations after first converting each negative
operand to 2’s complement notation
check your results in each
0.10001 − 0.10101
− 0.11011 − 0.11010 [2+4+10]

2. (a) Obtain the simplified expression in sum of products for the following Boolean
functions using Karnaugh-Map.
P P
i. F(w,x,y,z) = (1,3,7,11,15) + d (0, 2, 5)
ii. F(A, B,C,D) = ABD+ A C D+ A B+ A C D+A B D
(b) Show the truth table for each of the following function and find its simplest
product of sums form.(POS)
i. f (x, y, z) = xy + xz
ii. f (x, y, z) = x + yz [8+8]

3. (a) Implement the following Boolen function F together with the don?t care con-
ditions D using not more than two NOR gates. Assume that both normal and
complement inputs are available.
P
F (A, B, C, D) = P(0.1.2.9,11)
D(A, B, C, D) = (8,10,14,15)
(b) What are universal gates. Why they are so called. Give their truth tables.
[12+4]

4. (a) Write a note on ‘display decoders’

(b) Design a 4 to 1 mux using a 2 to 4 decoder and basic gates. [8+8]

5. (a) Define a sequential system and how does it differ from a combinational system?

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Code No: RR210203 Set No. 4
(b) Draw the schematic circuit of a negative edge-trigger S-R-Flip-Flop with “ac-
tive low preset” and “active low clear” inputs using NAND gates and explain
its operation with the help of Truth-Table [6+10]

6. A sequential circuit has three D flip-flops, A, B, C and one input x.. It is described
by the following flip-flops input functions
DA = (BC 1 + B 1 C)x + (BC + B 1 C 1 )x1
DB=A
DC=B

(a) Derive the state stable for the circuit.

(b) Draw two state diagrams one for x=0, and the other for x=1. [16]

7. Find the equivalence partition and a corresponding reduced machine in standard

form. [16]

PS NS, 2
X=0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0
F C,1 C,1
G C,1 D,1
H C,0 A,1

8. (a) Construct an ASM chart for a decimal system that counts the number of
people in a room. People enter the room from one door, with a photocell that
changes a signal x from 1 to 0, when the light is interpreted. They leave the
room from a second door, with a similar photocell with a signal y. Both x and
y are synchronized with a clock but they may stay on or off for more than
one clock pulse period. The data processor subsystem consists of an up down
counter with a display of its contents.
(b) Design a four bit counter with synchronous clear with a diagram specified in
the data processor [8+8]

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