#1 2012- Midterm 129 EE/CPE - Spring

-1-

tr) [12points]BASIC GATESAND DEVICES:

a) Below are Truih Tablesthat describedifferentbasic logicgates or digitaldevices(1 for iype of logicgate/device each table). Complete the requested information for eaclr device.
\ * Tr]j [A

B
0
1

0
0
I

Output 1 I
I

i'l

0 0
l

Lf, fjI

0 1

1
{

A 0 0 1
1

B 0 1 0
I

Output
O

I
2:

Draw this Logic Gate SYmbol:

Complete the Truth Table (above)

Name:hiei\ii? [, ll T t Device
Determinethis Device'soutput for the conditionsgiven below:

A i r . s i t ^

B
I

DI
I

DO
I

Output

0
I

1 0 0

1 0 1

0
I

1
Output 1 0

ffi

D0

0
Sel

Devic

EE/CPE - Spring l2q 2012 Midterm fit

-2-

2) [20 points] Given the following BooleanLogic function's Truth Table:

Fr(X.Y,Z)

Fxx,y.,z) F3(X,,Y,,L',) F . { 4 )
\.)

0 0 0 0 1
I I

0 0 1 I 0 0 1
I

0 I 0
I

0 0 0
I
d

0
$

c)
t

I
IJ

0
I

0
I

0 1 I 1

t i

I
0
{

o
I l

(a) Expressthe function,FTin compactminterm form (minterm list): F1(X,Y,Z):

(b) Express the same function Fl as a eauonreal Product-of-Sums (pOS)

using the input signalsX,Y.Z in a Booleanlogic expression.

F1(X,y,Z)

= i A " 8* e

fr,+ $-Z

11t' 1i -'tt

h + i !* f )

(c) Fill in the Truth Table for the following Booleanfunction:

F2(X,y,Z) - Fl NAND Z
(d) Fill in the Truth Table for the following Booleanfunction: (HINT. If you needmore than I minute to do this, comeback to it later.)

F,(x,y, - (x.y.z)+(X.f.z)+(X.y.z) z)
lc 1 -'6 f i - rf I

EEICPE i)9

2012-Midterm #1 Spring

F4(x z) - (w.x.Y\+ (v.z) .,Y,

i r':) *naiir a schematic diagram for a circuit implementation that provides the same output as the new function Fa(above),using the following constraints: XoR, or . You may use ONLY 1 TYPEOF LOGICGATE (AND, NOR, OR,NAND, (includinq makinq anv invertersneeded'usinq this XNOR) ALL functions for

n Use as few gatesas possible(butdo not try to reducethisexpression further). gatesare o Every one of yourlogicgates must have4 inputs (no 1, 2 or 3-input youaredoingwith anyunusedgateinputs! what Be available). sureto indicate (i.e.74xx138), lC pin#'s are notrequired. & (U1 iC f,r's , U2),lC identifiers

g.t:ro-lypc-of .g.alc.l.

Y L. ut ^ I

L-.''.

\s F,[*, r,,];a)

v x\t

\ Y ?'-' e u t : t I l i l U

. ,

A<,t

el

OI fI

C o

i' I I

tct 0

Ul
/u o6
haaar,\

o
NO

(0 Does your circuit implementation have a logic hazard?

Explain how did you determinedwhether it does or does not?

K- },IA , P
s t,tii t

n,r& Y ir

tul,e,tr \l = 0 r X = | , V = l lssfutttn 0 A n 6 .I , sun!,thixn

l"r h+.re l^p

I L, l,

EE/CPE - Spring 129 2012- Midterm #1

3) [25 points] Using the K-Maps below, determine the indicated minimized form of the mapped logic functions. Show vour sroupings in the K-Maps.

cD
A
FI

00
0

ol

ll

lo

C D

d I

t l

00

ol
li

etc etc etc.

t l

Ca _l
0 0 0 0

elc. in the usual order

a s\-Qq-Sqr+$sl
00

0 0

0l U
) d

etc etc etc.

qJ
r)

fr

Io

( a ) M i n i m u mS O P

(b) Minimum Hazard-Free POS

(a) Most Minimum Sum-of-ProductsLogic Expression(ignoring logic any hazards):

F r ( A , B , n ,n )) : ( n ' e t - ( n ' a+ fc ' D +

(b) Minimum" Hazard-Free Product-of-SumsLogic Expression: Fj(A,B,C,D):

n rB * D .) { a * b * A \ [, c " - [ + n
. [ n * B + z .) ( L + D + f t ) [ t r+ B + D )

EE/CPE 129 Spring 2012Midterm #1

-5-

(d) Show the K-Map groupines you would use to create the Best HazardFree Minimum Sum-of-Products Logic Expressions for the same function F3as in Part (a) [below left *]; and for new function F5 [below right 9]:

D A B \ 00 elc. in the usual order )A00 0 { l l 1 0

\c
etc etc etc.

cD
A
EI

00

t"t". in theusualorder

5r-

l r \u T----.. \!\

=l---\l

l--l

D 'e
0 0 ( 1 0

00
etc etc etC.

{r rI
I 1 1
))

l l

0
-

0 0 0

t
-5<a

t|-

:y

q_

\ rJ

Hazard-Free Minimum SOP of F3(A,B,C,D)

Hazard-Free Minimum SOP of Fs(A,B,G,D)

(You do NOT have to detetmine the Hazard-Free Logic Expressions. Just show the K-Map groups you would use to creqte theseexpressions.)

(e) Using the K-Map for F3(A,B,C,D)[aboveleft 6], write out a Truth Table for the logic function F3:

o
o U
0
fl

A
flt

a D
J
!..:t
t.)

{'-* 0
o
I
I

+ o
z
?
t4

u
J
d

'J
{ : } ff '
j

,f -l
o
A

o
()

d 0

:J

,J
!j

{l
i

(i
!

I
l!

I
i

tL
tl
i I

ii

{q

EEICPE129 Spring2012- Midterm#i

/

4) [20 points] Perform the following number conversions. You may assume the numbers are all positive (unsigned) integers.

( (a) (22)rc2 L l ( Y t l z \

lo ll o

),

1 o l { o
I -L

(b) (44)n: (

2L

tr6

u
{

\L tlt

' u r 'r o " i

(c) ( 1 yLelo: a 0 l o1 o u
00l0 Pat
-

Y r l

b
1 t
1 )" \ 'A

rr
l ]

g
f

)B;nary CodedDI"i-nl'

(d) (llolilol)z: ( b ' D

(e) (101101)2 (
4t-1184 | 7

6D
Ltg

)ro

)ro

1 t + \ + \ + I - t'lt

EF,ICPEl29 Spring2012Midterm#1

5) [15 points] Analyze the logic circuit below to determine F(A,B,C,D):

A
F(A,B,C,D)

(a) Write a Boolean logic expression for the output function F(A,B,C,D) fiom the circuit above,in a form that exactlv matches the implementation shown above. (You should NoT simplify or minimize the expressions.) Your answershould make it obvious exactly what tlpe of logic gateswere actually used above.

( A * E"l
F"inu;1(A,B,C,D) :

' ( B ' r . ).
7 i i ^ , - i l l

T '

ll\+lJ)'IHt*tj'v

b) Write a standard version of the Boolean logic function F in sum-of-products or productpI-Sg4t!-fo@, using Boolean Algebra theorems(DeMorgan's, etc.) and propertiesto accomphsh the requiredtransfotmation,(Createan expressionthat only usesAND' OR, and singleSHQW HOW YOU variable NOT operations,no NAND, NOR, XOR, XNOR terrns all^owed).

ARRIVEDATYqURANSWER.

I =*----::U-a-

<---r-..-

]-)"I :,
\ \ " /. , -L , '
.--"'-

--*--'"-i
-* _,.*::...

"n

\
.

l
,.-n

'll {4

d \t l
L }
\--'l

. t

t)
F"6r4ur4(A,B,C,D) =

/'

EE/CPE129- Spring2012- Midterm#1

6) [8 points] Timing Analysis:

Y
(a) The Timing Diagram below shows the operation of the circuit drawn above. Using the Timing Diagram, determine the missing values for the various gate propagation delays in the table below. (You do NOT needto label theseon the diagram.) (Assumethat the input signalshavebeen steadyat their prior initial values shown for )> 2Onsec. to the beginning of this diagram.) Gate:
toHL
toLII

AND
l0 5 nsec nsec

XOR
-7-S

nsec
nsec

X Y :
H

Z L

F
0 10
15

20

25

30

35

40

45 nsec

EE/CPE129- Winter2012- Midtem #1

Problem

Score

Max

I
)

ltLO

3 4
5

l c

I<
()

6 Total

q q

12 20 25 20 15 8 100

The above table is for INSTRUCTOR USE ONLY.