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which model?
where memory areas are located at sequential addresses; regardless of in what device they physically exist. Within the 8051 CPU there is one such memory, the DATA on-chip RAM . This starts at D:00H
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(the 'D:' prefix implies DATA segment) and ends at D:7fH (127 decimal). This RAM can be used for program variables. It is directly addressable, so that instructions like 'M OV A,x' are usable. Above 80H the special function registers are located, which are again directly addressable. However, a second memory area exists between 80H and 0FFH which is only indirectly addressable and is prefixed by I: and known as IDATA. It is only accessible via indirect addressing (M OV A,@Ri) and effectively overlays the directly addressable SFR area. This constitutes an extended on-chip RAM area and was added to the ordinary 8051 design when the 8052 appeared. As it is only indirectly addressable, it is best left for stack use, which is, by definition, always indirectly addressed via the stack pointer SP. Just to confuse things, the
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normal directly addressable RAM from D:00H-D:80H can also be indirectly addressed by the M OV A,@Ri instruction!
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Get the PC tool for programming NXP flash microcontrollers Learn more and download... A third memory space, the CODE segment, also starts at zero, but this is reserved for the program. It typically runs from C:0000H to C:0FFFFH (65536 bytes) but as it is held within an external Flash, it can be any size up to 64KB (65536 bytes). The CODE segment is accessed via the program counter (PC) for opcode fetches and by DPTR for data. Obviously, being ROM , only constants can be stored here. A fourth memory area is also off-chip, starting at X:0000H. This exists in an external RAM device and, like the C:0000H segment, can extend up to X:0FFFFH (65536 bytes). The 'X:' prefix implies the external XDATA segment (sometimes also referred to as XRAM ). The 8051's only 16bit register, the DPTR (data pointer) is used to access the XDATA. Finally, 256 bytes of XDATA can also be addressed in a paged mode. Here an 8-bit register (R0) is used to access this area, termed PDATA.
The obvious question is: "How does the 8051 prevent an access to C:0000H resulting in data
The obvious question is: "How does the 8051 prevent an access to C:0000H resulting in data being fetched from D:00H?" The answer is in the 8051 hardware: When the CPU intends to access D:00H, the on-chip RAM is enabled by a purely internal READ signal - the external /RD pin is unchanged.
1. MOV A,40 ; Put value held in location 40 into the accumulator.
This addressing mode (direct) is the basis of the SM ALL memory model.
1. 2. MOV R0,#0A0H ; Put the value held in IDATA location 0A0H into MOV A,@R0 ; the accumulator
This addressing mode is used to access the indirectly addressable on-chip memory above 80H and as an alternative way to get at the direct memory below this address. A variation on DATA is BDATA (bit data). This is a 16 byte (128 bit) area, starting at 020H in the direct segment. It is useful in that it can be both accessed byte-wise by the normal M OV instructions and addressed by special bit-orientated instructions, as shown below:
1. 2. SETB 20.0 ; CLRB 20.0 ;
The external ROM device (C:0000H) is not enabled during RAM access. In fact, the external ROM is only enabled when a pin on the 8051 named the PSEN (program store enable) is pulled low. The name indicates that the main function of the ROM is to hold the program that is executed on the CPU. The XDATA RAM and CODE ROM do not clash, as the XDATA device is only active during a request from the 8051 pins named READ or WRITE, whereas the CODE device only responds when the PSEN pin is low. To help access the external XDATA RAM , special instructions exist, conveniently containing an 'X'...
1. 2. MOV DPTR,#08000H MOVX A,@DPTR ; "Put a value in A located at address in the external RAM, contained in the DPTR register (8000H)".
The above addressing mode forms the basis of the LARGE model.
1. 2. MOVX R0,#080H ; MOVX A,@R0 ;
This alternative access mode to external RAM forms the basis of the COM PACT memory model. Note that if Port 2 is attached to the upper address lines of the RAM , it can act like a manually operated "paging" control. The important point to remember is that the PSEN pin is active when instructions are being fetched; READ and WRITE are active when M OVX.... ("move external") instructions are being carried-out. Note that the 'X' means that the address is not within the 8051 but is contained in an external device, enabled by the READ and WRITE pins.
SM ALL: all variables and parameter-passing segments will be placed in the 8051's internal memory. COM PACT: variables are stored in paged memory addressed by ports 0 and 2. Indirect addressing opcodes are used. On-chip registers are still used for locals and parameters. LARGE: variables etc. are placed in external memory addressed by @DPTR. Onchip registers are still used for locals and parameters. 3. BANKED: Code can occupy up to 1M B (Keil Compiler) or 4M B (Raisonance Compiler) by using either CPU port pins or memory-mapped latches to page memory above 0FFFFH. Within each 64KB memory block a COM M ON area must be set aside for C library code. Inter-bank function calls are possible. In addition, the Raisonance Compiler provides a TINY memory model, which is identical to the SM ALL memory model, except that ACALL and AJM P instructions are generated rather than LCALL and LJM P. This limits the code size to 2K bytes and is useful for those devices that do not support the LCALL and LJM P instructions. However when considering memory spaces the TINY and SM ALL memory models are identical. A variation on these models is to use one model globally and then to force certain variables and data objects into other memory spaces.
Best For:
Best For: Frequently accessed data requiring the fastest access. Interrupt routines whose run time is critical should use DATA, usually by declaring the function as "SM ALL". Another recommended usage is for background code that is frequently run and has many parameters to pass. If you are using re-entrant functions, the re-entrant stacks should be located here as a priority. Worst For: Variable arrays and structures that contain more than a few bytes. IDATA; 128 bytes or 256 bytes; Not model-dependant Best For: Fast access to data arrays and structures of limited size (up to around 32 bytes each) but not totalling more than 64 or so bytes. As these data types require indirect addressing, they are ideally placed in the indirectly addressable area. The stack is also located in IDATA as it is indirectly addressed. Worst For: Large data arrays and/or fast access words. CODE: 64K bytes Best For: Constants and large lookup tables, plus opcodes, of course! Worst For: Variables! It's ROM - Read Only M emory that can not be written to. PDATA: 256 bytes; COMPACT model default area Best For: M edium speed interrupt and fast background char (8 bit) variables and moderate-sized arrays and structures. Also good for variables which need to be viewed in real-time using an in-circuit emulator with dual ported memory. Worst For: Very large data arrays and structure above 256 bytes. Very frequently used data (in interrupts etc..). Integer and long data. XDATA; up to 64K bytes; LARGE model default area Best For: Large variable arrays and structures (over 256 bytes) Slow or infrequently-used background variables. Also good for variables which need to be viewed in real-time using an in-circuit emulator with dual ported memory. Worst For: Frequently-accessed or fast interrupt variables.
as the first line in the C source file. SM ALL is the default model and can be used for quite large programs, provided that full use is made of PDATA and XDATA memory spaces for less time-critical data.
resulting COM PACT program will not work. When using the Keil Compiler it is essential to set the PPAGE number in the startup.a51 file to some definite value - zero is a good choice. The PPAGEENABLE must be set to 1 to enable paged mode. Failure to do this properly can result in very dangerous results, as data placement is at the whim of PORT2! The Raisonance Compiler sets up P2 and enables paged mode automatically. When linking, the PDATA(ADDR) control must be used to tell the linker/locator where the PDATA area is.
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