Microelectronic Circuits

Common source amplifier

Single stage MOS amplifier

with drain-to gate feedback bias

Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.
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CSA with current mirror bias

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CSA with potential divider bias

Ac model with dc bias

No change in ac model with different biasing schemes So, for ac analysis, biasing circuit is not considered

T model

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Common Source

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Why do we need a capacitor Cs?

Without Cs. Vgs vin, As a result a.c current becomes small [gm (vgs-vx)] Hence drop across Rd reduces Gain reduces
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Pmos CSA

Common Source
Bias point Given--Kn= 80uA/v2, Vt=1v, Vdd= 5v Suppose, we want Id= 100uA, Vds= 2.5v, This gives ---Rd= 25k
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Design of common source for gain

To set gain

Av= 30 = - gm [ RD || ro ]
ro=1/ Id = 1M ohm; = .01V-1 gm= 1.2 mA / V = 2 Id / Vov Hence, Vov= 0.166V [designers choice depends on VDD, Small value for small supply ] gm= 1.2 mA / V = Kn (w/L) Vov W/L= 90.3, Vgs= 1.166V
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Practical design
Sketch VTC Choose bias current, choose a w/L Find corresponding Vgs, Vds, re calculate Rd, w/L Draw the schematic in eda tool Set voltages by applying sources Do .dc analysis Check all dc current and voltages Apply ac , check ac output. Do .ac analysis

gm/ Id
transconductance generation efficiency
It is strongly related to the performances of analog circuits 2) It gives an indication of the device operating region. 3) It provides a tool for calculating the transistors dimensions The gm/ID ratio is a measure of the efficiency to translate current (hence power) into transconductance; i.e., the greater the gm / ID value, the greater the transconductance we obtain at a constant current value.

Intrinsic gain

How to maximize gain in active region?

Av increases with W/L, VRD, or by dec ID

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Trade offs
W/L increased keeping ID and VRD constant ---greater device capacitance at output , time constant increases, speed of response is affected ---less overdrive voltage reqd. ( as Id constt.) so vomin reduces output swing range increases, bias point will shift ----gain increases Bits, pilani

Bias point for increased (w/L)--- ID and V

RD

constant

(w/L) 2 large (w/L) 1 small

vgs 2 small

vgs 1 large

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Id =
Vdd/Rd

(w/L) 2 > (w/L) 1 ID and VRD constant

Q1, Q2 (w/L)2 large Vov2 less

Less lower swing

vgs1 vgs2

(w/L)1 small Vov1 more

More lower swing

vov2 less

vov1 more

Vdd VdS

VRD increased keeping Id and

W/L constant
Gain increases Vdd - VRd inc., or Vout max reduces, output swing range decreases, MOS shifts towards triode region, Voltage swing is limited
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Bias point for increased VRD ------ID and w/L

constant

vgs 1,2 Bits, pilani

Id=
Vdd/Rd

(VRD)2 > (VRD)1 Id and W/L constant

(VRD)2 large

Q2 vgs Q1
Less lower swing

(VRD)1small
More lower swing

vds2 less

vds1 more

Vdd VdS

ID dec. keeping VRD and W/L const.

ID reduces---to keep VRd constant Rd must increase, So, Rout shd. be increased time constant increases, So, speed of response is affected Vgs must dec. Gain increases
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Bias point for decreased (ID)--- (w/L) and V

RD

constant

vgs 2 vgs 1 small large

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Id=
Vdd/Rd

VRD and W/L constt.

(Id)2 < (Id)1

Q1 vgs1 (Id) 2 small Vov2 less Q2 Less swing ((Id)1 large Vov1 more More swing vgs2

vov2 less

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Vdd VdS

Maximum gain possible (intrinsic

gain)

Av= - gm ro Make Rd infinite But this will make VRd=Vdd, MOS goes to cutoff How?---Rd replaced by current source
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GAIN and SWING COMPATIBILITY

What if gain is high but not sufficient voltage swing ? Output will be distorted as MOSFET slips in LINEAR/ CUTOFF region Hence, output voltage swing calculation is important

Output voltage swing under

dynamic state
Constraint---MOS must remain in saturation Vo max Vdd Vomin Vgs-Vt Output DC level [Vdd-IdRd]
Vdd= 3V Reduced upper swing Dc level Reduced lower swing For symm sigdc level shd. be in the middle for max swing

Vgs-Vt = 0.2

How to configure an Active current source ?

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Current source load

Pmos current mirror

Rout= ro1 || ro2

-Swing [ Vdd- Vov2] to Vov1 -MOS Cap. at output increases due to M2 RoutCout product inc.
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Output Voltage swing

Vomax---- Vdd - Vov2 Vomin---- Vov1 For Vdd=3v, Vgsp = Vgsn =.9v, Vt=0.7v Vomax---- 0.2v Vomin---- 2.8v

2.6v

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Penalty paid
Fixed Vgs required to support current bias No roll back flexibility for Q point Remedy--Place a current mirror at source also. Prob.---Then we have to use Cs to provide bypass path Cant we remove Cs??

Effect of technology scaling on intrinsic gain (C E SCALING)

MOS scaled down by constant electric field scaling strategy All dimensions scale down by a factor : ( > 1: usually =1.33) All voltages scale down by a factor
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Effect of technology scaling on intrinsic gain (C E

SCALING)

Keeping W/L constt----- Vdd decreases by L scaled down by , W also decreases to keep ratio constant, Cox, increases by -----Id decreases by ---gm remains constt. increases by , Id decreases by ---ro constt. Hence intrinsic gain does not change
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Guideline--To increase intrinsic gain by design

Keep L large Keep Id small Example--Keeping (w/L) constant L= 4L, W=4W, I = I/4 Intrinsic gain= 1/ [ x ]= 8 times increase Intrinsic gain [8] original intrinsic gain by properly choosing values
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Effect of increasing only L

Keeping I constt----L scaled up by , ro increases L scaled up, W also increases to keep ratio constant, so gm remains same Hence intrinsic gain increases by
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Effect of increasing L on CSA gain

Keeping I constt.----L1, L2 scaled up by , (ro1, ro2) increase W1, W2 also increase to keep ratio constant, so gm remains same Hence CSA gain increases by

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----Active load CS amplifierother types of load

Diode connected load--bad load small impedance, leads to small gain
I

I V

desirable

Vgs

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Equivalent Resistance calc.

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Active load amplifier

pmos

Small value Gain depends on device dim for same I. Also on p if load is pmos

Gain improvement technique for diode connected loadinc. I1

I1/4

But Vgs of M1 will increase to carry 4I current. Swing reduces

Double gain

Gain depends only on device dim. ---so, linear amplification, less distortion For lin. Amp. ----Gain shd. be independent of bias voltages and current Reason--|Av|= gm Rd changes as gm changes with the input signal swing (though close to Q point)

Non linearity due to bias dependence

V vi Voeach input point is amplified by a slightly different gain value

Bad drawing

Triode load

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CSA----

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ADV. / DISADV.
No bypass capacitor---------good High gain, high swing--------good Large capacitance at the output--------bad A fixed Vgs is reqd .----worst --- bias point shift with input signal variation, temp. , process variation We need to keep Vgs constant. (or make gain a weaker function of gm) So, allow source node to swing. ---Again place a current source at source node or put a resistor Rs
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Circuit trans-conductance Gm, Av CSA

=gm of MOS

Rout = ro1 || ro 2
Vout Vout Iout Av = = Vin Vin Iout Av = R out G m = g m R out
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Common source amplifier

with Source Degeneration

Motivation- remove Cs
Aim----How to remove Cs ? To allow source node to swing
Put a current mirror sink at source but it has high ro So, replace current mirror by low Rs in place of current mirror sink and remove Cs. Ibias is decided by current mirror load --Can we get minimum (ideally NO) reduction in gain??

CSA with Source Degeneration

vout

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Performance variation
Vgs < vin, gain reduces Output impedance will change Non linearity decreases as Id varies smoothly w.r.t vin variations
Without Rs With Rs

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Nonlinearity Error

Circuit trans-conductance Gm

ID

gm of MOS
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ID

Circuit trans-conductance

Voltage Gain

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Trans-conductance variationcomparison
Gm=

Without Rs

With Rs

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Gm, Rout from approximate small signal model

= gm (Vin-Vx) Vx= Iout Rs

Gm, Rout from small signal model with ro and gmb

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gm

For Rs=0, Gm = gm For Rs 0, Gm < gm

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Rout
Rout= Rd || Rout

Rout
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Rout

Rout

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Why Rout increases due to Rs?

A high impedance at a node means if voltage at that node is changed slightly, current through that node does no change much. Here we achieve this at Vout node through negative feedback in vgs.--If Vout ---Id (effect comes through ro)
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If Vout ---Id (effect comes through ro) At the same time, due to Vout , a voltage vs appears at source Vs causes reduction in Vgs, due to which Id falls more due to square dependence on Vgs Hence Id changes little in comparison to change in vout So Rout increases
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vs

Voltage gain (from ac model)

If ro >> Rs, Rd

Using GmRout

Gm
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Rout

Gain rewritten (simplified form)

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High / low impedance node

Look at R= V/ I

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Resistance looking into the source

Considering ro to be large Vx / ix

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Rout by inspection

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Gain by inspection

Replace by nmos

?
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Ideal Current source load--problem???

Av Effect of Rs is negated as I0 (ideal) can not sustain current variations
Can not change

We want non ideal active load

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Push-pull amplifier

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Power efficiency
Class A amplifierconducts for full cycle

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Power Efficiency ---power delivered to load

For equal swing in both directions, Vo shd. be biased at Vdd/2 and then current through RL= Vdd/2RL
PL = 100 % PS Now _ when _ up transition ; Vo max V o = Vdd ; for max Vo Ps = V dd I Vdd I PL = 2 2
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Vdd Vdd , IL 2 RL 2

( )

rms peak vout

-----for max. swing Vdc= vdd/2, IL=I/2 In up (or down) Transition Vomax=vdd (or 0), extreme value Peak vo amplitude= vdd/2 Peak current supplied by vdd = I/2 = 25%
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