Lovely Professional University,Punjab

Format For Instruction Plan [for Courses with Lectures and Tutorials

Course No ECE348

Cours Title FAULT TOLERANCE IN VLSI

Course Planner 14892 :: Tummala Anil Chowdary

Lectures Tutorial Practical Credits 3 1 0 4

Text Book:

1 Luang-Terng Wang,VLSI Test Principles and Architectures:Design for Testability The Morgan Kaufmann Series in Systems on Silicon, 2008

Other Specific Book: Other Reading Sr No Jouranls atricles as compulsary readings (specific articles, Complete reference) 2 Self-Checking and Fault Tolerant Digital Design by Parag.K.Lala Morgan Kaufmann Series 3 Reversible-Logic Design with on-line Testability by D. P. Vasudevan, P.K.Lala 4 Self-Checking Combinational circuit Design by Fadi Y. Busaba, P.K.Lala Relevant Websites Sr. No. (Web adress) (only if relevant to the courses) Salient Features

Detailed Plan For Lectures

Week Number Lecture Number Lecture Topic Chapters/Sections of Pedagogical tool Textbook/other Demonstration/case reference study/images/anmatio n ctc. planned

Part 1
Week 1 Lecture 1 Importance of Testing, Testing During the VLSI Lifecycle ->Reference :1,chapter xilinx software 1/ 1.1 to 1.2

Approved for Spring Session 2011-12

Week 1

Lecture 2 Lecture 3

VLSI Development Process, Design Verification, Yield and Reject Rate, Electronic System Manufacturing Process System-Level Operation, Challenges in VLSI Testing, Test Generation Fault Models, Stuck-At Faults, Transistor Faults, Open and Short Faults, Test 1

->Reference :1,chapter xilinx software 1/ 1.2 ->Reference :1,chapter xilinx software 1/ 1.2 ->Reference :1,chapter xilinx software 1/ 1.2 ->Reference :1,chapter xilinx software 1/ 1.3 Test 1

Week 2

Lecture 4 Lecture 5 Lecture 6

Week 3

Lecture 7

Delay Faults and Crosstalk, Pattern Sensitivity and ->Reference :1,chapter xilinx software Coupling Faults, Analog Fault Models, Levels of 1/ 1.3 to 1.4 Abstraction in VLSI Testing, Register-Transfer Level Behavioral Level, Gate Level, Switch Level, Physical Level Design for Testability: Testability Analysis SCOAP Testability Analysis ->Reference :1,chapter xilinx software 1/ 1.4 ->Reference :1,chapter xilinx software 2/ 2.1 to 2.2 ->Reference :1,chapter xilinx software 2/ 2.2

Lecture 8 Lecture 9 Week 4 Lecture 10

Part 2
Week 4 Lecture 11 Lecture 12 Week 5 Lecture 13 Lecture 14 Lecture 15 Week 6 Lecture 16 Lecture 17 Lecture 18 Week 7 Lecture 19 Lecture 20 Probability-Based Testability Analysis Simulation-Based Testability Analysis RTL Testability Analysis Design for Testability Basics, Ad Hoc Approach, Structured Approach Test 2 Scan Cell Designs, Scan Architectures, Scan Design Rules, Scan Flow. Introduction to Logic and Fault Simulation Simulation Models, Gate-Level Network, Logic Symbols, Logic Element Evaluation Timing Models, Logic Simulation, Compiled-Code Simulation, Event-Driven Simulation, Fault Simulation ->Reference :1,chapter xilinx software 2/ 2.2 ->Reference :1,chapter xilinx software 2/ 2.2 ->Reference :1,chapter xilinx software 2/ 2.2 ->Reference :1,chapter xilinx software 2/ 2.3 Test 2 ->Reference :1,chapter xilinx software 2/ 2.6 to 2.7 ->Reference :1,chapter xilinx software 3/ 3.1 to 3.2 ->Reference :1,chapter xilinx software 3/ 3.2 ->Reference :1,chapter xilinx software 3/ 3.2 ->Reference :1,chapter xilinx software 3/ 3.3 to 3.4 Approved for Spring Session 2011-12

Week 7

Lecture 21

Serial Fault Simulation, Parallel Fault Simulation, Fault Detection, Comparison of Fault Simulation Techniques.

->Reference :1,chapter xilinx software 3/ 3.4

MID-TERM Part 3
Week 8 Lecture 22 Lecture 23 Lecture 24 Introduction to Analog and Mixed Signal Testing Analog Circuit Properties, Continuous Signals, Large Range of Circuits ->Reference :1,chapter xilinx software 11/ 11.1 ->Reference :1,chapter xilinx software 11/ 11.1

Nonlinear Characteristics, Feedback Ambiguity, ->Reference :1,chapter xilinx software Complicated Cause- Effect Relationship, Absence of 11/ 11.1 Suitable Fault Model Quiz 1 Quiz 1 Requirement for Accurate Instruments for Measuring ->Reference :1,chapter xilinx software Analog Signals, Analog Defect Mechanisms and 11/ 11.1 Fault Models, Hard Faults, Soft Faults. Analog Circuit Testing, Analog Test Approaches, Analog Test Waveforms DC Parametric Testing, Open-Loop Gain Measurement, Unit Gain Bandwidth Measurement Common Mode Rejection Ratio Measurement, Power Supply Rejection Ratio Measurement ->Reference :1,chapter xilinx software 11/ 11.2 ->Reference :1,chapter xilinx software 11/ 11.2 ->Reference :1,chapter xilinx software 11/ 11.2

Week 9

Lecture 25 Lecture 26

Lecture 27 Week 10 Lecture 28 Lecture 29

Part 4
Week 10 Lecture 30 AC Parametric Testing, Maximal Output Amplitude ->Reference :1,chapter xilinx software Measurement, Frequency Response Measurement, 11/ 11.2 SNR and Distortion Measurement AC Parametric Testing, Maximal Output Amplitude ->Reference :1,chapter xilinx software Measurement, Frequency Response Measurement, 11/ 11.2 SNR and Distortion Measurement Inter-modulation Distortion Measurement, MixedSignal Testing. Inter-modulation Distortion Measurement, MixedSignal Testing. ->Reference :1,chapter xilinx software 11/ 11.2 to 11.3 ->Reference :1,chapter xilinx software 11/ 11.2 to 11.3

Week 11

Lecture 31

Lecture 32 Lecture 33 Week 12 Lecture 34 Lecture 35

Introduction to Analog-Digital Conversion, ADC and ->Reference :1,chapter xilinx software DAC Circuit Structure, DAC Circuit Structure 11/ 11.3 ADC Circuit Structure, ADC/DAC Specification and Fault Models ->Reference :1,chapter xilinx software 11/ 11.3

Approved for Spring Session 2011-12

Week 12 Week 13

Lecture 36 Lecture 37 Lecture 38 Lecture 39

Time-Domain ADC Testing, Code Bins

->Reference :1,chapter xilinx software 11/ 11.3

Code Transition Level Test (Static), Code Transition ->Reference :1,chapter xilinx software Level Test (Dynamic) 11/ 11.3 Gain and Offset Test, Linearity Error and Maximal Static Error ->Reference :1,chapter xilinx software 11/ 11.3

Sine Wave Curve-Fit Test, Frequency-Domain ADC ->Reference :1,chapter xilinx software Testing. 11/ 11.3

Spill Over
Week 14 Lecture 40 Lecture 41 xilinx software xilinx software

Details of homework and case studies

Homework No. Objective Topic of the Homework Nature of homework (group/individuals/field work Individual Individual Group Evaluation Mode Allottment / submission Week 2/4 5/7 10 / 11

Test 1 Test 2 Quiz 1

To Test their under Importance of Testing, Challenges in VLSI Testing, Levels of standing Abstraction in VLSI Testing To test Numerical ability to test their responsiveness Design for Testability, Logic and Fault Simulation Analog and Mixed Signal Testing, Analog Circuit Testing, Analog Test Approaches

Knowledge Problem solving ability To Test their instant response

Scheme for CA:out of 100*

Component Quiz,Test Frequency 2 Total :Out Of 3 Each Marks Total Marks 10 10 20 20

* In ENG courses wherever the total exceeds 100, consider x best out of y components of CA, as explained in teacher's guide available on the UMS

Plan for Tutorial: (Please do not use these time slots for syllabus coverage)
4 Approved for Spring Session 2011-12

Tutorial No.

Lecture Topic

Type of pedagogical tool(s) planned (case analysis,problem solving test,role play,business game etc)

Tutorial 1 Tutorial 2 Tutorial 3 Tutorial 4 Tutorial 5 Tutorial 6 Tutorial 7

Test Generation, Stuck-At Faults Levels of Abstraction in VLSI Testing Design for Testability Scan Design Rules, Scan Flow Logic and Fault Simulation Comparison of Fault Simulation Techniques Analog Defect Mechanisms and Fault Models

Problem solving Problem solving Problem solving Problem solving Problem solving Problem solving Problem solving

After Mid-Term
Tutorial 8 Tutorial 9 Tutorial 10 Tutorial 11 Tutorial 12 Tutorial 13 Analog Circuit Testing, Analog Test Approaches Mixed-Signal Testing DAC Circuit Structure ADC Circuit Structure Code Bins, Code Transition Level Test Problem solving Problem solving Problem solving Problem solving Problem solving

Gain and Offset Test, Linearity Error and Maximal Static Problem solving Error

Approved for Spring Session 2011-12