]<gj]<]<j<^]<]

EF

EF

? ? EF ?
K?

EF

KKK

K
K

K(Data Sheet)

KKKKKK


]<gj]<]<j<^]<]

EF

(AND)

(AND)


(AND)

EF

(Concept)
AND(Truth Table)
KAND

HIGH ANDHIGH

KAND
(Procedure)

(Pins)
LS(chip)

WKAND
KGND H Volts

{
SW, SW

(LED)HIGHLOW
KJ

L
(LOW output) ""KJ AND
K(HIGH output)""

--


(AND)

EF

KLS

A=SW B=SW AB=L

KANDJ

ANDAND
Kfx = (AB).C or A.B.C

KAND
--


(AND)

EF

ANDSW, SW, SW
KJ

A=SW B=SW C=SW

L=AB

L=ABC

KANDJ

--


]<gj]<]<j<^]<]

EF

(OR)

(OR)


(OR)

EF

(Concept)
OR (Truth Table)
KOR

ORHIGH

KHIGH

KOR
(Procedure)

(Pins)
LS(chip)

WKOR
KGND H Volts

SW,SW

(LED)HIGHLOW
KJ

L
(LOW output)""KJ AND

K(HIGH output)""

--


(OR)

EF

KLS

A=SW B=SW A+B=L

KORJ
OROR
Kfx = [(A+B)+C] or A+B+C

--


(OR)

EF

KOR

OR
SW, SW, SW
KJ

A=SW B=SW C=SW

L=A+B

L=A+B+C

KORJ

--


]<gj]<]<j<^]<]

EF

(NOT)

(NOT)


(NOT)

EF

(Concept)

KE FEFNOT(opposite state)

KNOT(Truth Table)J

KNOT
(Procedure)

(Pins)
LS(chip)

WKNOT
KGND H Volts

L HIGH LOW SW

.-

L
(LOW output)""KJ NOT

K(HIGH output)""

--


(NOT)

EF

KLS

Input=SW

Output=L

KNOTJ

--


]<gj]<]<j<^]<]

EF

(NAND)

(NAND)


(NAND)

EF

(Concept)
LOWKAND(inverted or negated)NAND
LOWKLOWHIGHHIGHAND
NOT-ANDANDKHIGH
NANDJ KNAND

KNANDJ

(Procedure)

(Pins)
LS(chip)

KNAND
W

KGND H Volts

SW,SW

(LED)HIGHLOW
KJ

--


(NAND)

EF

L
(LOW output)""KJ AND

K(HIGH output)""

KLS

A=SW B=SW C=L

KNANDJ

K
AND NAND
K(Inverter)NOTNAND

LOWSWJ
NANDLHIGH
KJ

KLS

- -


(NAND)

EF

Input=SW Output=L




KNANDJ

NANDNAND
K f x = ABC

KNAND

- -


(NAND)

EF

NANDSW, SW, SW
KJ

A=SW B=SW C=SW

L=AB

L3 = ABC

L1 = AB

KNANDJ

- -


]<gj]<]<j<^]<]

EF

(NOR)

(NOR)


(NOR)

EF

(Concept)
LOWKOR(inverted or negated)NOR

LOWKLOWHIGHHIGHOR
NOT-ORORKHIGH

KNORKNOR

KNORJ

(Procedure)

(Pins)
LS(chip)

WKNOR
KGND H Volts

SW,SW

(LED)HIGHLOW
KJ

L
(LOW output)""KJ AND

K(HIGH output)""

- -


(NOR)

EF

KLS

A=SW B=SW C=L

KNORJ

KORNOR

K(Inverter)NOTNOR

LOWSWJ

NORLHIGH
KJ

KLS

- -


(NOR)

EF

Input=SW

Output=L

KNORJ

NORNOR
K f x = A + B + C

KNOR

NORSW, SW, SW
KJ

A=SW B=SW C=SW L1 = A + B

L=A+B

L3 = A + B + C

KNORJ

- -


]<gj]<]<j<^]<]

EF

EF

(Concept)

NOT,OR(NAND)NOT,AND

K(NOR)

(double inversion) KJ
K

KJ

(Procedure)

LS, LS, LS, LS{LS : (chip)

KGND H Volts
(A B = A B) ANDW

SW,SWJ
KJ LJ

- -

EF

A B = A B .AND

KANDJ

A=SW B=SW

A B =L

KJ J

(A + B = A + B) ORW

SW,SWJ
KJ LJ

( A + B = A + B) .OR

KORJ

- -

EF

A=SW B=SW

A + B =L

KJ J

J W A B = A + B K
LJ SW,SW
KJ

KJ

A=SW B=SW

A + B =L

KJ J

- -

EF

A B = A + B .NAND

J W A + B = A B K
LJ SW,SW
KJ

KJ

A=SW B=SW

A B =L

KJ J

A + B = A B .NOR

[(A B) + C] = [(A + B) C ] W

J W [(A + B) C ] K
LJ SW,SW,SW
KJ

- -

EF

K [(A + B) C ] J

A=SW B=SW C=SW L1 = [(A + B) C ]

L= [(A B) + C]

KJ J J

J W [(A B) + C] K

LJ SW,SW,SW
KJ

- -

EF

K [(A B) + C] J
ELLFK
([ A B) + C] [(A + B) C ]

NANDORW

SW,SWJ
KJ LJ

A B = A + B .OR

KNANDORJ

A=SW B=SW

A B =L

KJ J

- -

EF

NORANDW

SW,SWJ
KJ LJ

A + B = A B .AND

KNORANDJ

A=SW B=SW

A + B =L

KJ J

- -


]<gj]<]<j<^]<]

EF

(XOR)

(XOR)


(XOR)

EF

(Concept)
HIGHExclusive-OR (XOR)
XORKLOWLOWHIGHHIGH

K A B
KXORNOR
NANDXOR
KXORJ

KXOR
(Procedure)

LS, LS, LS{LS : (chip)

KGND H Volts
LSXORW

SW,SWJ
KJ LJ

KXOR

--


(XOR)

EF

A=SW B=SW L= AB + AB

KXORJ
NANDXORW

SW,SWJ
KJ LJ

.XOR J

KNANDXORJ

--


(XOR)

EF

A=SW B=SW L= AB + AB

KJ J

NORXORW

SW,SWJ
KJ LJ

.XOR J

--


(XOR)

EF

KNORXORJ

A=SW B=SW L= AB + AB

KJ J

--


]<gj]<]<j<^]<]

EF

(Adder Circuits)

(Adder Circuits)


(Adder Circuits)

EF

(Concept)
(Truth Table)
K(Full Adder)(Half Adder)
(Procedure)

LS, LS{LS : (chip)

KGND H Volts
(Half Adder)W

SW,SWJ
KJ L, LJ

KJ

A=SW B=SW

SUM=L

CARRY=L

KJ

--


(Adder Circuits)

EF

(Full Adder)W

SW,SW,SW J

L, LJ
KJ

KJ

A=SW

B=SW

CARRY=SW

L=SUM

L=CARRY

KJ

--


(Adder Circuits)

EF

--


]<gj]<]<j<^]<]

EF

S-R

S-R


S-R

EF

(Concept)
SR
SR(basic)
(Clocked SR Latch)

K(Clear)(Preset)(Asynchronous Control Inputs)

(Procedure)

LS{LS, LS{LS : (chip)

KGND H Volts
NORSRW

SW,SWJ
KJ L, LJ

KNORSRJ

Q =L
R=SW S=SW
Q=L

KNORSRJ

NANDSRW

SW,SWJ
KJ L, LJ
--


S-R

EF

KNANDSRJ

KJ J

KJ J

S=SW R=SW
Q=L
Q =L

KNANDSRJ

--


S-R

EF

(ENABLE)SRW
SW, SW, SWJ
J L, LJ

KNANDSRJ
KJ J

KJ J

S=SW

R=SW

ENABLE=SW

Q=L

Q =L

KENABLESRJ
--


S-R

EF

SRW
SW, SW, SW, SW, SWJ
L, L,J

KJ

KSRJ

KJ J

KJ J

--


S-R

EF

Clear=SW

Preset=SW

Q =L

Q=L

S=SW R=SW Enable=SW

KSRJ

--


]<gj]<]<j<^]<]

EF

EF

(Concept)
KD
(Procedure)

LS{LS, LS{LS : (chip)

KGND H Volts
NOR, AND, NOTDW

SW,SWJ
KJ L, LJ

KNOR, AND, NOTDJ

D=SW

Enable=SW

Q=L

Q =L

KJ DJ

DW

KHIGHSWJ
LHIGHLOWSW
- -

EF

KHIGH(Enable)

KDJ

HIGHLOWSWKLOW SW
L
K

KLOW(Enable)

- -


]<gj]<]<j<^]<]

EF

JK

JK

EF

JK

(Concept)
JK
KTJK
(Procedure)

(Pins)
LS(chip)

H VoltsJK
KGND

SW,SWJ
KJ LJ

KJKJ

K=SW

J=SW

CLK=SW

Q=L

KJKJ

LOWSWKHIGHSW,SW
LLOWHIGH

HIGHSW (Toggle)
KLOW
- -


JK

EF

HIGHKHIGHJ
TK
KJ

KTJ

- -


]<gj]<]<j<^]<]

EF

(Shift Register)

(Shift Register)


(Shift Register)

EF

(Concept)
J
J

(Serial-In, Parallel-Out Shift Register)

K(Ring Counter)
(Procedure)

J J W

LS(-chips)

D(Pins)
KGNDH Volts

KLOWSW, SW, SWJ

(clear)LOWSW
K(Q's = )

KJ J J

HIGHSWKHIGHSW,SW
SWK(removes the clear input)

KHIGHHIGH

KLOW HIGHLOWSW
(clock inputs)SW
--


(Shift Register)

EF

(positive edge)
KL(HIGH)

K(second HIGH)
KHIGHL, L

KLOWLOWSW

LOWHIGHLOWSW
K

KLOWSWJ
()LOWSW

KL = LOW, L = LOW, L = LOW, L = HIGHW

KHIGH

HIGHSWKHIGHSW
K(releases the clear and preset inputs)

K(Hz clock)HIGH

--


(Shift Register)

EF

K(Ring

Counter) J

--


]<gj]<]<j<^]<]

EF

EF

(Concept)

KJ
(Procedure)

(Pins)LS(-chips)
JK

KGND H Volts

HIGHSWJ
LOWSWK(initializes clock setting)

(clear)HIGH
K(Q's = )

KJ

KLOWHIGH LOW SW
KJ L-L

--

INPUT
Number of
CLK

EF

OUTPUTS
L =

L =

L =

L =

Decimal
Equivalent

KJ

--

EF

LS(-chips)
KGND H Volts

HIGHSWJ
LOWSWK(initializes clock setting)

(preset)HIGH
K(Q's = )

KJ

KLOWHIGH LOW SW
KJ L-L

--

INPUT
Number of
CLK

EF

OUTPUTS
L =

L =

L =

L =

Decimal
Equivalent

KJ

J W
LS(-chips)
KLSNAND
--

EF

FHIGHSW J
HIGHLOWSWKE
K(Q's = )(clear)

KJ J

K
KEFLOWSW
K

--


]<gj]<]<j<^]<]

EF

EF

(Concept)

(Procedure)

LS(-chips)
NAND
LS

KLS

HIGHSWJ
LOWSWK(initializes clock setting)

(clear)HIGH
K(Q's = )

KJ

KLOWHIGH LOW SW
KJ L-L

--

INPUT
Number of
CLK

EF

OUTPUTS
L =

L =

L =

L =

Decimal
Equivalent

KJ

LS(-chips)
NANDLS

KLS

HIGHSWJ
LOWSWK(initializes clock setting)

(preset)HIGH
K(Q's = )

--

EF

KJ

KLOWHIGH LOW SW
KJ L-L

INPUT
Number of
CLK

OUTPUTS

L =

L =

L =

L =

Decimal
Equivalent

KJ

K
--

EF

(References)
[] Nigel P. Cook, Introductory Digital Electronics. New Jersey: Prentice-Hall,
Inc. .
[] M. Morris Mano, Digital Logic and Computer Design, Prentice- Hall, Inc.
of India - .
[] Thomas L. Floyd, Digital Fundamentals, Seventh Edition, Prentice-Hall,
Inc. .
[] M. Morris Mano, Digital Design, Prentice- Hall, Inc. Aug .

- -

EF

ANDW
ORW
NOTW
NANDW
NORW
W
XORW
W
S-RW
DW
JKW

W
W
W

EF
GOTEVOT appreciates the financial support provided by BAE SYSTEMS