Introduction to VHDL

Levels of Abstraction
Transistor: Signal values and time are continuous (analog). Modeled by a resistorcapacitor network. Switch: Time is continuous but voltage can either be continuous or discrete. Gate: Transistors are grouped into gates. Voltages are discrete values such as 0 and 1

Levels of Abstraction
Register Transfer level: Hardware is modeled as assignments to registers and combinational signals. Basic unit of time is one clock cycle. Transaction Level: A transaction is an operation such as transferring data across a bus. Building blocks are processors, controller, etc(VHDL, Verilog, SystemC). Electronic-System level: Looks at an entire electronic system, with both hardware and software.

What is VHDL?
VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit Developed originally by DARPA to: Describe the STRUCTURE and/or BEHAVIOR of digital systems Several versions of VHDL have been standardized by the IEEE standard: VHDL87 (IEEE 1076-1987) VHDL93 (IEEE 1076-1993) IEEE 1164 is the most recent one

What is VHDL?
The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases of electronic systems design. It is both machine and human readable as such it supports: The development, verification, synthesis and testing of hardware designs. The hardware design data communication The hardware maintenance, modificatin and procurement.

What is VHDL?
VHDL designs can be SIMULATED and/or SYNTHESIZED Practical benefits: A mechanism for digital design and reusable design documentation Event driven simulation Modularity/Extensibility Model interoperability among vendors Third party vendor support Design re-use.

What is VHDL?
Support different description levels
Structural (specifying interconnections of the gates), Dataflow (specifying logic equations), and Behavioral (specifying behavior)

Why use an HDL?

How do we know we have not made a mistake when we manually draw a schematic and connect components to implement a function? By describing the design in a high-level (=easy to understand) language, we can simulate our design before we manufacture it. This allows us to catch design errors, i.e., that the design does not work as we thought it would. Simulation guarantees that the design behaves as it should.

Semantics
The original goal of VHDL was to simulate circuits. The semantics of the language define the circuit BEHAVIOR.

Synthesis
Now, VHDL is used in simulation and synthesis. Synthesis relates to the STRUCTURE of the circuit. Synthesis converts one type of a high level description (behavioral) into lower level description (structural, usually a netlist).

VHDL
VHDL is a strongly-typed language for describing a digital hardware design. The structure of a VHDL design resembles the structure of a modern, object-oriented software design in the sense that every VHDL design describes both an external interface and an internal implementation.

VHDL
A VHDL design consists of the following specifications: Entity Architecture Configuration Entity: A specification of the external interface to the design that is unique.

VHDL
Architecture: A specification of the internal implementation of the design. There can be several specifications of the internal implementation of the design. Configuration: A specification of the mapping between an architecture and a particular instance of an entity. There must be a configuration for each instance of an entity. The configuration defaults to the last compiled architecture if one has not been explicitly specified.

Basic VHDL Code

Every VHDL design description consists of at least one entity / architecture pair, or one entity with multiple architectures. The entity section is used to declare I/O ports of the circuit. The architecture portion describes the circuits behavior.

Basic VHDL Code

A behavioral model is similar to a black box.

Basic VHDL Code

Each hardware module is described with an Entity/Architecture pair

Standard Libraries
Standardized design libraries are included before entity declaration: ieee.std_logic_1164 defines a standard for designers to use in describing interconnection data types used in VHDL modeling. ieee.std_logic_arith provides a set of arithmetic, conversion, comparison functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector. Ieee.std_logic_unsigned provides a set of unsigned arithmetic, conversion, and comparison functions for std_logic_vector.

Standard Logic 1164

Std_logic_1164: IEEE standard for signal values in VHDL:

If you see X in a simulation, it usually means that there is a mistake in your code.

Basic Syntax
Not case sensitive. Free format. Statements end with a semi-colon (;) that there is a mistake in your code. Comments start with -- and end at the end of the line. Any data is declared as constant, variable or signal.

VHDL Program Structure

BASIC VHDL STRUCTURE

Example

Code For This Module?

Entity Declaration
An entity declaration describes the interface of the component. PORT clause indicates input and output ports. An entity can be thought of as a symbol for a component.

PORT Declaration
PORT declaration establishes the interface of the object to the outside world. Three parts of the PORT declaration Name Any identifier that is not a reserved word. Mode In, Out, Inout, Buffer Data type Any declared or predefined datatype.

PORT Declaration

PORT Declaration
Port Name Consists of letters, digits, and/or underscores Must begin with a letter Case insensitive Port signal type STD_LOGIC STD_LOGIC_VECTOR(max DOWNTO min) Note that STD_LOGIC_VECTOR: An array of STD_LOGIC.

Architecture Declaration
Architecture declarations describe the operation of the component. Many architectures may exist for one entity, but only one may be active at a time An architecture is similar to a schematic of the component.

Signals
In VHDL, signals are used to convey information between (and within) entities. Signals represent connection points in a VHDL design. Sample Signal Specifications: SIGNAL c : STD_LOGIC; --Bit SIGNAL dinA : STD_LOGIC_VECTOR(1 TO 4); SIGNAL byte : STD_LOGIC__VECTOR(7 DOWNTO 0);

Constant Declaration
A constant can have a single value of a given type. A constants value cannot be changed during the simulation. Constants declared at the start of an architecture can be used anywhere in the architecture. Constants declared in a process can only be used inside the specific process.

CONSTANT constant_name : type_name [ : = value]; CONSTANT rise_fall_time : TIME : = 2 ns; CONSTANT data_bus : INTEGER : = 16;

Variable Declaration
Variables are used for local storage of data. Variables are generally not available to multiple components or processes. All variable assignments take place immediately. Variables are more convenient than signals for the storage of (temporary) data.

Operators

Assignment Statements

Assignment Statements

Description Examples of Combinational Networks

Process
A VHDL ARCHITECTURE is a set of processes concurrently executed. There are 2 process types: Implicit process Explicit process

Process
The process statement allows a designer to describe the behavior of a portion of an architecture. An explicit process is a set of statements executed sequentially and thus the order of the statements execution is important. A process can NOT be declared inside another process

Example: 3 AND Inputs