Analog Electronic Circuits

Lesson 9 JFET Amplifier

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Outline
JFET Amplifier Biasing Conditions Self Biased JFET JFET Load Line Amplifier Biasing

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JFET Biasing Conditions

VGS is Reverse Biased! JFET used in Saturation for amplifier Therefore VDS > VP Commonly IDS set to approximately 0.5IDSS When VGS = VP /3.4 then IDS = 0.5IDSS

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JFET Fixed Bias

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JFET Fixed Bias

RG sets input impedance - rgs very high Separate negative supply on Gate
Impractical in most cases Used at times Common at low VDD supply voltages

Self Biased config provides -ve VGS

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Self Biased Configuration

Add resistor between Source and Ground VDD must be higher than Fixed Bias ID through RS elevates VS above Ground VG held at Gnd through RG Sets up a -ive VGS Thus VGS = - ID x RS

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Self Biased Configuration

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JFET Load Line Self Bias

Provides a graphical method to visualize biasing characteristics and Q point Transfer curve at saturation is quadratic JFET operation predictable given VGS(OFF) and IDSS (datasheet) Drawing Load-Line identifies Q point

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JFET Load Line Self Bias

ID
IDSS

ID

V = I DSS (1 GS ) VP

IDSS 2 IDSS 4

VGS

VGS(OFF)

VGS(OFF) 2

VGS(OFF) 3.4

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JFET Load Line Self Bias

ID
IDSS ID

Q point

IDQ

VGS

VGS = IDRD

VGSQ

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Load Line Changing RS

ID
IDSS ID

IDQ

VGS

VGS = IDRD2
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VGSQ

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Load Line Changing RS

ID
IDSS ID

IDQ

VGS

VGSQ VGS = IDRD3

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Amplifier Biasing
Quadratic curve tricky biasing, take your time with the math... Useful shortcuts:
Solving: use substitution and quadratic formula Designing: IDS = 0.5IDSS when VGS = VP /3.4

Amplifier in saturation Ensure VDS > VP Remember RS sets Q point for Self Bias!

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Amplifier Biasing
ID V GS 2 = I DSS (1 ) VP
V GS = V P (1

ID ) I DSS

V GS = I D R S

substitute I D

I D RS = I DSS (1 ) VP

Amplifier Biasing
ID V GS 2 = I DSS (1 ) VP

V GS = I D R S

substitute I D
ID

I D RS = I DSS (1 ) VP

b b 24ac = 2a

where 0 = aI D2 + bI D + c

Amplifier Biasing
ID V GS 2 = I DSS (1 ) VP
2

V GS = I D R S

substitute I D

I D RS I D RS I D RS = I DSS (1 ) = I DSS (1 )(1 ) VP VP VP 2 I DSS R S RS 2 I D + I DSS ( ) ID VP VP

2 2

therefore I D = I DSS

RS 2 I DSS R S 2 and 0 = I DSS ( ) I D ( 1) I D + I DSS VP VP

Amplifier Biasing
ID V GS 2 = I DSS (1 ) VP
2

V GS = I D R S

substitute I D

I D RS I D RS I D RS = I DSS (1 ) = I DSS (1 )(1 ) VP VP VP 2 I DSS R S RS 2 I D + I DSS ( ) ID VP VP

2 2

therefore I D = I DSS

RS 2 I DSS R S 2 and 0 = I DSS ( ) I D ( 1) I D + I DSS VP VP

Amplifier Biasing
ID V GS 2 = I DSS (1 ) VP
V GS = V P (1

ID ) I DSS

V GS = I D R S

KVL : 0 = V DD I D R DV DS I D R S therefore : V DS = V DD I D ( R D + R S ) saturation... ensure that V DS > V P

Credits and Attributions

Reference Texts:
Boylestad, R.L., Nashelsky, L., (2009). Electronic Devices and Circuit Theory (10th ed.) Floyd, T.L., (2012). Electronic Devices: conventional current version (9th ed.)

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Copyright (c) 2012 by Mladen Hruska. This work is made available under the terms of the Creative Commons Attribution-ShareAlike 2.5 Canada license All images, diagrams, charts, etc. are the copyright work of Mladen Hruska if not immediately attributed otherwise For more information: http://creativecommons.org/licenses/by-sa/2.5/ca/

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