At mosfet, the charges stored at the gate electrode, conducting channel and at the depletion layers. We models this stored charges as a parasitic capacitance as in the next figure:
This lumped capacitance model from 1971 is somewhat partial. For this reason the charge conservation is not strictly enforced, resulting a minor error in circuit simulations. Capacitance model: We split the mosfet capacitance into the three lumped capacitances: , , , | , | , | gd gb gs gb gd gs g g g gs V V V V gb V V gs gd g gd b Q Q Q C C C V V V c c c = = = c c c
These 3 gate capacitance reflects the inversion charge and the depletion charge. We can now write: Gi Gd G Q Q Q = + , Gi Q - Gate invertion charge , Gd Q -Gate depletion charge. We will also assume for this model that the C GS and C GD dominated by the inversion charge. We calculate Gi Q : For the mosfet channel we could approximately write that charge per unit area as: ( ) s i T qn c V V ~ (this is because we can assume that in high frequency a mosfet capacitance in similar to mos low frequency capacitance , means c i ). So in order to calculate the charge we intergrate on the channel area, remembering that in the W dimention the charge is mostly the same, and that the voltage at the channel is depended on the x position(the position in the channel): | | 0 0 0 ( ) w L Gi i GS L s T Q qn dxdy Wc V V V x dx = =
Made by Ori Bass, BIU Page 2
We should notices the following: we assume zero drain source bias and that we have inversion at the entire length of the channel. In addition we add the ( ) V x which implies that the voltage on the channel is the dependent at the voltage at point X. We continue develop the equation: | | | | ( ) 2 2 2 0 0 3 2 3 2 2 | | ( ( )) ( ) ( ( )) ( ) 1 ( ) 3 : ( ) 2 DS i i ds n S n i GT ds i n Gi i GS T n i GT GT ds ds n i GT D L S GS T ds n i DS V ds C c WL GS T DS i I W qn E dV dx W c V V x I W c dV Q Wc V V V x W c V V x V V x dV I I C V V V V I L W c V For Linear state I V V V L C u u u u u u = = = = = =
=
| | = | \ .
n Wu n Wu i C L ( ) ( ) 3 3 3 3 2 2 2 ( ) 1 ( ) (*) 3 3 ( ) ( ) 2 2 (1) : (2) : 2( )( ) ( ) 2 GT DS GS T i GT DS GS T DS DS GS T DS GS T DS DS G G D S GS GD GS T GS GD GS GD V V V V C V V V V V V V V V L V V V V V V V V V V V V V V V V
= =
| |
| \ . = + = = 2 2 GS GS GD V V V 2 2 2 GS T T GD GS V V V V V + 2 GS GD V V + ( ) 2 2 2 3 3 3 3 2 2 2 2 2 2 ( 2 ) ( ) 2 ( ) ( ) 2 (*) 3 2( )( ) ( ) 3 ( ) ( ) GD GS GS T GD T GD GT DS GS T i GS T GD T i GS T GS GD GS GD GS T GD T T T V V V V V V V V V V V C V V V V C V V V V V V V V V V V V = = + +
= =
From here we derive the gate charge by the relevance voltage and we getting the following equations: 2 2 2 2 1 , 1 , 0 3 2 3 2 GT DS GT GS i i GB GT DS GT DS GD V V V C C C C C V V V V
| | | | = = = | |
\ . \ .
Now if you will take under consideration for saturation that DS V is the voltage of saturation (not velocity saturation), then we get : 2 , 0 , 0 3 GS i GD GB C C C C = = = . And for linear state we can take 0 DS V = and we get 0.5 , 0.5 , 0 SD i GD i GB C C C C C = = = .