BO CO LAB 3

N VI X L V CU TRC MY TNH

Nhm 22A

1. Yu cu:

- Thit k chip Mips Single-Cycle 32bit bao gm cc lnh LW, SW, J, JR, BNE, XORI, ADD, SUB v SLT. - Cc lnh u c x l trong 1 chu k lnh (Single Cycle). - Thit k da trn cc module c sn regfife, alu, instrmem v datamem 2. Tp lnh: Cc lnh chia lm 3 nhm: R-format: ADD, SUB, SLT, JR. I-format: LW, SW, BNE, XORI. J-format: J.

2.1. R-format: - ngha lnh: + ADD rd, rs, rt: Reg[rd] = Reg[rs] + Reg[rt]. + SLT rd, rs, rt: If (Reg[rs] < Reg[rt]) Reg[rd] = 1 else Reg[rd] = 0. + SUB rd, rs, rt: Reg[rd] = Reg[rs] Reg[rt]. + JR rs: PC = Reg[rs]. - Khun dng:

opcode 6 bit

rs 5 bit

rt 5 bit

rd 5 bit

shamt 5 bit

function 6 bit

2.2. I-format: - ngha lnh: + BNE rs, rt, imm16: if (Reg[rs] != Reg[rt]) PC = PC + 4 + Sign_ext(Imm16)<<2 else PC = PC + 4. + LW rt, imm16(rs): Reg[rt] = Mem[Reg[rs] + Sign_ext(Imm16)]. + SW rt, imm16(rs): Mem[Reg[rs] + Sign_ext(Imm16)] = Reg[rt]. + XORI rt, rs, imm16: Reg[rt] = Reg[rs] XOR Zero_ext(Imm16). - Khun dng:

opcode 6 bit

rs 5 bit

rt 5 bit

address/immediate 16 bit

2.3. J-format: - ngha lnh: + J target: PC = { PC[31:28], target, 00 }. - Khun dng:

opcode 6 bit

target address 26 bit

3. Thit k: 3.1. S khi tng qut:

3.2. Thit k cc module: 3.2.1. Module Control: - Khi iu khin trung tm, c nhim v gii m opcode ca cu lnh thnh cc tn hiu iu khin n cc khi khc trong chip.

RegDst Jump Branch MemRead

Instruction [31:26]

Main Control

MemReg ALUop Memwrite Aluscr Regwrite

- Cc tn hiu iu khin v gi tr tng ng trong tng cu lnh c cho trong bng sau:

R-format Opcode RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump SignEx ALUOp 0 ALUOp 1 000000 1 0 0 1 0 0 0 X 1 1

Jump 000010 X X X 0 0 0 1 X X X

BNE 000101 X 0 X 0 0 1 0 1 0 1

LW 100011 0 1 1 1 0 0 0 1 0 0

SW 101011 X 1 X 0 1 0 0 1 0 0

XORI 001110 0 1 0 1 0 0 0 0 1 0

- T bng trng thi, s dng cc cng logic AND v OR, ta lp c cc tn hiu ra t 6 bit Opcode - Code:
module Control(ALUOp, RegDst, Branch, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump, SignEx, InsOp); output [1:0] ALUOp; output RegDst, Branch, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump, SignEx; input [5:0] InsOp; wire wire wire wire wire not [5:0] nInsOp; ALUSrc1, ALUSrc2, ALUSrc3; RegWrite1, RegWrite2, RegWrite3; SignEx1, SignEx2, SignEx3; [1:0] ALUOp1, ALUOp2; #50 (nInsOp[0], InsOp[0]), (nInsOp[1], InsOp[1]), (nInsOp[2], InsOp[2]), (nInsOp[3], InsOp[3]), (nInsOp[4], InsOp[4]), (nInsOp[5], InsOp[5]);

and and

#100 (RegDst, nInsOp[0], nInsOp[1], nInsOp[2], nInsOp[3], nInsOp[4], nInsOp[5]); #100 (ALUSrc1, InsOp[0], InsOp[1], nInsOp[2], nInsOp[3], nInsOp[4], InsOp[5]), (ALUSrc2, InsOp[0], InsOp[1], nInsOp[2], InsOp[3], nInsOp[4], InsOp[5]), (ALUSrc3, nInsOp[0], InsOp[1], InsOp[2], InsOp[3], nInsOp[4], nInsOp[5]); #50 (ALUSrc, ALUSrc1, ALUSrc2, ALUSrc3); #100 (MemtoReg, InsOp[0], InsOp[1], nInsOp[2], nInsOp[3], nInsOp[4], InsOp[5]); #100 (RegWrite1, nInsOp[0], nInsOp[1], nInsOp[2], nInsOp[3], nInsOp[4], (RegWrite2, InsOp[0], nInsOp[0], InsOp[1], InsOp[1], nInsOp[2], InsOp[2], nInsOp[3], InsOp[3], nInsOp[4], nInsOp[4],

or and and nInsOp[5]), InsOp[5]),

(RegWrite3, nInsOp[5]); or and and and and #50

(RegWrite, RegWrite1, RegWrite2, RegWrite3);

#100 (MemWrite, InsOp[0], InsOp[1], nInsOp[2], InsOp[3], nInsOp[4], InsOp[5]); #100 (Branch, InsOp[0], nInsOp[1], InsOp[2], nInsOp[3], nInsOp[4], nInsOp[5]); #100 (Jump, nInsOp[0], InsOp[1], nInsOp[2], nInsOp[3], nInsOp[4], nInsOp[5]); #100 (SignEx1, InsOp[0], nInsOp[1], InsOp[2], nInsOp[3], nInsOp[4], nInsOp[5]), (SignEx2, InsOp[0], InsOp[1], nInsOp[2], nInsOp[3], nInsOp[4], InsOp[5]), (SignEx3, InsOp[0], InsOp[1], nInsOp[2], InsOp[3], nInsOp[4], InsOp[5]); #50 (SignEx, SignEx1, SignEx2, SignEx3); #100 (ALUOp1[1], nInsOp[0], nInsOp[1], nInsOp[2], nInsOp[3], nInsOp[4],

or and nInsOp[5]),

(ALUOp2[1], InsOp[0], nInsOp[1], InsOp[2], nInsOp[3], nInsOp[4], nInsOp[5]); or and nInsOp[5]), nInsOp[5]); or endmodule #50 (ALUOp[1], ALUOp1[1], ALUOp2[1]);

#100 (ALUOp1[0], nInsOp[0], nInsOp[1], nInsOp[2], nInsOp[3], nInsOp[4], (ALUOp2[0], #50 nInsOp[0], InsOp[1], InsOp[2], InsOp[3], nInsOp[4],

(ALUOp[0], ALUOp1[0], ALUOp2[0]);

3.2.2. Module ALUControl: - Gii m tn hiu iu khin ALUOp t khi Control, kt hp vi 6 bit Function a ra tn hiu iu khin cho khi ALU thc hin mt trong bn php ton ADD, SUB, SLT v XOR - Tn hiu iu khin cho ALU c cho trong bng sau:

ALUOp 00 (Load hoc Store) 01 (XOR) 10 (BNE) 11 (Lnh R)

Function X X X 100000 100010 101010

ALUCtr 00 (ADD) 01 (XOR) 10 (SUB) 00 (ADD) 10 (SUB) 11 (SLT)

- Ngoi ra khi ALUControl cn a ra mt tn hiu iu khin JumpReg cho cu lnh JR vi ALUOp = 11 v Function = 001000. - Code:
module ALUControl(ALUCtr, JumpReg, ALUOp, Function); output [1:0] ALUCtr; output JumpReg; input [1:0] ALUOp; input [5:0] Function; wire wire wire wire not [1:0] nALUOp; [5:0] nFunction; [1:0] R, nR; R1, R2, ALUCtr01, ALUCtr02, ALUCtr11, ALUCtr12, ALUCtr13; #50 (nALUOp[0], ALUOp[0]), (nALUOp[1], ALUOp[1]), (nFunction[0], Function[0]),

(nFunction[1], Function[1]), (nFunction[2], Function[2]), (nFunction[3], Function[3]), (nFunction[4], Function[4]), (nFunction[5], Function[5]), (nR[0], R[0]), (nR[1], R[1]); and Function[5]); and Function[5]), Function[5]); or and #100 (R[0], nFunction[0], Function[1], nFunction[2], Function[3], nFunction[4],

#100 (R1, nFunction[0], Function[1], nFunction[2], Function[3], nFunction[4], (R2, nFunction[0], Function[1], nFunction[2], nFunction[3], nFunction[4], #50 (R[1], R1, R2);

or and or

#50 (ALUCtr11, nALUOp[0], ALUOp[1]), (ALUCtr12, nR[0], R[1], ALUOp[0], ALUOp[1]), (ALUCtr13, R[0], R[1], ALUOp[0], ALUOp[1]); #50 (ALUCtr[1], ALUCtr11, ALUCtr12, ALUCtr13); #50 #50 (ALUCtr01, ALUOp[0], nALUOp[1]), (ALUCtr02, ALUOp[0], ALUOp[1], R[0], R[1]); (ALUCtr[0], ALUCtr01, ALUCtr02);

and #100 (JumpReg, ALUOp[0], ALUOp[1], nFunction[0], nFunction[1], nFunction[2], Function[3], nFunction[4], nFunction[5]); endmodule

3.2.3. Khi dch tri 2 (nhn 4):

- Do b nh chng trnh c nh a ch byte v cu trc lnh c lu trong 1 word, do i vi cc lnh r nhnh, gi tr trc khi a vo thanh ghi PC phi nhn vi 4, hay ni cch khc l dch tri gi tr nh phn i 2 n v. - Code:
module ShiftLeft2_1(data_out, data_in); output [31:0] data_out; input [31:0] data_in; genvar i; generate for (i=2; i<32; i=i+1) begin: SL2 assign data_out[i] = data_in[i-2]; end endgenerate assign data_out[0] = 0; assign data_out[1] = 0; endmodule module ShiftLeft2_2(data_out, data_in); output [27:0] data_out; input [25:0] data_in; genvar i; generate for (i=2; i<28; i=i+1) begin: SL2 assign data_out[i] = data_in[i-2]; end endgenerate assign data_out[0] = 0; assign data_out[1] = 0; endmodule

3.2.4. Khi m rng (Extend): - Phn address/immediate ca cc cu lnh I-format gm 16bit, trong khi i s ca cc lnh hoc a ch bao gm 32bit, do cn c bc m rng trc khi dng tnh ton. - Ty theo lnh m m rng du hay m rng zero, ta s dng 1 bit iu khin t khi Control la chn kiu m rng (SignEx). - Code:

module Extend(data_out, data_in, SignEx); output [31:0] data_out; input [15:0] data_in; input SignEx; assign data_out[15:0] = data_in; genvar i; generate for (i=16; i<32; i=i+1) begin: Ex and #50 (data_out[i], data_in[15], SignEx); end endgenerate endmodule

3.2.5. Cc b chn knh - Cc b chn knh c s dng chn 1 tn hiu ra t 2 tn hiu vo - Cc tn hiu iu khin ph thuc vo tng cu lnh v c a ra t khi Control - Code:
module Muxer32(data_out, data_in1, data_in2, sel); output [31:0] data_out; input [31:0] data_in1, data_in2; input sel; wire wire not buf [31:0] f1, f2; nsel, dsel; #50 #50 (nsel, sel); (dsel, sel);

genvar i; generate for (i=0; i<32; i=i+1) begin: Muxer and #50 (f1[i], nsel, data_in1[i]); and #50 (f2[i], dsel, data_in2[i]); or #50 (data_out[i], f1[i], f2[i]); end endgenerate endmodule

module Muxer5(data_out, data_in1, data_in2, sel); output [4:0] data_out; input [4:0] data_in1, data_in2; input sel;

wire wire not buf

[4:0] f1, f2; nsel, dsel; #50 #50 (nsel, sel); (dsel, sel);

genvar i; generate for (i=0; i<5; i=i+1) begin: Muxer and #50 (f1[i], nsel, data_in1[i]); and #50 (f2[i], dsel, data_in2[i]); or #50 (data_out[i], f1[i], f2[i]); end endgenerate endmodule

3.2.6. B nh chng trnh v b nh d liu: - B nh chng trnh dng lu m my ca cc cu lnh. B nh chng trnh c 210 word v c lu trong file instr.dat. - B nh d liu dng lu cc gi tr trong qu trnh tnh ton. B nh d liu c 28 word v c lu trong file data.dat. - c 2 b nh u c nh a ch byte.

3.3. Module chnh: 3.3.1. Thanh ghi PC:

- Thanh ghi PC c s dng ch n v tr ca cu lnh tip theo s c thc hin. - Khi khng c cc cu lnh r nhnh, gi tr ca thanh ghi PC sau mi chu k lnh s t ng tng ln 4. Cc cu lnh r nhnh J, JR, BNE s c tc ng lm thay i gi tr ca thanh ghi PC. - Ta s dng 1 thanh ghi PC lu gi tr hin thi v 1 thanh ghi PCIn lu gi tr tip theo ca PC khi c xung clk. - Mi khi c xung clk, gi tr ca thanh ghi PCIn s c t vo thnh ghi PC, b nh chng trnh s s dng gi tr ca thanh ghi PC ly ra cu lnh tip theo. Gi tr mi ca PC sau khi thc hin xong cu lnh s c lu vo thanh ghi PCIn i a vo PC khi c xung clk tip theo. 3.3.2. Tnh ton xung clk: - C 4 khi trong chip cn c xung clk theo th t sau: + Thanh ghi PC + B nh d liu (data memory) + B thanh ghi (Registers) + Thanh ghi PCIn - T lc c xung clk n thanh ghi PC, tn hiu i qua b nh chng trnh (1000ps), b thanh ghi (khong 500ps), khi ALU (khong 6000ps). Do , ta chn tr ca xung clk cho b nh d liu so vi xung clk ca PC l 10000ps m bo gi tr nhn c l chnh xc. - Tng t ta chn tr ca xung clk cho thanh ghi PCIn l 10000ps. - Tn hiu i qua b nh d liu mt 1000ps, ta chn tr ca xung clk cho b thanh ghi so vi b nh d liu l 2000ps. + Vic thc hin 1 cu lnh phi hon tt trong vng 1 chu k xung clk, do vy ta phi chn rng ca xung clk ln. Da vo tnh ton trn, ta chn rng ca xung clk l 15000ps, hay chu k ca xung clk l 30000ps. 3.3.3. Code:
module CPU(clk); input clk; reg reset; wire [31:0] PC, PCIn, PCIn1, PCIn2, PCIn3, PCplus4, Instruction, ExImm, SL2Imm, JumpAdr, BranchAdr; wire [31:0] ReadData1, ReadData2, RegWriteData, ALU2ndIn, ALUResult, MemOutput;

wire [4:0] WriteRegister; wire [1:0] ALUOp, ALUCtr; wire CarryOut, zero, overflow, negative, nzero; wire RegDst, Branch, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump, SignEx, JumpReg, BranchSel; wire Memclk, Regclk, PCInclk, PCclk; initial begin reset = 0; #50 reset = 1; #50 reset = 0; end assign PCclk = clk; buf #10000 (Memclk, PCclk); buf #1000 (Regclk, Memclk); buf #10000 (PCInclk, PCclk); SinReg PCInReg(PCIn, PCIn3, reset, PCInclk, 1'b1); SinReg PCReg(PC, PCIn, 1'b0, PCclk, 1'b1); InstructionMem InsMem(Instruction, PC); Regfile Registers(ReadData1, ReadData2, RegWriteData, Instruction[25:21] , Instruction[20:16], WriteRegister, RegWrite, Regclk, reset); alu ALU(ALUResult, CarryOut, zero, overflow, negative, ReadData1, ALU2ndIn, ALUCtr); DataMem DataMem(MemOutput, ALUResult, ReadData2, MemWrite, Memclk); Control Ctrl(ALUOp, RegDst, Branch, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump, SignEx, Instruction[31:26]); ALUControl ALUCtrl(ALUCtr, JumpReg, ALUOp, Instruction[5:0]); Extend Ext(ExImm, Instruction[15:0], SignEx); ShiftLeft2_1 SL1(SL2Imm, ExImm); ShiftLeft2_2 SL2(JumpAdr[27:0], Instruction[25:0]); AddCPU Add1(PCplus4, PC, 32'h00000004); AddCPU Add2(BranchAdr, PCplus4, SL2Imm); not #50 (nzero, zero); and #50 (BranchSel, Branch, nzero); assign JumpAdr[31:28] = PCplus4[31:28]; Muxer5 Muxer32 Muxer32 MemtoReg); Muxer32 Muxer32 Muxer32 Endmodule RegDstMux(WriteRegister, Instruction[20:16], Instruction[15:11], RegDst); ALUSrcMux(ALU2ndIn, ReadData2, ExImm, ALUSrc); MemtoRegMux(RegWriteData, ALUResult, MemOutput, BraSelMux(PCIn1, PCplus4, BranchAdr, BranchSel); JumpMux(PCIn2, PCIn1, JumpAdr, Jump); JumpRegMux(PCIn3, PCIn2, ReadData1, JumpReg);