8086 Signal Description

Plastic Package 40 Pins Single and Multi Processor Modes

Pin Diagram

 AD15-AD0:
Time Multiplexed Addr/Data Line T1- Address Cycle T2, T3, TW, T4- Data Cycle T are clock states of machine cycle

A19/S6- A16/S3:
Time Muxed Address/Status Lines During T1- Address line During I/O these lines are low. S5 -- status of IE Flag at beginning of each cycle. S4 , S3 indicate segment register used for memory Latches separate addr and status bits S6 is always low

S4
0 0

S3
0 1

Indication
Alternate Data Stack

1
1

0
1

Code or None
Data

 BHE /S7: BUS HIGH ENABLE

Indicates a transfer over D8-D15 S7 is not currently used. Indication BHE A0

0 0 Whole Word

0
1 1

1
0 1

Upper byte from/to odd addr

Lower byte from/to even add None

RD : Read
0 Processor is performing Read

READY:
Acknowledgement from slow devices that they completed transfer

 INTR: Interrupt Request

Level triggered input Sampled during last clock cycle of each instruction to determine availability of request. Internally Synchronized

TEST :
0 Execution continues 1 Idle State Examined by WAIT instruction

NMI:
Non-maskable interrupt Causes type 2 interrupt Cannot be masked internally

 RESET:
Stops execution and starts from FFFF0H Restarts when returns to low

CLK: Clock Input

Provides timing for processor. Square wave of 33% duty Cycle. Range: 5Mhz- 10 Mhz

VCC: +5V GND: Ground MN/MX:

1-- Min Mode 0-- Max Mode

 M/IO:
Memory/I/O Operation 0 I/O Operation 1 Memory Operation Active from T4 to present T4

INTA:
Interrupt Acknowledge 0 Processor accepted interrupt. Low during T2,T2,TW of interrupt acknowledge cycle.

ALE: Address Latch Enable

Indicates availability of valid address on address/data line Connected to latch enable input of Latches

 DT/R:
Data Transmit or receive 1- Transmit 0- Receive Same timing as M/IO

DEN: Data Enable

Availability of valid data over address/data lines Used to enable transreceivers to separate data from multiplexed address/data signal. Active from middle of T2 to middle of T4.

 HOLD/HLDA
Hold Acknowledge. 1 Another master is requesting bus access After hold processer gives hold acknowledge signal in middle of next clock cycle after current instruction cycle. 0 HDLA is also low

 S2,S1,S0:
Status lines Active from T4 to current T1,T2.
S2 0 0 0 0 1 S1 0 0 1 1 0 S0 0 1 0 1 0 Indication Interrupt Acknowledge Read I/O Port Write I/O Port Halt Code access

1
1 1

0
1 1

1
0 1

Read memory
Write memory Passive

 LOCK:
0 Other system bus masters will be prevented from gaining system bus. Activated by LOCK prefix Instruction.

QS1, QS0 Queue Status

Status of code-prefetch queue.
QS1 0 0 1 1 QS0 0 1 0 1 Indication No Operation First byte of opcode from the queue Empty Queue Subsequent byte from the queue

 RQ/GT0, RQ/GT1:
Request/Grant Used by other local bus masters to force the processor to release the local bus at end of processors current bus cycle. RQ/GT0 have high priority than RQ/GT1.