DISCRETE SEMICONDUCTORS

DATA SHEET

BF998; BF998R Silicon N-channel dual-gate MOS-FETs

Product specification Supersedes data of April 1991 1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

FEATURES Short channel transistor with high forward transfer admittance to input capacitance ratio Low noise gain controlled amplifier up to 1 GHz. APPLICATIONS VHF and UHF applications with 12 V supply voltage, such as television tuners and professional communications equipment.
Top view
handbook, halfpage

BF998; BF998R

3 g 2 g1

2 s,b
MAM039

DESCRIPTION Depletion type field effect transistor in a plastic microminiature SOT143B or SOT143R package with source and substrate interconnected. The transistors are protected against excessive input voltage surges by integrated back-to-back diodes between gates and source. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. PINNING PIN 1 2 3 4 SYMBOL s, b d g2 g1 source drain gate 2 gate 1 DESCRIPTION

Marking code: MOp.

Fig.1

Simplified outline (SOT143B) and symbol; BF998.

handbook, halfpage

d 4 g2 g1

2
Top view
Marking code: MOp.

1 s,b
MAM040

Fig.2

Simplified outline (SOT143R) and symbol; BF998R.

QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-s Crs F Tj drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure operating junction temperature f = 1 MHz f = 800 MHz PARAMETER drain-source voltage CONDITIONS 24 2.1 25 1 TYP. MAX. 12 30 200 150 V mA mW mS pF fF dB C UNIT

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Ptot Tstg Tj Notes 1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm. 2. Device mounted on a printed-circuit board. PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation; BF998 up to Tamb = 60 C; see Fig.3; note 1 up to Tamb = 50 C; see Fig.3; note 2 total power dissipation; BF998R up to Tamb = 50 C; see Fig.4; note 1 storage temperature operating junction temperature CONDITIONS 65

BF998; BF998R

MIN.

MAX. 12 30 10 10 200 200 200 +150 150 V

UNIT mA mA mA mW mW mW C C

MLA198

MGA002

handbook, halfpage

handbook, halfpage

200 Ptot max (mW) (2) (1)

200 Ptot max (mW)

100

100

0 0 100 Tamb (o C) 200

0 0 100 Tamb (C) 200

(1) Ceramic substrate. (2) Printed-circuit board.

Fig.3 Power derating curves; BF998.

Fig.4 Power derating curve; BF998R.

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-a Notes 1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm. 2. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VG2-S = VDS = 0; IG1-SS = 10 mA VG1-S = VDS = 0; IG2-SS = 10 mA VG2-S = 4 V; VDS = 8 V; ID = 20 A VG1-S = 0; VDS = 8 V; ID = 20 A PARAMETER thermal resistance from junction to ambient in free air; BF998

BF998; BF998R

CONDITIONS note 1 note 2

VALUE 460 500 500

UNIT K/W K/W K/W

thermal resistance from junction to ambient in free air; BF998R note 1

MIN. 6 6 2

MAX. 20 20 2.0 1.5 18 50 50

UNIT V V V V mA nA nA

V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS gate 2-source breakdown voltage V(P)G1-S V(P)G2-S IDSS IG1-SS IG2-SS Note 1. Measured under pulse condition. gate 1-source cut-off voltage gate 2-source cut-off voltage drain-source current gate 1 cut-off current gate 2 cut-off current

VG2-S = 4 V; VDS = 8 V; VG1-S = 0; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 5 V

DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VDS = 8 V; VG2-S = 4 V; ID = 10 mA. SYMBOL yfs Cig1-s Cig2-s Cos Crs F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance reverse transfer capacitance noise figure f = 1 kHz f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BSopt f = 800 MHz; GS = 3.3 mS; BS = BSopt CONDITIONS MIN. 21 TYP. 24 2.1 1.2 1.05 25 0.6 1.0 MAX. 2.5 UNIT mS pF pF pF fF dB dB

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

BF998; BF998R

handbook, halfpage I

24

MGE813

D (mA)

handbook, halfpage I

24

MGE815

VG1-S = 0.4 V 0.3 V

20

D (mA) 20

3V VG2-S = 4 V 2V 1V

16

0.2 V 0.1 V 0V

16

12

12

0.1 V 0.2 V

0 0 2 4 6 8 VDS (V)

0.3 V 0.4 V 0.5 V 10

0V

0 1

VG1 (V)

VG2-S = 4 V; Tamb = 25 C.

VDS = 8 V; Tamb = 25 C.

Fig.5 Output characteristics; typical values.

Fig.6 Transfer characteristics; typical values.

handbook, halfpage I

24

MGE814

MGE811

D (mA) 20

handbook, halfpage

30

max

typ

|yfs| (mS) 24

4V 3V 2V 1V

16 18 12 min 12 8 6 VG2-S = 0 V 0 0 4 8 12 16 ID (mA) 20 0.5 V

0 1600

1200

800

400

0 VG1 (mV)

400

VDS = 8 V; VG2-S = 4 V; Tamb = 25 C.

VDS = 8 V; Tamb = 25 C.

Fig.7

Drain current as a function of gate 1 voltage; typical values.

Fig.8

Forward transfer admittance as a function of drain current; typical values.

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

BF998; BF998R

MGE812

MGE810

handbook, halfpage

30

|yfs| (mS) 24

VG2-S = 4 V

handbook, halfpage

1.5

Cos (pF)

1.4 3V

18

1.3

12

2V

1.2 12 mA

1V

1.1

10 mA 8 mA

0V 0 1 1.0 0 VG1 (V) 1 4 6 8 10 12 VDS (V) 14

VDS = 8 V; Tamb = 25 C.

VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.

Fig.9

Forward transfer admittance as a function of gate 1 voltage; typical values.

Fig.10 Output capacitance as a function of drain-source voltage; typical values.

handbook, halfpage

2.3 Cis 2.1

MGE809

MBH479

handbook, halfpage

2.4

(pF)

Cis (pF) 2.3

1.9

2.2
1.7

2.1
1.5

1.3 2.4

1.6

0.8

2.0
0 0.8 VG1-S (V)

2 VG2S (V)

VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.

VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 C.

Fig.11 Gate 1 input capacitance as a function of gate 1-source voltage; typical values.

Fig.12 Gate 1 input capacitance as a function of gate 2-source voltage; typical values.

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

BF998; BF998R

MGC466

10 y is (mS) b is 1

10 3 y rs (S) 10 2

MGC467

10 3

rs (deg)

rs
y rs

10 2

10 1 g is

10

10

10 2 10

102

f (MHz)

10 3

1 10

1 102 f (MHz) 10 3

VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.

VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.

Fig.13 Input admittance as a function of the frequency; typical values.

Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values.

10 2

MGC468

10 2

MGC469

10 yos (mS) 1

y fs (mS)

y fs

fs
(deg)

bos

10

10 fs 10 1 gos

1 10

1 102 f (MHz) 10 3

10 2 10

102

f (MHz)

10 3

VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.

VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.

Fig.15 Forward transfer admittance and phase as a function of frequency; typical values.

Fig.16 Output admittance as a function of the frequency; typical values.

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

BF998; BF998R

handbook, full pagewidth

VDD 47 F Vagc 1 nF 1 nF 47 k 1 nF 50 input C1 5.5 pF 1 nF 15 pF L1 140 k VDD 1 nF D1 BB405 330 k D2 BB405 330 k 360 10 pF 1.8 k L2 1 nF

20 H 1 nF 50 output

100 k Vtun input

1 nF Vtun output

1 nF

MGE802

VDD = 12 V; GS = 2 mS; GL = 0.5 mS. L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm. L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm. Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS.

Fig.17 Gain control test circuit at f = 200 MHz.

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

BF998; BF998R

handbook, full pagewidth

VDD

Vagc 1 nF

VDD 1 nF

140 k 100 k 1 nF 270 k L1 50 input 1 nF L2 1 nF C1 2 to 18 pF C2 0.5 to 3.5 pF 1.8 k 360 1 nF L3 L4 1 nF 50 output

C3 0.5 to 3.5 pF

C4 4 to 40 pF

MGE801

VDD

VDD = 12 V; GS = 3.3 mS; GL = 1 mS. L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm. L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane. L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.

Fig.18 Gain control test circuit at f = 800 MHz.

1996 Aug 01

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

BF998; BF998R

MGE808

MGE807

handbook, halfpage

Gtr (dB)

handbook, halfpage

Gtr (dB)

10

10

IDSS = max typ min

20

20

30

30

40

IDSS = max typ min 0

2 4 6 8 Vagc (V)

40

50

10

50

8 Vagc (V)

10

VDD = 12 V; f = 200 MHz; Tamb = 25 C.

VDD = 12 V; f = 800 MHz; Tamb = 25 C.

Fig.19 Automatic gain control characteristics measured in circuit of Fig.17.

Fig.20 Automatic gain control characteristics measured in circuit of Fig.18.

1996 Aug 01

10

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

PACKAGE OUTLINES
Plastic surface-mounted package; 4 leads

BF998; BF998R

SOT143B

y v M A HE

e bp w M B

3
Q

A1 c

1
b1 e1

2
Lp detail X

1 scale

2 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1

OUTLINE VERSION SOT143B

REFERENCES IEC JEDEC JEITA

EUROPEAN PROJECTION

ISSUE DATE 04-11-16 06-03-16

1996 Aug 01

11

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

BF998; BF998R

Plastic surface-mounted package; reverse pinning; 4 leads

SOT143R

y v M A HE

e bp w M B

4
Q

A1 c

2
b1 e1

1
Lp detail X

1 scale

2 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1

OUTLINE VERSION SOT143R

REFERENCES IEC JEDEC JEITA SC-61AA

EUROPEAN PROJECTION

ISSUE DATE 04-11-16 06-03-16

1996 Aug 01

12

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

DATA SHEET STATUS DOCUMENT STATUS(1) Objective data sheet Preliminary data sheet Product data sheet Notes PRODUCT STATUS(2) Development Qualification Production DEFINITION

BF998; BF998R

This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.

1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DEFINITIONS Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customers sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customers applications and products planned, as well as for the planned application and use of customers third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

1996 Aug 01

13

NXP Semiconductors

Product specification

Silicon N-channel dual-gate MOS-FETs

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customers applications or products, or the application or use by customers third party customer(s). Customer is responsible for doing all necessary testing for the customers applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customers third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customers general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

BF998; BF998R

Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customers own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications.

1996 Aug 01

14

NXP Semiconductors
provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise

Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.

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NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands

R77/02/pp15

Date of release:1996 Aug 01