Professional Documents
Culture Documents
Synthesis
Pavan Kumar KV
Definition
Synthesis is a translation of a behavioral (RTL) representation of a design into a structural one. Automatic process with user control
Translation
Converts HDL to functional boolean equivalent HDL syntax/rule checks Optimizes HDL Arithmetic function mapping Sequential function mapping Combinational function mapping
Flattening
The conversion of multiple boolean equations into a two level sum-of-products form (AND/OR) is called flattening. All the intermediate terms are removed. Thus, flattening removes all logic structure from a design. The result of flattening is a two-level, sum-of-products form. Before flattening out = t1.t2 t1 = a + b(c + f) t2 = d + e' After flattening out = ad + bcd + bdf + ae+ bce' + be'f Not all designs can be flattened successfully by the tools. Small designs of 10 inputs or less can always be flattened. Large designs having 20 or more inputs are often impossible to flatten. Designs with many XOR and multiplexer gates, such as adders and ALUs, are generally difficult to flatten. For example An N-bit XOR function produces 2 n-1 terms. A 20-input XOR gate, when flattened, has 219 (524,288) terms.
Factorization/Structuring
The factorization of Boolean equations is a process of adding intermediate terms. This adds implied logic structure which both reduces the size of implied circuit and reduces large fanouts. Adding structure adds levels of logic which tend to make a circuit smaller but it may be slower.
In the above eg. Facorization after flattening gave better results. The results may vary from case to case. The tools will choose the optimal optimization tecniques to meet the constraints.
Mapping/Optimization
Maps boolean functions to technology specific primitive functions Modifies mapping to meet design goals Design Rules Timing Area Power
Optimization: Constraint-Driven
Synthesis/Physical Synthesis
Outline: Set Up
DC Setup Files
Setup files automatically read at DC startup .synopsys_dc.setup Possible locations (read in this order) 1. Root setup: $SYNOPSYS/admin/setup/.synopsys_dc.setup 2. Home setup: $HOME/.synopsys_dc.setup (optional) 3. Local setup: ./.synopsys_dc.setup (optional) Use to customize the work environment
Library Setup
search_path Allows files to be read in without specifying directory path in the command Directories in which DC will look for library/design .db files during a link target_library Technology cell library files (i.e. lsi_10k.db) Compile chooses inferred cells from target library link_library Used during design linking (pre- and post-compile) All cells in a design must be in one of the link libraries Inferred (chosen during compile based on RTL functionality) Instantiated (specific cell instance placed in design RTL) link_library must always start with "*", indicating loaded designs should be searched first when linking All synthetic and target libraries must be included in link_library synthetic_library Library of DesignWare components dw_foundation.sldb Advanced set of IP components optional to DC Wide variety moderate/high performance arithmetic architectures Fifos, stacks, counters, digital PLL, arbiters, priority encoders, SRAM models, ECC, CRC, debugger, decoders/encoders, more... Macrocells: 8051 microcontroller, 16550 UART, Memory BIST controller, AMBA peripherals(I2C, UART, SSI, APB, AHB, ) define_design_lib Directory where DC places intermediate design files (default is directory in which DC is run) set_dont_use <lib>/<cell> Specifies cells of a target library or implementations of a synthetic library to not use during compile
Analyze
Elaborate
Second step of HDL translation Builds generic technology(GTECH) database
HDL parameters are expanded Registers and latches are inferred Links design
read_file
read_file performs analysis and elaboration(except link) in one step Parameter passing/architecture selection not supported Recommended for reading mapped netlists
dc_shell-t> read_file help Usage: read_file # read file from disk [-format format_name] (verilog, vhdl, ddc, db) [-single_file file_name] (group all designs into this file) [-define macro_names] (list of top-level macros, Verilog and SystemVerilog only) [-library library_name] (Use this library as the work library, VHDL only) [-work library_name] (Use this library as the work library, VHDL only) [-names_file file_list] (list of files for name changes) [-ilm] (Read from the Milkyway ILM view) [-rtl] (register transfer-level verilog/vhdl format) file_list (list of files to read)
Defining Wireload Models (WLM) set_wireload_model, set_wireload_mode Fanout-based statistical model for estimating wire capacitance Needed for non-DCT runs Not as accurate as DCT method Default wireloads provided in technology library generally inaccurate Custom wireload generated from accurate floorplan of the design gives best results DC Topographical (DCT) calculates net parasitics based on physical layout Correlates well to place and route timing Modeling the System Interface Defining drive characteristics for input ports set_driving_cell (or) set_drive (or) set_input_transition Defining loads on input and output ports set_load Defining fanout loads on output ports
Constraint Guidelines
Golden rule #1: set realistic constraints Most critical for timing and DRC constraints Golden rule #2: validate constraints check_design check_timing report_timing_requirements Corollary: Garbage in, garbage out Correlation issues Derate Adjusting constraints to account for unmodeled effects Over-constraining Modifying constraints to drive optimization to desired goal
Optimization Priority
Design goals often conflict Optimization engines must resolve conflict Priority rules DC priority DRC Timing Power Area Can be modified with set_cost_priority
Example
Top-Down Compile
Benefits: Optimization engines work on full design, complete paths Usually get best optimization result No iteration required Simpler constraints Simpler data management Drawbacks: Longer runtime More processing required More memory required
Bottom-Up Compile
Benefits: Divide-and-conquer methodology localizes problem areas Budgeting method enables parallelized synthesis effort Less processing required per run Less memory required per run Drawbacks: Optimization works on sub-designs, hierarchical path segments Optimization result not as good as top-down compile Iterations may be required More hierarchies and data to maintain More work for user More error-prone
compile_ultra
Advanced datapath synthesis Optimized arithmetic trees Carry save logic Embedded scripts targeting area/timing Automatic ungrouping Automatic boundary optimization Topographical technology for best timing correlation Library aware structuring and mapping
Best Practice: Use a reasonable amount for critical range (i.e. 10% of the clock period). The larger the critical range, the longer the compile time.
Ungroup Hierarchy
Optimization works on paths within hierarchical boundaries Removing hierarchical boundaries allows optimization algorithms to work on larger or entire paths Produces better optimization results For best timing results, remove hierarchy on critical paths For best area results, remove as much hierarchy as possible compile_ultra automatically ungroups as needed ungroup allows manual ungrouping
Register Retiming
Moves registers through combinational gates to improve timing/area optimize_registers/set_optimize_registers Use for pipelined designs and aggressive retiming pipeline_design Use to pipeline designs compile_ultra retime Use for non-pipelined designs and less aggressive retiming
Clock Gating
Clock gating not only can save power, it can also help in area savings insert_clock_gating Run before compile_ultra
saves one mux per register, by using only one clock gate per register bank
report_design
Operating conditions Wire load model and mode Internal input and output pin delays Disabled timing arcs
report_clock
Clock definition Clock latency Clock skew
check_design
Use check_design to check consistency Consistency means no unintentionally unconnected ports no unintentionally tied ports no cells without input or output pins no mismatch between a cell and its reference no multiple-driver nets no recursive hierarchy
check_timing
Unconstrained timing paths Clock-gating logic
Unmapped cells
report_qor
Timing summary for all path groups Good overall status of design timing
report_constraint
Shows difference between user constraints and actual design values
report_delay_calculation
Shows how report_timing calculates delay of a timing arc (cell or net) Use to understand contributors to Delay calcs
.lib .lbr
.g .SDC
RTL
.SDC .g
Optimized netlist
Physical Design
Synthesis Features
Encounter RTL Compiler synthesis provides the following features: Large capacity for top-down synthesis Fast linear runtimes Global optimization finds the best overall structure Well balanced structure for congestion and timing closure Support for super-threading Support for multisupply voltage (MSV) design synthesis
Synthesis Flow
Netlist, SDC
Meet constraints?
No
Yes
Place and Route
Release - 2003.1
55
Setting Attributes
In the compiler, there are predefined attributes associated with objects in the database. Use the set_attribute or set_attr command to assign values to these attributes. Syntax set_attribute <attribute name> <value> <object> To get information on all the attributes containing the word clock, enter:
set_attr h *clock* *
Examples Root attribute (Notice the fourth argument): set_attribute lp_insert_clock_gating true / Design attribute: set_attr lp_clock_gating_exclude true /des*/top_mod
Querying Attributes
To retrieve the value of an attribute, use: Syntax get_attribute {attribute_name [object]} | {-h object_type [attribute_name]} Works on a single object. Or ls l a (a = attribute, l = long list) Examples get_attr propagated_clocks $pin get_attr load /libraries/slow/INVX1/A ls la / ls l a /designs/dtmf_chip
Finding all the output ports find /des* -port ports_out/* Finding all pins in a hierarchical instance v1 Finding all subdesigns. Finding all hierarchical instances in the design Finding all clocks in the design Finding all available wireload models in a library find /des* -pin find /des* -pin find / -subd * set inst_list [find / -instance *] echo $inst_list find / -clock * [find [find / -library <LibraryName>] wireload *] inst*hier/v1/* v1/*
The library attribute specifies the target technology for synthesis. To load a single library, enter set_attr library lsi500k.lib / The library attribute is a root attribute. To load multiple libraries, enter set lib_list1 01_wc3.lib mylib1.lib x1.lib set_attr library $lib_list Setting the library attribute loads the specified libraries into the synthesis environment (and populates the /libraries virtual directory). To append the main library database, enter set_attr library {{a.lib b.lib} c.lib {x.lib y.lib}} / In this example, the compiler loads a.lib and appends b.lib to a.lib. Next, it loads c.lib. Then, it loads x.lib and appends y.lib to x.lib.
process : 1 ; temperature : 125 ; voltage : 1.35 ; tree_type : balanced_tree ; } operating_conditions(TYPICAL) { process : 1 ; temperature : 70 ; voltage : 1.35 ; tree_type : balanced_tree ; } operating_conditions(BEST) { process : 1 ; temperature : 0 ; voltage : 1.35 ; tree_type : best_case_tree ; }
mode=top
60x60 40x40 20x20
60x60
20x20
40x40
20x20
mode=enclosed
60x60 40x40 20x20
wire_load_selection(predcaps){ wire_load_from_area(0, 10000, "10K"); wire_load_from_area(10000, 15000, "20K"); wire_load_from_area(15000, 40000, "40K"); ... } default_wire_load_mode : segmented; default_wire_load_selection : predcaps;
40x40
Reading Designs
Use the read_hdl or read_netlist commands to parse the HDL source. Syntax read_hdl [-h][-vhdl|-sv][-v1995|-v2001][-netlist] [-define macro=name] file(s)<.gz> -vhdl By default, the compiler reads VHDL-1993. -sv Read System Verilog files -v1995 (Boolean) force Verilog 1995 mode. -v2001 (Boolean) force Verilog 2001 mode. -define Define Verilog macros Examples To read the RTL or mixed source (RTL/gate) design: read_hdl {design1.v subdes1.v subdes2.v} To read the gate-level (structural) netlist: read_netlist design_struc1.v
Elaboration of Designs
The elaborate Command Builds data structures and infers registers in the design. Performs higher level HDL optimization, such as dead code removal. Uses generic gates in elaborated netlist Elaborate is only required for the top-level design and it automatically elaborates all its references. elaborate [-h] [-parameter {} ] [<top_module_name>] Example
elaborate -parameter {12 8 16} TOP When compiling, these parameters will be modified as follows: data_width1 = 12 averg_period = 8 data_width2 = 16
module TOP ( data_in , data_out , averg_per_sel ) ; parameter data_width1 = 12; 3; parameter averg_period = 8; 2; parameter data_width2 = 16; 4; input [data_width1-1:0] data_in ;
Missing Constraint
Unclocked primary I/Os Unclocked flops
Solution
Define external_delay for these I/Os. Check the fanin cone of these flops using the fanin command. To see which clocks are being propagated to that pin, use the inverting_clocks or non_inverting_clocks attribute of the pin. Use the timing_case_logic_value attribute to propagate only one clock to that pin (set_case_analysis).
Timing exceptions overwriting other timing exceptions, such as setting a false path and multicycle path starting in the same register. Timing exceptions that cannot be satisfied, such as a false path that starts in a flop that was deleted.
Reporting
report area report datapath report design_rules report gates report hierarchy report instance report memory report messages report power report qor report timing report summary Prints an exhaustive hierarchical area report. Prints a datapath resources report. Prints design rule violations. Reports libcells used, total area and instance count summary. Prints a hierarchy report. Prints an instance report. Prints a memory usage report. Prints a summary of error messages that have been issued. Prints a power report. Prints a quality of results report. Prints a timing report. Prints an area, timing, and design rules report.
[all::all_seqs]
The all:: commands are Tcl procedures that are part of load_etc.tcl, which is part of your installation hierarchy. Please include load_etc.tcl before using these commands. The .synth_init is a good place to do this.
puts "WNS path/timing among CLK to outputs in domain $clk " report timing -from $clk -to [all::all_outs] puts "WNS path/timing among CLK to D paths in domain $clk" report timing -from $clk -to [all::all_seqs]
puts "WNS path/timing among paths that cross from $clk to $clk2 domains" report timing -from $clk -to $clk2
Generating Outputs
Commands for Generating Outputs Use the write_hdl command to generate a gate-level netlist. write_hdl > | >> filename Use write_script command to generate the constraints file. write_script > | >> design_constraints.g Use write_sdc command to export RTL Complier constraints in the SDC Tcl format. write_sdc [design] > | >> [filename]
Use the > symbol to redirect the output to a file or >> to append it to the file.
write_hdl > <path to the output dir>/design.v
Example Script
set_attr information_level 9 / set_attr lib_search_path <UNIX Library Search Path> set_attr hdl_search_path <UNIX HDL Search Path> set_attr library {<library01> <library02> <libraryNN> } read_hdl { <design01>.v <design02>.v <designNN>.v }
Set the diagnostic variables.
Load all the libraries for the design. Load all the modules of the design. Elaborate the top level module. Set the design and timing constraints. Synthesize and map the design.
elaborate <TopLevel DesignName> read_sdc constraints.sdc synthesize -to_mapped report timing -num_path 10 > timing_10_worst.rpt report area > area.rpt report gates > gates.rpt write_hdl > <NetlistFileName> write_sdc > < file name>
Create reports.
Command Help
You can get help on all the commands by entering: man command_name To view man pages from the UNIX shell, set your environment using: setenv MANPATH $CDN_SYNTH_ROOT/share/synth/man When you are unsure of a command, type the first few letters of the command and press the Tab key to display a list of commands that start with those letters. Example path_ This command returns the following: ambiguous "path_": path_adjust path_delay path_disable path_group Entering path_* -h does the same as the previous command and provides help for commands.
Thank You