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Rev. 0.

3 4/09 Copyright 2009 by Silicon Laboratories AN94


AN94
Si 2401 MODEM DESI GNERS GUI DE
1. Introduction
This application note is intended to supplement the
Si2401 data sheet and is divided into two sections: The
"Functional Description" on page 4 and the "Software
Design Reference" on page 15. The Hardware Design
Reference provides functional descriptions and
information necessary to design ISOmodem

hardware.
Chipset specifications can be found in the data sheet.
The Software Design Reference includes information on
how to control the functionality of the modem with AT
commands and register settings. Particular topics of
interest in either design reference can be easily located
through the Table of Contents or the comprehensive
index located at the back of this document.
The Hardware Design Reference is divided into three
sections. The first section describes the modulations
and protocols supported by the chipset. Next, the
modem and DAA chip operation are described, and a
reference design including a suggested bill of materials
is presented. Silicon Laboratories also has printed
circuit board layout files available separately. These
include double-sided and single-sided layouts with
options for through-hole isolation components.
Additionally, evaluation boards, useful for evaluating the
modem chipset or for initial prototyping work, are
available. Check with your Silicon Laboratories
salesperson or distributor for more details.
The Software Design Reference consists of sections
focused on the modem controller, memory, and digital
interface. The modem controller section includes a
complete description of AT commands, fast connect
options, transparent HDLC/synchronous access mode,
escape methods, and default settings. The memory
section describes the S-Registers used to configure
both the modem chip and the line-side DAA chip. The
digital interface chapter provides details about the serial
interface capability of the modem. Additionally, there are
several programming examples, a section on testing,
and a comprehensive section with configuration settings
for most countries. Several appendices contain
information on PCB layout, a prototype bring-up guide,
and suggestions for transitioning a Si2400 design to a
Si2401 design.
Figure 1. Functional Block Diagram
Si3010
Isolation
Interface
Hybrid
and dc
Termination
Ring Detect
Off-Hook
TIP
RING
External
Circuitry
Isolation Barrier
U
A
R
T
Controller
(AT Decoder,
Call Progress)
I
s
o
l
a
t
i
o
n

I
n
t
e
r
f
a
c
e
Control
Interface
Clock
Interface
DSP
(Data Pump)
RXD
TXD
RESET
EOFR/GPIO1
XOUT
XTALI
Si2401
CTS
RI/GPIO5
INT/GPIO4
ESC/GPIO3
CD/GPIO2
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2 Rev. 0.3
AN94
Rev. 0.3 3
TABLE OF CONTENTS
Section Page
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Hardware Design Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1. Modulations and Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2. Modem and DAA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3. Modem (System-Side) Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5. Power Supply and Bias Circuitry (Si2401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.6. Isolation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.7. System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.8. DAA (Line-Side) Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.9. Power Supply and Bias Circuitry (Si3010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.10. Ringer Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.11. DAA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.12. Emissions/Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.13. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.14. AC Termination (Si3010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.15. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.16. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.17. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.18. Billing Tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.19. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.20. Bill of Materials: Si2401/3010 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Software Design Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2. Configurations and Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3. Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4. AT Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5. S-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7. Low Level DSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.8. Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5. Si2401 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1. CTR-21 Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.2. FCC68 Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.4. Board Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6. UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Appendix AISOmodem Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix BPrototype Bring-Up Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Appendix CTransitioning from the Si2400 to the Si2401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Appendix DSi3008 Supplement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Appendix ESi3006 Supplement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Appendix FSi2401/Si3008 Prototype Bring-Up Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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4 Rev. 0.3
2. Functional Description
The Si2401 is a complete modem chipset with integrated direct access arrangement (DAA) that provides a
programmable line interface to meet global telephone line requirements. Available in two 16-pin small-outline
packages, this solution includes a DSP data pump, modem controller, codec, and DAA.
The modem accepts simple modem AT commands and provides connect rates up to 2400 bps full-duplex over the
Public Switched Telephone Network (PSTN) with V.42 hardware support through HDLC framing. To minimize
handshake times, the Si2401 can implement a V.22-based fast connect. The modem also supports the V.23
reversing protocol and standard alarm formats including SIA.
This device is ideal for embedded modem applications due to its small board space, low power consumption, and
global compliance. The Si2401 solution integrates a silicon DAA using Silicon Laboratories proprietary third-
generation isolation technology. This highly-integrated DAA can be programmed to meet worldwide PTT
specifications for ac termination, dc termination, ringer impedance, and ringer threshold. The DAA can also monitor
line status for parallel handset detection and overcurrent conditions.
The Si2401 is designed for rapid assimilation into existing modem applications. The device interfaces directly
through a UART to a microcontroller. The Si2401URT-EVB evaluation board connects directly to a standard RS-
232 interface. This allows for evaluation of the modem immediately upon powerup via HyperTerminal or any
standard terminal software.
The chipset can be fully programmed to meet international telephone line interface requirements with full
compliance to FCC, TBR-21, JATE, and other country-specific PTT specifications. In addition, the Si2401 has been
designed to meet the most stringent worldwide requirements for out-of-band energy, billing-tone immunity, high-
voltage surges, and safety requirements.
Table 1. Selectable Configurations
Configuration Modulation
Carrier
Frequency (Hz)
Data Rate
(bps)
Standard
Compliance
V.21 FSK 1080/1750 300 Full
V.22
*
DPSK 1200/2400 1200 Full
V.22bis
*
QAM 1200/2400 2400 No retrain
V.23
FSK
1300/2100 1200/75
Full; plus reversing
(Europe)
V.23 1300/1700 600/75
Bell 103 FSK 1170/2125 300 Full
Bell 212A DPSK 1200/2400 1200 Full
Security DTMF 40 Full
SIAPulse Pulse Low Full
SIA Format FSK 1170/2125 300 half-duplex 300 bps only
*Note: The Si2401 only adjusts its DCE rate from 2400 bps to 1200 bps if it is connecting to a V.22-only (1200 bps only)
modem. Because the V.22bis specification does not outline a fallback procedure, the host should implement a
fallback mechanism consisting of hanging up and connecting at a lower baud rate. Retraining to accommodate
changes in line conditions that occur during a call must be implemented by terminating the call and redialing.
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Rev. 0.3 5
3. Hardware Design Reference
The Si2401 chipset consists of a 16-pin SOIC low-
voltage modem chip (Si2401) and a 16-pin SOIC line-
side DAA chip (Si3010) connecting directly with the
telephone local loop (TIP and RING). This modem
solution is a complete hardware (controller-based)
modem that connects to a host processor through a
serial interface. Isolation is provided by Silicon
Laboratories isolation technology, which uses high-
voltage capacitors instead of a transformer. This
isolation technology complies with global
telecommunications standards including FCC, CTR-21,
JATE, and all known country-specific requirements.
Country, EMI/EMC, and safety test reports are
available. Check with your Silicon Laboratories
salesperson or distributor for more details.
Additional features include programmable ac/dc
termination and ring impedance, on-hook and off-hook
intrusion detection, caller ID, loop voltage/loop current
monitoring, overcurrent detection, ring detection, and
the switch-hook function.
All required program and data memory is included in the
modem chip. When the modem receives a software or
hardware reset, all register settings revert to the default
values stored in the on-chip program memory. The host
processor interacts with the modem controller through
AT commands used to change register settings and
control modem operation. Changing register settings
and controlling the modem is described in the Software
Design Reference.
3.1. Modulations and Protocols
Tables 1 and 2 list the modulations and protocols and
carriers and tones supported by the Si2401 modem.
The Si2401 supports all modulations and protocols from
Bell 103 through V.22bis but does not include error
correction or compression.
Table 2. Carriers and Tones
Specification Transmit
Carrier (Hz)
Receive
Carrier (Hz)
Answer
Tone (Hz)
Carrier Detect
(Acquire/Release)
V.22bis, V.22
Originate
Answer
1200
2400
2400
1200
2100
43 dBm/48 dBm
43 dBm/48 dBm
V.23 fwd rev 1300/2100
390/450

43 dBm/48 dBm
43 dBm/48 dBm
V.21
Originate (M/S)
Answer (M/S)
1180/980
1850/1650
1850/1650
1180/980
2100
43 dBm/48 dBm
43 dBm/48 dBm
Bell212A
Originate
Answer
1200
2400
2400
1200
2225
43 dBm/48 dBm
43 dBm/48 dBm
Bell103
Originate (M/S)
Answer (M/S)
1270/1070
2225/2025
2225/2025
1270/1070
2225
43 dBm/48 dBm
43 dBm/48 dBm
AN94
6 Rev. 0.3
3.2. Modem and DAA Operation
This section describes hardware design requirements
for optimum Si2401 modem chipset implementation.
There are three important considerations for any
hardware design. First, the reference design and
components listed in the associated bill-of-materials
should be followed exactly. These designs reflect field
experience with millions of deployed units throughout
the world and are optimized for cost and performance.
Any deviation from the reference design schematic and
components will likely have an adverse affect on
performance. Secondly, circuit board layouts must
rigorously follow "Appendix AISOmodem Layout
Guidelines" on page 92. Deviations from these layout
techniques will likely impact modem performance and
regulatory compliance. Finally, all reference designs use
a standard component numbering scheme. This
simplifies documentation references and
communication with the Silicon Laboratories technical
support team. It is strongly recommended that these
same component reference designators be used in all
ISOmodem

designs.
The following sections describe the operation and
design considerations of the modem chip, DAA chip,
and associated circuitry.
3.3. Modem (System-Side) Chip
The Si2401 modem chip contains a controller, a DSP,
program memory (ROM), data memory (RAM), a serial
interface, a crystal oscillator, and an isolation interface.
The "Typical Application Schematic" on page 13 clearly
shows that in spite of the significant internal complexity
of the chip, the external support circuitry is very simple.
The following section describes the function and use of
the pins and some important considerations for the
selection and placement of components.
3.4. Crystal Oscillator
The Si2401 contains an on-chip clock generator. Using
a single master clock input, the Si2401 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 27 MHz or
4.9152 MHz clock on XTALI or a 4.9152 MHz crystal
across XTALI and XTALO form the master clock for the
Si2401. This clock source is sent to an internal phase
locked loop (PLL), which generates all necessary
internal system clocks. The PLL has a settling time of
~1 ms. Data on RXD should not be sent to the device
prior to settling of the PLL.
The crystal oscillator circuit requires a 4.9152 MHz
fundamental mode parallel-resonant crystal. Typical
crystals require a 20 pF load capacitance. This load is
calculated as the series combination of the capacitance
from each crystal terminal to ground including parasitic
capacitance due to package pins and PCB traces. The
parasitic capacitance is estimated as 7 pF per terminal.
This in combination with the 33 pF capacitor provides
40 pF per terminal, which, in series, yields the proper
20 pF load for the crystal.
Frequency stability and accuracy are critically important
to the performance of the modem. ITU-T specifications
require less than 200 ppm difference in the carrier
frequency of two modems. This value, split between the
two modems, requires the oscillator frequency of each
modem to be accurate and stable over all operating
conditions to within 100 ppm. This tolerance includes
the initial accuracy of the crystal, frequency drift over
the temperature range the crystal will experience, and
five year aging of the crystal. Other factors affecting the
oscillator frequency include the tolerance and
temperature drift of the load capacitor values.
The CLKIN/XTALI pin (pin 1) can accept a 3.3 V
external 4.9152 MHz clock signal meeting the accuracy
and stability requirements described above. This is the
only input pin on the modem that is not 5 V tolerant. The
Si2401 will accept a 27 MHz clock that meets the
voltage and stability requirements described above if a
<10 kO resistor is connected between Pin 11 (GPIO4)
and Pin 12 (Gnd) and the Si2401 is reset.
3.5. Power Supply and Bias Circuitry
(Si2401)
Power supply bypassing is important for the proper
operation of the Si2401, the suppression of unwanted
radiation and prevention of interfering signals and noise
from being coupled into the modem via the power
supply. C50 provides filtering of the 3.3 V system power
and must be located as close to the Si2401 chip as
possible to minimize lead lengths. The best practice is
to use surface mount components connected between a
power plane and a ground plane. This technique
minimizes the inductive effects of component leads and
PCB traces and provides bypassing over the widest
possible frequency range.
Two bias voltages used inside the modem chip require
external bypassing and/or clamping. V
A
(pin 13) is
bypassed by C51. R12 and R13 are optional resistors
that can, in some cases, reduce radiated emissions due
to signals associated with the isolation interface. These
components must be located as close to the Si2401
chip as possible to minimize lead lengths.
AN94
Rev. 0.3 7
3.6. Isolation Interface
The interface connecting the modem chip and the DAA
chip through a high-voltage isolation barrier provided by
capacitors C1 and C2 serves three purposes. First, it
transfers control signals and transmit data from the
modem chip to the DAA chip. Secondly, it transfers
receive and status data from the DAA chip to the
modem chip. Finally, it provides power from the modem
chip to the DAA chip while the modem is in the on-hook
condition. The signaling on this interface is intended for
communication between the modem and the DAA chips
and cannot be used for any other purpose. It is
important to keep the length of the C1 and C2 traces as
short and direct as possible. The layout guidelines for
the pins and components associated with this interface
are described in "Appendix AISOmodem Layout
Guidelines" on page 92 and must be carefully followed
to ensure proper operation and avoid unwanted
emissions.
3.7. System Interface
The serial interface allows the host processor to
communicate with the modem controller through a
UART driver. In this mode, the modem is analogous to
an external box modem. The interface pins are 5 V
tolerant, and communicate with TTL compatible low-
voltage CMOS levels. RS232 interface chips, such as
those used on the Si2401URT-EVB evaluation board,
can be used to make the serial interface directly
compatible with a PC or terminal serial port. The
operation of these pins is described in the section,
"Software Design Reference" on page 15.
3.8. DAA (Line-Side) Chip
The Si3010, DAA or line-side chip, contains an ADC, a
DAC, control circuitry, and an isolation interface. The
Si3010 and surrounding circuitry provide all functionality
for telephone line interface requirement compliance
including a full-wave bridge, hookswitch, dc termination,
ac termination, ring detect, loop voltage/current
monitoring, and call progress monitoring. A schematic
of the Si3010 circuitry is shown in Figure 2 with the
component functions identified. Additionally, the Si3010
external circuitry is largely responsible for EMI, EMC,
safety, and surge performance.
3.9. Power Supply and Bias Circuitry
(Si3010)
The Si3010 is powered by a small current passed
across the isolation barrier in the on-hook mode and by
the loop current in the off-hook mode. Since there is no
system ground reference for the line-side chip due to
isolation requirements, a virtual ground, IGND, is used
as a reference point for the Si3010. Several bias
voltages and signal reference points used inside the
DAA chip require external bypassing, filtering, and/or
clamping. VREG2 (pin 10) is bypassed by C6. VREG
(pin 7) is bypassed by C5. These components must be
located as close to the Si3010 chip as possible to
minimize lead lengths. The best practice is to use
surface mount components and very short PCB trace
lengths to minimize the inductive effects of component
leads and PCB traces thereby bypassing over the
widest possible frequency range and minimizing loop
areas that can radiate radio-frequency energy.
3.10. Ringer Network
R7 and R8 comprise the ringer network. These
components determine the modems on-hook
impedance at TIP and RING. These components are
selected to present a high impedance to the line, and
care must be taken to ensure the circuit board area
around these components is clean and free of
contaminants, such as solder flux and solder flakes.
Leakage on RNG1 (Si3010, pin 8) and RNG2 (Si3010,
pin 9) can impair modem performance.
AN94
8 Rev. 0.3
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AN94
Rev. 0.3 9
Figure 2. Si3010 Component Functions
3.11. DAA Operation
This section describes the detailed functionality of the integrated DAA included in the Si2401 chipset. This
functionality is generally transparent to the user when using the on-chip controller in the Si2401 modem. When
bypassing the on-chip controller, the low-level DAA functions of the Si3010 described in this section can be
controlled through S registers.
3.12. Emissions/Immunity
The Si2401 chipset and recommended DAA schematic is fully-compliant with and passes all international
electromagnetic emissions and conducted immunity tests (includes FCC part 15,68; EN50082-1). Careful attention
to the Si2401 "Bill of Materials: Si2401/3010 Chipset" on page 14, "Typical Application Schematic" on page 13, and
the layout guidelines included in "Appendix AISOmodem Layout Guidelines" on page 92 will ensure
compliance with these international standards.
3.13. DC Termination
The Si2401 has programmable settings for the dc impedance, current limiting, minimum operational loop current,
and TIP/RING voltage, which are selected with SF5, SF6, and SF8. The dc impedance of the Si2401 is normally
represented with a 50 O slope as shown in Figure 3 but can be changed to an 800 O slope by setting SF8[1]
(DCR). This higher dc termination presents a higher resistance to the line as loop current increases.
Figure 3. FCC Mode I/V Characteristics, DCV[1:0] = 11, MINI[1:0] = 00
12
11
10
9
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
FCC DCT Mode
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AN94
10 Rev. 0.3
legacy TBR-21 standard, SF5[3] (ILIM) may be set to
select this mode. In this mode, the dc I/V curve is
changed to a 2000 O slope above 40 mA, as shown in
Figure 4. This allows the Si2401 to operate with a 50 V,
230 O feed, which is the maximum linefeed specified in
the TBR-21 standard.
Figure 4. TBR-21 Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00
The SF6[7:6] (MINI[1:0]) selects the minimum
operational loop current for the Si2401, and SF6[5:4]
(DCV[1:0]) adjusts the DCT pin voltage, which affects
the TIP/RING voltage of the DAA. These bits allow
important trade-offs. Increasing TIP/RING voltage
increases signal headroom, whereas decreasing the
TIP/RING voltage allows compliance to PTT standards
in low-voltage countries, such as Japan. Increasing the
minimum operational loop current above 10 mA also
increases signal headroom and prevents degradation of
the signal level in low voltage countries.
3.14. AC Termination (Si3010)
The Si2401 has four ac termination impedances
selected with SF6[3:0] (ACT), which are listed in
Table 3. If an ACT setting other than the four listed in
Table 3 is selected, the ac termination is forced to 600 O
(ACT[3:0] = 0000).
The most widely-used ac terminations are available as
register options to satisfy various global PTT
requirements. The real 600 O impedance satisfies the
requirements of FCC Part 68, JATE, and other country
requirements. Setting ACT[3:0] = 0011 satisfies the
requirements of TBR-21, and most countries requiring a
complex impedance except New Zealand.
ACT[3:0] = 0100 is used for New Zealand.
ACT[3:0] = 1111, is designed to satisfy minimum return
loss requirements for every country that requires a
complex termination. Selecting this setting ensures
meeting minimum PTT requirements.
3.15. Ring Validation
Ring validation prevents false triggering of a ring
detection by validating the ring frequency. Invalid
signals, such as a loop current change when a parallel
handset goes off-hook, pulse dialing, or a high-voltage
line test, are ignored.
The ring validation circuit operates by calculating the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High- and low-frequency
tolerances are programmable in registers SED[5:0]
(RAS[5:0]) and SEE[3:0] (RMX[3:0]). Register SEC[3:1]
(RCC[2:0]) defines how long the ring signal must be
within tolerance.
Once the duration of the ring frequency is validated by
the RCC bits, the circuitry stops checking for frequency
tolerance and begins checking for the end of the ring
signal, which is defined by a lack of additional threshold
crossings for a period of time configured by register
SEE[7:4] (RTO[3:0]). When the ring frequency is first
validated, a timer defined by SEC[6:4] (RDLY[2:0]) is
started. If the RDLY[2:0] timer expires before the ring
timeout, the ring is validated, and a valid ring is
indicated. If the ring timeout expires before the
RDLY[2:0] timer, a valid ring is not indicated.
Ring validation requires the following five parameters:
Timeout parameter to place a lower limit on the
frequency of the ring signal (the RAS[5:0] bits. This
is measured by calculating the time between
crossings of positive and negative ring thresholds.
Minimum count to place an upper limit on the
frequency (the RMX[5:0] bits).
Time interval over which the ring signal must be the
correct frequency (the RCC[2:0] bits).
Timeout period that defines when the ring pulse has
ended based on the most recent ring threshold
crossing (the RTO[3:0] bits).
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
help accommodate distinctive rings (the RDLY[2:0]
bits).
45
40
35
30
25
20
15
10
5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
Loop Current (A)
CTR21 DCT Mode
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Table 3. AC Termination Settings
ACT[3:0] AC Termination
0000 600 O
0011 220 O + (820 O || 120 nF) and 220 O +
(820 O || 115 nF)
0100 370 O + (620 O || 310 nF)
1111 Global complex impedance
AN94
Rev. 0.3 11
There is also a ring validation enable bit, SEC[7]
(RNGVE), which enables or disables the ring validation
feature in both normal operating mode and low-power
sleep mode.
3.16. Ringer Impedance and Threshold
The ring detector in a typical DAA is ac-coupled to the
line with a large, 1 F, 250 V decoupling capacitor. The
ring detector on the Si3010 is resistively-coupled to the
line. Inherently, this network produces a very high ringer
impedance of approximately 20 MO to the line. This
value is acceptable for the majority of countries,
including FCC and TBR-21.
Several countries including Poland, South Africa, and
Slovenia, require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting SF5[2] (RZ) = 1. Certain countries also specify
ringer thresholds differently. SF5[1] (RT) selects
between two different ringer thresholds: 15 V 10% and
21 V 10%. This setting enables satisfaction of
worldwide ringer threshold requirements. Thresholds
are set so that a ring signal is guaranteed to not be
detected below the minimum, and a ring signal is
guaranteed to be detected above the maximum.
3.17. Pulse Dialing and Spark Quenching
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity, including make and
break times, make resistance, and rise and fall times. In
a traditional solid-state dc holding circuit, there are a
number of issues in meeting these requirements.
The Si2401 dc holding circuit has active control of the
on- and off-hook transients to maintain pulse dialing
fidelity.
Spark quenching requirements in countries, such as
Italy, the Netherlands, South Africa, and Australia, deal
with the on-hook transition during pulse dialing. These
tests provide an inductive dc feed resulting in a large
voltage spike. This spike is caused by the line
inductance and the sudden decrease in current through
the loop when going on-hook. The traditional way of
dealing with this problem is to put a parallel RC shunt
across the hookswitch relay. The capacitor is large
(~1 F, 250 V) and relatively expensive. By setting
SF5[5:4] (OHS[1:0]), the Si2401 loop current can be
controlled to achieve three distinct on-hook speeds to
pass spark quenching tests without additional BOM
components.
3.18. Billing Tone
Billing tones or metering pulses generated by the
central office can cause modem connection difficulties.
The billing tone is typically either a 12 or 16 kHz signal
and is sometimes used in Germany, Switzerland, and
South Africa. Depending on line conditions, the billing
tone may be large enough to cause major modem
errors.
Although the DAA remains off-hook during a billing tone
event, the received data from the line is corrupted (or a
modem disconnect or retrain may occur) in the presence
of large billing tones. If the user wishes to receive data
through a billing tone, an external LC filter must be
added. A modem manufacturer can provide this filter to
users in the form of a dongle that connects on the phone
line before the DAA. This keeps the manufacturer from
having to include a costly LC filter internal to the modem
when it may only be necessary for a few countries/
customers.
To operate without degradation during billing tones in
Germany, Switzerland, and South Africa, an external LC
notch filter is required. (The Si3010 can remain off-hook
during a billing tone event, but modem data will be lost
[or a modem disconnect or retrain may occur] in the
presence of large billing tone signals.) The notch filter
design requires two notches: One at 12 kHz and one at
16 kHz. Because these components are fairly
expensive and few countries supply billing tone support,
this filter is typically placed in an external dongle or
added as a population option for these countries.
Figure 5 shows an example billing tone filter. Figure 6
shows the billing tone filter and the ringer impedance
network for the Czech Republic. Both of these circuits
may be combined into a single external dongle.
L3 must carry the entire loop current. The series
resistance of the inductors is important to achieve a
narrow and deep notch. This design has more than
25 dB of attenuation at both 12 and 16 kHz.

Table 4. Component ValuesOptional Billing


Tone Filters
Symbol Value
C1,C2 0.027 F, 50 V, 10%
C3 0.01 F, 250 V, 10%
L3 3.3 mH, >120 mA, <10 O, 10%
L4 10 mH, >40 mA, <10 O, 10%
AN94
12 Rev. 0.3
Figure 5. Billing Tone Filter
Figure 6. Dongle Applications Circuit
The billing tone filter affects the ac termination and
return loss. The current complex ac termination passes
worldwide return loss specifications both with and
without the billing tone filter by at least 3 dB. The ac
termination is optimized for frequency response and
hybrid cancellation while having greater than 4 dB of
margin with or without the dongle for South Africa,
Australia, TBR-21, Germany, and Swiss country-
specific specifications.
L4
C3
RING
TIP
FROM
LINE
To
DAA
C1
C2
L3
TIP
RING
L3
3.3 mH, 120 mA
C1
0.027 F, 50 V
C2
0.027 F, 50 V
From
Line
To
Si3010
L4
3.3 mH, 40 mA
C3
0.01 F, 250 V
AN94
Rev. 0.3 13
3.19. Typical Application Schematic
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AN94
14 Rev. 0.3
3.20. Bill of Materials: Si2401/3010 Chipset
Component Value Supplier(s)
C1, C2 33 pF, Y2, X7R, 20% Panasonic, Murata, Vishay
C3 10 nF, 250 V, X7R, 20% Venkel, SMEC
C4 1.0 F, 50 V, X7R, 20% Venkel, SMEC
C5, C6, C50 0.1 F, 16 V, X7R, 20% Venkel, SMEC
C7 2.7 nF, 50 V, X7R, 20% Venkel, SMEC
C8, C9 680 pF, Y2, X7R, 10% Panasonic, Murata, Vishay
C10 0.01 F, 16 V, X7R, 20% Venkel, SMEC
C40, C41
1
33 pF, 16 V, NPO, 5% Venkel, SMEC
C51 0.22 F, 16 V, X7R, 20% Venkel, SMEC
D1, D2
2
Dual Diode, 225 mA, 300 V, CMPD2004S Central Semiconductor
FB1, FB2 Ferrite Bead, BLM21AG601SN1 Murata
Q1, Q3 NPN, 300 V, MMBTA42 OnSemi, Fairchild
Q2 PNP, 300 V, MMBTA92 OnSemi, Fairchild
Q4, Q5 NPN, 80 V, 330 mW, MMBTA06 OnSemi, Fairchild
RV1 Sidactor, 275 V, 100 A Teccor, Protek, ST Micro
R1 1.07 kO, 1/2 W, 1% Venkel, SMEC, Panasonic
R2 150 O, 1/16 W, 5% Venkel, SMEC, Panasonic
R3 3.65 kO, 1/2 W, 1% Venkel, SMEC, Panasonic
R4 2.49 kO, 1/2 W, 1% Venkel, SMEC, Panasonic
R5, R6 100 kO, 1/16 W, 5% Venkel, SMEC, Panasonic
R7, R8 20 MO, 1/16 W, 5% Venkel, SMEC, Panasonic
R9 1 MO, 1/16 W, 1% Venkel, SMEC, Panasonic
R10 536 O, 1/4 W, 1% Venkel, SMEC, Panasonic
R11 73.2 O, 1/2 W, 1% Venkel, SMEC, Panasonic
R12, R13 56 O, 1/16 W, 1% Venkel, SMEC, Panasonic
R15, R16
3
0 O, 1/16 W Venkel, SMEC, Panasonic
U1 Si2401 Silicon Labs
U2 Si3010 Silicon Labs
Y1
1,4
4.9152 MHz, 20 pF, 100 ppm, 150 O ESR ECS Inc., Siward
Z1 Zener Diode, 43 V, 1/2 W, BZT52C43 On Semi
Notes:
1. In STB applications, C40, C41, and Y1 can be removed when using the 27 MHz clock input feature.
2. Several diode bridge configurations are acceptable. For example, a single DF04S or four 1N4004 diodes may be
used.
3. Murata BLM21AG601SN1 may be substituted for R15R16 (0 O) to decrease emissions.
4. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial
accuracy, 5-year aging, 0 to 70 C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this
requirement.
AN94
Rev. 0.3 15
4. Software Design Reference
The Si2401 modem chipset is controller-based. No
modem drivers are required to run on the system
processor. This makes the Si2401 ideal for embedded
systems because a wide variety of processors and
operating systems can interface with the Si2401
through a simple UART (universal asynchronous
receiver transmitter) driver.
The Si2401 can be programmed to comply with FCC,
JATE, CTR-21, and other country-specific PTT
requirements. Fast connect and transparent HDLC
modes are also supported.
The Si2401 is highly integrated. The basic Si2401
functional blocks are shown in Figure 8. The Si2401
includes a controller, data pump (DSP), ROM, RAM, an
oscillator, phase-locked loop (PLL), timer, serial
interface, UART, and a DAA interface. The modem
software is permanently stored in the on-chip ROM.
Only modem setup information (other than defaults) and
other software updates must be stored on the host and
downloaded to the on-chip RAM during initialization.
There is no non-volatile on-chip memory other than
Program ROM. The default user interface for the Si2401
is the serial interface including the UART.
This section provides information about the architecture
of the modem, the functional blocks, registers, and their
interaction. The AT command set is presented and
options are explained. The accessible memory
locations (S-Registers) are described. Instructions for
writing to and reading from them are discussed along
with any limitations or special considerations. A large
number of configuration and programming examples
are offered as illustrations of actual testable
applications. These examples can be used alone or in
combination to create the desired modem operation.
This section is organized into seven major sections:
Serial Interface, Controller, AT Command S-Registers,
Fast Connect, DSP Control, and Programming
Examples. The Controller section contains information
about using controller functions and features, such as
the AT command set, result codes, escape methods,
power control, and system reset information. The DSP
section is brief because the programmer has little
control over the operation of the DSP. The use of
features that modify DSP behavior is described in other
sections. The Memory section describes the use of S-
Registers to control the operation, features, and
configuration of the modem.
Finally, the Programming Examples section illustrates
the implementation of modem functions and features
with the required AT commands and register values.
Configuration data is provided for most countries. These
examples can be used both to test modem operation
and as a programming aid.
Figure 8. Si2401 Functional Block Diagram
Serial
Interface/
UART
D
S
P
DAA
Interface
ROM
PLL
Clocking
XTI XTO
INT
RESET
C1
To Phone
Line
AOUT
Data Bus
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CTS
CD
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C2
Timer
AN94
16 Rev. 0.3
4.1. Serial Interface
The Si2401 has a universal asynchronous receiver/
transmitter (UART) serial interface compatible with
standard microcontroller serial interfaces. After powerup
or reset, the speed of the serial (Data Terminal
EquipmentDTE) interface is set by default to
2400 bps with the 8-bit, no parity, and one-stop bit (8N1)
format described below.
The serial interface DTE rate can be modified by writing
SE0[2:0] (SD) with the value corresponding to the
desired DTE rate. (See Table 5.) This is accomplished
with the command, ATSE0=xx, where xx is the
hexadecimal value of the SE0 register.
Immediately after the ATSE0=xx string is sent, the host
UART must be reprogrammed to the new DTE rate in
order to communicate with the Si2401.
The carriage return character following the ATSE0=xx
string must be sent at the new DTE rate to observe the
O response code. See Table 7 on page 18 for the
response code summary.
4.2. Configurations and Data Rates
The Si2401 can be configured to any of the Bell and
CCITT operation modes listed in Table 6. When
configured for V.22bis, the modem connects at
1200 bps if the far end modem is configured for V.22.
This device also supports SIA and other protocols for
the security industry. Table 1 on page 4 provides the
modulation method, carrier frequencies, data rate, baud
rate, and notes on standard compliance for each
modem configuration of the Si2401. Table 6 shows
example register settings (S07) for some of the modem
configurations.
As shown in Figure 9, 8-bit and 9-bit data modes refer to
the DTE format over the UART. Line data formats are
configured through registers S07 (MF1) and S15 (MLC).
If the number of bits specified by the format differs from
the number of bits specified by the DCE data
communications equipment or line (DTE) format, the
MSBs are either dropped or bit-stuffed, as appropriate.
For example, if the DTE format is 9 data bits (9N1), and
the line data format is 8 data bits (8N1), the MSB from
the DTE is dropped as the 9-bit word is passed from the
DTE side to the DCE (line) side. In this case, the
dropped ninth bit can then be used as an escape
mechanism. However, if the DTE format is 8N1, and the
line data format is 9N1, an MSB equal to 0 is added to
the 8-bit word as it is passed from the DTE side to the
DCE side.
The Si2401 UART does not continuously check for stop
bits on the incoming digital data. Therefore, if the TXD
pin is not high, the RXD pin may echo meaningless
characters to the host UART. This requires the host
UART to flush its receiver FIFO upon initialization.
Figure 9. Link and Line Data Formats
Table 5. DTE Rates
DTE Rate (bps) SE0[2:0] (SD)
300 000
1200 001
2400 010
9600 011
19200 100
38400 101
115200 110
307200 111
Table 6. Modem Configuration Examples
(S07[7] (HDEN) = 0, S07[6] (BD) = 0)
Modem Protocol Register S07 Values
V.22bis 0x06
V.22 0x02
V.21 0x03
Bell 212A 0x00
Bell 103 0x01
V.23 (1200 tx, 75 rx) 0x16
V.23 (75 tx, 1200 rx) 0x26
V.23 (600 tx, 75 rx) 0x10
V.23 (75 tx, 600 rx) 0x20
DTE Interface
Data Rate: SE0[2:0] (SD)
Data Format: SE0[3] (ND)
DCE (Line) Interface
Data Rate: S07 (MF1)
Data Format: S15 (MLC)
Si3010 Si2401
RJ11
TXD
RXD
AN94
Rev. 0.3 17
4.2.1. 8-Bit Data Mode (8N1)
The 8-bit data mode is the default mode after powerup
or reset and is set by SE0[3] (ND) = 0
b
. It is
asynchronous, full duplex, and uses a total of 10 bits
including a start bit (logic 0), eight data bits, and a stop
bit (logic 1). Data received from the remote modem is
transferred from the Si2401 to the host on the RXD pin.
Data transfer to the host begins when the Si2401
asserts a logic 0 start bit on RXD. Data is shifted out of
the Si2401 LSB first at the DTE rate determined by the
SE0[2:0] (SD) setting and terminates with a stop bit.
Data from the host for transmission to the remote
modem is shifted to the Si2401 on TXD beginning with a
start bit, LSB first at the DTE rate determined by the
SE0[2:0] setting and terminates with a stop bit. After the
middle of the stop bit time, the Si2401 begins looking for
a logic 1 to logic 0 transition signaling the start of the
next character on TXD to be sent to the line (remote
modem).
4.2.2. 9-Bit Data Mode (9N1)
The 9-bit data mode is set by SE0[3] (ND) = 1. It is
asynchronous, full duplex, and uses a total of 11 bits
including a start bit (logic 0), 9 data bits, and a stop bit
(logic 1). Data received from the line (remote modem) is
transferred from the Si2401 to the host on the RXD pin.
Data transfer to the host begins when the Si2401
asserts a logic 0 start bit on RXD. Data is shifted out of
the Si2401 LSB first at the DTE rate determined by the
SE0[2:0] (SD) setting and terminates with a stop bit.
Data from the host for transmission to the line (remote
modem) is shifted to the Si2401 on TXD beginning with
a start bit, LSB first at the DTE rate determined by the
S-Register SE0[2:0] (SD) setting, and terminates with a
stop bit. After the middle of the stop bit time, the Si2401
begins looking for a logic 1 to logic 0 transition signaling
the start of the next character on TXD to be sent to the
line (remote modem).
The ninth data bit may be used to indicate an escape by
setting S15[0] (NBE) = 1. In this mode, the ninth data bit
is normally set to 0 when the modem is online. When
the ninth data bit is set to 1, the modem goes offline into
command mode, and the next frame is interpreted as an
AT command. Data mode can be reentered using the
ATO command.
4.2.3. Flow Control
No flow control is needed if the DTE rate and DCE rate
are the same. If the serial link (DTE) data rate is set
higher than the line (DCE) rate of the modem, flow
control is required to prevent loss of data to the
transmitter.
To control data flow, the clear-to-send (CTS) pin is used.
When CTS is asserted, the Si2401 is ready to accept a
character. While CTS is negated, no data should be
sent to the Si2401 on TXD. To simplify flow control, the
Si2401 has an integrated ten character transmit FIFO
and allows for two different CTS reporting methods. By
default, the CTS pin is negated as soon as a start bit is
detected on the TXD pin and remains negated until the
modem is ready to accept another character (see
Figure 2 on page 9.) By setting SFC[7] = 1 (CTSM),
CTS is negated when the FIFO is 70% full and is
reasserted when the FIFO is 30% full.
4.3. Controller
The controller provides several vital functions including
AT command parsing, DAA control, connect sequence
control, DCE protocol control, intrusion detection,
parallel phone off-hook detection, escape control, caller
ID control, ring detect, DTMF control, call progress
monitoring, and HDLC framing. The controller also
writes to the control registers that configure the modem.
Virtually all interaction between the host and the modem
is done via the controller. The controller uses AT
(ATtention) commands and S-Registers to configure
and control the modem.
The modem has two modes of operation: command
mode and data mode. The Si2401 is asynchronous in
both command mode and data mode. The modem is in
command mode at powerup, after a reset, before a
connection is made, after a connection is dropped, and
during a connection after successfully Escaping from
the data mode back to the command mode using one of
the methods previously described. The following section
describes the AT command set available in command
mode.
Upon reset, the modem is in command mode and
accepts AT-style commands. An outgoing modem call
can be made using the ATDT# (tone dial) or ATDP#
(pulse dial) command after the device is configured. If
the handshake is successful, the modem responds with
the c, d, or v string and enter data mode. (The byte
following the c, d, or v is the first data byte.) At this
point, AT-style commands are not accepted. There are
three methods that may be used to return the Si2401 to
command mode:
Use the ESC pinTo program the GPIO3 pin to
function as an ESCAPE input, set GPIO3
SE2[5:4] = 11. In this setting, a positive edge
detected on this pin returns the modem to command
mode. The ATO string can be used to re-enter data
mode.
Use 9-bit data modeIf 9-bit data format with
escape is programmed, a 1 detected on bit 9 returns
the modem to command mode. (See Figure 2 on
page 9.) This is enabled by setting SE0[3] (ND) = 1
AN94
18 Rev. 0.3
and S15[0] (NBE) = 1. The ATO string can be used
to reenter data mode. Ninth bit escape does not
work in the security modes.
Use +++The escape sequence is a sequence of
three escape characters that are set in S-register
S0F (+ characters by default). If the ISOmodem


chipset detects the +++ sequence and detects no
activity on the UART before or after the +++
sequence for a time period set by S-register S10, it
returns to command mode. To disable this escape
sequence, set S-register S10=FF. To remove the
time-dependent behavior, set S-register S10=00.
Whether using an escape method or not, when the
carrier is lost, the modem automatically returns to
command mode and reports N.
4.4. AT Command Set
The Si2401 supports a subset of the typical modem AT
command set since it is intended for use with a
dedicated microcontroller instead of general terminal
applications. AT commands begin with the letters AT
and are followed directly (no space) by the command.
All AT commands must be entered in upper case or
lower case (not mixed) except w##, r#, m#, q#, and z
(wakeup-on-ring).
AT commands can be divided into two groups: control
commands and configuration commands. Control
commands, such as ATD, cause the modem to perform
an action (going off-hook and dialing). The value of this
type of command is changed at a particular time to
perform a particular action. For example, the
ATDT1234<CR> command causes the modem to go
off-hook and dial the number, 1234, via DTMF. This
action exists only during a connection attempt. No
enduring change in the modem configuration exists
after the connection or connection attempt has ended.
Configuration commands change modem
characteristics until they are modified or reversed by a
subsequent configuration command or the modem is
reset. Modem configuration status can be determined
with the use of ATSR?<CR> Where R is the two
character hexadecimal address of an S-register.
A command line is defined as a string of characters
starting with AT and ending with an end-of-line
character, <CR> (13 decimal). Command lines may
contain several commands one after the other. If there
are no characters between AT and <CR>, the modem
responds with O after the carriage return.
4.4.1. Command Line Execution
The characters in a command line are executed one at
a time. Unexpected command characters are ignored,
but unexpected data characters may be interpreted
incorrectly.
After the modem has executed a command line, the
result code corresponding to the last command
executed is returned to the terminal or host. In addition
to the ATH and ATZ commands, the commands that
warrant a response (e.g., ATSR? or ATI) must be the
last in the string and followed by a <CR>. All other
commands may be concatenated on a single line. To
echo command line characters, set the Si2401 to echo
mode using the E1 command.
All numeric arguments, including the address and value
of an S-register, are in hexidecimal format, and two
digits must always be entered.
4.4.2. <CR> End-Of-Line Character
This character is typed to end a command line. The
value of the <CR> character is 13 in decimal, the ASCII
carriage return character. When the <CR> character is
entered, the modem executes the commands in the
command line.
Note: Commands that do not require a response are exe-
cuted immediately and do not need a <CR>.
4.4.3. AT Command Set Description
A Answer
The A command makes the modem go off-hook and
respond to an incoming call. This command is to be
executed after the Si2401 has indicated a ring has
occurred. (The Si2401 indicates an incoming ring by
echoing an R.)
Table 7. AT Command Set Summary
Command Function
A Answer line immediately with modem
DT# Tone dial number
DP# Pulse dial number
E Local echo on/off
H0 Go on-hook (hang up modem)
H1 Go off-hook
I Chip revision
:I Interrupt read and clear
M Speaker control options
O Return online
RO V.23 reverse
S Read/write S-Registers
w## Write S-Register in binary
r# Read S-Register in binary
m# Monitor S-Register in binary
q# Read S-Register in binary
V0 Result code with no carriage return
V1 Result code with added carriage returns
Z Software reset
z Wakeup on ring
AN94
Rev. 0.3 19
This command is aborted if any other character is
transmitted to the Si2401 before the answer process is
completed.
Auto answer mode is entered by setting S00 (NR) to a
non-zero value. NR indicates the number of rings before
answering the line.
Upon answering, the modem communicates by
whatever protocol has been determined via the modem
control registers in S07 (MF1).
If no transmit carrier signal is received from the calling
modem within the time specified in S39 (CDT), the
modem hangs up and enters the idle state.
D Dial
DT# Tone Dial Number.
DP# Pulse Dial Number.
The D commands make the modem dial a telephone
call according to the digits and dial modifiers in the dial
string following the command. A maximum of 64 digits is
allowed. A DT command performs tone dialing, and a
DP command performs pulse dialing.
The ATH1 command can be used to go off-hook without
detecting a dial tone or dialing.
The dial string must contain only the digits 09, *, #,
A, B, C, D, or the modifiers ;, /, or ,. Other
characters are interpreted incorrectly. The modifier ,
causes a two second delay (added to the spacing value
in S04) in dialing. The modifier / causes a 125 ms
delay (added to the spacing value in S04) in dialing. The
modifier ; returns the device to command mode after
dialing and must be the last character.
If any character is received by the Si2401 between the
ATDT#<CR> (or ATDP#<CR>) command and when the
connection is made (c or d is echoed), the extra
character is interpreted as an abort, and the Si2401
returns to command mode ready to accept AT
commands. A line feed character immediately following
the <CR> is treated as an extra character and aborts
the call.
If the modem does not have to dial (i.e., ATDT<CR> or
ATDP<CR> with no dial string), the Si2401 assumes
the call was manually established and attempts to make
a connection.
Automatic Tone/Pulse Dialing
The Si2401 can be configured to attempt DTMF dialing
and automatically revert to pulse dialing if it determines
that the line is not DTMF-capable. This feature is best
explained by the following example:
If it is desired that the telephone number, 12345, be
dialed, it is normally accomplished through either the
ATDT12345 or the ATDP12345 command. In the force
pulse dialing mode of operation, the following string
should be issued instead:
ATDT1,p12345
If the result code returned is t, this indicates that the
dialing was accomplished using DTMF dialing. If the
result code returned is tt,, it indicates that the dialing
was accomplished using pulse dialing.
In the above example, the Si2401 dials the first digit 1
using DTMF dialing. The , is used to pause in order to
ensure that the central office has had time to accept the
DTMF digit 1. When the Si2401 processes the p
command, it attempts to detect a dial tone. If a dial tone
is detected, the DTMF digit 1 was not effective, hence,
the line does not support DTMF dialing. Conversely, if
the dial tone is not detected, the DTMF digit 1 was
effective, and the line supports DTMF dialing. The
character after the p may or may not be dialed
depending on whether the DTMF digit 1 was effective
or not. If the 1 was effective (DTMF mode), the
character after the p is skipped. The next DTMF digit
to be dialed is 2. Subsequent digits are all DTMF. If the
1 was not effective, the first character after the p (the
1) is pulse dialed, and subsequent digits are all pulse
dialed. When using the character p, there need to be
at least two digits following it for proper operation.
E Command Mode Echo
Tells the Si2401 whether or not to echo characters sent
from the terminal.
EO
Does not echo characters sent from the terminal.
E1
Echoes characters sent from the terminal.
H0 Hangup
Hang up and go into command mode (go offline).
H1 Off-hook
Go off-hook and remain in command mode. (Before
ATH1, set register SAA = 00 for proper operation.)
I Chip Identification
This command causes the modem to echo the chip
revision for the Si2401 device.
A = Revision A
B = Revision B
C = Revision C, etc.
I6
Display the ISOmodem model number.
2401 = Si2401.
AN94
20 Rev. 0.3
:I Interrupt Read
This command causes the ISOmodem chipset to report
the contents of the interrupt status register (S09). The
WOR, PPD, NLD, RI, OCD, and REV bits are also
cleared, and the INT is deactivated on this read.
M Speaker On/Off Options
These options are used to control AOUT for use with a
call progress monitor speaker. Register SF4[3:0] and
SE4 and SE2 need to be programmed properly prior to
the ATMx command.
M0
Speaker always off.
M1
Speaker on until carrier established. The modem sets
SF4[3:2] (ARL) = 11
b
and SF4[1:0] (ATL) = 11
b
after a
connection is established.
M2
Speaker always on.
M3
Speaker on after last digit dialed, off at carrier detect.
O Return to Online Mode
This command returns the modem to the online mode. It
is frequently used after an escape sequence to resume
communication with the remote modem.
RO Turn-Around
This command initiates a V.23 direct turnaround
sequence and returns online.
S S Register Control
SR=N
Write an S register. This command writes the value N
to the S-register specified by R. R is a hexidecimal
number, and N must also be a hexadecimal number
from 00FF. This command does not wait for a carriage
return <CR> before taking effect.
Note: Two digits must always be entered for both R and N.
SR?
Read an S register. This command causes the Si2401
to echo the value of the S-register specified by R in hex
format. R must be a hexidecimal number.
Note: Two digits must always be entered for R.
w## Write S Register in Binary
This command writes a register in binary format. The
first byte following the w is the address in binary
format and the second byte is the data in binary format.
This is a more rapid method to write registers than the
SR=N command and is recommended for use by a
host microcontroller.
r# Read S Register in Binary
This command reads a register in binary format. The
byte following the r is the address in binary format.
The modem echoes the contents of this register in
binary format. This is a more rapid method to read
registers than the SR? command and is
recommended for use by a host microcontroller.
Notes:
1. w## and r# are not required to be on separate lines (i.e.,
no <CR> between them). Also, the result of an r# is
returned immediately without waiting for a <CR> at the end
of the AT command line.
2. Once a <CR> is encountered, AT is again required to
begin the next AT command.
3. Modem result codes should be disabled to avoid confusion
with data being read. This can be done by setting
S62 = 40.
m# Monitor S Register in Binary
This command monitors a register in binary format. The
byte following the m is the address in binary format.
The Si2401 constantly transmits the contents of the
register at the set baud rate until a new byte is
transmitted to the device. The new byte is ignored and
viewed as a stop command. The modem result codes
should be disabled (as described above in r#) before
using this command.
q# Read S Register in Binary
This command is exactly the same as the r# command;
however, the response from the Si2401 is formatted as
0x55 followed by the contents of the register in binary.
This guarantees that the register contents are always
preceded by 0x55 and allows the result codes to remain
enabled.
V Result Code Options
V0
Result codes reported according to Table 9.
V1
Result codes reported with an additional carriage return
and line feed (default).
Z Software Reset
The Z command initiates a software reset causing all
registers, with the exception of E0, which controls the
DTE settings, to default to their powerup value.
The hardware reset pin, RESET (Si2401, pin 8), is used
to reset the Si2401 to factory default settings.
z Wakeup on Ring (lower-case z)
The Si2401 enters a low-power mode in which the DSP
and microcontroller are powered down. In this mode,
only the line-side device (Si3010) and the C1/C2
communication link are functional. An incoming ring
signal or line transient causes the Si2401 to power up
and echo an R. Any character received on the RXD
AN94
Rev. 0.3 21
pin also causes the Si2401 to exit the wakeup-on-ring
state. Return from wake-on-ring can also be set to
trigger the INT pin by setting S08[6] (WORM) = 1
b
.
4.4.4. Alarm Industry AT Commands
The Si2401 supports a complete set of commands
necessary for making connections in security industry
systems. The Si2401 is configurable in two modes for
these applications. The first mode uses DTMF
messaging and is selected with the !1 command. The
second mode uses FSK transmit with a tone
acknowledgement and is selected with !2.
The following are a few general comments about the
use of ! commands. Specific details for each command
are given below. The first instance of the ! must be on
the same line as the ATDT or ATDP command. DRT
must be set to data mode (SE4[5:4] (DRT) = 0
b
) before
attempting to send tones after a ! command. The three
data-mode escape sequences (+++, escape pin and
ninth-bit) function in !2 mode. However, using the
+++ or ninth-bit is not recommended because
characters could be sent to and misinterpreted by the
remote modem. Only the escape pin (Si2401, pin 14)
is recommended for use in the !2 mode. The !1 mode
has a special escape provision described below. The AT
commands for Alarm Industry applications are
described in Table 8.
4.4.4.1. !1
Dial number and follow the DTMF security protocol.
The format for this command is as follows:
ATDT<phone number>!1<message 1><CR>
K
!<message 2><CR>
K
!<message 3><CR>
K
K
!<message n><CR>
The modem dials the phone number and echoes r
(ring), b (busy), and c (connect) as appropriate. c
echoes only after the Si2401 detects the Handshake
Tone. After a 250 ms delay, the modem sends the
DTMF tones containing the first message (message
must contain digits 09, BF only as shown in column 3
of Table 11), then listens for a Kissoff Tone. If a Kissoff
Tone shorter than or equal to the value stored in
S36(KTL) (default = 480 ms) is detected, the Si2401
echoes a K. A k is echoed if the length of the Kissoff
Tone is longer than the S36(KTL) value. The controller
can then send the next message. All messages must be
preceded by a ! and followed by a <CR> and received
by the Si2401 within 250 ms after the K is echoed.
Setting S0C[0] (MCH) = 1
b
causes a . to be echoed
when the DTMF tone is turned on and a / character to
be echoed when the DTMF tone is turned off. This helps
the host monitor the status of the message being sent.
The previous message can be resent if the host
responds with a ~ after the Si2401 echoes a K. Any
character other than a ! or a ~ sent to the modem
immediately after the K causes the modem to escape
to the command mode and remain off-hook. Any
character except ! and ~ sent during the transmission
of a message causes the message to be aborted and
the modem to return to the command mode.
If the Kissoff Tone is not received within 1.25 seconds,
the modem echoes a ^. A ~ from the host causes the
last message to be resent. Any character other than a
! or a ~ sent to the modem immediately after the ^
causes the modem to escape to the command mode
and remain off-hook.
4.4.4.2. !2
Dial the number and follow the SIA Format protocol for
Alarm System Communications.
The modem dials the phone number and echoes r
(ring), b (busy), and c (connect) as appropriate. c
echoes only after the Si2401 detects the Handshake
Tone and the speed synchronization signal is sent. The
signaling is at 300 bps, half-duplex FSK. The host can
send the first SIA block after the c is received. Once
the block is transmitted, the modem can monitor for the
acknowledge tone by completing the following
sequence:
1. Place the Si2401 in the command mode by pulsing
the ESCAPE pin (Si2401 pin 14). The +++ and
ninth-bit escape modes operate in the !2 mode
but are not recommended because they can send
unwanted characters to the remote modem.
2. Issue the ATX1 command to turn the modem
transmitter off and begin monitoring for the
acknowledgment tones.
Table 8. AT Command Set Extensions
for the Alarm Industry
Command Function
!1 Dial and switch to DTMF security
mode
!2 Dial and switch to SIA Format
X1 SIA half-duplex mode search
X2 SIA half-duplex return online as
transmitter
X3 SIA half-duplex return online as
receiver
AN94
22 Rev. 0.3
3. Monitor for a positive (negative) acknowledgment P
(N) after the tone has been detected for at least
400 ms.
4. The modem, still in command mode, can be placed
online as a transmitter by issuing the ATX2
command or a receiver by issuing the ATX3
command. If tonal acknowledgement is not used, the
host can toggle the ESCAPE pin to place the Si2401
in the command mode and issue an ATX2 or an
ATX3 command to reverse data direction.
This sequence can be repeated for long messages.
4.4.5. Modem Result Codes and Call Progress
Table 9 shows the modem result codes that can be
used in call progress monitoring. All result codes are a
single character to speed up communication and ease
host processing.
4.4.5.1. Automatic Call Progress Detection
The Si2401 has the ability to detect dial, busy, and
ringback tones automatically. The following is a
description of the algorithms that have been
implemented for these three tones.
Dial Tone. The dial tone detector looks for a dial
tone after going off-hook and before dialing is
initiated. This can be bypassed by enabling blind
dialing (set S07[6] (BD) = 1
b
). After going off-hook,
the Si2401 waits the number of seconds in S01
(DW) before searching for the dial tone.
In order for a dial tone to be detected, it must be
present for the length of time programmed in S1C
(DTT). Once the dial tone is detected, dialing
commences. If a dial tone is not detected within the
time programmed in S02 (CW), the Si2401 hangs up
and echoes an n to the user.
Busy/Ringback Tone. After dialing has completed,
the Si2401 monitors for Busy/Ringback and modem
answer tones. The busy and ringback tone detectors
both use the call progress energy detector. The
registers that set the cadence for busy and ringback
are listed in Table 10.
Si2401 register settings for global cadences for busy and
ringback tones are listed in Table 22 on page 86.
Table 9. Modem Result Codes
Command Function
a British Telecom Caller ID Idle Tone
Alert Detected
b Busy Tone Detected
c Connect
d Connect 1200 bps (when pro-
grammed as V.22bis modem)
f Hookswitch Flash or Battery Reversal
Detected
H Modem Automatically Hanging Up in
!2, !1
I Intrusion Completed (parallel phone
back on-hook)
i Intrusion Detected (parallel phone off-
hook on the line)
K Kissoff Tone Detected
k Contact ID Kissoff Tone too long (!1)
L Phone Line Detected
l No Phone Line Detected
m Caller ID Mark Signal Detected
N No Carrier Detected
n No Dial tone (time-out set by CW
[S02])
O Modem OK Response
R Incoming Ring Signal Detected
r Ringback Tone Detected
t Dial Tone
v Connect 75 bps TX (V.23 originate
only)
x Overcurrent State Detected After an
Off-Hook Event
^ Kissoff tone detection required
, Dialing Complete
Table 10. Busy and Ringback Cadence
Registers
Register Name Function Units
S16 BTON Busy tone on time 10 ms
S17 BTOF Busy tone off time 10 ms
S18 BTOD Busy tone delta time 10 ms
S19 RTON Ringback tone on time 53.333
ms
S1A RTOF Ringback tone off time 53.333
ms
S1B RTOD Ringback tone delta time 53.333
ms
Table 9. Modem Result Codes (Continued)
AN94
Rev. 0.3 23
4.4.5.2. Manual Call Progress Detection
Because other call progress tones beyond those
described above may exist, the Si2401 supports manual
call progress. This requires the host to read and write
the low-level DSP registers and may require realtime
control by the host. Manual call progress may be
required for detection of application-specific ringback,
dial tone, and busy signals. The section on DSP low-
level control should be read before attempting manual
call progress detection.
The call progress biquad filters can be programmed to
have a custom frequency response and detection level
(as described in "S-Registers" on page 25).
Four dedicated user-defined frequency detectors can
be programmed to search for individual tones. The four
detectors have center frequencies that can be set by
registers UDFD14 (see Table 15 on page 66).
SE5[6] [TDET] [SE8 = 0x02] Read Only Definition can
be monitored, along with TONE, to detect energy at
these user-defined frequencies. The default trip-
threshold for UDFD14 is 43 dBm but can be modified
with the DSP register, UDFSL.
By issuing the ATDT; command, the modem goes off-
hook, checks for dial tone, and if it exists, returns to
command mode. The blind dialing bit S07[6] can be set
to suppress dial tone detection. The user can then put
the DSP into call progress monitoring by first setting
SE8 = 0x02. Next, set SE5 (DSP2) = 0x00 so no tones
are transmitted, and set SE6 (DSP3) to the appropriate
code, depending on which types of tones are to be
detected.
The tone is detected while present. Use ATmE5 to
create a stream of data to parse for the tone
information.
At this point, users may program their own algorithm to
monitor the detected tones. If the host wishes to dial, it
should do so by blind dialing, setting the dial timeout
S01 (DW) to 0 seconds and issuing an
ATDT<Phone Number>;<CR> command. This
immediately causes the ISOmodem chipset to dial and
return to command mode.
Once the host has detected an answer tone using
manual call progress, the host should immediately
execute the ATDT command in order to make a
connection. This causes the Si2401 to search for the
modem answer tone and begin the correct connect
sequence.
In manual call progress, the DSP can be programmed
to detect specific tones. The result of the detection is
reported in SE5 (SE8 = 0x2) as explained above. The
output is priority-encoded such that if multiple tones are
detected, the one with the highest priority whose
detection is also enabled is reported (see SE5 [SE8=02]
Read Only.)
In manual call progress, the DSP can be programmed
to generate specific tones (see SE5[2:0] (TONC)
(SE8 = 02) Write Only). For example, setting
SE5[2:0] (TONC) = 110
b
generates the user-defined
tone (as indicated by UFRQ in Table 15 on page 66)
with an amplitude of TGNL.
Table 11 shows the mappings of Si2401 DTMF values,
keyboard equivalents, and the related dual tones.
AN94
24 Rev. 0.3
Table 11. DTMF Values
DTMF
Code
Keyboard
Equivalent
Contact ID
Digit
Tones
Low High
0 0 0 941 1336
1 1 1 697 1209
2 2 2 697 1336
3 3 3 697 1477
4 4 4 770 1209
5 5 5 770 1336
6 6 6 770 1477
7 7 7 852 1209
8 8 8 852 1336
9 9 9 852 1477
10 D 941 1633
11 * B 941 1209
12 # C 941 1477
13 A D 697 1633
14 B E 770 1633
15 C F 852 1633
AN94
Rev. 0.3 25
4.5. S-Registers
Any register not documented here is reserved and should not be written. Bold selection in bit-mapped registers
indicates default values.
Table 12. S-Register Summary
S
Register
Register
Address
(hex)
Name Function Reset
S00 0x00 NR Number of rings before answer; 0 suppresses auto answer.
0x00
S01 0x01 DW Number of seconds modem waits before dialing after going
off-hook (maximum of 109 seconds).
0x02
S02 0x02 CW Number of seconds modem waits for a dial tone before hang-up
added to time specified by DW (maximum of 109 seconds).
0x03
S03 0x03 CLW Duration that the modem waits (53.33 ms units) after loss of
carrier before hanging up.
0x0E
S04 0x04 TD Both duration and spacing (5/3 ms units) of DTMF dialed tones.
0x30
S05 0x05 OFFPD Duration of off-hook time (5/3 ms units) for pulse dialing.
0x18
S06 0x06 ONPD Duration of on-hook time (5/3 ms units) for pulse dialing.
0x24
S07 0x07 MF1 This is a bit-mapped register.
*
0x06
S08 0x08 INTM This is a bit-mapped register.
*
0x00
S09 0x09 INTS This is a bit-mapped register.
*
0x00
S0C 0x0C MF2 This is a bit-mapped register.
*
0x00
S0D 0x0D MF3 This is a bit-mapped register.
*
0x00
S0E 0x0E DIT Pulse dialing Interdigit time (10 ms units added to a minimum
time of 64 ms).
0x46
S0F 0x0F TEC TIES escape character. Default = +.
0x2B
S10 0x10 TDT TIES delay time (53.33 ms units).
0x13
S11 0x11 OFHI This is a bit-mapped register.
*
0x04
S12 0x12 ACL
Absolute Current Level. When S13[4] (OFHD) = 0
b
, ACL
represents the absolute current threshold used by the off-hook
intrusion algorithm (1.1 mA units).
0x00
S13 0x13 MF4 This is a bit-mapped register.
*
0x10
S15 0x15 MLC This is a bit-mapped register.
*
0x04
S16 0x16 BTON Busy tone on. Time that the busy tone must be on (10 ms units)
for busy tone detector.
0x32
S17 0x17 BTOF Busy tone off. Time that the busy tone must be off (10 ms units)
for busy tone detector.
0x32
S18 0x18 BTOD Busy tone delta time (10 ms units). A busy tone is detected to be
valid if (BTON BTOD < on time < BTON + BTOD) and (BTOF
BTOD < off time < BTOF + BTOD).
0x0F
*Note: These registers are explained in detail in the following section.
AN94
26 Rev. 0.3
S19 0x19 RTON Ringback tone on. Time that the ringback tone must be on
(53.333 ms units) for ringback tone detector.
0x26
S1A 0x1A RTOF Ringback tone off. Time that the ringback tone must be off
(53.333 ms units) for ringback tone detector.
0x4B
S1B 0x1B RTOD Detector time delta (53.333 ms units). A ringback tone is deter-
mined to be valid if (RTON RTOD < on time < RTON + RTOD)
and (RTOF RTOD < off time < RTOF + RTOD).
0x07
S1C 0x1C DTT Dial tone detect time. The time that the dial tone must be valid
before being detected
(10 ms units).
0x0A
S1E 0x1E TATL Transmit answer tone length. Answer tone length in seconds
when answering a call (1 s units).
0x03
S1F 0x1F ARM3 Answer tone to transmit delay. Delay between answer tone end
and transmit data start (5/3 ms units).
0x2D
S20 0x20 UNL Unscrambled ones length. Minimum length of time required for
detection of unscrambled binary ones during V.22 handshaking
by a calling modem (5/3 ms units).
0x5D
S21 0x21 TSOD Transmit scrambled ones delay. Time between unscrambled
binary one detection and scrambled binary one transmission by
a call mode V.22 modem (53.3 ms units).
0x09
S22 0x22 TSOL Transmit scrambled ones length. Length of time scrambled ones
are sent by a call mode V.22 modem (5/3 ms units).
0xA2
S23 0x23 VDDL V.22X data delay low. Delay between handshake complete and
data connection for a V.22X call mode modem (5/3 ms units
added to the time specified by VDDH).
0xCB
S24 0x24 VDDH V.22X data delay high. Delay between handshake complete and
data connection for a V.22X call mode modem (256 x 5/3 ms
units added to the time specified by VDDL).
0x08
S25 0x25 SPTL S1 pattern time length. Amount of time the unscrambled S1 pat-
tern is sent by a call mode V.22bis modem (5/3 ms units).
0x3C
S26 0x26 VTSO V.22bis 1200 bps scrambled ones length. Minimum length of
time for transmission of 1200 bps scrambled binary ones by a
call mode V.22bis modem after the end of pattern S1 detection
(53.3 ms).
0x0C
S27 0x27 VTSOL V.22bis 2400 bps scrambled ones length low. Minimum length of
time for transmission of 2400 bps scrambled binary ones by a
call mode V.22bis modem (5/3 ms units).
0x78
S28 0x28 VTSOH V.22bis 2400 bps scrambled ones length high. Minimum length
of time for transmission of 2400 bps scrambled binary ones by a
call mode V.22bis modem (256 x 5/3 ms units added to the time
specified by VTSOL).
0x08
Table 12. S-Register Summary (Continued)
S
Register
Register
Address
(hex)
Name Function Reset
*Note: These registers are explained in detail in the following section.
AN94
Rev. 0.3 27
S29 0x29 IS Intrusion suspend. When S82[2:1] (IB) = 10
b
, this register sets
the length of time from when dialing begins that the off-hook
intrusion algorithm is blocked (suspended) (500 ms units).
0x00
S2A 0x2A RSO Receive scrambled ones V.22bis (2400 bps) length.
Minimum length of time required for detection of scrambled
binary ones during V.22bis handshaking by the answering
modem after S1 pattern conclusion (5/3 ms units).
0xD2
S2B 0x2B DTL V.23 direct turnaround carrier length. Minimum length of time that
a master mode V.23 modem must detect carrier when searching
for a direct turnaround sequence (5/3 ms units).
0x18
S2C 0x2C DTTO V.23 direct turnaround timeout. Length of time that the modem
searches for a direct turnaround carrier (5/3 ms units added to a
minimum time of 426.66 ms).
0x08
S2D 0x2D SDL V.23 slave carrier detect loss. Minimum length of time that a
slave mode V.23 modem must lose carrier before searching
for a reverse turnaround sequence (5/3 ms units).
0x0C
S2E 0x2E RTCT V.23 reverse turnaround carrier timeout. Amount of time a slave
mode V.23 modem searches for carriers during potential reverse
turnaround sequences (5/3 ms units).
0xF0
S2F 0x2F FCD FSK connection delay low. Amount of time delay added
between end of answer tone handshake and actual modem
connection for FSK modem connections (5/3 ms units).
0x3C
S30 0x30 FCDH FSK connection delay high. Amount of time delay added
between end of answer tone handshake and actual modem con-
nection for FSK modem connections (256 x 5/3 ms units).
0x00
S31 0x31 RATL Receive answer tone length. Minimum length of time required
for detection of a CCITT answer tone (5/3 ms units).
0x3C
S32 0x32 OCDT The time after going off-hook when the loop current sense bits
are checked for overcurrent status (5/3 ms units).
0x0C
S34 0x34 TASL Answer tone length when answering a call (5/3 ms units). This
register is only used if TATL (1E) has a value of zero.
0x5A
S35 0x35 RSOL Receive scrambled ones V.22 length (5/3 ms units). Minimum
length of time that an originating V.22 (1200 bps) modem must
detect 1200 bps scrambled ones during a V.22 handshake.
0xA2
S36 0x36 ARM1 Second kissoff tone detector length. The security modes, A1 and
!1, echo a k if a kissoff tone longer than the value stored in
SKDTL is detected (10 ms units).
0x30
S37 0x37 CDR Carrier detect return. Minimum length of time that a carrier must
return and be detected in order to be recognized after a carrier
loss is detected
(5/3 ms units).
0x20
Table 12. S-Register Summary (Continued)
S
Register
Register
Address
(hex)
Name Function Reset
*Note: These registers are explained in detail in the following section.
AN94
28 Rev. 0.3
S39 0x39 CDT Carrier detect timeout. Amount of time modem waits for carrier
detect before aborting call (1 second units).
0x3C
S3A 0x3A ATD Delay between going off-hook and answer tone generation when
in answer mode (53.33 ms units).
0x29
S3C 0x3C CIDG This is a bit mapped register.
*
0x01
S62 0x62 RC This is a bit mapped register.
*
0x41
S82 0x82 IST This is a bit mapped register.
*
0x08
SAA 0xAA OPC Overload protect counter. Set SAA = 00 when used with ATH1.
0x04
SC0 0xC0 V80C This is a bit mapped register.
*
0x00
SC1 0xC1 ITF1 Transmit flow control off threshold. Threshold, in bytes, above
which the modem will generate a flow off signal (maximum
threshold value of 20).
0x14
SC2 0xC2 ITF2 Transmit flow control on threshold. Threshold, in bytes, below
which the modem will generate a flow on signal. This value must
be less than ITF1.
0x04
SC3 0xC3 V80M This is a bit mapped register.
*
0x00
SDB 0xDB LVS Line Voltage Status. Eight bit signed, 2s complement number
representing the tip-ring voltage. Each bit represents 1 volt.
Polarity of the voltage is represented by the MSB (sign bit).
0000_0000 = Measured voltage is < 3 V.
SDF 0xDF DGSR This is a bit mapped register.
*
0x0C
SE0 0xE0 CF1 This is a bit mapped register.
*
0x22
SE1 0xE1 GPIO1 This is a bit mapped register.
*
0x0E
SE2 0xE2 GPIO2 This is a bit mapped register.
*
0x00
SE3 0xE3 GPD This is a bit mapped register.
*
SE4 0xE4 CF5 This is a bit mapped register.
*
0x00
SE5 0xE5 DADL (SE8 = 0x00) Write only definition. DSP register address lower
bits [7:0].
*
SE5 0xE5 DDL (SE8 = 0x01) Write only definition. DSP data word lower bits
[7:0].
*
SE5 0xE5 DSP1 (SE8 = 0x02) Read only definition. This is a bit mapped register.
1
SE5 0xE5 DSP2 (SE8 = 0x02) Write only definition. This is a bit mapped register.
1
SE6 0xE6 DADH (SE8 = 0x00) Write only definition. DSP register address upper
bits [15:8].
SE6 0xE6 DDH (SE8 = 0x01) Write only definition. DSP data word upper bits
[13:8]
Table 12. S-Register Summary (Continued)
S
Register
Register
Address
(hex)
Name Function Reset
*Note: These registers are explained in detail in the following section.
AN94
Rev. 0.3 29
SE6 0xE6 DSP3 (SE8 = 0x02) Write only definition. This is a bit mapped register.
1
SE8 0xE8 DSPR4 Set the mode to define E5 and E6 for low level DSP control.
SEB 0xEB TPD This is a bit mapped register.
*
0x00
SEC 0xEC RV1 This is a bit mapped register.
*
0x88
SED 0xED RV2 This is a bit mapped register.
*
0x19
SEE 0xEE RV3 This is a bit mapped register.
*
0x16
SF0 0xF0 DAA0 This is a bit mapped register.
*
0x40
SF1 0xF1 DAA1 This is a bit mapped register.
*
0x0C
SF2 0xF2 DAA2 This is a bit mapped register.
*
SF3 0xF3 DAA3
Line Current Status. Eight-bit value returning the loop current.
Each bit represents 1.1 mA of loop current.
0000_0000 = Loop current is less than required for normal oper-
ation.
0x00
SF4 0xF4 DAA4 This is a bit mapped register.
*
0x0F
SF5 0xF5 DAA5 This is a bit mapped register.
*
0x00
SF6 0xF6 DAA6 This is a bit mapped register.
*
0xF0
SF7 0xF7 DAA7 This is a bit mapped register.
*
0x00
SF8 0xF8 DAA8 This is a bit mapped register.
*

SF9 0xF9 DAA9 This is a bit mapped register.


*
0x20
Table 12. S-Register Summary (Continued)
S
Register
Register
Address
(hex)
Name Function Reset
*Note: These registers are explained in detail in the following section.
AN94
30 Rev. 0.3
Table 13. Bit-Mapped Register Summary
S
Register
Register
Address
(hex)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
Binary
S07 0x07 MF1 BD V23R V23T BAUD CCITT FSK 0000_0110
S08 0x08 INTM CDM WORM PPDM NVDM RIM CIDM OCDM REVM 0000_0000
S09 0x09 INTS CD WOR PPD NVD RI CID OCD REV 0000_0000
S0C 0x0C MF2 CDE CIDM[1:0] 9BF BDL MLB 0000_0000
S0D 0x0D MF3 RI INTP RBTS EHR EHB EHI EHE 0000_0000
S11 0x11 OFHI DCL[3:0] 0000_0100
S13 0x13 MF3 BTID OFHD CIDB HDEN 0001_0000
S15 0x15 MLC ATPRE VCTE FHGE EHGE STB BDA[1:0] NBE 0000_0100
S3C 0x3C CIDG CIDG[2:0] 0000_0001
S62 0x62 RC OCR IR NLR RR 0100_0001
S82 0x82 IST IST[3:0] LCLD IB[1:0] 0000_1000
SC0 0xC0 V80C ITC[1:0] ESA1 ESA2 ESOM[1:0] ESAM[1:0] 0000_0000
SC3 0xC3 V80M TRANSP[1:0] 0000_0000
SDF 0xDF DGSR DGSR[6:0] 0000_1100
SE0 0xE0 CF1 ICTS ND SD[2:0] 0010_0010
SE1 0xE1 GPIO1 GPD5 GPIO5 0000_1110
SE2 0xE2 GPIO2 GPIO4[1:0] GPIO3[1:0] GPIO2[1:0] GPIO1[1:0] 0000_0000
SE3 0xE3 GPD GPD4 GPD3 GPD2 GPD1 0000_0000
SE4 0xE4 CF5 NBCK SBCK DRT GPE 0000_0000
SE5 0xE5 DSP1 DDAV TDET TONE[4:0] 0000_0000
SE5 0xE5 DSP2 DTM[3:0] TONC[2:0] 0000_0000
SE6 0xE6 DSP3 CPSQ CPCD USEN2 USEN1 V23E ANSE DTMFE 0000_0000
SEB 0xEB TPD PDDE 0000_0000
SEC 0xEC RVC1 RNGV RDLY[2:0] RCC[2:0] 1000_1000
SED 0xED RVC2 RAS[5:0] 0001_1001
SEE 0xEE RVC3 RTO[3:0] RMX[3:0] 0001_0110
SF0 0xF0 DAA0 FOH[1:0] LM[1:0] 0100_0000
SF1 0xF1 DAA1 BTE PDN PDL LVFD HBE 0000_1100
SF2 0xF2 DAA2 FDT 0000_1000
SF4 0xF4 DAA4 ARL[1:0] ATL[1:0] 0000_1111
SF5 0xF5 DAA5 OHS[1:0] ILIM RZ RT 0000_0000
SF6 0xF6 DAA6 MINI[1:0] DCV[1:0] ACT[3:0] 1111_0000
SF8 0xF8 DAA8 LRV[3:0] DCR
SF9 0xF9 DAA9 BTD OVL ROV 0010_0000
SFC 0xFC DAAFC CTSM 0000_0000
AN94
Rev. 0.3 31
Reset settings = 0000_0110 (0x06)
S07 (MF1). Modem Functions 1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name BD V23R V23T BAUD CCITT FSK
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 BD Blind Dialing.
0 = Disable.
1 = Enable (Blind dialing occurs immediately after ATDT# command).
5 V23R V.23 Receive.*
V.23 75 bps send/600 (BAUD = 0) or 1200 (BAUD = 1) bps receive.
0 = Disable.
1 = Enable.
4 V23T V.23 Transmit.*
V.23 600 (BAUD = 0) or 1200 (BAUD = 1) bps send/75 bps receive.
0 = Disable.
1 = Enable.
3 Reserved Read returns zero.
2 BAUD 2400/1200 Baud Select.*
2400/1200 baud select (V23R = 0 and V23T = 0).
0 = 1200
1 = 2400
600/1200 baud select (V23R = 1 and V23T = 1).
0 = 600
1 = 1200
1 CCITT CCITT/Bell Mode.*
0 = Bell.
1 = CCITT.
0 FSK 300 bps FSK.*
0 = Disable.
1 = Enable.
*Note: See Table 6 on page 16 for proper setting of modem protocols.
AN94
32 Rev. 0.3
Reset settings = 0000_0000 (0x00)
S08 (INTM). Interrupt Mask
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CDM WORM PPDM NVDM RIM CIDM OCDM REVM
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 CDM Carrier Detect Mask.
0 = Change in CD does not affect INT.
1 = A high to low transition in CD (S09, bit 7), which indicates loss of carrier, activates
INT.
6 WORM Wake-on-Ring Mask.
0 = Change in CD does not affect INT.
1 = A low to high transition in WOR (S09, bit 6) activatesINT.
5 PPDM Parallel Phone Detect Mask.
0 = Change in PPD does not affect INT.
1 = A low to high transition in PPD (S09, bit 5) activates INT.
4 NVDM No Phone Line Detect Mask.
0 = Change in NLD does not affect INT.
1 = A low to high transition in NLD (S09, bit 4) activates INT.
3 RIM Ring Indicator Mask.
0 = Change in RI does not affect INT.
1 = A low to high transition in RI (S09, bit 3) activates INT.
2 CIDM Caller ID Mask.
0 = Change in CID does not affect INT.
1 = A low to high transition in CID (S09, bit 2) activates INT.
1 OCDM Overcurrent Detect Mask.
0 = Change in OCD does not affect INT.
1 = A low to high transition in OCD (S09, bit 1) activates INT.
0 REVM V.23 Reversal Detect Mask.
0 = Change in REV does not affect INT.
1 = A low to high transition in REV (S09, bit 0) activates INT.
AN94
Rev. 0.3 33
Reset settings = 0000_0000 (0x00)
S09 (INTS). Interrupt Status
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CD WOR PPD NVD RI CID OCD REV
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 CD Carrier Detect (sticky).
Active high bit indicates carrier detected (equivalent to inverse of CD pin). Clears on :1
read.
6 WOR Wake-on-Ring (sticky).
Wake-on-ring has occurred. Clears on :I read.
5 PPD Parallel Phone Detect (sticky).
Parallel phone detected since last off-hook event. Clears on :I read.
4 NVD No Phone Line Detect (sticky).
No line phone detected. Clears on :I read.
3 RI Ring Indicator (sticky).
Active high bit when the Si2403 is on-hook, indicates ring event has occurred. Clears on
:I read.
2 CID Caller ID (sticky).
Caller ID preamble has been detected; data soon follows. Clears on :I read.
1 OCD Overcurrent Detect (sticky).
Overcurrent condition has occurred. Clears on :I read.
0 REV V.23 Reversal Detect (sticky).
V.23 reversal condition has occurred. Clears on :I read.
AN94
34 Rev. 0.3
Reset settings = 0000_0000

(0x00)
S0C (MF2). Modem Functions 2
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CDE CIDM[1:0] 9BF BDL MLB
Type R/W R/W R/W R/W R/W
Bit Name Function
7
CDE
Carrier Detect Enable.
0 = Disable.
1 = Enable GPI02 as an active low carrier detect pin (must also set SE2[3:2]
[GPIO2] = 01).
6:5 CIDM[1:0] Caller ID Monitor.
00 = Caller ID monitor disabled.
01 = Caller ID monitor enabled. Si2401 must detect channel seizure signal followed by
marks in order to report caller ID data. (Normal Bellcore caller ID)
10 = Reserved.
11 = Caller ID monitor enabled. Si2401 must only detect marks in order to report caller ID
data.
4 Reserved Read returns zero.
3 9BF Ninth Bit Function.
Only valid if the ninth bit escape is set S15[0] (NBE).
0 = Ninth bit equivalent to ALERT.
1 = Ninth bit equivalent to HDLC EOFR.
2 BDL Blind Dialing.
0 = Blind dialing disabled.
1 = Enables blind dialing after dial timeout register S02 (CW) expires.
1 MLB Modem Loopback.
0 = Not swapped.
1 = Swaps frequency bands in modem algorithm to do a loopback in a test mode.
0 Reserved Read returns zero.
AN94
Rev. 0.3 35
Reset settings = 0000_0000 (0x00)
SOD (MF3). Modem Functions 3
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name RI INTP RBTS EHR EHB EHI EHE
Type R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7
Reserved Read returns zero.
6 RI Ring Indicator.
Specifies the functionality of pin3.
0 = Pin 3 functions as GPIO5 controlled by register SE1.
1 = Pin 3 functions as RI. RI asserts during a ring and negates when no
ring is present.
5 INTP INT Polarity.
Specifies the polarity of the INT function on pin 11.
0 = An interrupt forces pin 11 low.
1 = An interrupt forces pin 11 high.
4 RBTS Ringback Tone Selector.
Controls the unit step size for registers S19, S1A and S1B.
0 = 53.33 ms units. Necessary for detecting a ringback tone.
1 = 10 ms units. Necessary for detecting a reorder tone.
3 EHR Enable Hangup on Reorder.
Modem is placed on-hook if a ringback or reorder tone is detected. See S0D[4].
0 = Disable.
1 = Enable.
2 EHB Enable Hangup on Busy.
Modem is placed on-hook if a busy signal is detected.
0 = Disable.
1 = Enable.
1 EHI Enable Hangup on Intrusion.
Modem is placed on-hook if parallel intrusion is detected.
0 = Disable.
1 = Enable.
0 EHE Enable Hangup on Escape.
Modem is placed on-hook if a ESC signal is detected.
0 = Disable.
1 = Enable.
AN94
36 Rev. 0.3
Reset settings = 0000_0100 (0x04)
Reset settings = 0001_0000 (0x10)
S11 (OFHI). Off-Hook Intrusion
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name DCL[3:0]
Type R/W
Bit Name Function
7:4 Reserved Read returns zero.
3:0 DCL[3:0] Differential Current Level.
Differential current level to detect intrusion event (1 mA units).
S13 (MF3). Modem Function 3
Bit
D7 D6 D5 D4 D3 D2 D1 D0
Name BTID OFHD CIDB HDEN
Type R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 BTID BT Caller ID Wetting Pulse.
0 = Enable.
1 = Disable.
5 Reserved Read returns zero.
4 OFHD Off-Hook Intrusion Detect Method.
0 = Absolute.
1 = Differential.
3 Reserved Read returns zero.
2 CIDB British Telecom Caller ID Decode.
0 = Disable.
1 = Enable.
When set, SOC[6:5] is overwritten by the modem, as needed.
1 HDEN HDLC Framing.
0 = Disable.
1 = Enable.
0 Reserved Read returns zero.
AN94
Rev. 0.3 37
Reset settings = 0000_0100 (0x04)
S15 (MLC). Modem Link Control
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name ATPRE VCTE FHGE EHGE STB BDA[1:0] NBE
Type R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 ATPRE Answer Tone Phase Reversal.
0 = Disable.
1 = Enable answer tone phase reversal.
6 VCTE V.25 Calling Tone.
0 = Disable.
1 = Enable V.25 calling tone.
5 FHGE 550 Hz Guardtone.
0 = Disable.
1 = Enable 550 Hz guardtone.
4 EHGE 1800 Hz Guardtone.
0 = Disable.
1 = Enable 1800 Hz guardtone.
3 STB Stop Bits.
0 = 1 stop bit.
1 = 2 stop bits.
2:1 BDA[1:0] Bit Data.
00 = 6 bit data.
01 = 7 bit data.
10 = 8 bit data.
11 = 9 bit data.
0 NBE Ninth Bit Enable.
0 = Disable.
1 = Enable ninth bit as Escape and ninth bit function (register C).
AN94
38 Rev. 0.3
Reset settings = 0000_0001 (0x01)
S3C (CIDG). Caller ID Gain
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CIDG[2:0]
Type R/W
Bit Name Function
7:3 Reserved Read returns 0.
2:0 CIDG[2:0] Caller ID Gain.
The Si2400 dynamically sets the On-Hook Analog Receive Gain SF4[6:4] (ARG) to
CIDG during a caller ID event (or continuously if S0C[6:5] (CIDM = 11
b
). This field should
be set prior to caller ID operation.
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
AN94
Rev. 0.3 39
Reset settings = 0100_0001 (0x41)
S62 (RC). Result Codes Override
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name OCR IR NLR RR
Type R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 OCR Overcurrent Result Code (x).
0 = Enable.
1 = Disable.
5:3 Reserved Read returns zero.
2 IR Intrusion Result Code (I and i).
0 = Disable.
1 = Enable.
1 NLR No Phone Line Result Code (L and l).
0 = Disable.
1 = Enable.
0 RR Ring Result Code (R).
0 = Disable.
1 = Enable.
AN94
40 Rev. 0.3
Reset settings = 0000_1000 (0x08)
S82 (IST). Intrusion
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name IST[3:0] LCLD IB[1:0]
Type R/W R/W R/W
Bit Name Function
7:4 IST[3:0] Intrusion Settling Time.
0000 = IST equals 1 second.
Delay between when the ISOmodem chipset goes off-hook and the off-hook intrusion
algorithm begins (250 ms units).
3 LCLD Loop Current Loss Detect.
0 = Disable.
1 = Enables the reporting of I and L result codes while off-hook. Asserts INT if
GPIO4 (SE2[7:6]) is enabled as INT.
2:1 IB[1:0] Intrusion Blocking.
This feature only works when SDF = 0x00. Defines the method used to block the off-hook
intrusion algorithm from operating after dialing has begun.
00 = No intrusion blocking.
01 = Intrusion disabled from start of dial to end of dial.
10 = Intrusion disabled from start of dial to register S29 time out.
11 = Intrusion disabled from start of dial to carrier detect or to N or n result code.
0 Reserved Read returns zero.
AN94
Rev. 0.3 41
Reset settings = 0000_0000 (0x00)
SC0 (V80C). V80 Commands
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name ITC[1:0] ESA1 ESA2 ESOM[1:0] ESAM[1:0]
Type R/W R/W R/W R/W R/W
Bit Name Function
7:6 ITC[1:0] Transmit Flow Control.
Specifies the flow control to be implemented.
00 = No flow control/CTS only*
01 = Partial XON/XOFF flow control (modem -> host only)
10 = Hardware flow control (CTS and RTS*)
01 = Full XON/XOFF flow control
5 ESA1 Synchronous Access Mode control parameter 1.
Specifies the actions taken if a transmit data buffer underrun or overrun condition occurs
immediately after a non-flag octet, while operating in framed sub-mode.
0 = In framed sub-mode, abort on underrun in middle of frame
1 = In framed sub-mode, transmit a flag on underrun in middle of frame and notify host of
underrun or overrun
4 ESA2 Synchronous Access Mode control parameter 2.
Specifies the CRC polynomial used while operating in framed sub-mode.
0 = CRC generation and checking disable
1 = In framed sub-mode, a 16-bit CRC is generated by the modem in the transmit direc-
tion and checked by the DCE in the receive direction
3:2 ESOM[1:0] Enable Synchronous Originate Mode.
00 = Direct
01 = Initiate synchronous access mode when connection is completed and data state is
entered (See Table 1 on page 4 for the V.80 commands supported)
10 = Reserved
11 = Reserved
1:0 ESAM[1:0] Enable Synchronous Answer Mode.
00 = Direct
01 = Initiate synchronous access mode when connection is completed and data state is
entered (See Table 1 on page 4 for the V.80 commands supported)
10 = Reserved
11 = Reserved
*Note: CTS can be ignored, thereby implementing no flow control; GPIO1 is used as RTS.
AN94
42 Rev. 0.3
Reset settings = 0000_0000 (0x00)
Reset settings = 0000_1100 (0x0C)
SC3 (V80M). V80 Options
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name TRANSP[1:0]
Type R/W
Bit Name Function
7:1 Reserved Read returns zero.
0 TRANSP[1:0] Chooses which Submode is entered upon connection.
0 = Framed submode
1 = Transparent submode
SDF (DGSR). Intrusion Deglitch
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name DGSR[6:0]
Type R/W
Bit Name Function
7 Reserved Read returns zero.
6:0 DGSR[6:0] Deglitch Sample Rate.
Sets the sample rate for the deglitch algorithm and the off-hook intrusion algorithm
(40 ms units).
0000000 = Disables the deglitch algorithm, and sets the off-hook intrusion sample rate to
200 ms and delay between compared samples to 800 ms.
AN94
Rev. 0.3 43
Reset settings = 0010_0010 (0x22)
SE0 (CF1). Chip Functions 1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name ICTS ND SD[2:0]
Type R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5 ITCS
Invert CTS Pin.
0 = Inverted (CTS).
1 = Normal (CTS).
4 Reserved Read returns zero.
3 ND 0 = 8N1.
1 = 9N1 (hardware UART only).
2:0 SD[2:0] Serial Dividers.
000 = 300 bps serial link.
001 = 1200 bps serial link.
010 = 2400 bps serial link.
011 = 9600 bps serial link.
100 = 19200 bps serial link.
101 = 38400 bps serial link
110 = 115200 bps serial link.
111 = 307200 bps serial link.
AN94
44 Rev. 0.3
Reset settings = 0000_1110 (0x0E)
Reset settings = 0000_0000 (0x00)
SE1 (GPIO1). General Purpose Input/Output 1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name GPD5 GPIO5
Type R/W R/W
Bit Name Function
7:2 Reserved Read returns zero.
1 GPD5 GPIO5 Data.
Data = 0.
Data = 1.
0 GPIO5 GPIO5.
0 = Digital input.
1 = Digital output (relay drive).
SE2 (GPIO2). General Purpose Input/Output 2
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name GPIO4[1:0] GPIO3[1:0] GPIO2[1:0] GPIO1[1:0]
Type R/W R/W R/W R/W
Bit Name Function
7:6 GPIO4[1:0] GPIO4.
00 = Digital input.
01 = Digital output (relay drive).
10 = AOUT.
11 = INT function defined by S08.
5:4 GPIO3[1:0] GPIO3.
00 = Digital input.
01 = Digital output (relay drive).
10 = Reserved.
11 = ESC function (digital input).
3:2 GPIO2[1:0] GPIO2.
00 = Digital input.
01 = Digital output (relay drive; also used for CD function).
10 = Reserved.
11 = Digital input.
1:0 GPIO1[1:0] GPIO1*.
00 = Digital input.
01 = Digital output (relay drive).
10 = Reserved.
11 = Reserved.
*Note: To be used as a GPIO pin; SE4[3] (GPE) must equal zero.
AN94
Rev. 0.3 45
Reset settings = 0000_0000 (0x00)
Reset settings = 0000_0000 (0x00)
SE3 (GPD). GPIO Data
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name GPD4 GPD3 GPD2 GPD1
Type R/W R/W R/W R/W
Bit Name Function
7:4 Reserved Read returns zero.
3 GPD4 GPIO4 Data.
Data = 0
Data = 1
2 GPD3 GPIO3 Data.
Data = 0
Data = 1
1 GPD2 GPIO2 Data.
Data = 0
Data = 1
0 GPD1 GPIO1 Data.
Data = 0
Data = 1
SE4 (CF5). Chip Functions 5
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name NBCK SBCK DRT GPE
Type R R R/W R/W
Bit Name Function
7 NBCK 9600 Baud Clock (Read Only).
6 SBCK 600 Baud Clock (Read Only).
5 DRT Data Routing.
0 = Data mode, DSP output transmitted to line, line received by DSP input.
1 = Loopback mode, TXD through microcontroller (DSP) to RXD. AIN looped to AOUT.
4 Reserved Read returns zero.
3 GPE GPIO1 Enable.
0 = Disable.
1 = Enable GPIO1 to be HDLC end-of-frame flag.
2:0 Reserved Read returns zero.
AN94
46 Rev. 0.3
Reset settings = 0000_0000 (0x00)
SE5 (DSP1). (SE8 = 0x02) Read Only Definition
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name DDAV TDET TONE[4:0]
Type R R R
Bit Name Function
7 DDAV DSP Data Available.
6 TDET Tone Detected.
Indicates a TONE (any of type 025 below) has been detected.
0 = Not detected.
1 = Detected.
5 Reserved Read returns zero.
4:0 TONE[4:0] Tone Type Detected.
When TDET goes high, TONE indicates which tone has been detected from the following:
TONE Tone Type Priority
0000001111 DTMF 015 (DTMFE = 1)
1
See Table 11 on page 24. 1
10000 Answer tone detected 2100 Hz (ANSE = 1)
2
2
10001 Bell 103 answer tone detected 2225 Hz (ANSE = 1) 2
10010 V.23 forward channel mark 1300 Hz (V23E = 1)
3
3
10011 V.23 backward channel mark 390 Hz (V23E = 1) 3
10100 User defined frequency 1 (USEN1 = 1)
4
4
10101 User defined frequency 2 (USEN1 = 1) 4
10110 Call progress filter A detected 6
10111 User defined frequency 3 (USEN2 = 1)
5
5
11000 User defined frequency 4 (USEN2 = 1) 5
11001 Call progress filter B detected 6
Notes:
1. SE6[0] (DTMFE) SE8 = 0x02.
2. SE6[1] (ANSE) SE8 = 0x02.
3. SE6[2] (V23E) SE8 = 0x02.
4. SE6[3] (USEN1) SE8 = 0x02.
5. SE6[4] (USEN2) SE8 = 0x02.
AN94
Rev. 0.3 47
Reset settings = 0000_0000 (0x00)
SE5 (DSP2). (SE8 = 0x02) Write Only Definition
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name DTM[3:0] TONC[2:0]
Type W W
Bit Name Function
7 Reserved Always write zero.
6:3 DTM[3:0] Tone Type Generated.
DTMF tone (015) to transmit when selected by TONC = 001. See Table 11 on page 24.
2:0 TONC[2:0] DTMF Tone Selector.
ToneTone Type
000 Mute
001 DTMF
010 2225 Hz Bell mode answer tone with phase reversal
011 2100 Hz CCITT mode answer tone with phase reversal
100 2225 Hz Bell mode answer tone without phase reversal
101 2100 Hz CCITT mode answer tone without phase reversal
110 User-defined programmable frequency tone (UFRQ)
(see Table 15 on page 66, default = 1700 Hz)
111 1300 Hz V.25 calling tone
AN94
48 Rev. 0.3
Reset settings = 0000_0000 (0x00)
SE6 (DSP3). (SE8 = 0x02) Write Only Definition
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CPSQ CPCD USEN2 USEN1 V23E ANSE DTMFE
Type W W W W W W W
Bit Name Function
7 CPSQ Call Progress Squaring Filter.
0 = Disable.
1 = Enables a squaring function on the output of filter B before the input to A (cascade
only).
6 CPCD Call Progress Cascade Disable.
0 = Call progress filter B output is input into call progress filter A. Output from fil-
ter A is used in the detector.
1 = Cascade disabled. Two independent fourth order filters available (A and B). The
largest output of the two is used in the detector.
5 Reserved
4 USEN2 User Tone Reporting Enable 2.
0 = Disable.
1 = Enable the reporting of user defined frequency tones 3 and 4 through TONE.
3 USEN1 User Tone Reporting Enable 1.
0 = Disable.
1 = Enable the reporting of user defined frequency tones 1 and 2.
2 V23E V.23 Tone Reporting Enable.
0 = Disable.
1 = Enable the reporting of V.23 tones, 390 Hz and 1300 Hz.
1 ANSE Answering Tone Reporting Enable.
0 = Disable.
1 = Enable the reporting of answer tones.
0 DTMFE DTMF Tone Reporting Enable.
0 = Disable.
1 = Enable the reporting of DTMF tones.
AN94
Rev. 0.3 49
Reset settings = 0000_0000 (0x00)
SEB (TPD). Timer and Powerdown
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name PDDE
Type R/W
Bit Name Function
7:4 Reserved Read returns zero.
3 PDDE Powerdown DSP Engine.
0 = Power on.
1 = Powerdown.
2:0 Reserved Read returns zero.
AN94
50 Rev. 0.3
Reset settings = 1000_1000 (0x88)
SEC (RVC1). Ring Validation Control 1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name RNGV RDLY[2:0] RCC[2:0]
Type R/W R/W R/W
Bit Name Function
7 RNGV Ring Validation Enable.
0 = Ring validation feature is disabled.
1 = Ring validation feature is enabled in both normal operating mode and low-
power mode.
6:4 RDLY[2:0] Ring Delay.
These bits set the amount of time between when a ring signal is validated and when a
valid ring signal is indicated.
RDLY[2:0] Delay
000 0 ms
001 256 ms
010 512 ms
.
.
.
111 1792 ms
3:1 RCC[2:0] Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances
set by the RAS[5:0] bits and the RMX[3:0] bits to be classified as a valid ring signal.
RCC[2:0] Ring Confirmation Count Time
000 100 ms
001 150 ms
010 200 ms
011 256 ms
100 384 ms
101 512 ms
110 640 ms
111 1024 ms
0 Reserved This bit must always be written to zero.
AN94
Rev. 0.3 51
Reset settings = 0001_1001 (0x19)
SED (RVC2). Ring Validation Control 2
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name RAS[5:0]
Type R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:0 RAS[5:0] Ring Assertion Time.
These bits set the minimum ring frequency for a valid ring signal. During ring qualification, a
timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular
rate. If a second or subsequent TIP/RING event occurs after the timer has timed out, the
frequency of the ring is too low, and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every
1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range [f_min,
f_max], the following equation should be used: RAS[5:0] = 1 / (2 x f_min).
AN94
52 Rev. 0.3
Reset settings = 0001_0110 (0x16)
SEE (RVC3). Ring Validation Control 3
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name RTO[3:0] RMX[3:0]
Type R/W R/W
Bit Name Function
7:4 RTO[3:0] Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0] Ring Timeout
0000 80 ms
0001 128 ms
0010 256 ms
.
.
.
1111 1920 ms
3:0 RMX[3:0] Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-
ular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the
RMX[3:0] field, and if it exceeds the value in RMX[3:0], the frequency of the ring is too
high, and the ring is invalidated. The difference between RAS[5:0] and RMX[3:0] identifies
the minimum duration between TIP/RING events to qualify as a ring, in binary-coded incre-
ments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period.
At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the cor-
rect RMX[3:0] value for a frequency range [f_min, f_max], the following equation should be
used: RMX[3:0] x 2 ms = RAS[5:0] 2 ms (1/(2 x f_max)).
AN94
Rev. 0.3 53
Reset settings = 0100_0000 (0x40)
SF0 (DAA0). DAA Low Level Functions 0
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name FOH[1:0] LM[1:0]
Type R/W R/W R/W
Bit Name Function
7:6 FOH[1:0] Fast Off-Hook Selection.
These bits determine the length of the off-hook counter. The default setting is 128 ms.
00 = 512 ms
01 = 128 ms
10 = 64 ms
11 = 8 ms
5:2 Reserved Read returns zero.
1:0 LM[1:0] Line Mode.
These bits determine the line status of the Si2401.*
00 = On-hook
01 = Off-hook
10 = On-hook line monitor mode
11 = Reserved
*Note: Under normal operation, the Si2401 internal microcontroller automatically sets these bits appropriately.
AN94
54 Rev. 0.3
Reset settings = 0000_1100 (0x0C)
SF1 (DAA1). DAA Low Level Functions 1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name BTE PDN PDL LVFD HBE
Type R/W R/W R/W R/W R/W
Bit Name Function
7 BTE Billing Tone Enable.
When the line-side device detects a billing tone, SF9[3] (BTD) is set.
0 = Disable.
1 = Enable.
6 PDN Powerdown.
0 = Normal operation.
1 = Powers down the Si2401.
5 PDL Powerdown Line-Side Chip (typically only used for board level debug.)
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the line-side device in lower power mode.
4 LVFD Line Voltage Force Disable.
0 = Normal operation.
1 = The circuitry that forces the LVS register to all 0s at 3 V or less is disabled. This reg-
ister may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed
if the line voltage is 0 V.
3 Reserved Do not modify.
2 HBE Hybrid Transmit Path Connect.
0 = Disable.
1 = Enable.
1:0 Reserved Do not modify.
AN94
Rev. 0.3 55
Reset settings = 0000_1000 (0x08)
Reset settings = 0000_1111 (0x0F)
SF2 (DAA2). DAA Low Level Functions 2
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name FDT
Type R
Bit Name Function
7:4 Reserved Read only.
3 FDT Frame Detect (Typically only used for board-level debug).
1 = Indicates frame lock has been established.
0 = Indicates frame lock has not been established.
2:0 Reserved Reserved
SF4 (DAA4). DAA Low Level Functions 4
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name ARL[1:0] ATL[1:0]
Type R/W R/W
Bit Name Function
7:4 Reserved Read returns zero.
3:2 ARL[1:0] AOUT ReceivePath Level.
DAA receive path signal AOUT gain.
00 = 0 dB
01 = 6 dB
10 = 12 dB
11 = Mute
1:0 ATL[1:0] AOUT TransmitPath Level.
DAA transmit path signal AOUT gain.
00 = 18 dB
01 = 24 dB
10 = 30 dB
11 = Mute
AN94
56 Rev. 0.3
Reset settings = 0000_0000 (0x00)
SF5 (DAA5). DAA Low Level Functions 5
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name OHS[1:0] ILIM RZ RT
Type R/W R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:4 OHS[1:0]
On-Hook Speed.
These bits set the amount of time for the line-side device to go on-hook. The on-hook
speeds specified are measured from the time the register is written until loop current
equals zero.
OHS[1:0] Mean On-Hook Speed
00 Less than 0.5 ms
01 3 ms 10% (Meets ETSI standard)
1X 20 ms 10% (Meets Australian spark quenching spec)
3 ILIM Current Limiting Enable.
0 = Current limiting mode disabled.
1 = Current limiting mode enabled. This mode limits loop current to a maximum of 60 mA
per the TBR-21 standard.
2 RZ Ringer Impedance.
0 = Maximum (high) ringer impedance.
1 = Synthesized ringer impedance used to satisfy a maximum ringer impedance specifi-
cation in countries, such as Poland, South Africa, and Slovenia.
1 Reserved Do not modify.
0 RT Ringer Threshold Select.
Used to satisfy country requirements on ring detection. Signals below the lower level do
not generate a ring detection; Signals above the upper level are guaranteed to generated
a ring detection.
0 = 13.5 to 16.5 V
RMS
1 = 19.35 to 23.65 V
RMS
AN94
Rev. 0.3 57
Reset settings = 1111_0000 (0xF0)
SF6 (DAA6). DAA Low Level Functions 6
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name MINI[1:0] DCV[1:0] ACT[3:0]
Type R/W R/W R/W
Bit Name Function
7:6 MINI[1:0] Minimum Operational Loop Current.
Adjusts the minimum loop current at which the DAA can operate. Increasing the mini-
mum operational loop current can improve signal headroom at a lower TIP/RING volt-
age.
MINI[1:0] Min Loop Current
00 10 mA
01 12 mA
10 14 mA
11 16 mA
5:4 DCV[1:0] TIP/RING Voltage Adjust.
These bits adjust the voltage on the DCT pin of the line-side device, which affects the
TIP/RING voltage on the line. Low voltage countries should use a lower TIP/RING volt-
age. Raising the TIP/RING voltage can improve signal headroom.
DCV[1:0] DCT Pin Voltage
00 3.1 V
01 3.2 V
10 3.35 V
11 3.5 V
3:0 ACT[3:0] AC Termination Select.
ACT[3:0] AC Termination
0000 Real 600 O termination that satisfies the impedance requirements
of FCC part 68, JATE, and other countries.
0011 Global complex impedance. Complex impedance that satisfies global
impedance requirements EXCEPT New Zealand. May achieve higher
return loss for countries requiring complex ac termination.
[220 O + (820 O || 120 nF) and 220 O + (820 O || 115 nF)].
0100 Complex impedance for use in New Zealand.
[370 O + (620 O || 310 nF)]
1111 Complex impedance that satisfies global impedance requirements.
AN94
58 Rev. 0.3
Reset settings vary with line-side vision.
Reset settings = 0010_0000 (0x20)
SF8 (DAA8). DAA Low Level Functions 8
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name LRV[3:0] DCR
Type R R/W
Bit Name Function
7:4 LRV[3:0] Line-Side Device Revision Number.
0011 = Si3010 Rev C
0100 = Si3010 Rev D
0101 = Si3010 Rev E
0110 = Si3010 Rev F
3:2 Reserved Read returns an indeterministic value.
1 DCR DC Impedance Selection.
0 = 50 O dc termination is selected. This mode should be used for all standard
applications.
1 = 800 O dc termination is selected.
0 Reserved Do not modify.
SF9 (DAA9). DAA Low Level Functions 9 Read Only
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name BTD OVL ROV
Type R/W R R/W
Bit Name Function
7:4 Reserved Do not modify.
3 BTD Billing Tone Detect (sticky).
0 = No billing tone detected.
1 = Billing tone detected.
2 OVL Receive overload.
Same as ROV, except not sticky.
1 ROV Receive Overload (sticky).
0 = No excessive level detected.
1 = Excessive input level detected.
0 Reserved Do not modify.
AN94
Rev. 0.3 59
Reset settings = 0000_0000 (0x00)
SFC (DAAFC). DAA Low Level Functions
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name CTSM
Type R/W
Bit Name Function
7 CTSM Clear-to-Send (CTS) Mode.
0 = CTS pin is negated as soon as a start bit is detected and reasserted when the
transmit FIFO is empty.
1 = CTS pin is negated when the FIFO is > 70% full and reasserted when the FIFO is <
30% full.
6:0 Reserved Read value indeterminate.
AN94
60 Rev. 0.3
4.6. Fast Connect
In modem applications that require fast connection
times, it is possible to reduce the length of the
handshake.
Additional modem handshaking control can be adjusted
through the registers shown in Table 15. These
registers are most useful if the user has control of both
the originating and answering modems.
When the fast connect settings are used, there may be
unintended data received initially.The host must tolerate
these bytes. Figures 10, 14, 15 and illustrate the
connect sequence for V.22 and V.22b.
4.6.1. Internal Connect Sequence
V.22 and Bell212 modes use the same state machines.
They do not deviate much. Assuming NAT = 0...
After dialing, these are the events that occur, assuming
that S07=02
Check answer tone length for S31 time units
(Checking of answer tone is totally skipped if
S31=0)
Wait until the end of answer tone
Wait an additional S1F time units
Begin detection of unscrambled ones pattern (S20
time units minimum)
If successful,
Wait S21 time units
Transmit scrambled ones for S22 time units
Transmit scrambled ones while detecting
scrambled ones (S35 time units minimum)
If successful,
Transmit scrambled ones for S23+S24 time units
send 'c' result code
data connection (includes HDLC handling)
For S07=00, these are the events that occur:
Check answer tone length for S31 time units
(Checking of answer tone is totally skipped if
S31=0)
Wait S1F time units then
Wait an additional S1F time units
Begin detection of unscrambled ones pattern (S20
time units minimum)
If successful,
Wait S21 time units
Transmit scrambled ones for S22 time units
Transmit scrambled ones while detecting
scrambled ones (S35 time units minimum)
If successful,
Transmit scrambled ones for S23+S24 time units
send 'c' result code
data connection (includes HDLC handling)
For S07=01, Bell103, these are the events that occur:
Check answer tone length for S31 time units
(Checking of answer tone is totally skipped if
S31=0)
Wait S1F time units then
Wait an additional S1F time units
Begin transmitting mark
Table 14. V.22/Bell212 Handshaking Control Registers
Register Name Function Units Default Fast Connect
S1E TATL Transmit Answer Tone Length 1 s 0x03 00
S1F ATTD Answer Tone to Transmit Delay 5/3 ms 0x2D 00
S20 UNL Unscrambled Ones LengthV.22 5/3 ms 0x5D 00
S21 TSOD Transmit Scrambled Ones DelayV.22 53.3 ms 0x09 00
S22 TSOL Transmit Scrambled Ones LengthV.22 5/3 ms 0xA2 00
S23 VDDL V.22/22b Data Delay Low 5/3 ms 0xCB 00
S24 VDDH V.22/22b Data Delay High (256) 5/3 ms 0x08 00
S34 TASL Answer Tone Length
(only used in S1E[TATL] = 0x00)
5/3 ms 0x5A F0
S35 RSOL Receive V.22 Scrambled Ones Length 5/3 ms 0xA2 00
AN94
Rev. 0.3 61
Wait S2F+S30 time units
send 'c' result code
data connection (includes HDLC handling)
Assuming that the NAT bit is set...
Case #1:If the answer tone length is non-zero.
The modem will need to detect a "short answer tone".
"Short" being defined as detection of one single
instance of an answer tone.
Once the "short answer tone" is detected, the Si2400
goes directly into the S1F delay loop.
Case #2: If the answer tone length is zero
NAT bit is a don't care.
Figure 10. V.22
Originate
Transmitter
Receiver
Scrambled binary 1 @ 1200 bps Data
S21
480 ms
S22
270 ms
S23 + S24
765 10 ms
3752 ms
S31
100 ms
S1F
S20
155 ms
Detect unscrambled
binary 1s
S35
270 40 ms
270 ms
Scrambled binary 1 @ 1200 bps Data
S3A
2.187s
S20
155 ms
Unscrambled binary 1 @ 1200 bps Ans tone
Answer
S1E
3s
75 ms
Tx
Rx
B212
Look for end of ans tone
for bell 212A wait only S1F time
S22
270 40 ms
S23 + S24
765 10 ms
3752 ms
Detect scrambled
binary 1s
B212
S1F
S1F
AN94
62 Rev. 0.3
Figure 11. V.22 (NAT)
Figure 12. V.22bis
Originate
Transmitter
Receiver
Scrambled binary 1 @ 1200 bps Data
S21
480 ms
S22
270 ms
S23 + S24
765 10 ms
3752 ms
S35
270 40 ms
270 ms
Scrambled binary 1 @ 1200 bps Data
S3A
2.187s
S1F S20
155 ms
Unscrambled binary 1 @ 1200 bps Ans tone
Answer
S1E
3s
75 ms
Tx
Rx
S22
270 40 ms
S23 + S24
765 10 ms
3752 ms
Detect scrambled
binary 1s
Originate
Transmitter
Receiver
Scrambled binary 1 @ 1200 bps
Scrambled
1s 2400 bps
S1
Data
squelch
Data
S21
456 10
480 ms
S25
100 3
100 ms
S26
600 10
640 ms
S27
200 10
200 ms
S28
No spec
3413 ms
S31
?
100 ms
S1F
S20
155 10
155 ms
Detect unscrambled
binary 1s
S35
270
40 ms
Direct SI
or 270 ms
of scr.1
6.3.1.1.1.c
450 10 ms
Receive @ 1200
450 ms
Detect 32 bits
@ 2400
Equalizer enabled
Receive @ 2400
Scrambled binary 1 @ 1200 bps
Scrambled
1s 2400 bps
S1
Data
squelch
Data
S25
100 3
100 ms
600 10
S27
200 10
200 ms
S28
No spec
3413 ms
S3A
215
.35s
2.187s
S20
155 ms
450 10 ms
Receive @ 1200
Detect 32 bits
@ 2400
Equalizer enabled
Receive @ 2400
Unscrambled binary 1 @ 1200 bps Ans tone
Answer
S1E
3300 700
3s
75
20
75 ms 350 ms
52A
We align this and
ignore the 600
Detect
S1
If S22 time of scrambled 1s
detected, use V.22
Tx
Rx
S1F
S1F
AN94
Rev. 0.3 63
Figure 13. V.22bis
1200bps (1300 Hz)
Si2401
Transmit
Si2401
Receive
75bps (390 Hz)
75bps (390Hz)
S2D S2E
1200bps (1300 Hz)
S2B
Carrier
Detect
v
Si2401
TX pin
ALERT
pin
1200bps (1300 Hz)
Si2401
Transmit
Si2401
Receive
75bps (390 Hz)
75bps (390 Hz)
S2D S2E
Carrier
Detect
c
Si2401
TX pin
ALERT
pin
S2E
75bps (390 Hz)
S2B
Si2401 V.23 Reversal Behavior
1200 Hz
S2B
1200bps (1300 Hz)
AN94
64 Rev. 0.3
4.6.2. Overall Protocol Supported by the Si2401 Fast Connect Sequence
Si2401 Originate Modem Answer Modem
Host initializes Modem (Note 1)
Host sends ATDT command (Note 2)
Modem Goes Off Hook, Dial.
Go Off Hook in response to Incoming Ring.
Wait for billing delay.
Begin Answer Tone for at least 100 ms up to 2.3 s.
Modem Detects Answer Tone for 100 ms
Modem sends 'c' to Host
Host must not transmit/receive for 300 ms to allow send-
ing of Scrambled 1s or (HDLC Sync) to answering
modem. Garbage data received during this time must be
discarded.
Detect Scrambled 1s (or HDLC Sync) for 100 ms. Stop
Answer Tone then send Scrambled 1s (or HDLC Sync)
for 100 ms. Enter Data Mode, begin Receive and
Transmit.
Once 300 ms has elapsed, begin data receive/transmit.
Notes:
1. Register Initialization
ATS07=00 Bell212 mode, (if HDLC, use ATS07=80)
ATS31=3 receive answer tone length = 100 ms
ATS1F=00 transmit delay from answer tone end = 0
ATS20=00 detection of unscrambled ones minimum time = 0
ATS21=00 scrambled ones transmit delay = 0
ATS22=00 scrambled ones transmit duration = 0
ATS35=00 receive scrambled ones minimum duration = 0
ATS23=00 V22 data delay lower byte
ATS24=00 V22 data delay upper byte
2. Dialing Procedure
This sequence must be used instead of ATDT####<cr>, after the registers above have been initialized.
ATDT####<cr> Originate Call
Wait for 'c'
Wait an additional 300 ms to provide answering modem time to detect the scrambled 1s (or HDLC sync)
AN94
Rev. 0.3 65
4.7. Low Level DSP Control
Although not necessary for most applications, the DSP
low-level control functions are available for users with
very specific applications requiring direct DSP control.
4.7.1. DSP Registers
Several DSP registers are accessible through the
Si2401 microcontroller via S-registers SE5, SE6, and
SE8. SE5 and SE6 are used as conduits to write data to
specific DSP registers and read status. SE8 defines the
function of SE5 and SE6 depending on whether they
are being written to or read from. Care must be
exercised when writing to DSP registers. DSP registers
can only be written while the Si2401 is on-hook and in
the command mode. Writing to any register address not
listed in Tables 15 and 16 or writing out-of-range values
is likely to cause the DSP to exhibit unpredictable
behavior.
The DSP register address is 16-bits wide, and the DSP
data field is 14-bits wide. DSP register addresses and
data are written in hexadecimal. To write a value to a
DSP register, the register address is written, and then
the data is written. When SE8 = 0x00, SE5(DADL) is
written with the low bits [7:0] of the DSP register
address, and SE6 (DADH) is written with the high bits
[15:8] of the DSP address. When SE8 = 0x01,
SE5 (DDL) is written with the low bits [7:0] of the DSP
data word corresponding to the previously written
address, and SE6 (DDH) is written with the high bits
[15:8] of the data word corresponding to the previously
written address. Example 1 illustrates the proper
procedure for writing to DSP registers.
Example1: The user would like to program call
progress filter coefficient A2_k0 (0x15) to be 309
(0x135).
Host Command:
ATSE8=00SE6=00SE5=15SE8=01SE6=01SE5=35SE8=00
In this command, ATSE8=00 sets up registers SE5 and
SE6 as DSP address registers. SE6=00 sets the high
bits of the address, and SE5=15 sets the low bits.
SE8=01 sets up registers SE5 and SE6 as DSP data
registers for the previously-written DSP address (0x15).
SE6=01 sets the six high bits of the 14-bit data word,
and SE5=35 sets the eight low bits of the 14-bit data
word.
AN94
66 Rev. 0.3
Table 15. Low-Level DSP Parameters
DSP Reg. Addr.
Name Description Function Default
(dec)
0x0002 XMTL DAA modem full-scale transmit level,
default = 10 dBm.
Level = 20log
10
(XTML/4096)
10 dBm
4096
0x0003 DTML DTMF high-tone transmit level,
default = 5.5 dBm.
Level = 20log
10
(DTML/4868)
5.5 dBm
4868
0x0004 DTMT DTMF twist ratio (low/high),
default = 2 dBm.
Level = 20log
10
(DTMT/3277)
2 dB
3277
0x0005 UFRQ User-defined transmit tone frequency. See
register SE5 (SE8=0x02 (Write Only)).
f = (9600/512) UFRQ (Hz) 91
0x0006 CPDL Call progress detect level (see Figure 14),
default = 43 dBm.
Level = 20log
10
(4096/CPDL)
43 dBm
4096
0x0007 UDFD1 User-defined frequency detector 1. Center
frequency for detector 1.
UDFD1 = 8192 cos (2t f/9600) 4987
0x0008 UDFD2 User-defined frequency detector 2. Center
frequency for detector 2.
UDFD2 = 8192 cos (2t f/9600) 536
0x0009 UDFD3 User-defined frequency detector 3. Center
frequency for detector 3.
UDFD3 = 8192 cos (2t f/9600) 4987
0x000A UDFD4 User-defined frequency detector 4. Center
frequency for detector 4.
UDFD4 = 8192 cos (2t f/9600) 536
0x000B TGNL Tone generation level associated with TONC
(SE5 (SE8 = 0x02) Write Only Definition),
default = 10 dBm.
Level = 20log
10
(TGNL/2896)
10 dBm
2896
0x000E UDFSL Sensitivity setting for UDFD14 detectors,
default = 43 dBm.
Sensitivity = 10log
10
(UDFSL/
4096) 43 dBm
4096
0x0024 CONL Carrier ON level. Carrier is valid once it
reaches this level.
Level = 20log
10
(2620/CONL)
43 dBm
2620
0x0025 COFL Carrier OFF level. Carrier is invalid once it
falls below this level.
Level = 20log
10
(3300/COFL)
45.5 dBm
3300
0x0026 AONL Answer ON level. Answer tone is valid once it
reaches this level.
Level = 10log
10
(AONL/107)
43 dBm
67
0x0027 AOFL Answer OFF level. Answer tone is invalid
once it falls below this level.
Level = 10log
10
(AOFL/58)
45.5 dBm
37
AN94
Rev. 0.3 67
Table 16 defines the relationship between SE5, SE6, and SE8.
4.7.2. Call Progress Filters
The programmable call progress filter coefficients are located in DSP address locations 0x0010 through 0x0023.
There are two independent 4th order filters, A and B, each consisting of two biquads, for a total of 20 coefficients.
Coefficients are 14 bits (8192 to 8191) and are interpreted as, for example, b0 = value/4096, thus giving a floating
point value of approximately 2.0 to 2.0. Output of each biquad is calculated as follows:
The output of the filters is input to an energy detector and then compared to a fixed threshold with hysteresis (DSP
register CPDL). Defaults shown are a bandpass filter from 290630 Hz (3 dB). These registers are located in the
DSP and, thus, must be written in the same manner described in "DSP Registers" on page 65.
The filters may be configured in either parallel or cascade through SE6[6] (CPCD) with SE8 = 0x02, and the output
of filter B may be squared by selecting SE6[7] (CPSQ) = 1. Figure 14 shows a block diagram of the call progress
filter structure.
Table 16. SE5, SE6, and SE8 Relationship
SE8 SE6 SE5
R/W Name Description Name Description
0x00 W DADH
DSP register address bits [15:8]
DADL DSP register address bits [7:0]
0x01 W DDH
DSP register data bits [15:8]
DDL DSP register data bits [7:0]
0x02 R DSP1 7 = DSP data available
6 = Tone detected
5 = Reserved
4:0 = Tone type
0x02 W DSP3
7 = Enable squaring function
6 = Call progress cascade disable
5 = Reserved
4 = User tone 3 and 4 reporting
3 = User tone 1 and 2 reporting
2 = V.23 tone reporting
1 = Answer tone reporting
0 = DTMF tone reporting
DSP2 7 = Reserved
6:3 = DTMF tone to transmit
2:0 = Tone type
w n | | k0 x n | | a1 w n 1 | | a2 w n 2 | | + + =
y n | | w n | | b1 w n 1 | | b2 w n 2 | | + + =
AN94
68 Rev. 0.3
Figure 14. Programmable Call Progress Filter Architecture
Table 17. Call Progress Filters
DSP Register
Address
Coefficient Default (dec)
0x0010 A1_k0 256
0x0011 A1_b1 8184
0x0012 A1_b2 4096
0x0013 A1_a1 7737
0x0014 A1_a2 3801
0x0015 A2_k0 1236
0x0016 A2_b1 133
0x0017 A2_b2 4096
0x0018 A2_a1 7109
0x0019 A2_a2 3565
0x001A B1_k0 256
0x001B B1_b1 8184
0x001C B1_b2 4096
0x001D B1_a1 7737
0x001E B1_a2 3801
0x001F B2_k0 1236
0x0020 B2_b1 133
0x0021 B2_b2 4096
0x0022 B2_a1 7109
0x0023 B2_a2 3565
Filter B
1 0
1
0
1
0
Filter A
Filter Input
y = x
2
CPSQ
Energy
Detect
0
CPCD
Max
(A,B)
Hysteresis
A > B?
20log
10
(4096/CPDL) 43 dBm
TDET
A
B
A
B
CPCD
Energy
Detect
AN94
Rev. 0.3 69
4.8. Programming Examples
The following are examples of how to configure the
Si2401 and take advantage of key features.
4.8.1. Parallel Phone Detection
The ISOmodem

chipset is able to detect when another


telephone, modem, or other device is using the phone
line. This allows the host to avoid interrupting another
phone call when the phone line is already in use and to
intelligently handle an interruption when the ISOmodem
chipset is using the phone line.
4.8.1.1. On-Hook Intrusion Detection
When the ISOmodem chipset is sharing the telephone
line with other devices, it is important that it not interrupt
a call in progress. To detect when another device is
using the shared telephone line, the host can use the
ISOmodem chipset to monitor the TIP-RING dc voltage
with the LVS[7:0] bits (SDB). The LVS[7:0] bits have a
resolution of 1 V per bit with an accuracy of
approximately 10%. Bits 0 through 6 of this 8-bit signed
2s complement number indicate the value of the line
voltage, and the sign bit (bit 7) indicates the polarity of
TIP and RING.
When all devices on a particular telephone line are on-
hook, there is no loop current flowing through TIP and
RING. Therefore, the voltage across TIP and RING is at
a maximum. (On most telephone lines, this on-hook
voltage is a minimum of 40 V.) Once a device goes off-
hook, current flows through TIP and RING on that
device, and the TIP-RING voltage drops appreciably.
(On most telephone lines, this off-hook voltage is a
maximum of 20 V.)
If the host checks the TIP-RING voltage via LVS before
causing the ISOmodem chipset to dial out or go off-
hook, the host can determine if another device is using
the telephone line. One way to do this is to verify that
the voltage represented in LVS is above some fixed
threshold, such as 21 V.
4.8.1.2. Off-Hook Intrusion Detection
After it has been determined that it is safe to use the
phone line without interrupting a call, the host can
instruct the ISOmodem chipset to begin a call or go off-
hook. However, once the call has begun and the
ISOmodem chipset is in data mode, the serial port is
used for modem data making it difficult for the host to
monitor registers. Therefore, when the ISOmodem
chipset is off-hook, an algorithm is implemented to
automatically monitor the TIP-RING loop current via the
LCS register (SF3). Because the TIP-RING voltage
drops significantly when off-hook, TIP-RING current is a
better indicator of another device using the phone line.
The LCS[7:0] bits have a resolution of 1.1 mA per bit, as
long as the represented loop current value is greater
than the minimum loop indicated by the MINI bit field
(SF6[7:6]).
The off-hook intrusion algorithm monitors the value of
LCS (SF3) at a sample rate determined by the DGSR
(SDF, bits 6:0) register (40 ms units). The algorithm
compares each LCS sample to the reference value in
the ACL register (S12). If LCS is lower than ACL by an
amount greater than DCL (S11, bits 4:0), the algorithm
waits for another LCS sample, and if the next LCS
sample is also lower than ACL by an amount greater
than DCL, an interrupt occurs. This helps the
ISOmodem chipset avoid a false parallel phone
detection (PPD) interrupt due to glitches on the phone
line. The ACL is continually updated with the value of
LCS as outlined below. The algorithm can be outlined
as follows:
If LCS(t) = LCS(t 40 ms x DGSR)
and
LCS(t) ACL > DCL
then ACL = LCS(t)
If (ACL LCS[t 40 ms x DGSR]) > DCL)
and
(ACL LCS[t]) > DCL)
then an intrusion is sent to the host.
Upon detecting an intrusion, an "i" result code is sent to
the host if it is in the call negotiation stage or command
mode. Otherwise, the modem can be programmed to
generate an interrupt to notify the host of the intrusion.
4.8.1.3. How MINI and LCS Affect Programming
DCL
This section applies to applications expected to use a
large DCL value.
The value returned by the LCS register (SF3) is
expected to represent the loop current in 1.1 mA steps
as long as the actual loop current is greater than the
minimum required indicated by MINI (SF6[7:6]). If the
loop current available to the DAA is less than the
required minimum current, then the DAA returns a non-
accurate LCS reading.
For example, if MINI is 11, the minimum loop current for
proper operation of the DAA is 16 mA. If LCS returns
0x10, this represents a loop current value of 17.6 mA.
Since 17.6 mA is greater than 16 mA, then, the LCS is
expected to be accurate.
However, let's say that LCS returns the value of 0x0E.
In this case, the implied loop current is 15.4 mA less
than 16 mA. In this case, LCS is not accurate, and the
actual loop current is most likely to be much less than
the 15.4 mA represented.
AN94
70 Rev. 0.3
If the loop current value returned by LCS is less than the
loop current minimum (MINI), this condition should be
treated as an intrusion event, even though the
difference, compared to the loop current reference, is
less than the desired DCL difference.
However, the internal off hook intrusion algorithm does
not automatically treat these low loop current values as
an automatic intrusion event. Therefore, it is the
responsibility for host software to account for the above
non-linear operation. This can be achieved by
dynamically adjusting the DCL value based on the
algorithm shown below.
The subroutine shown in Example Intrusion
Subroutine can be used to synthesize the 'actual DCL'
to be written to register S11, when given ACL, MINI and
'desired DCL'. This subroutine is best placed prior to an
ATDT command.
AN94
Rev. 0.3 71
4.8.2. Example Intrusion Subroutine
---------------------
//
// Inputs:
// ACL is the value derived from S12
// If ACL == 0, means this is first call
// otherwise, it is the ACL read from a previous call, representing loop current
// MINI is the value derived from SF6[7:6], representing minimum loop current required
// Valid Values:
// 0 - represents 10 mA
// 1 - 12
// 2 - 14
// 3 - 16
// DesiredDCL represents the desired delta current level, in milliamp units.
//
// Output:
// Returns the DCL value that is to be written into the register S11
//
int ActualDCL(int MINI, int ACL, int DesiredDCL)
{
int MinimumLoop;
//
// Translates MINI to a minimum loop current floor.
//
MinimumLoop = 10 + ( MINI << 1) ;
//
// Note that ACL==0 means that the up-coming call is expected to be the first call.
// The best guess is to set the DCL to DesiredDCL.
//
// There is a risk that on the first call, the intrusion may be missed if the
// DesiredDCL is large, and the loop current is low. However, the ACL for the next
// call will be set properly.
if (ACL == 0) return DesiredDCL;
//
// If the loop current is large enough, just use the desired DCL. Otherwise
// Adjust DCL based on the expected MinimumLoop conditions.
//
if ( (MinimumLoop + DesiredDCL) < ACL ) {
return DesiredDCL;
} else {
return (ACL - MinimumLoop);
}
//
// All cases should have been handled, and should never get here.
return ERROR;
}
AN94
72 Rev. 0.3
The very first sample of LCS the algorithm uses after
going off-hook does not have any previous samples for
comparison. If LCS was measured during a previous
call, this value of LCS may be used as an initial
reference. ACL may be written by the host with this
known value of LCS. If ACL is non-zero, the ISOmodem
chipset uses ACL as the first valid LCS sample in the
off-hook intrusion algorithm. If ACL is 0 (default after
reset), the ISOmodem chipset ignores the register and
does not begin operating the algorithm until two LCS
samples have been received. Additionally, immediately
after a modem call, ACL is updated automatically with
the last valid LCS value before a parallel phone
detection (PPD) intrusion or going back on-hook.
The off-hook intrusion algorithm does not begin to
operate immediately after going off-hook. This is to
avoid triggering an interrupt due to transients resulting
from the ISOmodem chipset itself going from on-hook to
off-hook. The time that elapses between the ISOmodem
chipset going off-hook and the intrusion algorithm
starting defaults to one second and may be adjusted via
the IST register (S82, bits 7:4). If ACL is written to a
non-zero value before going off-hook, a parallel phone
intrusion that occurs during this IST interval and
sustains through the end of the interval triggers an
interrupt.
The off-hook intrusion algorithm may additionally be
disabled for a period of time after dialing begins via the
IB register (S82, bits 2:1). This avoids triggering an
interrupt due to pulse dialing, open-switch intervals, or
line transients from central office switching. Intrusion
may be disabled from the start of dialing to the end of
dialing (IB = 01
b
), from the start of dialing to the timeout
of the IS (S29, bits 7:0) by setting IB = 10
b
(IB = 2) or
from the start of dial to carrier detect by setting IB = 11
b
.
The off-hook intrusion algorithm is only suspended (not
disabled) during this IB interval. Therefore, any intrusion
that occurs during the IB interval and sustains through
the end of the interval triggers a PPD interrupt.
4.8.3. Interrupt Detection
The INT interrupt pin can be programmed to alert the
host of loss-of-carrier, loss-of-phone-line voltage/
current, parallel phone detection, and other interrupts
listed in the interrupt status mask (S08). After the host
receives an interrupt via the INT pin, the host should
issue the AT:I command. This command causes a read-
clear of the WOR, PPD, NLD, RI, OCD, and REV bits of
the S09 register and raises (deactivates) the INT pin. All
the interrupt status bits in register S09 remain high after
being set until cleared by the AT:I command.
4.8.3.1. Loop Current Detection
In addition to monitoring parallel phone intrusion, it is
possible to monitor the loss of loop current. This feature
can be enabled by setting S08[4] (NLDM) = 1. This
feature is disabled by default. If the loop current is too
low for normal DAA operation, S09[4] (NLD) is set.
During this event, if the NLR result code is enabled by
setting S62[1](NLR) = 1, the l result code is sent. Once
the loop current returns to a normal current state, the L
result code is sent. The INT pin is also asserted if
enabled.
4.8.3.2. Loss-of-Carrier Detection
The Si2401 has two methods of implementing a loss-of-
carrier function. If GPIO4 is programmed as INT and if
S08[7](CDM) = 1, INT asserts in data mode when a
loss-of-carrier is detected. The carrier detect function
may also be implemented on GPIO2 by setting SE2[3:2]
(GPIO2) = 01 and SOC[7](CDE) = 1.
4.8.3.3. Overcurrent Detection
The Si2401 has an integrated overcurrent detection
feature. The Si2401 begins monitoring for an
overcurrent condition at a programmable time set by
S32 (OCDT) after going off-hook (default = 20 ms). If an
overcurrent condition is detected, the Si2401 sets
S09[1] interrupt status. As long as GPIO4 is
programmed as INT and the overcurrent mask bit is
enabled by setting S08[1](OCDM) = 1, INT asserts
during an overcurrent situation. The host may then
check S09[1] (OCD) via the AT:I command to confirm
that an overcurrent condition occurred.
4.8.3.3.1. Bug Summary
When an overcurrent event occurs, the Si2401 is
expected to snooze the event, much like pressing the
snooze button on an alarm clock. The Si2401 will take
action when the overcurrent event is reported four
times. In other words, it is a deglitch function, similar to
the concept we have for parallel phone intrusion events,
but in a much shorter time-base.
The action taken by the Si2401 is to set
ISTAT_OVERCURRENT status after four overcurrent
events (or whatever is set in register SAA). If the INT*
interrupt pin is enabled (SE2 = C0) and the overcurrent
interrupt is unmasked (S08 = 02), the host will get an
interrupt upon detection of this status. The host is then
expected to respond to the interrupt event by going
back on hook.
The problem is the first event expects the overcurrent
bit to be cleared by the toggling of OPE. Since the
toggling of the OPE is too fast for the Si3010, the
overcurrent bit is not cleared, and the code keeps
responding to the single event. In other words, only one
AN94
Rev. 0.3 73
overcurrent event is capable of causing the Si2401 to
report ISTAT_OVERCURRENT.
Therefore, there is a risk of false overcurrent event
reporting if the loop current is high and an open switch
interval event occurs.
The risk of a nuisance overcurrent detection is low since
most phone lines are in the neighborhood of 30 mA loop
current. There are many other mitigating factors.
4.8.3.3.2. Software Workaround
Set SAA = 00 if the effect of a nuisance OSI event is
worse than the risk of encountering a metallic
overcurrent event. As it is currently written, the Si2401
can pass a rather severe metallic off hook 600 Vrms
(1A) for one second. SAA (opthresh) disables the
overcurrent detection.
// Pseudo Code of Overcurrent Detection executed once every 6.67 msec
// Upon going off hook, the value in opthresh (SAA) is copied
// into opcnt (SCB).
// OPE and OPD is a representation of the DAA bits
//
if (OPD == 1 && OPE == 1 && opthresh != 0)
{
if (opcnt & 0x80) // MS-bit of opcnt is a 'flag'
{
// Case if MS-bit of opcnt is set ...
opcnt &= ~0x80 ; // clear opcnt msb
OPE = 0 ; // toggle OPE
OPE = 1 ; // !!!! BUG HERE !!!
OPD = 0 ; // clear OPD
} else {
// Case if MS-bit of opcnt is clear...
opcnt -= 1 ; // decrement opcnt

if (opcnt == 0) {
ISTAT_OVERCURRENT = 1 ;
} else {
opcnt |= 0x80 ; // This sets the flag
} // END if (opcnt == 0)
} // END if (opcnt & 0x80)
} // END if (OPD == 1 && OPE == 1 && opthresh != 0) //
AN94
74 Rev. 0.3
4.8.4. Caller ID Decoding Operation
The Si2401 supports full caller ID detection and decode
for US Bellcore and UK standards. To use the caller ID
decoding feature, the following configuration is
necessary:
1. Set SE0[3] (ND) = 0
b
(set modem to 8N1
configuration).
2. Set S0C[7:6] (CIDM) = 01 (set modem to Bellcore
type caller ID) or S13[2] (CIDB) = 1 (set modem to
UK type caller ID).
4.8.4.1. Caller ID Monitor/Bellcore Caller ID
The Si2401 continuously monitors the phone line for the
caller ID mark signals. This can be useful in systems
that require detection of caller ID data before the ring
signal, voice mail indicator signals, and Type II caller ID
monitor support. To force the Si2401 into caller ID
monitor mode, set SOC[6:5] (CIDM) = 11.
Note: CIDM should be disabled before going off-hook.
4.8.4.2. UK Caller ID Operation
The Si2401 starts searching for the Idle State Tone Alert
Signal. When this signal has been detected, the Si2401
transmits an a to the host. After the Idle State Tone
Alert Signal is completed, the Si2401 applies the
wetting pulse for the required 15 ms by quickly going
off-hook and on-hook. From this point on, the algorithm
is identical to that of Bellcore in that it searches for the
channel seizure signal and the marks before echoing an
m and then reports the decoded caller ID data.
4.8.5. V.23 Operation/V.23 Reversing
The Si2401 supports full V.23 operation including the
V.23 reversing procedure. V.23 operation is enabled by
setting S07 (MF1) = xx10x110
b
or xx01x110
b
. If
S07[5] (V23R) = 1
b
, the Si2401 transmits data at 75 bps
and receives data at 600 or 1200 bps. If
S07[4] (V23T) = 1
b
, the Si2401 receives data at 75 bps
and transmits data at 600 or 1200 bps. S07[2] (BAUD)
is the 1200 or 600 bps indicator. BAUD = 1b enables
the 1200/600 V.23 channel to run at 1200 bps, while
BAUD = 0
b
enables 600 bps operation.
When a V.23 connection is successfully established, the
modem responds with a c character if the connection
is made with the modem transmitting at 1200/600 bps
and receiving at 75 bps. The modem responds with a
v character if a V.23 connection is established with the
modem transmitting at 75 bps and receiving at 1200/
600 bps.
The Si2401 supports the V.23 turnaround procedure.
This allows a modem that is transmitting at 75 bps to
initiate a turnaround procedure so that it can begin
transmitting data at 1200/600 bps and receiving data at
75 bps. The modem is defined as being in V.23 master
mode if it is transmitting at 75 bps, and it is defined as
being in slave mode if the modem is transmitting at
1200/600 bps. The following paragraphs give a detailed
description of the V.23 turnaround procedure.
4.8.5.1. Modem in Master Mode
To perform a direct turnaround once a modem
connection is established, the master host goes into
online-command-mode by sending an escape
command (Escape pin activation, TIES, or ninth bit
escape) to the master modem.
Note: The host can initiate a turnaround only if the Si2401 is
the master.
The host then sends the ATRO command to the Si2401
to initiate a V.23 turnaround and return to the online
(data) mode.
The Si2401 then changes its carrier frequency (from
390 Hz to 1300 Hz) and waits to detect a 390 Hz carrier
for 440 ms. If the modem detects more than 40 ms of a
390 Hz carrier in a time window of 440 ms, it echoes the
c response character. If the modem does not detect
more than 40 ms of a 390 Hz carrier in a time window of
440 ms, it hangs up and echoes the N (no carrier)
character as a response.
4.8.5.2. Modem in Slave Mode
Configure GPIO4 as INT (SE2[7:6] [GPIO4] = 11
b
). The
Si2401 performs a reverse turnaround when it detects a
carrier drop longer than 20 ms. The Si2401 then
reverses (changes its carrier from 1300 Hz to 390 Hz)
and waits to detect a 1300 Hz carrier for 400 ms. If the
Si2401 detects more than 40 ms of a 1300 Hz carrier in
a time window of 400 ms, it sets the S09[7] bit, and the
next character echoed by the Si2401 is a v.
If the Si2401 does not detect more than 40 ms of the
1300 Hz carrier in a time window of 400 ms, it reverses
again and waits to detect a 390 Hz carrier for 440 ms.
Then, if the Si2401 detects more than 40 ms of a
390 Hz carrier in a time window of 220 ms, it sets the
S09[7] bit, and the next character echoed by the Si2401
is a c.
At this point, if the Si2401 does not detect more than
40 ms of the 390 Hz carrier in a time window of 440 ms,
it hangs up, sets the S09[7] bit, and the next character
echoed by the Si2401 is an N (no carrier).
Successful completion of a turnaround procedure in
master or slave mode automatically updates
S07[4] (V23T) and S07[5] (V23R) to indicate the new
status of the V.23 connection.
To avoid using the INT pin, the host may also be notified
of the INT condition by using 9-bit data mode. Setting
S15[0] (NBE) = 1
b
and S0C[3] (9BF) = 0
b
configures
the ninth bit on the Si2401 TXD path to function exactly
as the INT pin has been described.
AN94
Rev. 0.3 75
4.8.6. V.42 HDLC Mode
The Si2401 supports V.42 through hardware HDLC
framing in all modem data modes. Frame packing and
unpacking including opening and closing flag generation
and detection, CRC computation and checking, zero
insertion and deletion, and modem data transmission
and reception are all performed by the Si2401. V.42
error correction and V.42bis data compression must be
performed by the host.
The digital link interface in this mode uses the same
UART interface (8-bit data and 9-bit data formats) as in
the asynchronous modes, and the ninth data bit may be
used as an escape by setting S15[0] (NBE) = 1
b
. When
using HDLC in 9-bit data mode, if the ninth bit is not
used as an escape, it is ignored.
To use the HDLC feature on the Si2401, the host must
enable HDLC operation by setting S13[1] (HDEN) = 1
b
.
The host may initiate the call or answer the call using
either the ATDT#, the ATA command or the auto-
answer mode. (The auto-answer mode is implemented
by setting register S00 (NR) to a non-zero value.) When
the call is connected, a c, d, or a v is echoed to the
host controller. The host may now send/receive data
across the UART using either the 8-bit data or 9-bit data
formats with flow control.
At this point, the Si2401 begins framing data into the
HDLC format. On the transmit side, if no data is
available from the host, the HDLC flag pattern is sent
repeatedly. When data is available, the Si2401
computes the CRC code throughout the frame, and the
data is sent with the HDLC zero-bit insertion algorithm.
HDLC flow control operates in a similar manner to
normal asynchronous flow control across the UART and
is shown in Figure 15. To operate flow control (using the
CTS pin to indicate when the Si2401 is ready to accept
a character), a DTE rate higher than the line rate should
be selected. The method of transmitting HDLC frames
is as follows:
1. After the call is connected, the host should begin
sending the frame data to the Si2401 using the CTS
flow control to ensure data synchronicity.
2. When the frame is complete, the host should simply
stop sending data to the Si2401. Since the Si2401
does not yet recognize the end-of-frame, it expects
an extra byte and asserts CTS as shown in
Figure 15A. If CTS is used to cause a host interrupt,
this final interrupt should be ignored by the host.
3. When the Si2401 is ready to send the next byte, if it
has not yet received any data from the host, it
recognizes this as an end-of-frame, raises CTS,
calculates the final CRC code, transmits the code,
and begins transmitting stop flags.
4. After transmitting the first stop flag, the Si2401
lowers CTS indicating that it is ready to receive the
next frame from the host. At this point, the process
repeats as in Step 1.
The method of receiving HDLC frames is as follows:
1. After the call is connected, the Si2401 searches for
flag data. Then, once the first non-flag word is
detected, the CRC is continuously computed, and
the data is sent across the UART (8-bit data or 9-bit
data mode) to the host after removing the HDLC
zero-bit insertion. The DTE rate of the host must be
at least as high as that of data transmission. HDLC
mode only works with 8-bit data words; the ninth bit
is used only for escape on TXD and end-of-frame
received (EOFR) on RXD.
2. When the Si2401 detects the stop flag, it sends the
last data word in the frame as well as the two CRC
bytes and determines if the CRC checksum
matches. Thus, the last two bytes are not frame data
but are the CRC bytes, which can be discarded by
the host. If the checksum matches, the Si2401
echoes G (good). If the checksum does not match,
the Si2401 echoes e (error). Additionally, if the
Si2401 detects an abort (seven or more contiguous
ones), it echoes an A.
When the G, e, or A (referred to as a frame
result word) is sent, the Si2401 raises the EOFR
(end of frame receive) pin (see Figure 15B). The
GPIO1 pin must be configured as EOFR by setting
SE4[3] (GPE) = 1
b
. In addition to using the EOFR
pin to indicate that the byte is a frame result word, if
in 9-bit data mode (set S15[0] (NBE) = 1
b
), the ninth
bit is raised if the byte is a frame result word. To
program this mode, set S0C[3] (9BF) = 1
b
and
SE0[3] (ND) = 1
b
.
3. When the next frame of data is detected, EOFR is
lowered, and the process repeats at Step 1.
To summarize, when receiving HDLC frames, the host
begins receiving data asynchronously from the Si2401.
When each byte is received, the host should check the
EOFR pin (or the ninth bit). If the EOFR pin (or the ninth
bit) is low, the data is valid frame data. If the EOFR pin
(or the ninth bit) is high, the data is a frame result word.
AN94
76 Rev. 0.3
Figure 15. HDLC Timing
4.8.7. V.80 Synchronous Access Mode Interface
In addition to the V.42 HDLC interface in the previous
section, the Si2401 revision B implements V.80
synchronous access mode in-band commands (see
Table 2 on page 5). Please refer to the ITU-T
Specification V.80 for additional background
information. The main advantage of using the V.80
Synchronous Access Mode (SAM) Interface instead of
the V.42 HDLC interface is that there are no longer any
hardware dependencies associated with CTS, EOFR
timing.
The SC0, SC1, SC2 and SC3 registers are V80
configuration commands that are programmed by the
host prior to the ATDT command. Table 19 shows a
command summary. Also refer to documentation on
register SC0, SC1 and SC2.
ITC (in SC0) should be set according to how the host is
expected to implement flow control. For proper
operation of SAM, the DTE rate must be programmed to
be greater than the expected DCE rate. At the very
least, the baud rate must be 9600. Flow control in the
transmit control is mandatory for proper operation. Flow
control in the receive direction is optional.
To control flow in the transmit direction, the host is
expected to receive, and act on, signals from the
modem. The modem asserts/negates CTS (hardware
flow control) or inserts XON/XOFF (software flow
control) onto the receive data path based on how full the
transmit buffer is. The thresholds for flow-on/flow-off are
programmable through the SC1 and SC2 registers.
The Si2401 also supports flow control in the receive
direction. When receive flow control is activated, the
modem obeys signals originating from the host, whether
it be the assertion/negation of RTS, or the transmission
of XON/XOFF characters in the transmit path. Receive
flow control is not a requirement because the DTE rate
is expected to be greater than the DCE rate. When
enabling RTS hardware flow control (ITC=10), the host
is expected to program the GPIO1 as a digital input prior
to the ATDT command. RTS hardware flow control
becomes active only when there is an active connection
(after 'c' result code).
The ESA2 bit in the SC0 register determines whether or
not the Frame Check Sequence (FCS) is calculated and
transmitted, and whether or not the received frame CRC
checking is done. Most point-of-sale applications will
require ESA2 = 1.
The Si2401 supports both the Framed and Transparent
Sub-modes described in the V.80. V.80 requires that the
modem begin operating in the Transparent Submode
upon connection. The Si2401, through the TRANSP bit
in the SC3 register, allows the modem to enter the
Framed Submode directly without going through the
Transparent Sub-mode initially.
Finally, the ESOM and ESAM fields in register SC0
determine whether to enter V.80 SAM operation. The
ESOM describes operation of the modem if it is the
originating modem. The ESAM describes operation of
the modem as an answering modem. Note that ESOM/
ESAM must be cleared when the V.42 HDLC Mode is
enabled (S12[1] = 1).
Once a connection has been established, the Si2401
sends the respond code 'c' or 'd' to indicate the
connection speed. After the 'c' or 'd' result code, the
Si2401 sends an <19> <BE> <20> <20> sequence,
regardless of the actual DTE rate.
After the above connection sequence, the in-band
commands apply. Refer to Table 2. The goal of many of
B. Frame Receive
A. Frame Transmit
TXD
RXD
Start Stop Start
Host begins frame N
Frame N Start Start Stop
Host finished sending frame N Host begins frame N + 1
CTS
Frame N + 1
CRC Byte 2 Stop Stop Start Start Stop Receive Data
EOFR
(or bit 9)
Si2400 ready for byte 1 of frame N
Note: Figure not to scale.
(CTS used as normal flow control.)
Si2401 detects end of frame N.
Si2401 ready for byte 1
of frame N + 1.
CRC Byte 1 Frame Result Word
AN94
Rev. 0.3 77
the transparency commands is to ensure that the
following bytes are reserved for special purposes:
<19> can be used to represent EM
<99> can be used to represent EM
<11> can be used as DC1 (XON)
<13> can be used as DC3 (XOFF)
If the host implements EM-shielding properly, the above
bytes will appear at the Si2401-host interface, as the
special functions they represent.
Once a connection has been established, the Si2401
enters the Transparent Sub-mode or the Framed Sub-
mode based on the setting of the TRANSP bit in register
SC3. If the modem is in the transparent mode, the data
following the above connect sequence is received, while
0xFF are transmitted to the remote modem until the
host begins transmitting. At any time, the host can send
the <EM><B1> command to cause the modem to enter
the Framed Sub-mode. The Si2401 receiver then hunts
for HDLC flags responds with the <19><B2> when the
receiver detects an HDLC flag.
Once the connection has been established, if the
Si2401 enters the Framed Sub-mode, the receiver
hunts for HDLC flags and sends an <19><B1> once a
flag has been detected. The Si2401 transmits HDLC
flags to the remote modem until the host begins
transmitting.
When in the Framed Sub-mode, once the upper
threshold in SC1 is reached, the Si2401 begins to
transmit actual data, while at the same time, indicating a
flow-off status to the host. The host is expected to stop
transmission until the Si2401 sends a flow-on status.
The Si2401 then begins to transmit, and empties the
transmit FIFO. Once the transmit FIFO reaches the
threshold in SC2, the Si2401 sends the flow-on status to
the host. The host is expected to respond with data by
the time the last byte in the transmit FIFO has been
sent. To indicate an end of frame, the host sends the
<EM> <B1> command at the end of a frame.
The Si2401, upon receipt of the <EM> <B1> indicator,
appends the 16-bit FCS (frame check sequence,
assuming ESA2=1) and then sends HDLC flags to end
the frame.
In the receive path, if ESA2 = 1, the Si2401 looks for the
data frame in-between the HDLC flags. Once the
receive data has been received, the appended FCS is
compared against a running CRC calculation as a check
for the validity of the receive frame. A good frame
results in the Si2401 sending an <19> <B1> to the host,
while a bad frame is indicated by a <19> <B2> indicator.
Note that the transmitted frame check sequence is not
sent to the host.
The Si2401 can also send indicators for transmit
underrun, transmit overrun and receiver overrun
conditions. Host software must be modified to remove
these error conditions by obeying proper flow control
methods.
The host can send and escape command <EM> <BB>
or an escape/carrier terminate command <EM> <BA>.
In either case, the Si2401 transitions over to command
mode and terminates the transmit carrier (if <EM>
<BA>). The Si2401 is kept in the off hook condition until
an ATH command has been sent to the modem.
If the remote modem terminates the carrier, the Si2401
indicates this condition by sending the <19> <BA>
indicator, enters the command state, but will remain in
the off hook condition until an ATH command is
received.
Note that the Si2401 does not implement the same
syntax used by the V.80 standard to configure the
Si2401 Synchronous Access Mode. Instead of using
AT+ commands, the Si2401 uses S-registers. The
following AT+ commands are supported via S-register
settings:
+ESEnable/disable synchronous mode
+ESAConfigure the operation of synchronous mode
+IFCSpecifies the flow control to be implemented
+ITFConfigure the transmit flow thresholds
AN94
78 Rev. 0.3
Table 18. S-Register Example
AT+ command Si2401 equivalent Comments
AT+ES=6,8
AT+ESA=0,0,0,1,0,255
AT+IFC=0,2
ATSC0=15
SAM originate or answer
CRC16
CTS flow control
Single S-register write does all three AT+ com-
mands
AT+ITF=20,4 ATSC1=14SC2=04 Transmit Flow Control settings
no equivalent ATSC3=00 Upon connection, operate in Framed Submode.
Note V.80 always begins in Transparent Submode,
and provides no choice.
Table 19. Si2401 V80 HDLC Synchronous Access Mode Configuration Registers
S-Register Register
Address
(hex)
Name Function Reset
SC0 0xC0 V80C This is a bit mapped register.
0x00
SC1 0xC1 ITF1 Transmit flow control off threshold. Threshold, in bytes, above
which the modem will generate a flow off signal (maximum
threshold value of 20).
0x14
SC2 0xC2 ITF2 Transmit flow control on threshold. Threshold, in bytes, below
which the modem will generate a flow on signal. This value must
be less than ITF1.
0x04
SC3 0xC3 V80M This is a bit mapped register.
0x00
AN94
Rev. 0.3 79
4.8.8. Low Power Modes
The Si2401 has three low-power modes:
DSP Powerdown. The DSP processor can be
powered down by setting register
SEB[3] (PDDE) = 1.
In this mode, the serial interface still functions, and
the modem detects ringing and intrusion. However,
no modem modes or tone detection features
function.
Wake-Up-On-Ring. By issuing the ATz command,
the Si2401 goes into a low-power mode where both
the microcontroller and DSP are powered down.
Only an incoming ring, a low TXD signal, or a total
reset will power up the chip again. Return from
wake-on-ring triggers the INT pin if S09[6]
(WOR) = 1 (WOR = 0
b
by default).
Total Powerdown. Setting SF1[5] = 1 and SF1[6] = 1
places the Si2401 into a total powerdown mode. All
logic is powered down including the crystal oscillator
and clock-out pin. Only a hardware reset can restart
the Si2401.
4.8.9. Global Configuration
The Si2401 chipset contains an integrated silicon direct
access arrangement (silicon DAA) that provides a
programmable line interface to meet international
telephone line requirements. Table 20 on page 80 gives
the DAA register settings required to meet various
country PTT standards. A detailed description of the
registers in this table can be found in "DAA Operation"
on page 10.
There have been several recent changes to various
country requirements. This section summarizes these
changes. Check with your compliance laboratory to
verify whether countries now accepting TBR-21 still
accept their previous settings.
Countries now accepting TBR-21 include the following.
Egypt
Hungary
Slovakia
A recent change to TBR-21 drops the requirement for
loop current limiting. Table 20 on page 80 is configured
to enable current limiting. If you want to disable loop
current limiting, Change the setting for SF5(ILIM)[3] =
0b.
AN94
80 Rev. 0.3
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F
6
=
1
0
B
r
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
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6
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2
0
B
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a
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1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
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S
F
5
=
2
8
S
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6
=
2
3
C
a
n
a
d
a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
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5
=
0
0
S
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6
=
2
0
C
a
r
i
b
b
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a
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
C
h
i
l
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
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A
T
S
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5
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0
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C
h
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a

P
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p
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s

R
e
p
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b
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
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A
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S
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5
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6
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C
o
l
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0
0
0
0
0
0
0
0
0
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0
0
0
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C
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R
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c
a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
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2
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6
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2
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C
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a
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a
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
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2
3
A
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6
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2
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C
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E
U
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1
0
1
0
0
0
2
8
0
0
1
0
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0
1
1
2
3
A
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S
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5
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2
8
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6
=
2
3
C
z
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c
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R
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p
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b
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(
E
U
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1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
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6
=
2
3
D
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k

(
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U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
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5
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8
S
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6
=
2
3
D
o
m
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n
i
c
a
n

R
e
p
u
b
l
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c
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
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0
0
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6
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2
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D
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0
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0
0
0
0
0
0
0
0
1
0
0
0
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2
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S
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5
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6
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q
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1
0
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1
0
1
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2
8
0
0
1
0
0
0
1
1
2
3
A
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S
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5
=
2
8
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6
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3
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l

S
a
l
v
a
d
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r
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
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5
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0
0
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6
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2
0
E
s
t
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a

(
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U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
AN94
Rev. 0.3 81
F
i
n
l
a
n
d

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
F
r
a
n
c
e

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
G
e
o
r
g
i
a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
G
e
r
m
a
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y

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
G
r
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e
c
e

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
G
u
a
d
e
l
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1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
G
u
a
m
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
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2
0
A
T
S
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5
=
0
0
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6
=
2
0
H
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K
o
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g
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
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6
=
2
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H
u
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a
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(
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)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3

I
c
e
l
a
n
d

(
C
T
R
-
2
1
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
I
n
d
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a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
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S
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5
=
0
0
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6
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I
n
d
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s
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
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F
6
=
2
0
I
r
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l
a
n
d

(
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)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
I
s
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l
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
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6
=
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I
t
a
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(
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)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
J
a
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0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
9
0
A
T
S
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5
=
0
0
S
F
6
=
9
0
J
o
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d
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0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
9
0
A
T
S
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5
=
0
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S
F
6
=
9
0
K
a
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a
k
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s
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a
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0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
A
T
S
F
5
=
0
0
S
F
6
=
1
0
K
o
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a
0
0
0
1
0
0
0
4
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
4
S
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6
=
2
0
K
u
w
a
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
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5
=
0
0
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6
=
2
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K
y
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y
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
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6
=
2
0
L
a
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v
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a

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
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S
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5
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2
8
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6
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2
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L
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b
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1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
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=
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3

L
i
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c
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n
s
t
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n

(
C
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R
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2
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1
0
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2
8
0
0
1
0
0
0
1
1
2
3
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5
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2
8
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L
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(
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)
1
0
1
0
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0
2
8
0
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0
1
1
2
3
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5
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8
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2
3
L
u
x
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m
b
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u
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g

(
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1
0
1
0
0
0
2
8
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0
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0
1
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2
3
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0
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M
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(
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)
1
0
1
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2
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1
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2
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0
0
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0
0
0
1
1
2
3
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3
T
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b
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2
0
.

S
i
2
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0
1

C
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T
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(
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d
)
S
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2
4
0
1

R
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g
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s
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5
S
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S
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C
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1
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0
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D
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3
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C
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A
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C
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m
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s
t
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AN94
82 Rev. 0.3
M
e
x
i
c
o
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
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S
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6
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0
M
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d
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0
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0
0
0
0
0
0
0
0
1
0
0
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S
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5
=
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6
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M
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1
0
1
0
0
0
2
8
0
0
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0
0
0
1
1
2
3
A
T
S
F
5
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2
8
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6
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2
3
N
e
t
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l
a
n
d
s

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
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6
=
2
3
N
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Z
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a
l
a
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0
0
0
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0
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0
0
0
0
1
0
0
1
0
0
2
4
A
T
S
F
5
=
0
0
S
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6
=
2
4
N
i
g
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a
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
N
o
r
w
a
y

(
C
T
R
-
2
1
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
O
m
a
n
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
9
0
A
T
S
F
5
=
0
0
S
F
6
=
9
0
P
a
k
i
s
t
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n
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
9
0
A
T
S
F
5
=
0
0
S
F
6
=
9
0
P
a
r
a
g
u
a
y
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
P
e
r
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0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
P
h
i
l
i
p
p
i
n
e
s
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
9
0
A
T
S
F
5
=
0
0
S
F
6
=
9
0
P
o
l
a
n
d

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
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S
F
5
=
2
8
S
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6
=
2
3
P
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s
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a

(
F
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c
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)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
P
o
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g
a
l

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
P
u
e
r
t
o

R
i
c
o
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
Q
a
t
a
r
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
9
0
A
T
S
F
5
=
0
0
S
F
6
=
9
0
R
e
u
n
i
o
n
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
R
o
m
a
n
i
a
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
R
u
s
s
i
a
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
A
T
S
F
5
=
0
0
S
F
6
=
1
0
S
a
u
d
i

A
r
a
b
i
a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
S
i
n
g
a
p
o
r
e
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
S
l
o
v
a
k
i
a

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
S
l
o
v
e
n
i
a

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
S
o
u
t
h

A
f
r
i
c
a
0
0
0
1
0
0
0
4
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
0
4
S
F
6
=
2
3
S
p
a
i
n

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
S
r
i

L
a
n
k
a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
S
w
e
d
e
n

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3

S
w
i
t
z
e
r
l
a
n
d

(
C
T
R
-
2
1
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
S
y
r
i
a
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
9
0
A
T
S
F
5
=
0
0
S
F
6
=
9
0
T
a
b
l
e

2
0
.

S
i
2
4
0
1

C
o
u
n
t
r
y

T
a
b
l
e


(
C
o
n
t
i
n
u
e
d
)
S
i
2
4
0
1

R
e
g
i
s
t
e
r
S
F
5
S
F
5
S
F
6
S
F
6
C
o
u
n
t
r
y
O
H
S
2
O
H
S
I
L
I
M
R
Z
R
T
2
R
T
C
o
m
b
i
n
e
d
M
I
N
I
[
1
:
0
]
D
C
V
[
1
:
0
]
A
C
I
M
[
3
:
0
]
C
o
m
b
i
n
e
d
A
T

C
o
m
m
a
n
d

s
t
r
i
n
g
AN94
Rev. 0.3 83
T
a
i
w
a
n
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
T
h
a
i
l
a
n
d
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
A
T
S
F
5
=
0
0
S
F
6
=
1
0
T
u
n
i
s
i
a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
T
u
r
k
e
y
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
U
A
E
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
U
k
r
a
i
n
e
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
U
n
i
t
e
d

K
i
n
g
d
o
m

(
E
U
)
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
U
r
u
g
u
a
y
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
U
S
A
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
U
z
b
e
k
i
s
t
a
n
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
V
e
n
e
z
u
e
l
a
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
Y
e
m
e
n
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
A
T
S
F
5
=
0
0
S
F
6
=
2
0
Z
a
m
b
i
a
1
0
1
0
0
0
2
8
0
0
1
0
0
0
1
1
2
3
A
T
S
F
5
=
2
8
S
F
6
=
2
3
T
a
b
l
e

2
0
.

S
i
2
4
0
1

C
o
u
n
t
r
y

T
a
b
l
e


(
C
o
n
t
i
n
u
e
d
)
S
i
2
4
0
1

R
e
g
i
s
t
e
r
S
F
5
S
F
5
S
F
6
S
F
6
C
o
u
n
t
r
y
O
H
S
2
O
H
S
I
L
I
M
R
Z
R
T
2
R
T
C
o
m
b
i
n
e
d
M
I
N
I
[
1
:
0
]
D
C
V
[
1
:
0
]
A
C
I
M
[
3
:
0
]
C
o
m
b
i
n
e
d
A
T

C
o
m
m
a
n
d

s
t
r
i
n
g
AN94
84 Rev. 0.3
Table 21. Countries Grouped by Common AT
Commands
AT Command string Country
ATSF5=00SF6=20 Argentina
Canada
Chile
Colombia
El Salvador
Guam
Hong Kong
India
Indonesia
Kuwait
Macao
Mexico
Peru
Saudi Arabia
Singapore
Taiwan
UAE
USA
Yemen
Armenia
Bahamas
Belarus
Bermuda
Brunei
Caribbean
ChinaPeople's Republic
Costa Rica
Dominican Republic
Dubai
Equador
Georgia
Kyrgyzstan
Moldova
Paraguay
Puerto Rico
Sri Lanka
Tunisia
Ukraine
Uruguay
Uzbekistan
Venezuela
ATSF5=00SF6=90 Japan
Jordan
Oman
Pakistan
Syria
Malaysia
Philippines
Qatar
ATSF5=00SF6=24 New Zealand
ATSF5=04SF6=20 Korea
ATSF5=28SF6=23 Bahrain
Bulgaria
Croatia
Egypt
Israel
Lebanon
Morocco
Nigeria
Romania
Algeria
Austria (EU)
Belgium (EU)
Cyprus (EU)
Czech Republic (EU)
Denmark (EU)
Estonia (EU)
Finland (EU)
France (EU)
Germany (EU)
Greece (EU)
Guadeloupe
Hungary (EU)
Iceland (CTR-21)
Ireland (EU)
Italy (EU)
Latvia (EU)
Liechtenstein (CTR-21)
Lithuania (EU)
Table 21. Countries Grouped by Common AT
Commands (Continued)
AT Command string Country
AN94
Rev. 0.3 85
Luxembourg (EU)
Malta (EU)
Martinique
Netherlands (EU)
Norway (CTR-21)
Poland (EU)
Polynesia (French)
Portugal (EU)
Reunion
Slovakia (EU)
Slovenia EU)
Spain (EU)
Sweden (EU)
Switzerland (CTR-21)
Turkey
United Kingdom (EU)
Zambia
ATSF5=10SF6=93 Australia
ATSF5=00SF6=10 Brazil
Kazakhstan
Russia
Thailand
ATSF5=04SF6=23 South Africa
Table 21. Countries Grouped by Common AT
Commands (Continued)
AT Command string Country
AN94
86 Rev. 0.3
Table 22. Si2401 Global Ringer and Busy Tone Cadence Settings
Country RTON RTOF RTOD BTON BTOF BTOD
S19 S1A S1B S16 S17 S18
Australia 0x07 0x03 0x01 0x25 0x25 0x04
Austria 0x12 0x5D 0x0A 0x1E 0x1E 0x03
Belgium 0x12 0x38 0x06 0x32 0x32 0x05
Brazil 0x12 0x4B 0x08 0x19 0x19 0x03
Bulgaria 0x12 0x4B 0x08 0x14 0x32 0x05
China 0x12 0x4B 0x08 0x23 0x23 0x04
Cyprus 0x1C 0x38 0x06 0x32 0x32 0x05
Czech Republic 0x12 0x4B 0x08 0x18 0x24 0x0A
Denmark 0x0E 0x8C 0x0F 0x19 0x19 0x03
Finland 0x0E 0x5D 0x0A 0x1E 0x1E 0x03
France 0x1C 0x41 0x07 0x32 0x32 0x05
Germany 0x12 0x4B 0x08 0x32 0x32 0x05
Great Britain 0x07 0x03 0x01 0x25 0x25 0x04
Greece 0x12 0x4B 0x08 0x1E 0x1E 0x03
Hong Kong, New Zealand 0x07 0x03 0x01 0x32 0x32 0x05
Hungary 0x17 0x46 0x0F 0x1E 0x1E 0x03
Iceland 0x16 0x58 0x09 0x19 0x19 0x03
India 0x07 0x03 0x01 0x4B 0x4B 0x08
Ireland 0x07 0x03 0x01 0x32 0x32 0x05
Italy, Netherlands, Norway, Thailand,
Switzerland, Israel
0x12 0x4B 0x08 0x32 0x32 0x05
Japan, Korea 0x12 0x25 0x04 0x32 0x32 0x05
Luxembourg 0x12 0x4B 0x08 0x30 0x30 0x05
Malaysia 0x07 0x03 0x01 0x23 0x41 0x07
Malta 0x00 0x00 0x00 0x00 0x00 0x00
Mexico 0x12 0x4B 0x08 0x19 0x19 0x03
Poland 0x12 0x4B 0x10 0x32 0x32 0x05
Portugal 0x12 0x5D 0x0A 0x32 0x32 0x05
Singapore 0x07 0x03 0x01 0x4B 0x4B 0x08
Spain 0x1C 0x38 0x06 0x14 0x14 0x02
Sweden 0x12 0x5D 0x0A 0x19 0x19 0x03
Taiwan 0x12 0x25 0x04 0x32 0x32 0x05
U.S., Canada (default) 0x25 0x4B 0x08 0x32 0x32 0x05
AN94
Rev. 0.3 87
5. Si2401 Testing
Set SAA=00 prior to going off-hook with ATH1 to
measure DCI curves.
5.1. CTR-21 Test Instructions
Section B: TEST MODES AND LEVELS
B.1
Please indicate the method for allowing the TE to loop
the line and draw direct current without transmitting
signals of any description:
ATSF6=33SF5=08
ATS07=46DT;
B.2
Please detail the method to enable pseudo random data
to be transmitted to line indefinitely in the absence of
carrier or other signals from the remote end: (The TE
should be capable of being placed in its 'Originate'
signal state, with random modulation on the Originate
carrier and of being placed in its 'Answer' carrier
modulated by random data)
ATSF6=23SF5=08 must be sent prior to the PTT Test
Scripts shown below. The specific script to send is
dependent on which protocol is desired.
V.21 answer
ATS07=43S33=01S94=00S95=00SE8=04SE5=01SF0
=01S83=0B
V.21 originate
ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF0
=01S83=0B
ATS07=43S33=01S94=00S95=00SE8=04SE5=09SF0
=01S83=0B
Bell103 answer
ATS07=41S33=01S94=00S95=00SE8=04SE5=03SF0
=01S83=0B
Bell103 originate
ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF0
=01S83=0B
ATS07=41S33=01S94=00S95=00SE8=04SE5=0BSF0
=01S83=0B
V.22 answer
ATS07=42S33=01S94=00S95=01SE8=05SE5=01SF0
=01S83=0B
V.22 answer w/ 1800 Hz Guard Tone
ATS07=42S33=01S94=00S95=01SE8=05SE5=11SF0=
01S83=0B
V.22 answer w/ 550 Hz Guard Tone
ATS07=42S33=01S94=00S95=01SE8=05SE5=21SF0
=01S83=0B
V.22 originate
ATS07=42S33=01S94=00S95=01SE8=05SE5=09SF0
=01S83=0B
Bell212a answer
ATS07=40S33=01S94=00S95=01SE8=05SE5=01SF0
=01S83=0B
Bell212a originate
ATS07=40S33=01S94=00S95=01SE8=05SE5=09SF0
=01S83=0B
V.22bis answer
ATS07=46S33=01S94=00S95=07SE8=05SE5=05SF0
=01S83=0B
V.22bis answer w/ 1800 Hz Guard Tone
ATS07=46S33=01S94=00S95=07SE8=05SE5=15SF0
=01S83=0B
V.22bis answer w/ 550 Hz Guard Tone
ATS07=46S33=01S94=00S95=07SE8=05SE5=25SF0
=01S83=0B
V.22bis originate
ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF0
=01S83=0B
V.23 1200 bps transmit
ATS07=54S33=01S94=00S95=01SE8=04SE5=1DSF0
=01S83=0B
V.23 75 bps transmit
ATS07=64S33=01S94=00S95=00SE8=04SE5=05SF0
=01S83=0B
AN94
88 Rev. 0.3
V.23 600 bps transmit
ATS07=50S33=01S94=00S95=00SE8=04SE5=0DSF0
=01S83=0B
B.3
For MF testing purposes, a continuous digit '9' is
required. Please indicate below the method of obtaining
this:
ATSF6=23SF5=08
ATS07=46DT;
ATSE8=02SE6=00SE5=49
B.4
If the TE is capable of voice recording, please indicate
the method for the apparatus to seize and indefinitely
hold the line in recording and announcement modes
without speech or tone transmissions to line.
ATSF6=23SF5=08
ATS07=46
ATDT;
B.5
Please indicate the method of disabling any dial tone
detection:
ATSF6=23SF5=08
ATS07=46
ATDT####
5.2. FCC68 Test Instructions
Section B: TEST MODES AND LEVELS
B.1
Please indicate the method for allowing the TE to loop
the line and draw direct current without transmitting
signals of any description:
apply reset to the Si2401
ATS07=46DT;
B.2
Please detail the method to enable pseudo random data
to be transmitted to line indefinitely in the absence of
carrier or other signals from the remote end: (The TE
should be capable of being placed in its 'Originate'
signal state, with random modulation on the Originate
carrier and of being placed in its 'Answer' carrier
modulated by random data)
Reset to the Si2401 must be applied prior to the PTT
Test Scripts shown below. The specific script to send is
dependent on which protocol is desired.
V.21 answer
ATS07=43S33=01S94=00S95=00SE8=04SE5=01SF7
=00SF0=01S83=0B
V.21 originate
ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF7
=00SF0=01S83=0B
ATS07=43S33=01S94=00S95=00SE8=04SE5=09SF7
=00SF0=01S83=0B
Bell103 answer
ATS07=41S33=01S94=00S95=00SE8=04SE5=03SF7
=00SF0=01S83=0B
Bell103 originate
ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF7
=00SF0=01S83=0B
ATS07=41S33=01S94=00S95=00SE8=04SE5=0BSF7
=00SF0=01S83=0B
V.22 answer
ATS07=42S33=01S94=00S95=01SE8=05SE5=01SF7
=00SF0=01S83=0B
V.22 originate
ATS07=42S33=01S94=00S95=01SE8=05SE5=09SF7
=00SF0=01S83=0B
Bell212a answer
ATS07=40S33=01S94=00S95=01SE8=05SE5=01SF7
=00SF0=01S83=0B
Bell212a originate
ATS07=40S33=01S94=00S95=01SE8=05SE5=09SF7
=00SF0=01S83=0B
V.22bis answer
ATS07=46S33=01S94=00S95=07SE8=05SE5=05SF7
AN94
Rev. 0.3 89
=00SF0=01S83=0B
V.22bis originate
ATS07=46S33=01S94=00S95=07SE8=05SE5=0DSF7
=00SF0=01S83=0B
V.23 1200 bps transmit
ATS07=54S33=01S94=00S95=01SE8=04SE5=1DSF7
=00SF0=01S83=0B
V.23 75 bps transmit
ATS07=64S33=01S94=00S95=00SE8=04SE5=05SF7
=00SF0=01S83=0B
V.23 600 bps transmit
ATS07=50S33=01S94=00S95=00SE8=04SE5=0DSF7
=00SF0=01S83=0B
B.3
For MF testing purposes, a continuous digit '9' is
required. Please indicate below the method of obtaining
this:
apply reset to the Si2401
ATS07=46DT;
ATSE8=02SE6=00SE5=49
B.4
If the TE is capable of voice recording, please indicate
the method for the apparatus to seize and indefinitely
hold the line in recording and announcement modes
without speech or tone transmissions to line.
apply reset to the Si2401
ATS07=46
ATDT;
B.5
Please indicate the method of disabling any dial tone
detection:
apply reset to the Si2401
ATS07=46
ATDT####;
5.3. In-Circuit Testing
The Si2401s advanced design provides the system
manufacturer with increased ability to determine system
functionality during production line test as well as
support for end-user diagnostics.
There are many methods to check to discover whether
the link between the Si2401 and Si3010 is operational.
These tests do not require any loop current on the DAA.
The first method is to check SF2[3] (FDT). If it is set, the
Si2401 and the Si3010 are communicating. Another
method is to read SF8[7:4] (LRV) to verify that the
Si3010 is properly sending its version number back to
the Si2401. Finally, the voltage between the Si3010
VREG pin and the IGND pin may be measured and
should be approximately 2.3 V.
Once the clock, UART, and isolation links are proven
functional, the production test can proceed to verify
operation of the discrete components mounted on the
board. In general, there are two approaches to the
production line test. The first approach is to execute
complete modem connections through a commercially-
available telephone line simulator. This approach is
simple to implement but incurs a relatively long per-unit
test time. If per-unit test time is an important
consideration, another approach is to use the internal
tone generator on the Si2401 to generate a tone at TIP/
RING. The Si3010 can be programmed to disable the
hybrid (clearing SF1[2] [HBE]), thereby, allowing the
transmitted signal to be looped back through the receive
path. The Si2401 receives the loopback tone and
should be programmed to drive the tone to AOUT. This
approach requires loop current consistent with the
equivalent circuit shown in Figure 16.
Note: AOUT is a PWM signal and requires additional circuitry
to arrive at an analog waveform.
As an example, the following strings can be sent to the
Si2401 to set up the 2225 Hz answer tone as the
stimulus waveform.
1. ATE0SF1=08SF0=41 to go off-hook and to disable
transmit hybrid
2. ATM2SF4=03 to drive AOUT with the received
loopback tone from the line.
3. ATSE8=00SE6=00SE5=0BSE8=01SE6=08SE5=FCS
E8=00 to set the tone amplitude to 12 dBm.
4. ATSE8=02SE5=04SE6=02 to begin the 2225 Hz
answer tone.
With the above strings, a number of points can be
probed to determine if the DAA is functioning properly.
Assuming a 30 mA loop current, the dc value of the TIP/
RING voltage should be in the neighborhood of 7.5 V.
The actual voltage is dependent on the chosen dc
termination.
AN94
90 Rev. 0.3
When the hybrid is disabled, an internal dc offset is
realized. The size of this dc offset is approximately half
scale. To guarantee no clipping under all conditions, a
12 dBm maximum transmit level is recommended. If a
slightly distorted signal is acceptable on AOUT, a signal
exceeding 12 dBm may be implemented instead using
the method shown previously in step 3.
To complete the production test, it may be necessary to
simulate a ring signal. A sine wave pulse of 500 ms with
a 20 Hz frequency and an amplitude of 35 V
RMS
is
sufficient for the Si2401 to return an R result code.
Additional production tests may be employed to check
the DAA. For example, a 300 V dc test between TIP and
RING can be used to ensure that the hookswitch
transistors are operational and are not leaking any
significant amount of current. Also, a HIPOT (High
Potential, such as 1500 V) test applied longitudinally
between TIP/RING and GND can be used to ensure
that the isolation barrier is not bridged inadvertently.
5.4. Board Test
Figure 16. Loop Test Circuit
The modem and DAA chips come from Silicon
Laboratories 100% functionally tested on automatic test
equipment to guarantee compliance with the published
chip specifications. The functionality of a finished
product containing an ISOmodem chipset depends on
not only the functionality of the modem chipset after
assembly but also discrete parts and product-related
software. Therefore, finished product test requirements
and procedures depend on the manufacturer and the
product. Consequently, no universal final test procedure
can be defined.
Testing the modem in a finished product is done for
several reasons. First, it is important to be sure the
modem chipset and peripheral components were
installed correctly during assembly and were not
damaged. Second, it is necessary to be sure the correct
component values were installed and that there are no
manufacturing problems, such as solder bridges, cold
solder joints, or missing components.
Functional testing can be used to test special features,
such as intrusion detection, caller ID, and overcurrent
detection. An intrusion can be simulated by placing a
1 kO resistor across TIP and RING through a relay.
Caller ID testing requires special test equipment, such
as the Advent AI-150.
Many manufacturers choose to use built-in self-test
features, such as the test described above. Others do a
complete functional test of the modem by originating
and answering a call and successfully passing a data
file in each direction. This process tests the modem and
line-side chip functionality, the associated external
components, and the software controlling the modem.
This test can be done with a modem under test (MUT)
and a known-good reference modem or between two
modems under test. Testing two modems under test at
once reduces test and setup time. Modem operational
testing is time consuming and adds to product cost. It is
up to the manufacturer to determine whether
operational testing is warranted.
Analog modems (Bell 103 through V.34) can be tested
by connecting the modems through a telephone line
simulator, such as Teltone TLS-3. A call can be placed
or received in either direction at the speed set in the
modems. A test script must be written for a computer to
control the dialing, monitor the call progress, send a file,
and compare the received and sent file. Figure 17
illustrates this test configuration.
Figure 17. Bell 103V.34 Modem Functional
Test Connection
I
L
10 F
600 O
TIP
+

RING
V
TR
Si3010
>20 mA
Teltone TLS 3
Modem Under
Test
Reference Modem
Test
Computer
AN94
Rev. 0.3 91
6. UL1950 3rd Edition
The Si2401 reference design complies with global
safety standards including the EN60950, UL1950 3rd
Edition and UL60950 as long as layout guidelines are
met.
Safety compliance for the United States may require
additional power cross tests. However, exemption from
all power cross testing can be achieved if the system is
shipped with a 26 AWG phone cord, user
documentation is clear, internal DAA spacing
requirements are met, and the system enclosure can be
classified as a fire enclosure. Consultation with a safety
compliance expert early in the product design cycle is
recommended to ensure that this option is available.
If compliance is to be accomplished through actual
power cross testing, an additional fuse (Teccor F1250T
or equivalent) or PTC (Raychem TR600-150) is
recommended. See circuit in Figure 18 for placement.

Figure 18. Fuse/PTC placement
RV1
Fuse/PTC
TIP
RING
1.25 A
D
A
A

B
O
M
AN94
92 Rev. 0.3
APPENDIX AISOMODEM

LAYOUT GUIDELINES
Layout Guidelines
The key to a good layout is proper placement of
components. It is best to copy the placement shown in
Figure 19. Alternatively, perform the following steps,
referring to the schematics and Figure 20. It is strongly
recommended that the checklist in Table 22 be
completed while reviewing the final layout.
1. All traces, open pad sites and vias connected to the
following components are considered to be in the
DAA section, and must be physically separated from
non-DAA circuits by 5 mm to achieve best possible
surge performance: R1, R2, R3, R4, R5, R6, R7, R8,
R9, R10, R11, R15, R16, U2, Z1, D1, FB1, FB2,
RJ11, Q1, Q2, Q3, Q4, Q5, C3, C4, C5, C6, C7, C8,
C9, C10, RV1, C1 pin 2 only, C2 pin 2 only, C8 pin 2
only, C9 pin 2 only.
2. The Isolation Capacitors C1, C2, C8 and C9 are the
only components permitted to straddle between the
DAA section and non-DAA section components and
traces. This means that for each of these capacitors,
one of the terminals is on the DAA-side, the other is
not. Maximize the spacing between the terminals
(between pin 1 to pin 2) of each of these capacitors.
3. Place and group the following components: U1, U2,
R12, R13, C1, C2.
a.U1 and U2 are placed so that the right side of U1
faces the left side of U2.
b.C1 and C2 should be placed directly between U1
and U2.
c.Keep R12 and R13 close to U1.
d.Place U1, U2, C1, and C2 so that the
recommended minimum creepage spacing for
the target application is implemented.
e.Place C1 and C2 so that traces connected to U2
pin 5 (C1B) and U2 pin 6 (C2B) are physically
separated from traces connected to:
i.C8, R15, FB1
ii.C9, R16, FB2
iii.U2 pin 8, R7
iv.U2 pin 9, R9
4. Place and group the following components around
U2: C4, R9, C7, R2, C5, C6, R7, R8. These
components should form the critical 'inner circle' of
components around U2.
a.Place C4 close to U2 pin 3. This is best achieved
by placing C4 northwest of U2.
b.Place R9 close to U2 pin 4. This is best achieved
by placing R9 horizontally, directly to the north of
U2.
c.Place C7 close to U2 pin 15. This is best
achieved by placing C7 next to R9.
d.Place R2 next to U2 pin 16. This is best achieved
by placing R2 northeast of U2.
e.Place C6 close to U2 pin 10. This is best
achieved by placing C6 southeast of U2.
f.Place R7 and R8 close to U2. This is best
achieved by placing these components to the
south of U2.
g.Place C5 close to U2 pin 7. This is best achieved
by placing C5 southwest of U2.
5. Place Q5 next to R2 so that the base of Q5 can be
connected to R2 directly.
6. Place Q4 such that the base of Q4 can be routed to
U2 pin 13 easily, and that the emitter of Q4 can be
routed to U2 pin 12 easily. Route these two traces
next to each other so that the loop area formed by
these two traces are minimized.
7. Place and group the following components around
the RJ11 jack: FB1, FB2, RV1, R15, R16, C8 and
C9.
a.Use 20 mil width traces on this grouping to
minimize impedance.
b.Place C8 and C9 close to the RJ11 jack,
recognizing that, a GND trace will be routed
between C8 and C9, back the Si2401GND pin,
through a 20-mil width trace. The GND trace from
C8 and C9 must be isolated from the rest of the
Si3010 traces.
c.The trace from C8 to GND and the trace from C9
to GND must be short and equidistant.
8. After the previous step, there should be some space
between the grouping around U2 and the grouping
of components around the RJ11 jack. Place the rest
of the components in this area, given the following
guidelines:
a.Space U2, Q4, Q5, R1, R3, R4, R10 and R11
away from each other for best thermal
performance.
b.The tightest layout can be achieved by grouping
R6, C10, Q2, R3, R5 and Q1.
c.Place C3 next to D1.
d.Make the size of the Q3, Q4, and Q5 collector
AN94
Rev. 0.3 93
pads each large enough for the transistor to
safely dissipate 0.5 W under worst case
conditions. See the transistor data sheet for
thermal resistance and maximum operating
temperature information. Implement collector
pads on solder side as well and use vias between
the component and solder side pads to improve
heat transfer for best performance.
9. U2 pin 15 is also known as IGND. This is the ground
return path for many of the discrete components,
and requires special mention
a.Route traces associated with IGND using 20 mil
traces.
b.The area underneath U2 should be ground-filled
and connected to IGND (U2 pin 15). Ground fill
both solder side and component side and stitch
together using vias.
c.C5, C6, C7 IGND return path should be direct.
d.The IGND plane must not extend past Q4 and
Q5.
10.The traces from R7 to FB1 and from R8 to FB2
should be well matched. This can be achieved by
routing these traces next to each other as possible.
Ensure that these traces are not routed close to the
traces connected to C1 or C2.
11. Minimize all traces associated with Y1, C40, and
C41.
12.Decoupling capacitors (size 0.22 F and 0.1 F
capacitors connected to V
A
, V
D
) must be placed next
to those pins. Traces of these decoupling capacitors
back to the Si2401 GND pin should be direct and
short.
Figure 19. Reference Placement
AN94
94 Rev. 0.3
Figure 20. Illustrated Layout Guidelines
G N I R
P I T
A 4
B 4
C 4
D 4
E 4
F 4
G 4
F 4
5
6
A 3
E 3 C 3
B 3
A 3
E 3
E 3
E 3 E 3
A 7
C 7 C 7 B 7 B 7 B 7
A 9
0 1
0 1
1 1
2 1
2 1
2 1
1 1
C 8
D 8
D 8
B 9
C 9
C 9
C 9
1 1
2
2
2 2
a t o n s i s i h T t n e n o p m o c l a c i t i r c y l n O . c i t a m e h c s e t e l p m o c . n w a r d e r a s t e n d n a t n e m e c a l p
1
, s e c a r T s a i v d n a s e t i s d a p
d e s o l c n e A A D e h t n i e r a x o b n i
, n o i t c e s d e t a r a p e s e b t s u m d n a
l l a m o r f . m m 5 y b s t i u c r i c r e h t o
e h t n i d e b i r c s e d e r a s e c n e r e f e r d e l c r i c n E : e t o N d e r e b m u n . A x i d n e p p A n i s h p a r g a r a p
9 R
8 R
9 C
2 B F
1 4 C
1 V R
2 1 R
+ -
1 D
7 R
6 1 R
1 C
5 C
8 C
0 5 C
1 Y
1 2
1 0 4 2 i S 1 U
I L A T X
1
O L A T X
2
D V
4
D N G
12
A 1 C
0 1
A 2 C
9
A V
13
0 1 0 3 i S 2 U
E Q
1
T C D
2
X R
3
B I
4
B 1 C
5
B 2 C
6
G E R V
7
1 G N R
8
2 T C D
6 1
D N G I
5 1
3 T C D
4 1
B Q
3 1
2 E Q
2 1
C S
1 1
2 G E R V
0 1
2 G N R
9
5 1 R
0 4 C
5 Q
2 R
2 C
7 C
4 Q
+
4 C
6 C
1 B F
1 5 C
3 1 R
3 C
AN94
Rev. 0.3 95
Si2401 Layout Check List
Figure 23 is a checklist that the designer can use during the layout process to ensure all the recommendations in
this application note have been implemented.
Table 23. Si2401 Layout Check List
# Layout Items Required
1 U1 and U2 are placed so that pins 916 of U1 are facing pins 18 of U2. C1 and C2 are
placed directly between U1 and U2.
2
Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the
target application is implemented. R12 and R13 should be close to U1.
3
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be
used to connect C1 and C2 to U1 and U2. These traces should never be longer than two
inches and should be minimized in length. Place C2 such that its accompanying trace to
the C2B pin (pin 6) on the Si3010 is not close to the trace from R7 to the RNG1 pin on
the Si3010 (pin 8).
4 Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9),
ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor. In
order to space the R7 component further from the trace from C2 to the C2B pin, it is
acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).
5
The area of the loop from C50 to U1 pin 4 and from C51 to pin 13 back to pin 12 (DGND)
should be minimized. The return traces to U2 pin 12 (DGND) should be on the compo-
nent side.
6 The loop formed by XTALI, Y1, and XTALO should be minimized and routed on one
layer. The loop formed by Y1, C40, and C41 should be minimized and routed on one
layer.
7
The digital ground plane is made as small as possible, and the ground plane has
rounded corners.
8 Series resistors on clock signals are placed near source.
9
Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width
traces for IGND.
10 C3 should be placed across the diode bridge, and the area of the loop formed from
Si3010 pin 11 through C3 to the diode bridge and back to Si3010 pin 15 should be mini-
mized.
11
FB1, FB2, and RV1 should be placed as close as possible to the RJ11.
12
C8 and C9 should be placed so that there is a minimal distance between the nodes
where they connect to chassis ground.
13 Use a minimum of 20 mil wide trace from RJ11 to FB1, FB2, RV1, C8, C9, and F1.
14
The routing from TIP and RING of the RJ11 through F1 to the ferrite beads should be
well matched.
15
The traces from the RJ11 through R7 and R8 to U2 pin 8 and pin 9 should be well
matched. These traces may be up to 10 cm long.
AN94
96 Rev. 0.3
16
Distance from TIP and RING through EMC capacitors C8 and C9 to chassis ground is
short.
17
There should be no digital ground plane in the DAA Section.
18 Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those
components to U2 pin 15 (IGND).
19
R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should be
less than 20 mm.
20
Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
21 The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the
emitter of Q4 should be minimized.
22
The trace from C7 to U2 pin 15 should be short and direct.
23
The trace from C3 to the D1/D2 node should be short and direct.
24 Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a
guideline for small form factor applications) from any TNV component, pad or trace to
any SELV component, pad or trace.
25
Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15.
26
Cathode marking for Z1.
27 Pin 1 marking for U1 and U2.
28
Space and mounting holes to accommodate for fire enclosure if necessary.
29
IGND plane does not extend under C3, D1, FB1, FB2, R15, R16, C8, C9, or RV1.
30 Size Q3, Q4, and Q5 collector pads to safely dissipate 0.5 W (see text).
31
Submit layout to Silicon Laboratories for review.
Table 23. Si2401 Layout Check List (Continued)
# Layout Items Required
AN94
Rev. 0.3 97
Module Design and Application
Considerations
Modem modules are more susceptible to radiated fields
and ESD discharges than modems routed directly on
the motherboard because the module ground plane is
discontinuous and elevated above the motherboard
ground plane. This separation also creates the
possibility of loops that couple these interfering signals
to the modem. Additionally, system designers can
adversely impact the ESD and EMI immunity and
performance of a properly-designed module with a poor
motherboard layout.
Module Design
Particular attention should be paid to power supply
bypassing and reset line filtering when designing a
modem module. Trace routing is normally very short on
modules since they are generally designed to be as
small as possible. Care should be taken to use ground
and power planes in the low-voltage circuitry whenever
possible and to minimize the number of vias in the
ground and power traces. Ground and power should
each be connected to the motherboard through one pin
only to avoid the creation of loops. Bypassing and
filtering components should be placed as close to the
modem chip as possible with the shortest possible
traces to a solid ground. It is recommended that a pi
filter be placed in series with the module V
CC
pin with a
filter, such as the one shown in Figure 21, on the reset
line. This filter also provides a proper power-on reset to
the modem. Careful module design is critical since the
module designer frequently has little control over the
motherboard design and the environment the module
will be used in.
Motherboard Design
Motherboard design is critical to proper modem module
performance and immunity to EMI and ESD events.
First and foremost, good design and layout practices
must be followed. Use ground and power planes
whenever possible. Keep all traces short and direct.
Use ground fill on top and bottom layers. Use adequate
power supply bypassing and use special precautions
with the power and reset lines to the modem module.
Bypass V
CC
right at the modem module connector. Be
sure the modem module is connected to V
CC
through a
single pin. Likewise, be sure ground is connected to the
modem module through one pin connected to the
motherboard ground plane. The modem reset line is
sensitive and must be kept very short and routed well
away from any circuitry or components that could be
subjected to an ESD event. Finally, mount the modem
module as close to the motherboard as possible. Avoid
high-profile sockets that increase the separation
between the modem module and the motherboard.
Figure 21. Modem Module V
CC
and RESET Filter
RESET
Motherboard
Connector
1.0 F .01 F .01 F 1.0 F
10 kO
2.2 F
To RESET
GND
To Modem Chip V
D
(Si2401 pin 4)
(Si2401 pin 8)
GND
3.3 V
Murata BLM 21A G601 SN1
AN94
98 Rev. 0.3
APPENDIX BPROTOTYPE BRING-UP GUIDE
Introduction
This appendix provides help with the debugging of initial
prototypes. Although most ISOmodem prototype
designs function as expected, there is the potential for
layout errors, omitted or incorrect components used in
the initial assembly run, and host software problems. If
the prototype modem does not function correctly, the
techniques outlined in this guide will help quickly isolate
the problem and get the prototype functioning correctly.
A functional Si2401URT-EVB and data sheet and a
computer with HyperTerm is required for some of the
troubleshooting steps. It is assumed that the designer
has read the data sheet, used the reference design and
recommended bill-of-materials, and has carefully
followed the layout guidelines presented in
Appendix AISOmodem Layout Guidelines. The
troubleshooting steps begin with system-level checks,
and then proceed to the component level.
Visual Inspection
Before troubleshooting, be certain that the circuit boards
and components are clean. Carefully wash the boards
to remove all solder flux and solder flakes. Inspect the
modem circuitry to ensure all components are installed,
and inspect all solder joints for incomplete connections,
cold solder joints, and solder bridges. Check all
polarized components, such as diodes, Zener diodes,
and capacitors for correct orientation. Thoroughly clean
the circuit board after replacing a component or
soldering any connections.
Reset the Modem
Be sure the modem is properly reset after power is
applied and stable.
Basic Troubleshooting Steps
Check Power
With power off, use an Ohm meter to verify system
ground is connected to Si2401 pin 12. Turn on
system power and measure the voltage between
pin 4 and pin 12 and between pin 13 and pin 12 on
the Si2401. In both cases, the voltage should be
3.3 V. If this is not the case, check the power routing.
If power is present, go to the next step.
Check Phone Line
Check the phone line with a manual telephone to be
sure there is a dial tone and dialing is possible. The
dc voltage across TIP and RING should read
approximately 4052 V with the phone on-hook.
Reset Modem
Do a manual reset on the modem. Hold Si2401 pin 8
(RESET) low for 300 ms, return to V
DD
(3.3 V) in
less than 5 ms and wait for at least 300 ms before
executing the first AT command.
Check DTE Setup
Be sure the DTE (Host) serial port is configured the
same as the modem. The default condition is eight
data bits, no parity-bit, one stop-bit, and a DTE rate
of 2400 bps.
Check DTE Connection
Check the DTE interface connection. Be sure the
CTS (Si2401 pin 7) signal is low.
Check pullup/pulldown configuration resistor.
Check modem configuration
Read back the modem register settings and correct any
inconsistencies. Use the ATSR or ATr# commands to
list the contents of the S-Registers.
If the problem was not located with these basic
troubleshooting steps, it is time to narrow the problem
down to the host system (hardware and software), the
Si2401 chip (and associated components), or the
Si3010 (and associated components).
AT OK?
The modem responds with an O to the command
AT<cr>.
This indicates the host processor/software is
communicating with the modem controller and problems
are in one of the following areas:
Inappropriate Commands
Verify that all AT commands used are supported by
the Si2401 and comply with the proper format. Be
sure the command and argument are correct. Do not
mix upper and lower case alpha characters in an AT
command (except the r, m, q, and w
commands).
Command Timing
The execution time for an AT command is
approximately 200 ms. Execution is complete when
the O is received. Subsequent AT commands
should wait for the O message, which appears
within 100 ms after the carriage return. The reset
recovery time (the time between a hardware reset or
the carriage return of an ATZ command and the time
the next AT command can be executed) is
approximately 100 ms. When a data connection is
being established, do not try to escape to the
AN94
Rev. 0.3 99
command mode until after the protocol message.
Si3010 and/or Associated Components
If the modem goes off-hook and draws loop current
as a result of giving the ATH1 command, go to the
Si3010 Troubleshooting section.
If the modem does not go off-hook and draw loop
current as a result of giving the ATH1 command and
receiving an O message, begin troubleshooting on
the Si2401 side of the isolation barrier. First check all
solder joints on the isolation capacitors, Si3010, and
associated external components. If no problems are
found, proceed to the following Troubleshooting
section to verify whether the problem is on the
Si2401 or the Si3010 side of the isolation capacitors.
If the problem is found to be on the Si2401 side,
check C50, C51, C53, the corresponding PCB
traces, and Si2401 pins. Correct any problems. If no
problems are found with the external components,
replace the Si2401.
If the problem is found to be on the Si3010 side of
the isolation barrier, go to the Si3010
Troubleshooting section.
If the modem does NOT respond with an O to the
command AT<cr>,
this indicates the host processor/software is not
communicating with the modem controller, and the
problem can be isolated as follows.
Si2401 Clock is Oscillating
First be sure the Si2401 is properly reset and
RESET, pin 8, is at 3.3 V. Next, check the DTE
connection with the host system. If this does not
isolate the problem, go to the Host Interface
Troubleshooting section.
Si2401 Clock is Not Oscillating
Check the voltage on the Si2401, pin 4, to be sure
the chip is powered. Also, check that pin 12 is
grounded. Next, check the solder joints and
connections (PCB traces) on C40, C41, Y1 and the
Si2401 pin 1 and pin 2. Measure C26 and C27 (or
replace them with known good parts) to ensure they
are the correct value. If these steps do not isolate the
problem, replace the Si2401.
Host Interface Troubleshooting
The methods described in this section are useful as a
starting point for debugging a prototype system or as a
continuation of the troubleshooting process described
above. The procedures presented in this section require
a known good Si2401URT-EVB evaluation board and
data sheet. This section describes how to substitute the
evaluation board for the entire modem circuitry in the
prototype system. Substituting a known operational
modem can help to quickly isolate problems. The first
step is to substitute the evaluation board for the
complete modem solution in the prototype system. This
demonstrates immediately whether any modem
functionality problems are in the prototype modem
circuitry or in the host processor, interface, or software.
Verify Si2401URT-EVB Functionality
Connect the evaluation board to a PC and a phone
line or telephone line simulator. Using a program
such as HyperTerm, make a data connection
between the evaluation board and a remote modem.
Remove power and the RS232 cable from the
evaluation board and proceed to the next step.
Connect Evaluation Board to Prototype System
Completely disconnect the embedded modem from
the host interface in the prototype system. Connect
the Si2401URT-EVB to the host interface using JP3
as described in the Si2401URT-EVB data sheet
section titled Direct Access Interface. This
connection is illustrated in Figure 22. Be sure to
connect the evaluation board ground to the
prototype system ground. Power up and manually
reset the evaluation board then power up the
prototype system and send AT<cr>. If an OK
response is received, make a connection to the
remote modem as in the previous step. If no OK
response is received, debug host interface and/or
software. If a connection is successfully made, go to
the next step to isolate the problem in the prototype
modem.
An alternative approach is to connect the prototype
modem to the Si2401URT-EVB motherboard in
place of the daughter card and use a PC and
HyperTerm to test the prototype modem. See Figure
Figure 23 for details.
Troubleshooting
Connect Evaluation Board to Prototype Modem Si3010.
Remove C1 on the evaluation board and on the
prototype system. Solder one end of the evaluation
board, C1, to the Si2401-side pad leaving the other end
of C1 unconnected. Next, solder a short jumper wire
from the unconnected side of C1 on the evaluation
board to the Si3010-side C1 pad on the prototype
system. This connection is illustrated in Figure 24.
Connect the phone line to the prototype system RJ-11
jack.
Power up and manually reset the evaluation board, then
power up the prototype system. Attempt to make a
connection using the host processor and software, the
evaluation board Si2401 and the prototype system
Si3010 and associated external components. If this
connection is successful, the problem lies with the PCB
layout, the external components associated with the
Si2401 or the Si2401 device itself.
AN94
100 Rev. 0.3
If the connection attempt is not successful, the problem
lies with the Si3010 and/or associated components.
Proceed to the section, Si3010 Troubleshooting.
This diagnosis can be validated by connecting the Host
isolation capacitors to the Si3010 on the evaluation
board as shown in Figure 25.
Si3010 Troubleshooting
Start by measuring the on-hook and off-hook voltages at
the Si3010 pins with respect to IGND (pin 15). Compare
these voltages to those in Figure 26. This may indicate
an area of circuitry to investigate further using the
Component Troubleshooting techniques. The voltages
you measure should be close to (although not exactly
the same as) those in the figure.
If any of the on-hook and off-hook Si3010 pin voltages
are grossly different than those in Figure 26 and nothing
seems wrong with the external circuitry after using the
Component Troubleshooting techniques, replace the
Si3010.
Component Troubleshooting
A digital multi-meter is a valuable tool to verify
resistance across components, diode direction,
transistor polarity and node voltages. During this phase
of troubleshooting, it is highly useful to have a known
good Si2401URT-EVB to compare against
measurements taken from the prototype system. The
resistance values and voltages listed in Tables 24, 25,
and 26 will generally be sufficient to troubleshoot all but
the most unusual problem.
Start with power off and the phone line disconnected.
Measure the resistance of all Si3010 pins with respect
to pin 15 (IGND). Compare these measurements with
the values in Table 24. Next, measure the resistance
across the components listed in Table 25 and compare
the readings to the values listed in the table. Finally,
using the diode checker function on the multi-meter,
check the polarities of the transistors and diodes as
described in Table 26. The combination of these
measurements should indicate the faulty component or
connection. If none of the measurements appears
unusual and the prototype modem is not working,
replace the Si3010.
Figure 22. Test the Host Interface
Host
Controller
Host
UART
Si2401 Si3010 Discretes
RS232
Transceiver
Si2401 Si3010 Discretes
EVB
Prototype System
To
Phone
Line
Connect prototype system ground to EVB ground
Disable RS232 transceiver outputs (check evaluation board data sheet)
Disconnect prototype modem interface
Connect the evaluation board to the target system
AN94
Rev. 0.3 101
Figure 23. Test the Prototype Modem
Figure 24. Test the Prototype Si3010 Circuitry
Host
Controller
Host
UART
Si2401 Si3010 Discretes
RS232
Transceiver
Si2401 Si3010 Discretes
EVB
Prototype System
Connect prototype system ground to EVB ground
Remove modem module from EVB
Disconnect host outputs from prototype modem
Connect EVB RS232 transceivers to prototype modem
Use PC with HyperTerminal to test prototype modem
To
Phone
Line
PC
To
Phone
Line
Host
Controller
Host
UART
Si2401 Si3010 Discretes
RS232
Transceiver
Si2401 Si3010 Discretes
EVB
Connect the prototype ground to the EVB ground.
Lif t prototype C1 and C2 and EVB C1 and C2 so the Si3010 is disconnected f rom the Si2401 on both
modems.
Connect EVB C1 and C2 to the Si3010 pad of prototype system C1 and C2.
Connect the phone line to the RJ11 jack on the prototype system.
Use PC and HyperTerm and attempt to establish a modem connection.
PC
C2
C1
C2
Prototype System
C1
AN94
102 Rev. 0.3
Figure 25. Verify Prototype Si3010 Failure
Figure 26. Si3010 Typical Voltages
To
Phone
Line
Host
Controller
Host
UART
Si2401 Si3010 Discretes
RS232
Transceiver
Si2401 Si3010 Discretes
EVB
Connect the prototype ground to the EVB ground
Lif t prototype and EVB C1 and C2 to decouple the line side f rom the DSP side. Do same on evaluation board.
Connect prototype system C1 and C2 to the Si3010 pad of EVB C1 and C2
Connect the phone line to the RJ11 jack on the EVB
Run the prototype system sof tware to attempt a modem connection
C2
C1
C2
C1
Prototype System
On-Hook
0 V
~1.0 V
~2.3 V
0.7
0.8 V
0 V
0 V
0 V
QE
RNG1
VREG
C2B
C1B
IB
RX
DCT
0 V
~1.0 V
0 V
0 V
0 V
0 V
0 V
DCT2
RNG2
VREG2
SC
QE2
QB
DCT3
IGND
Off-Hook
1.6 V
1.0 V
2.3 V
0.8 V
0.8 V
0 V
2.5 V
3.4 V
QE
RNG1
VREG
C2B
C1B
IB
RX
DCT
2.2 V
0.9 V
1.8 V
0 V
2.1 V
2.8 V
1.6 V
Reference
DCT2
RNG2
VREG2
SC
QE2
QB
DCT3
IGND
Voltages measured with respect to IGND (Si3010 pin 15)
Reference
AN94
Rev. 0.3 103
Table 24. Resistance to Si3010 Pin 15
Si3010 Resistance
Pin 1 >6 M
Pin 2 >5 M
Pin 3 >2 M
Pin 4 1 M
Pin 5 >5 M
Pin 6 >5 M
Pin 7 >1 M
Pin 8 >2 M
Pin 9 >2 M
Pin 10 >1 M
Pin 11 0
Pin 12 >2 M
Pin 13 >5 M
Pin 14 >14 M
Pin 16 >5 M
Table 25. Resistance across Components
Si3010 Resistance
FB1 <1
FB2 <1
RV1 >20 M
R1 1.07 K
R2 150
R3 3.65 K
R4 2.49 K
R5 100 K
R6 100 K
R7 4.5 M or 16 M
R8 4.5 M or 16 M
R9 >800 k
R10 536
R11 73
R12 <1
R13 <1
R15 <1
R16 <1
C1 >20 M
C2 >20 M
C3 >3 M
C4 3.5 M or 9.7 M
C7 2 M or 5 M
C8 >20 M
C9 >20 M
Note: If two values are given, the resistance measured is
dependent on polarity.
Table 26. Voltage across Components with
Diode Checker
Component Voltage
Q1, Q3, Q4, Q5
Base to Emitter
Base to Collector
Verifies transistors are NPN
0.6 V
0.6 V
Q2
Emitter to Base
Collector to Base
Verifies transistor is PNP
0.6 V
0.6 V
Q2 collector to Si3010 pin 1
If test fails, Z1 is reversed
>1 V
AN94
104 Rev. 0.3
Si2401 Host Software Design
Checklist and Troubleshooting
Introduction
The following information is intended to aid the
development of an Si2401 application. The points
contained in the design checklist must be carefully
considered before a design incorporating the Si2401 is
completed. While it is impossible to cover all issues for
every design, the important topics for most systems,
including a modem, are discussed. In addition to a
design checklist, a troubleshooting guide is presented.
This guide offers tips for debugging potential problems
involving the integration of the Si2401 chipset into a
system.
Design Checklist
In most applications the exact conditions and physical
environment of the modem in the field are variable.
Therefore, it is generally a good idea to include some
software on the host that can adapt to the changing
conditions the modem might encounter. Some of the
variables a system could encounter in the field are as
follows:
Is the phone line extremely noisy or does it exhibit
adverse conditions in relation to one of the modem
algorithms?
Is the modem connected to a phone line?
Does the phone line supply a dial tone?
Does the phone line support tone dialing or pulse
dialing only?
The following host software checklist will help handle
these situations.
Software fallback mechanism.
Because the V.22bis algorithm does not include
automatic fallback, the host must supply a fallback
mechanism to deal with extremely noisy or adverse line
conditions. It is highly recommended that any host
software include this simple feature to absolutely ensure
modem connections will be established by your product
in the field. One thing to note is that the V.22bis
algorithm allows for connection at 1200 bps if the
connecting modem is a V.22 modem. This is not the
same as a retrain. The following steps outline an easy
procedure to implement a fallback mechanism:
1. Set the Si2401 to V.22bis mode and attempt a
connection (ATS07=06ATDT#). If the Si2401 does
not connect (c result code echoed if the other
modem is V.22bis compatible, and d result code of
the other modem is V.22 only), then the host should
hang up the modem and go to step 2.
2. Set the Si2401 to V.22 mode and attempt a
connection (ATS07=02ATDT#). If the Si2401 does
not connect (c result code), then the host should
hang up and go to step 3.
3. Set the Si2401 to V.21 mode or Bell 103 mode and
attempt a connection (ATS07=03ATDT# or
ATS07=01ATDT#).
Because each of the different modem protocols use
different algorithms, the likelihood of establishing a
connection under any line conditions is extremely high
using these steps.
Software checks phone line connection.
Check the value of SDB (ATSDB?) while on-hook. If the
reading of this register is anything other than 0x00, the
Si2401 is connected to an active phone line.
Software checks for parallel phone off-hook.
Several methods for implementing this are detailed in
the Si2401 data sheet and the troubleshooting guide.
Software checks dial tone.
The host software must comprehend that after
attempting to dial (ATDT# or ATDP#), the first response
echoed by the Si2401 will be a t if a dial tone is
present and an n followed by a hang up if no dial tone
is present. Additionally, the following procedure may be
used to check for dial tone before any attempt is made
to dial out: Issue the command ATS01=01S02=01 (or
any arbitrarily small number). S01 sets the number of
seconds the modem waits after going off-hook before
dialing, and S02 sets the number of seconds the
modem waits for a dial tone before hanging up. Next
issue the command ATDT5; (the 5 is arbitrary), if there
is no dial tone, the Si2401 will hang up and echo an n.
If there is a dial tone the Si2401 will echo a t.
Software checks phone line for tone or pulse
dialing support.
One method to check for tone dialing is to simply try to
connect with ATDT#, and if unsuccessful try to
connect with ATDP#. Additionally, the Si2401 has an
automatic tone/pulse detect dial modifier. See "AT
Command Set Description" on page 18 for more details.
Software checks for off-hook parallel phone
intrusion.
To check for a parallel phone intrusion while the Si2401
is off-hook, the host must configure GPIO4 (or ninth bit)
as the ALERT pin and send AT:I when ALERT is set as
described in the Si2401 data sheet.
AN94
Rev. 0.3 105
Troubleshooting
The following sections describe some of the features of
the Si2401 and the related areas where a correction
may be found. Additionally, these sections discuss
design tips and deliver a more detailed description of
each feature than is provided in the Si2401 and
Si2401URT-EVB data sheets.
Parallel Phone Detection
The Si2401 includes an automatic parallel phone
intrusion detection algorithm while off-hook. While the
Si2401 is off-hook it continually monitors for parallel
phone intrusions. The INTb pin (or ninth bit INTb) must
be enabled (ATSE2=C0). The two most significant bits
enable INTb, the others can be any value
(SE2[GPIO] = 11xx,xxxxb). When an intrusion is
detected, it pulls the INTb pin high and the host
processor must act on the intrusion or ignore it. The
INTb function is a sticky bit and must be cleared by
sending AT:I.
UART
Care should be taken to ensure that the host UART and
Si2401 UART are set to the same rate. In particular, a
V.22bis connection has the ability to fallback to
1200 baud if the other modem only supports V.22. In
this case, the Si2401 will echo a d instead of c.
If CTS flow control is not implemented, it is necessary
upon receipt of the d to escape into command mode,
change the Si2401 UART to 1200 baud, change the
host UART to 1200 baud, and put the Si2401 back on
line with ATO. If CTS is implemented, then this
procedure is not necessary. The use of CTS is
recommended to simplify the host software.
The Si2401 UART is also capable of different baud
rates separate from the line rate. It is configurable via
register SE0 to be 300, 1200, 2400, 9600, 19200,
38,400, 115,200, and 307200 bps. When programming
a new baud rate, the following procedure should be
followed (example shows a change to 9600 baud).
1. Issue the command ATSE0=23.
2. Wait for the host UART to empty, indicating that the
entire command has been sent.
3. Change the host UART to 9600 baud.
4. Issue a carriage return to ensure that the Si2401 is
ready to accept a new command.
For most applications, it is recommended that the
Si2401 UART be set to 9600 baud, and to implement
CD handshaking. This setting allows for the widest
margin under varying DCE rate conditions.
Reset
RESET is the only method to return all of the Si2401
registers to their power-up state. (ATZ does not affect
SE0, SE2, SE4, SE5, SE6, SE7, SEA, SF8, SF9 or
internal registers.) Reset is also the only way to take the
Si2401 out of total powerdown mode. For these
reasons, it is recommended that reset be connected to
a software controllable pin. It is also important that reset
meets the specifications in the data sheet (held low for
at least 5 ms). During RESET, CTS should be held high.
This can be implemented with a pull-up resistor to V
CC
.
After releasing RESET, the host must wait 3 ms prior to
transmitting any characters to the Si2401.
AN94
106 Rev. 0.3
APPENDIX CTRANSITIONING FROM THE Si2400 TO THE Si2401
Overview
The new Si2401 ISOmodem chipset integrates Silicon
Laboratories third-generation DAA technology with
many new and improved features. While the Si2401 is
largely software compatible with the Si2400, there are a
few changes that must be considered. This document is
intended to ease software transition and reduce
development time for existing Si2400 ISOmodem
customers redesigning with the Si2401. For most
customers, only minor Si2400 software changes will be
required to be compatible with the Si2401, such as new
DAA register settings. Utilizing the Si2401s enhanced
features and updated register settings may also require
software changes.
Enhanced features
The Si2401 has several new features that may require
software changes; a summary of these features is listed
in Table 27. Refer to the Si2401 data sheet for a more
detailed functional description.
AN94
Rev. 0.3 107
Table 27. Enhanced Si2401 Features
Feature Description
27 MHz clock input A 27 MHz clock input option has been added to the Si2401. To enable this option, a
pulldown resistor <10 kO must be placed between GPIO4 (pin 11) and GND. The
Si2401 default clock mode (no resistor present on pin 11) requires a 4.9152 MHz
crystal or clock input.
Transmit FIFO The Si2401 has an integrated 10-byte transmit FIFO and allows for two distinct CTS
reporting methods. By default, Si2401 CTS operation is the same as the Si2400;
every incoming byte causes a CTS transition. However, on the Si2401, the host pro-
cessor can continue to send up to 9 more bytes after CTS asserts. In addition, by
programming the transmit control register TC (SFC) to 0x80, CTS is asserted when
the FIFO is full and cleared when the FIFO is empty.
Line voltage monitoring Line voltage monitoring has improved from a resolution of 3 V to 1 V with a 127 V
range. Tip and ring polarity are reported, and the Si2401 has the capability of return-
ing line voltage while off-hook.
Line current monitoring Line current monitoring resolution has improved from 3 mA to 1.1 mA allowing more
accurate control over the off-hook intrusion algorithm. The Si2401 has a loop cur-
rent reporting range of 120 mAs.
Interrupt reporting An interrupt status register INTS (S09) and an interrupt mask register INTM (S08)
were created to simplify software design. A new command has been added (AT:I),
which reports the contents of INTS and clears the GPIO pin automatically without
writing to the GPIO data register GPD (SE3).
Ring detection Ring detection offers more flexibility for detecting distinctive rings.
GPIO5 / RI pin Pin 3 has been programmed to function as a general purpose input/output (GPIO)
pin or a ring indicator pin.
DTE rates New DTE rates are available. The 228,613 bps and 245,760 bps rates have been
replaced by the more common 38,400 bps and 115,200 bps rates.
Echoing Unlike the Si2400, the Si2401 does not echo in data mode. Also, the Si2401
defaults to verbose mode (ATV1), which proceeds and follows each response with a
carriage return and linefeed. Like the Si2400, command echoing occurs in com-
mand mode.
AN94
108 Rev. 0.3
Register Changes
To accommodate the third generation DAA and other new features, several registers have been modified. If
software written for the Si2400 utilizes the registers listed in Table 28, the software may need to be modified in
order to support the Si2401.
0
Table 28. Modified Register Settings
Register Si2400
Name
Si2401
Name
Si2400 Function Si2401 Function
S07 MF1 MF1 Bit 7HDLC enable (moved to S13) Reserved
S08 MNRP INTM Minimum ring period
1
Interrupt mask
2
S09 MXRP INTS Maximum ring period
1
Interrupt status
2
S0A ROT Ringer off time
1
Reserved
S0B MNRO Minimum ringer off time
1
Reserved
S0D RPE Ringer off time allowed error
1
Reserved
S11 ONHI OFHI On-hook intrusion settings
3
7:4Reserved
3:0Differential current level
S12 OFHI ACL Off-hook intrusion settings Absolute current level
S13 MF3 MF3 Bit 7Japan CID
Bit 3On-hook intrusion method
Bit 1Bellcore CID (moved to S0C)
Bit 0PCM data mode
Bit 7Reserved
Bit 3Reserved
Bit 1HDLC enable
Bit 0Reserved
S14 MF4 Bit 7Disable result codes (Now con-
trolled by S62)
Bit 5TIES Enable
Bits 3:0Line status (moved to S09)
By default TIES is enabled, to disable
set register S10 to 0xFF.
S33 MDMO MDMO Bit 6On-hook intrusion disable
3
Bit 5Off-hook intrusion disable
Bit 6Reserved
Bit 5Reserved
S3B RP Minimum number of ring pulses per
ring burst
1
Reserved
SD1 INTS Intrusion state Reserved
SDB LVCS LVS LVCS LVSA 2s complement number with
finer resolution.
2
SE0 CF1 CF1 DTE rates 228613 and 245760
removed.
DTE rates 38400 and 115200 added.
SE1 CLK1 GPIO1 Bits 7:6Microcontroller clock rate
Bit 5Reserved
Bit 4:0CLK_OUT divider
Bits 7:2Reserved (Clock rate is no
longer programmable)
Bits 1:0CLK_OUT is now a GPIO
2
SE2 GPIO GPIO2 GPIO register settings AIN option on GPIOs removed
ALERT is now INTb (active low)
GPIO4 can be used as AOUT
2
SE3 GPD GPD Bits 7:6AIN gain control Bits 7:6Reserved
AN94
Rev. 0.3 109
SE4 CF5 CF5 Bit 4DRT voice and codec modes
Bit 1Analog codec
Bit 0Secondary serial port
Bit 4Reserved
Bit 1:0Reserved
SEC RDC1 Reserved Bit 7Ring validation enable
1
Bits 6:4Ring delay
Bits 3:1Ring confirmation count
SED RAS Reserved Bits 5:0Ring assertion time
1
SEE RDC2 Reserved Bits 7:4Ring timeout
1
Bits 3:0Ring assertion maximum
count
SF0 DAA0 DAA0 Bits 7:6Reserved Bits 7:6Fast off-hook selection
SF4 DAA4 DAA4 Bit 7Ring squelch
Bits 6:4Analog receive gain
Bits 7:4Reserved
SF5 DAA5 DAA5 Bit 7Full scale
Bit 6DC termination off
Bit 5On-hook speed
Bit 4AC termination
Bits 3:2DC termination
Bit 1Ringer impedance
Bits 7:6Reserved
Bits 5:4On-hook speed
Bit 3Current limiting enable
Bit 2Ringer impedance
Bit 1Reserved
SF6 DAA6 DAA6 Bits 7:4Reserved
Bit 3Force Japan DC termination
Bit 2DTMF dialing mode
Bit 1Line voltage adjust
Bit 0Force low voltage mode
Bits 7:6Minimum loop current
Bits 5:4Tip/ring voltage adjust
Bits 3:0AC termination select
SF7 DAA7 DAA7 Bit 4LMO
Bit 3Current limiting enable
Reserved
SF8 DAA8 DAA8 Bits 3:0Reserved Bit 1DC impedance selection
Bit 0Over protect enable
SF9 DAA9 DAA9 Bit 6Receive overload (non-sticky)
Bit 0Reserved
Bit 6Reserved
Bit 0Overcurrent protect detect
Notes:
1. On the Si2401, ring detection features are programmed using registers SEC, SED, and SEE.
2. See Si2401datasheet for further details.
3. On-hook voltage detection must be performed by the host controller. This can be accomplished by reading the
line voltage status register (SDB) before going off-hook.
Table 28. Modified Register Settings (Continued)
AN94
110 Rev. 0.3
Default Register Settings
The default settings for several registers in the Si2401 are different than the Si2400 default settings in order to
comply with standard modem values. If software written for the Si2400 relies on any of the default values listed in
Table 29, the software may need to be modified for the Si2401.
Table 29. Updated Default Register Settings
Reg. Si2400
default
Si2401
default
Description
S01 0x03 0x02 Number of seconds modem
waits before dialing after
going off-hook changed from
3 seconds to 2 seconds
S02 0x14 0x03 Number of additional seconds
modem waits for a dial tone
before hang-up changed from
20 seconds to 3 seconds
S07 0x01 0x06 Default modem modulation
changed from Bell 103 to
V.22bis
S10 0x07 0x03 Default TIES guard band
changed from 3 seconds to
1.3 seconds
S15 0x84 0x04 Answer tone phase reversal
changed to be disabled by
default
S2E 0x84 0xF0 V.23 reversal turnaround tim-
eout changed from 220 ms to
400 ms
S62 0x00 0x41 Result codes x, i, I, l, and
L changed to be disabled by
default and result code R
changed to be enable by
default
S82 0x00 0x08 Loop current loss detect
changed to be enabled by
default
SDF 0x00 0x0C Deglitching sample rate
changed to 480 ms
AN94
Rev. 0.3 111
Prototyping an Si2401 on an Si2400 design
The Si2401 evaluation board, along with an existing
Si2400 design, can be configured to easily test Si2400
software for use with the Si2401 and reduce software
development time. Jumper wires can by used to
connect from the host processor in an existing design
directly to the Si2401 on the Si2401URT-EVB
evaluation board bypassing the existing Si2400 circuit.
A minimum of three jumper wires is required to pass the
TX, RX, and GND signals. However, depending on the
number of signals utilized by the existing Si2400 design,
additional jumper wires may be required. The
Si2401URT-EVB evaluation board can provide power
and clock signals. If using Revision 3.1 of the
ISOmodem motherboard, place a jumper on JP8 to
disable the RS232-mux. If using an earlier version of the
motherboard, remove the jumper on JP8 and all of the
jumpers on JP6. This will allow the extra header (JP3)
to be driven by the jumper wires. On the existing Si2400
design, depopulate the Si2400 and jumper wires
between the pads and JP3 of the Si2401URT-EVB
evaluation board according to Table 30.
Table 30. Jumper Wiring Pinout
Si2400 Pad Si2400 Pinout
Description
Si2401 EVB JP3
Pins
4 V
D
15
5 RXD 7
6 TXD 9
7 CTS 11
8 RESET 13
9 AOUT 16
10 ALERT/GPIO4 16
12 GND 6
14 ESC/GPIO3 8
15 CD/GPIO2 4
16 EOFR/GPIO1 2
AN94
112 Rev. 0.3
APPENDIX DSi3008 SUPPLEMENT
Si3008 Introduction
The Si3008 is a small form factor line-side device with a
reduced peripheral component count. The Si3008
meets the telephone network compatibility requirements
for North America and many other countries. This
appendix describes the Si3008 and its use with the
Si2401 ISOmodem. The Si3008 features are described
and compared to those of the Si3010, and a reference
design is presented. Si3008 layout guidelines and a
sample layout are also included. Finally, a prototype
bring-up guide is presented for Si3008-based designs.
Si3008 Capabilities and Limitations
Features supported
The Si3008 uses Silicon Laboratories' patented
isolation technology to communicate with the Si2401
ISOmodem and provide high-voltage isolation. The
Si3008 meets the telephone network interface
requirements of the countries listed in Table 31 and
provides up to 6 kV of surge performance with Y2
isolation capacitors. The Si2401/3008 chipset meets all
global requirements for EMI, EMC, and safety if proper
layout guidelines are followed. The information
presented here is a summary. For complete details see
the Si2401/Si3008 data sheet.
Table 31. Country Compatibility
Argentina Macao
Canada Malaysia**
Chile Mexico
China Oman
Colombia Pakistan
Ecuador Peru
Egypt Romania
El Salvador Russia
Guam Saudi Arabia
Hong Kong Singapore
Hungary Slovakia
India Syria
Indonesia Taiwan
Japan* UAE
Jordan USA
Kazakhstan Yemen
Kuwait ** Loop current >20 mA
* Requires waiver for <300 O
AN94
Rev. 0.3 113
A feature comparison between the Si3010 and the Si3008 is presented in Table 32. This table is designed to
present a quick capability comparison of the Si3010 and the Si3008 to enable the selection of the best DAA chip for
a particular design.
The Si3008 supports parallel handset off-hook/on-hook detection in both the on and off-hook modes. Loop current
is measured with 3.3 mA/bit resolution by the LCS bits. The LCS bits V loop current response is shown in
Figure 27, and the LCS transfer function is explained in Table 33. The DC I/V characteristic is illustrated in
Figure 28 and meets the requirements of the countries listed in Table 31. The Si3008 provides a ringer impedance
of approximately 5 MO and has an on-hook line monitor mode that supports Type 1, Type 2, and UK Caller ID.
The Si3008 meets the DTMF and pulse dialing requirements for the countries in Table 31. Higher DTMF signal
levels than those required can be achieved.
Sufficiently high DTMF levels will clip due to the output signal level limitations of the Si3008. DTMF distortion
between 1020% is generally acceptable.
Loop current limiting (previously required by CTR/TBR-21 countries such as France) is not supported by the
Si3008. Although current limiting is no longer required for certification, some customers require it for backward
compatibility.
Table 32. Si3010/Si3008 Feature Comparison
Feature Name Si3010 Si3008
Type I Caller ID
Type II Caller ID Snoop
UK Caller ID
Parallel phone detection
On-hook intrusion
Loop current limiting ICL
Loop current loss detection LCLD
Minimum loop current MINI
Loop voltage adjust DCV
DC impedance selection DCR
AC impedance selection ACT
Ringer impedance RZ
Billing tone enable BTE
Billing tone detect BTD
On-hook speed OHS
AN94
114 Rev. 0.3
Figure 27. Typical LCS Transfer Function
Table 33. Loop Current Sense Transfer Function
LCS[4:0] Condition
00000
b
00011
b
Insufficient line current for normal operation. Use the DODI bit
(Offset 0x34, bit 3) to determine if a line is still connected.
00100
b
11110
b
Normal operation.
11111
b
Loop current is excessive (>160 mA).
0
32
64
96
128
160
192
224
256
0 16 32 48 64 80 96 112 128 144
Loop Current (mA)
L
C
S

B
i
t
s
AN94
Rev. 0.3 115
Figure 28. DC/IV Characteristics
Reference Design
The Si3008 requires fewer peripheral components (specifically, fewer expensive high voltage transistors) than the
Si3010. Table 34 compares the Si3010 and Si3008 peripheral component requirements.
Table 34. Si3010 vs. Si3008 Peripheral Component Requirements
Component Si3010 Si3008
Resistors 1/16 W 9 12
Resistors 3/4 W 3 2
Capacitors (NP) 11 9
Capacitors (polar) 1 0
Y2 capacitors 4 4
Diode bridge 1 1
Zener diodes 1 2
pnp transistors 1 1
npn transistors 4 2
Ferrite beads 4 4
SiDactor 1 1
Crystal 1 1
Total Components 41 39
DCIV
0
5
10
15
20
25
0 20 40 60 80 100 120 140 160 180
Loop Cur r ent (mA)
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AN94
116 Rev. 0.3
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AN94
Rev. 0.3 117
Bill of Materials: Si24xx Daughter Card
Table 35. Bill of Materials: Si24xx Daughter Card
Item Qty Reference Value Rating Tolerance Foot Print Dielectric Manufacturer Number Manufacturer
1 2 C1,C2 33 pF Y2 20% C1808-GF-Y2 X7R GA342D1XGF330JY02L Murata
2 1 C3 10 nF 250 V 20% CC0805 X7R C0805X7R251-103MNE Venkel
3 1 C4 1.0 F 25 V
(50 V used)
20% CC1206 X7R GRM31MR71H105KA88L Murata
4 4 C5,C50,C55,C56 0.1 F 16 V 20% CC0603 X7R C0603X7R160-104MNE Venkel
5 2 C8,C9 680 pF Y3 10% C1808-GD-Y3 X7R GA342QR7GD681KW01L Murata
6 1 C11 330 pF 50 V 20% CC0603 X7R C0603X7R500-331MNE Venkel
7 2 C40,C41 33 pF 16 V 5% CC0603 NPO C0603NPO160-330JNE Venkel
8 1 C51 0.22 F 16 V 20% CC0603 X7R C0603X7R160-224MNE Venkel
9 1 C54 1.0 F 10 V 10% 3216_EIAA Tant TA010TCM105-KAL Venkel
10 1 D1 HD04 400 V MINIDIP4 HD04-T Diodes, Inc.
11 5 FB1,FB2,FB5,
R15,R16
Ferrite Bead RC0603 BLM18AG601SN1B Murata
12 1 JP1 HEADER
8X2
CONN2X8-100-SMT TSM-108-01-T-DV Samtec
13 1 JP2 4X1
Header_0
CONN1X4-100-SMT 68000-403 Berg
14 2 Q1,Q3 NPN 300 V SOT-23 MMBTA42LT1 Motorola
15 1 Q2 PNP 300 V SOT-23 MMBTA92LT1 Motorola
16 1 RV1 SiDactor 275 V 100 A SOD6 P3100SB Teccor
17 3 R1X,R1Y,R1Z 619 O 1/4 W 1% RC1206 CR1206-4W-6190FT Venkel
18 3 R2X,R2Y,R2Z 732 O 1/4 W 1% RC1206 CR1206-4W-7320FT Venkel
19 1 R4 3.9 K 1/16 W 5% RC0603 CR0603-16W-392JT Venkel
20 2 R5,R6 100 K 1/16 W 5% RC0603 CR0603-16W-104JT Venkel
21 2 R7,R8 10 M 1/8 W 5% RC0805 CR0805-8W-106JT Venkel
22 1 R10 1 K 1/16 W 5% RC0603 CR0603-16W-102JT Venkel
23 2 R12,R13 56 O 1/16 W 5% RC0603 CR0603-16W-560JT Venkel
24 1 R18 1.5 M 1/16 W 5% RC0603 CR0603-16W-155JT Venkel
25 1 R19 180 K 1/16 W 5% RC0603 CR0603-16W-184JT Venkel
26 2 R20,R21 3 M 1/16 W 5% RC0603 CR0603-16W-305JT Venkel
27 1 U1 Si2401 SO16 Si2401-FT Silicon Labs
28 1 U2 Si3008 SO8E Si3008-FS Silicon Labs
29 1 Y1 4.9152 MHz 20 pF load,
150 ESR
50 ppm XTAL-ATS-SM 559-FOXSD049-20 CTS Reeves
30 1 Z1 20 V Dual
Zener
1/4 W SOT-23 AZ23C20 Vishay
AN94
118 Rev. 0.3
Layout Guidelines
The key to a good layout is proper placement of
components. It is best to copy the placement shown on
our evaluation boards (see the reference layout
included in this appendix). Alternatively, perform the
following steps, referring to the schematics.
1. All traces, open pad sites, and vias connected to the
following components are considered to be in the
DAA section and must be physically separated from
non-DAA circuits by 5 mm to achieve best possible
surge performance: R1, R2, R4, R5, R6, R7, R8,
R10, R15, R16, R18, R19, R20, R21, U2, Z1, D1,
FB1, FB2, RJ11, Q1, Q2, Q3, C3, C4, C5, C8, C9,
C11, RV1, C1 pin 2 only, C2 pin 2 only, C8 pin 2 only,
C9 pin 2 only.
2. The isolation capacitors C1, C2, C8, and C9 are the
only components permitted to straddle between the
DAA section and non-DAA section components and
traces. This means that for each of these capacitors,
one of the terminals is on the DAA-side, the other is
not. Maximize the spacing between the terminals
(between pin 1 to pin 2) of each of these capacitors.
3. Place and group the following components: U1, U2,
R12, R13, C1, C2.
a.U1 and U2 are placed so that the right side of U1
faces the left side of U2.
b.C1 and C2 should be placed directly between U1
and U2.
c.Keep R12 and R13 close to U1.
d.Place U1, U2, C1, and C2 to realize the
recommended minimum creepage spacing for
the target application.
e.Place C1 and C2 so that traces connected to U2
pin 1 (C1B) and U2 pin 2 (C2B) are physically
separated from traces connected to:
iC8, R15, FB1
ii.C9, R16, FB2
4. Place and group the following components around
U2: C4, R18, R19, R20, R21, C5, C11, R7, R8.
These components should form the critical inner
circle of components around U2. Refer to Figure 30
for proper placement.
5. Place and group the following components around
the RJ11 jack: FB1, FB2, RV1, R15, R16, C8 and
C9.
a.Use 20 mil width traces on this grouping to
minimize impedance.
b.Place C8 and C9 close to the RJ11 jack,
recognizing that, a GND trace will be routed
between C8 and C9, back to the Si24xx GND pin,
through a minimum 20 mil width trace. The GND
trace from C8 and C9 must be isolated from the
rest of the Si3008 traces.
c.The trace from C8 to GND and from C9 to GND
must be short and equidistant.
6. After the previous step, there should be some space
between the grouping around U2 and the grouping
of components around the RJ11 jack. Place the rest
of the components in this area, given the following
guidelines:
a.Space U2, Q1, Q2, Q3, R1, R2, and R10 away
from each other for best thermal performance. R1
and R2 can each dissipate nearly 0.75 W under
worst case conditions.
b.Place C3 next to D1.
c.Make the size of the Q1, Q2, and Q3 collector
pads each large enough to safely dissipate
0.15 W under worst case conditions. See the
transistor data sheet for thermal resistance and
maximum operating temperature information.
Implement collector pads on solder side and use
vias between them to improve heat transfer for
best performance.
7. The epad of U2 (pin 9) is also known as IGND. This
is the ground return path for many of the discrete
components, and requires special mention
a.Route traces associated with IGND using 20 mil
traces.
b.The area underneath U2 should be ground-filled
and connected to IGND (U2 pin 9). Ground fill
both solder side and component side and stitch
together using vias.
c.C5, IGND return path should be direct.
d.The IGND plane must not extend past the diode
bridge.
8. The traces from R7 to FB1 and from R8 to FB2
should be well matched. This can be achieved by
routing these traces next to each other as possible.
Ensure that these traces are not routed close to the
traces connected to C1 or C2.
9. Minimize all traces associated with Y1, C40, and
C41 and allow NO other traces to be routed through
this circuitry.
10.Decoupling capacitors (0.22 F and 0.1 F
capacitors) connected to V
A
, V
D
must be placed next
to those pins. Traces of these decoupling capacitors
back to the Si2401 GND pin should be direct and
short.
AN94
Rev. 0.3 119
Table 36. Si2401/Si3008 Layout Checklist
# Layout Requirement
1 Place U1 and U2 so pins 9-16 of U1 are facing pins 1-4 of U2.
2 Place U1, U2, C1 and C2 to provide minimum required creepage distance.
3 Place R12 and R13 close to U1.
4 Place C1 and C2 directly between U1 and U2, connect with short direct traces.
5 Place R7, R8 and C11 close to U2 keeping away from U2 pins 1 and 2.
6 Provide large collector pads for heat sinking Q2 and Q3.
7 Use >15mil trace widths in DAA section and >20 mil IGND trace widths.
8 Place C3 directly across D1 and minimize IGND trace length.
9 Place FB1, FB2, R15, R16, and RV1 close to the RJ-11 jack.
10 Place C8 and C9 to minimize trace length to chassis ground.
11 The traces from the RJ-11 through C8 and C9 to chassis ground must be short.
12 Keep C8 and C9 away from C1 and C2 or place at 90 degrees.
13 Use >20mil trace widths between RJ-11, FB1-2, R15, R16, RV1 C8 and C9.
14 Match the routing from the RJ-11 to FB1 and FB2.
15 Match traces from FB1, R7, C11 to U2 to those from FB2, R8, R18 to U2.
16 There must be no digital ground or power plane in DAA area.
17 Place C4 close to U2 and connect with very short direct traces.
18 Minimize U2 pin6, Q4 base, Q4 emitter to U2 pin5 loop area.
19 >5 mm creepage between any TNV and SELV component, pad or trace.
20 Mark U1 pin 1 and U2 pin1.
21 Allow space and mounting holes for fire enclosure if required.
22 IGND plane does NOT extend under C3, D1, FB1-2, R15-16, C8-9 or RV1.
23 All traces connecting C50, C51, C52 and U1 must be short and direct.
24 The XTALI, Y1, XTALO loop must be minimized and routed on one layer.
25 The Y1, C40, C41 loop must be minimized and routed on one layer.
26 No traces can be routed through the Y1, C40, C41 loop.
27 Space U2, Q1, Q2, Q3, R1, R2, and R10 for best thermal performance.
28 Size Q1, Q2, and Q3 collector pads to safely dissipate 0.15 W (see text).
29 Submit layout to Silicon Laboratories for review.
AN94
120 Rev. 0.3
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AN94
Rev. 0.3 121
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122 Rev. 0.3
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AN94
Rev. 0.3 123
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AN94
124 Rev. 0.3
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AN94
Rev. 0.3 125
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AN94
126 Rev. 0.3
Module Design and Application
Considerations
Modem modules are more susceptible to radiated fields
and ESD discharges than modems routed directly on
the motherboard because the module ground plane is
discontinuous and elevated above the motherboard
ground plane. This separation also creates the
possibility of loops that couple these interfering signals
to the modem. Additionally, system designers can
adversely impact the ESD and EMI immunity and
performance of a properly-designed module with a poor
motherboard layout.
Module Design
Particular attention should be paid to power supply
bypassing and reset line filtering when designing a
modem module. Trace routing is normally very short on
modules since they are generally designed to be as
small as possible. Care should be taken to use ground
and power planes in the low-voltage circuitry whenever
possible and to minimize the number of vias in the
ground and power traces. Ground and power should
each be connected to the motherboard through one pin
only to avoid the creation of loops. Bypassing and
filtering components should be placed as close to the
modem chip as possible with the shortest possible
traces to a solid ground. It is recommended that a pi
filter be placed in series with the module V
CC
pin with a
filter, such as the one shown in Figure 36, on the reset
line. This filter also provides a proper power-on reset to
the modem. Careful module design is critical since the
module designer frequently has little control over the
motherboard design and the environment the module
will be used in.
Motherboard Design
Motherboard design is critical to proper modem module
performance and immunity to EMI and ESD events.
First and foremost, good design and layout practices
must be followed. Use ground and power planes
whenever possible. Keep all traces short and direct.
Use ground fill on top and bottom layers. Use adequate
power supply bypassing and use special precautions
with the power and reset lines to the modem module.
Bypass V
CC
right at the modem module connector. Be
sure the modem module is connected to V
CC
through a
single pin. Likewise, be sure ground is connected to the
modem module through one pin connected to the
motherboard ground plane. The modem reset line is
sensitive and must be kept very short and routed well
away from any circuitry or components that could be
subjected to an ESD event. Finally, mount the modem
module as close to the motherboard as possible. Avoid
high-profile sockets that increase the separation
between the modem module and the motherboard.
Figure 36. Modem Module V
CC
and RESET Filter
RESET
Motherboard
Connector
1.0 F .01 F .01 F 1.0 F
10 kO
2.2 F
To RESET
GND
To Modem Chip V
CC
(Si2401 pins 5, 21)
(Si2401 pin 12)
GND
VCC
Murata BLM 18A
G601 SN1
AN94
Rev. 0.3 127
APPENDIX ESi3006 SUPPLEMENT
Si3006 Introduction
The Si3006 is a small form factor line-side device with a
reduced peripheral component count. The Si3006
meets the telephone network compatibility requirements
for countries worldwide. This appendix describes the
Si3006 and its use with the Si2401 ISOmodem. The
Si3006 features are described and compared to those
of the Si3010 and the Si3008. A reference design is
presented. Si3006 layout guidelines and a sample
layout are also included.
Si3006 Capabilities and Limitations
Supported Features
The Si3006 uses Silicon Laboratories' patented
isolation technology to communicate with the Si2401
ISOmodem and provide high-voltage isolation. The
Si3006 meets the telephone network interface
requirements of the countries listed in Table 37. It
provides up to 6 kV of surge performance with Y2
isolation capacitors. The Si2401/3006 chipset meets the
most stringent requirements for EMI, EMC, and safety if
proper layout guidelines are followed. The information
presented here is a summary. For complete details, see
the Si2401/Si3006 data sheet.
Table 37. Country Support List
Supported Countries
Argentina Lebanon
Australia
1
Luxembourg (EU)
Austria (EU) Macao
Bahrain Malaysia
3
Belgium (EU) Malta (EU)
Brazil
2
Mexico
3,6
Bulgaria (EU) Morocco
Canada Netherlands (EU)
Chile New Zealand
4
China Nigeria
Columbia Norway
Croatia Oman
Cyprus (EU) Pakistan
Czech Republic (EU) Paraguay
Denmark (EU) Peru
Ecuador Philippines
Egypt Poland (EU)
El Salvador Portugal (EU)
Finland (EU) Romania (EU)
AN94
128 Rev. 0.3
France (EU) Russia
Germany (EU) Saudi Arabia
Greece (EU) Singapore
Guam Slovakia (EU)
Hong Kong Slovenia (EU)
Hungary (EU) South Africa
5,6
Iceland South Korea6
India Spain (EU)
Indonesia Sweden (EU)
Ireland (EU) Switzerland
Israel Taiwan
Italy (EU) Thailand
Japan
3
UAE
Jordan United Kingdom (EU)
Kazakhstan USA
Kuwait Yemen
Latvia (EU)
Notes:
1. Additional components required; contact Silicon Labs. Per current PTT
recommendations, only DTMF dialing is supported.
2. Component value changes required; Contact Silicon Labs.
3. DCT bit must be set to 1.
4. 600 O ac termination requires disclaimer in product documentation.
5. Additional surge components required; Contact Silicon Labs.
6. Additional components required to pass on-hook or ringer impedance
specifications. See "Ringer Impedance" on page 131.
Table 37. Country Support List (Continued)
Supported Countries
AN94
Rev. 0.3 129
A feature comparison between the Si3010, Si3008, and Si3006 is presented in Table 38. This table is designed to
present a quick capability comparison of the three parts to enable the selection of the best DAA chip for a particular
design.
The Si3006 supports parallel handset off-hook/on-hook detection in both the on- and off-hook modes. Loop current
is measured with 1.1 mA/bit resolution by the LCS bits. The LCS bits V loop current response is shown in Figure 27
on page 114, and the LCS transfer function is explained in Table 33 on page 114. The DC I/V characteristic is
illustrated in Figure 28 on page 115. It meets the requirements of the countries listed in Table 37 on page 127. The
Si3006 provides a ringer impedance of approximately 5 MO. It has an on-hook line monitor mode that supports
Type 1, Type 2 and UK Caller ID.
The Si3006 meets the DTMF and pulse dialing requirements for the countries in Table 37. Higher DTMF signal
levels than those required can be achieved.
Sufficiently high DTMF levels will clip due to the output signal level limitations of the Si3006. DTMF distortion
between 1020% is generally acceptable.
Loop current limiting (previously required by CTR/TBR-21 countries such as France) is not supported by the
Si3006. Although current limiting is no longer required for certification, some customers require it for backward
compatibility.
Table 38. DAA Feature Comparison
Feature Name Name Si3010 Si3008 Si3006
Type I Caller ID X X X
Type II Caller ID Snoop X X X
UK Caller ID X X X
Parallel phone detection X X X
On-hook intrusion X X X
Loop current limiting ILIM X
Loop current loss detection LCLD X X
Minimum loop current MINI X
Loop voltage adjust DCV X
DC impedance selection DCR X
AC impedance selection ACT X
Ringer impedance RZ X
Billing tone enable BTE X
Billing tone detect BTD X
On-hook speed OHS X
AN94
130 Rev. 0.3
Reference Design
The Si3006 and Si3008 require fewer peripheral components, in particular fewer expensive high voltage
transistors, that the Si3010. Table 39 compares the Si3010, Si3008 and Si3006 requirements for peripheral
components.
Table 39. Si3010, Si3008, Si3006 Peripheral Component Requirements
Component Si3010 Si3008 Si3006
Resistors 1/16 W 9 12 10
Resistors 3/4 W 3 2 1
Resistors 1/2 W 0 0 1
Resistors 1/4 W 0 0 1
Resistors 1/8 W 0 0 1
Capacitors (NPO) 11 2 2
Capacitors (X7R) 0 8 8
Capacitors (polar) 1 0 0
Y2/Y3 capacitors 4 4 4
Diode bridge 1 1 1
Zener diodes 1 2 2
pnp transistors 1 1 2
npn transistors 4 2 1
Ferrite beads 4 4 4
SiDactor 1 1 1
Crystal 1 1 1
Total Components 41 39 39
AN94
Rev. 0.3 131
Ringer Impedance
The ring detector in many DAAs is ac-coupled to the line with a large 1 F, 250 V decoupling capacitor. The ring
detector on the Si3006 is resistively coupled to the line. The network presents a high ringer impedance to the line
of approximately 5 MO to meet the majority of PTT specifications, including FCC. Certain countries have specific
on-hook and/or ringer impedance requirements, e.g., Mexico, South Africa, and South Korea. The ringer
impedance network shown in Figure 37 is required for compliance with these specifications.
This network is only required if the application will be deployed in one of these countries. However, it is
recommended that it be included on all DAA PCB layouts, space permitting. This provides maximum flexibility.
International telecommunications requirements are subject to change. The test setup and the interpretation of a
specification can vary from one test facility to another. If the network is not required, the components are simply not
populated. The network components for each country are detailed in Tables 40, 41, and 42.
Figure 37. Universal Oh-Hook/Ringer Impedance Network
R55b
Z2
Z3
RING
R56
C15
R55a
TIP
AN94
132 Rev. 0.3
Table 40. South Korea Ringer Impedance Network Components
Component Value PCB Footprint Part Number Supplier(s)
C15 1 F, 25 V CC0805 ECJ-2FB1E105K Panasonic
R55a
1
15 kO, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel
R55b
1
15 kO, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel
R56 Not installed N/A N/A N/A
Z2 18 V, 200 mW SOD323
2
BZT52C18S Diodes, Inc.
Z3 18 V, 200 mW SOD323
2
BZT52C18S Diodes, Inc.
Notes:
1. R55 may be a single resistor of equal or higher power and voltage rating.
2. Z2 and Z3 may be a dual device in a SOT23 or similar package of equal or greater power rating.
Table 41. South Africa Ringer Impedance Network Components
Component Value PCB Footprint Part Number Supplier(s)
C15 0.47 F, 50 V CC0805 GRM21BR71H474KA88L Murata
R55a
1
15 kO, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel
R55b
1
15 kO, 5%, 1/4 W, 200 V R1206 CR1206-4W-153J Venkel
R56 Not installed N/A N/A N/A
Z2 18 V, 200 mW SOD323
2
BZT52C18S Diodes, Inc.
Z3 18 V, 200 mW SOD323
2
BZT52C18S Diodes, Inc.
Notes:
1. R55 may be a single resistor of equal or higher power and voltage rating.
2. Z2 and Z3 may be a dual device in a SOT23 or similar package of equal or greater power rating.
Table 42. Mexico On-Hook Impedance Network Components
Component Value PCB Footprint Part Number Supplier(s)
C15 0.047 F, 250V CC0805 C0805X7R101-473JNE Venkel
R55a
*
11.5 kO, 1%, 1/8 W R1206 CR1206-8W-1152FT Venkel
R55b
*
11.5 kO, 1%, 1/8 W R1206 CR1206-8W-1152FT Venkel
R56 0 O R0402 CR0402-16W-000T Venkel
Z2 Not installed N/A N/A N/A
Z3 Not installed N/A N/A N/A
*Note: R55 may be a single resistor of equal or higher power and voltage rating.
AN94
Rev. 0.3 133
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134 Rev. 0.3
Table 43. Bill of Materials: Si24xx Daughter Card
Component Description PCB Footprint Part Number Supplier(s)
C1,C2 33 pF, Y2 X7R 10% C1808-GF-Y2 GA342D1XGF330JY02L Panasonic, Murata, Vishay
C4 1.0 F, 35 V, Elect X7R 20% CC1206 GRM31MR71H105KA88L Panasonic
C5 0.1 F, 16 V, X7R 20% CC0603 C0603X7R160-104MNE Venkel, SMEC
C6 1.5 nF, 250 V, X7R 20% CC0805 C0805X7R251-153MNE Venkel, SMEC
C8,C9 680 pF, Y3, X7R 10% C1808-GD-Y3 GA342QR7GD681KW01L Panasonic, Murata, Vishay
C11 27 pF, 250 V, X7R 20% CC0603 C1608C0G2E270J TDK, Venkel, SMEC
C40,C41
1
33 pF, 16 V, NPO 5% CC0603 C0603NPO160-330JNE Venkel, SMEC
C50,C51,
C52,C53
0.1 F, 16 V, X7R 20% CC0603 C0603X7R160-104MNE Venkel, SMEC
D1, D2 Dual Diode 300 V
2
SOT-23 MMBD2400S Central Semiconductor
FB1,FB2,
R15,R16
Ferrite Bead / Resistor
3
RC0603 CR0603-16W-104JT Murata
Q1 PNP 300 V
4
SOT-23
4
MMBT6520LT1 On Semiconductor
Q2 PNP 300 V SOT-23
4
MMBTA92LT1 On Semiconductor
Q3 NPN 300 V SOT-23 MMBTA42LT1 On Semiconductor
RV1 Sidactor 275 V, 100 A
4
SDO6 P3100SB Teccor, LittelFuse,ST Micro,Protek
R1 158 O, 3/4 W
5,6,7
, 1% RC1206 x 3
CR2010-1W-1580FT
Venkel, SMEC, Panasonic
R2 261 O, 1/2 W
8
1% RC1206 x 2 CR1210-2W-2610FT Venkel, SMEC, Panasonic
R5 200 O
4
, 1/16 W 5% RC0603 CR0603-16W-201JT Venkel, SMEC, Panasonic
R8 2.2 MO, 1/8 W 5% RC0805 CR0805-8W-225JT Venkel, SMEC, Panasonic
R10 1 kO, 1/16 W 5% RC0603 CR0603-16W-102JT Venkel, SMEC, Panasonic
R12,R13 56 O, 1/16 W 1% RC0603 CR0603-16W-560FT Venkel, SMEC, Panasonic
R14 910 O, 1/4 W 5% RC1206 CR1206-4W-911JT Venkel, SMEC, Panasonic
Notes:
1. In STB applications, C40, C41, and Y1 can be removed by using the 27 MHz clock input feature.
2. Diode Bridge (D1, D2) can be four diodes such as 1N4001, dual diodes such as MMBD3004S as shown, or a single-
chip diode bridge, such as DF04S.
3. R15 and R16 may be populated with either ferrite beads or 0 O resistors as needed to comply with radiated emissions.
4. For Brazil, use 2SA1776 for Q1 and 170 V sidactor (Littlefuse PI800SBLRP).
5. Three (3) 475 O, 1/4 W resistors in parallel may be used to achieve the resistance value and power rating shown.
6. For Chile, the value of R1 must be raised to 200 O @ 3/4W or three 604 O 1/4 W resistors.
7. For Australia, make R1 = 130 O, 3/4 W, while R
Z
is a series combination of an R
ZA
(120 O, 1/4 W) and an R
ZB
(150 O,
1/4 W). Shunt R
ZB
with a 150 nF, 50 V, 20%, X7R capacitor.
8. Two (2) 523 O, 1/4W resistors in parallel may be used to achieve the resistance value and power rating shown.
9. To ensure compliance with ITU specifications frequency tolerance must be less than 100 ppm including initial accuracy,
5-year aging, 0 to 70 C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this requirement.
AN94
Rev. 0.3 135
R19 75 kO, 1/16 W 5% RC0603 CR0603-16W-753JT Venkel, SMEC, Panasonic
R20,R21 3 MO, 1/16 W 5% RC0603 CR0603-16W-305JT Venkel, SMEC, Panasonic
R31 6.2 kO, 1/16 W 5% RC0603 CR0603-16W-622JT Venkel, SMEC, Panasonic
R32 2 kO, 1/16 W 5% RC0603 CR0603-16W-202JT Venkel, SMEC, Panasonic
R35 2.7 MO, 1/16 W 5% RC0603 CR0603-16W-275JT Venkel, SMEC, Panasonic
U1 Modem IC SOIC-16 Si2401-FS Silicon Laboratories
U2 DAA IC MSOP-10 Si3006-B-FT Silicon Laboratories
Y1
1,7,9
4.9152 MHz, 20 pF, 100 ppm,
150 O ESR
7,8
XTAL-ATS-SM 559-FOXSD049-20 CTS Reeves, ECS, Siward
Z1 20 V, 1/4 W AZ23C20 SOT-23 AZ23C20 Vishay
Table 43. Bill of Materials: Si24xx Daughter Card (Continued)
Component Description PCB Footprint Part Number Supplier(s)
Notes:
1. In STB applications, C40, C41, and Y1 can be removed by using the 27 MHz clock input feature.
2. Diode Bridge (D1, D2) can be four diodes such as 1N4001, dual diodes such as MMBD3004S as shown, or a single-
chip diode bridge, such as DF04S.
3. R15 and R16 may be populated with either ferrite beads or 0 O resistors as needed to comply with radiated emissions.
4. For Brazil, use 2SA1776 for Q1 and 170 V sidactor (Littlefuse PI800SBLRP).
5. Three (3) 475 O, 1/4 W resistors in parallel may be used to achieve the resistance value and power rating shown.
6. For Chile, the value of R1 must be raised to 200 O @ 3/4W or three 604 O 1/4 W resistors.
7. For Australia, make R1 = 130 O, 3/4 W, while R
Z
is a series combination of an R
ZA
(120 O, 1/4 W) and an R
ZB
(150 O,
1/4 W). Shunt R
ZB
with a 150 nF, 50 V, 20%, X7R capacitor.
8. Two (2) 523 O, 1/4W resistors in parallel may be used to achieve the resistance value and power rating shown.
9. To ensure compliance with ITU specifications frequency tolerance must be less than 100 ppm including initial accuracy,
5-year aging, 0 to 70 C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this requirement.
AN94
136 Rev. 0.3
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142 Rev. 0.3
APPENDIX FSi2401/Si3008 PROTOTYPE BRING-UP GUIDE
Introduction
This appendix provides help with the debugging of initial
prototypes. Although most ISOmodem

prototype
designs function as expected, there is the potential for
layout errors, omitted or incorrect components used in
the initial assembly run, and host software problems. If
the prototype modem does not function correctly, the
techniques outlined in this guide will help quickly isolate
the problem and get the prototype functioning correctly.
A functional Si2401URT-EVB and data sheet and a
computer with HyperTerm is required for some of the
troubleshooting steps. It is assumed that the designer
has read the data sheet, used the reference design and
recommended bill-of-materials, and has carefully
followed the layout guidelines presented in
Appendix AISOmodem Layout Guidelines. The
troubleshooting steps begin with system-level checks,
and then proceed to the component level.
Visual Inspection
Before troubleshooting, be certain that the circuit boards
and components are clean. Carefully wash the boards
to remove all solder flux and solder flakes. Inspect the
modem circuitry to ensure all components are installed,
and inspect all solder joints for incomplete connections,
cold solder joints, and solder bridges. Check all
polarized components, such as diodes, Zener diodes,
and capacitors for correct orientation. Thoroughly clean
the circuit board after replacing a component or
soldering any connections.
Reset the Modem
Be sure the modem is properly reset after power is
applied and stable.
Basic Troubleshooting Steps
Check Power
With power off, use an Ohm meter to verify system
ground is connected to Si2401 pin 12. Turn on
system power and measure the voltage between
pin 4 and pin 12 and between pin 13 and pin 12 on
the Si2401. In both cases, the voltage should be
3.3 V. If this is not the case, check the power routing.
If power is present, go to the next step.
Check Phone Line
Check the phone line with a manual telephone to be
sure there is a dial tone and dialing is possible. The
dc voltage across TIP and RING should read
approximately 4052 V with the phone on-hook.
Reset Modem
Do a manual reset on the modem. Hold Si2401 pin 8
(RESET) low for 300 ms, return to V
DD
(3.3 V) in
less than 5 ms and wait for at least 300 ms before
executing the first AT command.
Check DTE Setup
Be sure the DTE (Host) serial port is configured the
same as the modem. The default condition is eight
data bits, no parity-bit, one stop-bit, and a DTE rate
of 2400 bps.
Check DTE Connection
Check the DTE interface connection. Be sure the
CTS (Si2401 pin 7) signal is low.
Check pullup/pulldown configuration resistor.
Check modem configuration
Read back the modem register settings and correct any
inconsistencies. Use the ATSR or ATr# commands to
list the contents of the S-Registers.
If the problem was not located with these basic
troubleshooting steps, it is time to narrow the problem
down to the host system (hardware and software), the
Si2401 chip (and associated components), or the
Si3008 (and associated components).
AT OK?
The modem responds with an O to the command
AT<cr>.
This indicates the host processor/software is
communicating with the modem controller and problems
are in one of the following areas:
Inappropriate Commands
Verify that all AT commands used are supported by
the Si2401 and comply with the proper format. Be
sure the command and argument are correct. Do not
mix upper and lower case alpha characters in an AT
command (except the r, m, q, and w
commands).
Command Timing
The execution time for an AT command is
approximately 200 ms. Execution is complete when
the O is received. Subsequent AT commands
should wait for the O message, which appears
within 100 ms after the carriage return. The reset
recovery time (the time between a hardware reset or
the carriage return of an ATZ command and the time
the next AT command can be executed) is
approximately 100 ms. When a data connection is
being established, do not try to escape to the
AN94
Rev. 0.3 143
command mode until after the protocol message.
Si3008 and/or Associated Components
If the modem goes off-hook and draws loop current
as a result of giving the ATH1 command, go to the
Si3008 Troubleshooting section.
If the modem does not go off-hook and draw loop
current as a result of giving the ATH1 command and
receiving an O message, begin troubleshooting
with the isolation capacitor at the Si2401. First check
all solder joints on the isolation capacitors, Si3008,
and associated external components. If no problems
are found, proceed to the following Troubleshooting
section to verify whether the problem is on the
Si2401 or the Si3008 side of the isolation barrier. If
the problem is found to be on the Si2401 side, check
C50, C51, C53, the corresponding PCB traces, and
Si2401 pins. Correct any problems. If no problems
are found with the external components, replace the
Si2401.
If the problem is found to be on the Si3008 side of
the isolation barrier, go to the Si3008
Troubleshooting section.
If the modem does NOT respond with an O to the
command AT<cr>,
this indicates the host processor/software is not
communicating with the modem controller, and the
problem can be isolated as follows.
Si2401 Clock is Oscillating
First be sure the Si2401 is properly reset and
RESET, pin 8, is at 3.3 V. Next, check the DTE
connection with the host system. If this does not
isolate the problem, go to the Host Interface
Troubleshooting section.
Si2401 Clock is Not Oscillating
Check the voltage on the Si2401, pin 4, to be sure
the chip is powered. Also, check that pin 12 is
grounded. Next, check the solder joints and
connections (PCB traces) on C40, C41, Y1 and the
Si2401 pin 1 and pin 2. Measure C26 and C27 (or
replace them with known good parts) to ensure they
are the correct value. If these steps do not isolate the
problem, replace the Si2401.
Host Interface Troubleshooting
The methods described in this section are useful as a
starting point for debugging a prototype system or as a
continuation of the troubleshooting process described
above. The procedures presented in this section require
a known good Si2401URT-EVB evaluation board and
data sheet. This section describes how to substitute the
evaluation board for the entire modem circuitry in the
prototype system. Substituting a known operational
modem can help to quickly isolate problems. The first
step is to substitute the evaluation board for the
complete modem solution in the prototype system. This
demonstrates immediately whether any modem
functionality problems are in the prototype modem
circuitry or in the host processor, interface, or software.
Verify Si2401URT-EVB Functionality
Connect the evaluation board to a PC and a phone
line or telephone line simulator. Using a program
such as HyperTerm, make a data connection
between the evaluation board and a remote modem.
Remove power and the RS232 cable from the
evaluation board and proceed to the next step.
Connect Evaluation Board to Prototype System
Completely disconnect the embedded modem from
the host interface in the prototype system. Connect
the Si2401URT-EVB to the host interface using JP3
as described in the Si2401URT-EVB data sheet
section titled Direct Access Interface. This
connection is illustrated in Figure 22. Be sure to
connect the evaluation board ground to the
prototype system ground. Power up and manually
reset the evaluation board then power up the
prototype system and send AT<cr>. If an OK
response is received, make a connection to the
remote modem as in the previous step. If no OK
response is received, debug host interface and/or
software. If a connection is successfully made, go to
the next step to isolate the problem in the prototype
modem.
An alternative approach is to connect the prototype
modem to the Si2401URT-EVB motherboard in
place of the daughter card and use a PC and
HyperTerm to test the prototype modem. See Figure
Figure 23 for details.
Troubleshooting
Connect Evaluation Board isolation capacitors to
Prototype Modem Si3008. Remove C1 on the
evaluation board and on the prototype system. Solder
one end of the evaluation board, C1, to the Si2401-side
pad leaving the other end of C1 unconnected. Next,
solder a short jumper wire from the unconnected side of
C1 on the evaluation board to the Si3008-side C1 pad
on the prototype system. This connection is illustrated in
Figure 24. Connect the phone line to the prototype
system RJ-11 jack.
Power up and manually reset the evaluation board, then
power up the prototype system. Attempt to make a
connection using the host processor and software, the
evaluation board Si2401 and the prototype system
Si3008 and associated external components. If this
connection is successful, the problem lies with the PCB
layout, the external components associated with the
Si2401 or the Si2401 device itself.
AN94
144 Rev. 0.3
If the connection attempt is not successful, the problem
lies with the Si3008 and/or associated components.
Proceed to the section, Si3008 Troubleshooting.
This diagnosis can be validated by connecting the Host
isolation capacitors to the Si3008 on the evaluation
board as shown in Figure 25.
Si3008 Troubleshooting
Start by measuring the on-hook and off-hook voltages at
the Si3008 pins with respect to IGND (pin 15). Compare
these voltages to those in Figure 26. This may indicate
an area of circuitry to investigate further using the
Component Troubleshooting techniques. The voltages
you measure should be close to (although not exactly
the same as) those in the figure.
If any of the on-hook and off-hook Si3008 pin voltages
are grossly different than those in Figure 26 and nothing
seems wrong with the external circuitry after using the
Component Troubleshooting techniques, replace the
Si3008.
Component Troubleshooting
A digital multi-meter is a valuable tool to verify
resistance across components, diode direction,
transistor polarity and node voltages. During this phase
of troubleshooting, it is highly useful to have a known
good Si2401URT-EVB to compare against
measurements taken from the prototype system. The
resistance values and voltages listed in Tables 24, 25,
and 26 will generally be sufficient to troubleshoot all but
the most unusual problem.
Start with power off and the phone line disconnected.
Measure the resistance of all Si3008 pins with respect
to pin 9 (IGND). Compare these measurements with the
values in Table 24. Next, measure the resistance across
the components listed in Table 25 and compare the
readings to the values listed in the table. Finally, using
the diode checker function on the multi-meter, check the
polarities of the transistors as described in Table 26.
The combination of these measurements should
indicate the faulty component or connection. If none of
the measurements appears unusual and the prototype
modem is not working, replace the Si3008.
Figure 45. Test the Host Interface
Host
Controller
Host
UART
Si2401 Si3008 Discretes
RS232
Transceiver
Si2401 Si3008 Discretes
EVB
Prototype System
To
Phone
Line
Connect prototype system ground to EVB ground
Disable RS232 transceiver outputs (check evaluation board data sheet)
Disconnect prototype modem interface
Connect the evaluation board to the target system
AN94
Rev. 0.3 145
Figure 46. Test the Prototype Modem
Figure 47. Test the Prototype Si3008 Circuitry
Host
Controller
Host
UART
Si2401 Si3008 Discretes
RS232
Transceiver
Si2401 Si3008 Discretes
EVB
Prototype System
Connect prototype system ground to EVB ground
Remove modem module from EVB
Disconnect host outputs from prototype modem
Connect EVB RS232 transceivers to prototype modem
Use PC with HyperTerminal to test prototype modem
To
Phone
Line
PC
To
Phone
Line
Host
Controller
Host
UART
Si2401 Si3008 Discretes
RS232
Transceiver
Si2401 Si3008 Discretes
EVB
Connect the prototype ground to the EVB ground.
Lift prototype C1 and C2 and EVB C1 and C2 so the Si3008 is disconnected from the Si2401 on both modems.
Connect EVB C1 and C2 to the Si3008 pad of prototype system C1 and C2.
Connect the phone line to the RJ11 jack on the prototype system.
Use PC and HyperTerm and attempt to establish a modem connection.
PC
C2
C1
C2
Prototype System
C1
AN94
146 Rev. 0.3
Figure 48. Verify Prototype Si3008 Failure
Figure 49. Si3008 Typical Voltages
Figure 50. Si3008 In-Circuit Resistance to IGND (Si3008 Pin 9)
To
Phone
Line
Host
Controller
Host
UART
Si2401 Si3008 Discretes
RS232
Transceiver
Si2401 Si3008 Discretes
EVB
Connect the prototype ground to the EVB ground
Lift prototype and EVB C1 and C2 to decouple the line side from the DSP side. Do same on evaluation board.
Connect prototype system C1 and C2 to the Si3008 pad of EVB C1 and C2
Connect the phone line to the RJ11 jack on the EVB
Run the prototype system software to attempt a modem connection
C2
C1
C2
C1
Prototype System
On-Hook
0.54 V
1.0 V
2.3 V
0.88 V
C1B
CID
VREG
C2B
0.04 V
0.52 V
0.06 V
0.05 V
DCT2
VREG2
QE2
DCT3
Voltages measured with respect to IGND (Si3008 pin 9)
Off-Hook
N/A
1.0 V
2.3 V
N/A
C1B
CID
VREG
C2B
1.1 V
1.7 V
2.3 V
3.0 V
Rx
QE
QB
DCT
Resistance measured with power and phone line removed
2.7 MO
1.6 MO
480 kO
C1B
CID
VREG
C2B
180 kO
Rx
QE
QB
DCT 2.7 MO
2.6 MO
1.4 MO
1.4 MO
AN94
Rev. 0.3 147
Table 44. Resistance across Components
Si3008 Circuit Component Resistance
FB1 <1 O
FB2 <1 O
RV1 >10 MO
R1 206 O
R2 243 O
R4 3.8 kO
R5 4.0 kO
R6 100 kO
R7 2.7 MO / 8.4 MO
R8 2.7 MO / 8.7 MO
R10 1.0 kO
R12 56 O
R13 56 O
R15 <1 O
R16 <1 O
R18 1.3 MO / 1.6 MO
R19 165 kO
R20 1.6 MO
R21 1.6 MO
C1 >20 MO
C2 >20 MO
C3 2.8 MO / >20 MO
C4 4.5 MO / 3.3 MO
C5 440 kO
C8 >20 MO
C9 >20 MO
C11 3.2 MO / 3.0 MO
Note: If two values are given, the resistance measured is dependent upon polarity.
Table 45. Voltage across Components with Diode Checker
Component Voltage
Q1, Q3
Base to Emitter
Base to Collector
Verifies transistors are NPN
0.6 V
0.6 V
Q2
Emitter to Base
Collector to Base
Verifies transistor is PNP
0.6 V
0.6 V
AN94
148 Rev. 0.3
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed heading levels.
Updated Table 20, Si2401 Country Table, on
page 80.
Added "Appendix DSi3008 Supplement" on page
112.
Revision 0.2 to Revision 0.3
Added "Appendix ESi3006 Supplement" on page
127.
AN94
I NDEX
Rev. 0.3 149
A
AC Termination 10
Answer 18
assembly 90, 98, 142
AT Command Set 18
B
Basic Troubleshooting Steps 98, 142
Bias Circuitry 6, 8
C
call progress monitor 20
Caller ID 22, 34, 36, 38, 74, 113
Carrier Detect 5, 32, 33, 34, 72
Carrier detect 27
Command
mode 17
Timing 98
Compliance 4
compliance 4, 6, 7
Component Troubleshooting 100
Controller 17
controller 5, 6, 7, 10, 98
Crystal Oscillator 6
crystal oscillator 6
D
DAA (Line-Side) Chip 7
default settings 110
Digital Interface 15
DSP 15, 65, 66
DTE 75, 76, 107
Connection 98, 142
Setup 98, 142
E
EMC 7, 9, 13, 96, 112
EMI 9, 13, 97, 112, 126
Emissions 10
emissions 6, 7
Escape 35
escape 16, 17, 20, 21
methods 1, 15
H
Hardware
Design Reference 5
reset 20
HDLC 36, 64, 75, 78
I
Intrusion Detection 69
intrusion detection 105
Isolation 92, 99, 112
Interface 7
ISOmodem 69, 92
L
Layout Guidelines 92, 94, 118
Loop
Current 10, 99, 113, 114
Voltage 113
M
manual reset 98, 142
memory 6, 15
Modem 6
modem 4, 5
Modulations 5
O
Off-Hook 12, 18, 19, 22, 36, 69, 72, 108
On-Hook 8, 11, 18, 35, 56, 69, 108, 109, 113
Oscillator 6
P
PLL 6
Power
Control 15
Supply 6, 8
Program ROM 15
Programming Examples 69
Protocols 5
Prototype Bring-Up Guide 98, 142
R
Receive Carrier 5
Reference Design 6, 115, 130
RESET 97, 126
Reset 17, 20, 25, 97, 98, 105, 142
Result Codes 20, 22, 39
Ringer
Impedance 131
Network 8
ROM 15
RTS 41, 76
S
Safety 91
Serial Interface 6, 7, 15, 16
Si3010 Troubleshooting 100
S-Registers 25, 65, 77, 98, 142
surge performance 92, 112, 118
switch-hook 5
System Interface 7
T
Testing 87, 89, 90, 91
Transmit Carrier 5
Troubleshooting 98, 99, 100, 104, 105, 142, 143, 144
Typical Voltages 102, 146
U
UART 15, 16, 75, 105
V
Visual Inspection 98, 142
AN94
150 Rev. 0.3
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