Xilinx Library

Libraries Guide
ISE 6.li
"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.
The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACTFloorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2003 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.
Libraries Guide
www.xilinx.com 1-800-255-7778
ISE 6.li
About This Guide

The Libraries Guide is part of the ISE documentation collection.
Guide Contents
This guide contains the following: Discussion of the Xilinx Unified Libraries Slice Count information for FPGAs A listing of the various Functional Categories of design elements Architecture Specific Information chapters Individual chapters for each of the Design Elements
Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.
Resource Tutorials Description/URL Tutorials covering Xilinx design flows, from design entry to verification and debugging
http://support.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser
Database of Xilinx solution records http://support.xilinx.com/xlnx/xil_ans_browser.jsp
Application Notes Data Book
Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm

Pages from The Programmable Logic Data Book, which contains devicespecific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging
http://support.xilinx.com/partinfo/databook.htm
Problem Solvers Tech Tips Interactive tools that allow you to troubleshoot your design issues
http://support.xilinx.com/support/troubleshoot/psolvers.htm
Latest news, design tips, and patch information for the Xilinx design environment
http://www.support.xilinx.com/xlnx/xil_tt_home.jsp
Libraries Guide ISE 6.li
About This Guide
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention Courier font Courier bold Meaning or Use Messages, prompts, and program files that the system displays Example speed grade: - 100
Literal commands that you enter in ngdbuild design_name a syntactical statement Commands that you select from a menu Keyboard shortcuts
Helvetica bold
File Open Ctrl+C
Italic font
Variables in a syntax statement for ngdbuild design_name which you must supply values References to other manuals See the Development System Reference Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. ngdbuild [option_name] design_name
Emphasis in text
Square brackets [ ]
An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required. A list of items from which you must choose one or more Separates items in a list of choices Repetitive material that has been omitted
Braces
{ }
lowpwr ={on|off} lowpwr ={on|off} IOB #1: Name = QOUT IOB #2: Name = CLKIN . . . allow block block_name loc1 loc2 ... locn;
Vertical bar | Vertical ellipsis . . . Horizontal ellipsis . . .
Repetitive material that has been omitted
Online Document
The following conventions are used in this document:
Convention Blue text Red text Meaning or Use Example
Cross-reference link to a location See the section Additional in the current document Resources for details. Cross-reference link to a location See Figure 2-5 in the Virtex-II in another document Handbook. Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.
Blue, underlined text
Whats New in This Release
Whats New in This Release

The following design elements have been removed from the current release:
GT10_3GIO_n MUXF8_D MUXF8_L
The following design elements have been added to the current release: IBUFDS_DIFF_OUT
About This Guide
Table of Contents
About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Whats New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Xilinx Unified Libraries

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applicable Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attributes and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 18 18 18 18 19 19
19 Spartan-II, Spartan-IIE, Virtex, and Virtex-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3 . . . . . . . . . . . . . . . . . . . . . . . . . 20
Flip-Flop, Counter, and Register Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Unconnected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Slice Count
About Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Slice Count for FPGA Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Architecture Specific Information

Spartan-II and Spartan-IIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex and Virtex-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-II, Virtex-II Pro, Virtex-II Pro X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9500/XV/XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CoolRunner XPLA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CoolRunner-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39 41 45 47 51 53 55
Functional Categories
Arithmetic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Input Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Input/Output Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Input/Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Logic Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Map Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Memory Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Design Elements
ACC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACC4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADSU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADSU4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRLSHFT4, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUF4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGDLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGMUX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107 111 119 121 127 131 137 145 149 153 155 157 159 161 163 165 167 171 173 175 177 179 181 183 185
BUFGTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2CE, CB4CE, CB8CE, CB16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2CLE, CB4CLE, CB8CLE, CB16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2CLED, CB4CLED, CB8CLED, CB16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2RE, CB4RE, CB8RE, CB16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2RLE, CB4RLE, CB8RLE, CB16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2X1, CB4X1, CB8X1, CB16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2X2, CB4X2, CB8X2, CB16X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2CE, CBD4CE, CBD8CE, CBD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED . . . . . . . . . . . . . . . . . . . . . . . CBD2RE, CBD4RE, CBD8RE, CBD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2X1, CBD4X1, CBD8X1, CBD16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2X2, CBD4X2, CBD8X2, CBD16X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8CE, CC16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8CLE, CC16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8CLED, CC16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8RE, CC16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJ4CE, CJ5CE, CJ8CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJ4RE, CJ5RE, CJ8RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJD4CE, CJD5CE, CJD8CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJD4RE, CJD5RE, CJD8RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16RSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKDLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKDLLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
187 189 193 195 197 199 201 207 213 219 223 227 233 239 243 247 253 257 261 265 271 277 283 289 295 299 303 307 313 317 321 325 331 335 339 343 347 349 351 353 355 359
CLKDLLHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMP2, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMPM2, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMPMC8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR8CE, CR16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRD8CE, CRD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D2_4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D3_8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D4_16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEC_CC4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DECODE4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DECODE32, 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD4CE, FD8CE, FD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD4RE, FD8RE, FD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDC_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD4,8,16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD4CE, FDD8CE, FDD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD4RE, FDD8RE, FDD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
363 367 371 377 381 385 389 391 395 399 409 411 415 417 421 423 425 429 433 437 441 445 449 453 457 461 465 469 471 473 477 481 485 489 493 497 501 503 507 509 513 517
10
FDDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDR_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRS_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRSE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDS_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTDCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
519 521 523 525 527 531 535 539 543 547 551 555 559 563 567 571 575 579 583 587 591 595 599 601 603 607 611 615 619 623 627 631 635 637 641 645 649 653 657 659 663 665
11
FTDCLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 FTDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 FTDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 FTDRSLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 FTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 FTPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 FTPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 FTRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 FTRSLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 FTSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 FTSRLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 GT_AURORA_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 GT_CUSTOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 GT_ETHERNET_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 GT_FIBRE_CHAN_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 GT_INFINIBAND_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 GT_XAUI_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 GT10_AURORA_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 GT10_AURORAX_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 GT10_CUSTOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 GT10_INFINIBAND_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 GT10_XAUI_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 GT10_10GE_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 GT10_10GFC_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 GT10_OC48_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 GT10_OC192_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 GT10_PCI_EXPRESS_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 IBUF, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 IBUF_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 IBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 IBUFG, IBUFG_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 IBUFGDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 IBUFGDS_DIFF_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 ICAP_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043 IFD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 IFD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 IFDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 IFDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 IFDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059 IFDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 IFDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
12
IFDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INV, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOBUF, IOBUF_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAGPPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KEEPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDC_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD4CE, LD8CE, LD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDG4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LUT1, 2, 3, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LUT1_D, LUT2_D, LUT3_D, LUT4_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LUT1_L, LUT2_L, LUT3_L, LUT4_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1067 1069 1071 1073 1077 1079 1081 1083 1087 1089 1091 1093 1095 1101 1103 1105 1107 1109 1111 1115 1117 1121 1125 1129 1133 1137 1141 1145 1149 1153 1157 1161 1165 1167 1169 1173 1177 1181 1185 1191 1197 1203
13
M2_1B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2_1B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M8_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M16_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULT_AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULT18X18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULT18X18S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXCY_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXCY_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF5_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF5_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF6_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF6_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF7_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF7_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUF, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUF_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFT_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFTDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRTCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRTRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1205 1207 1209 1211 1213 1217 1221 1223 1225 1227 1229 1231 1233 1235 1237 1239 1241 1243 1245 1247 1249 1251 1253 1259 1263 1271 1275 1279 1285 1287 1291 1295 1301 1305 1311 1313 1315 1319 1323 1327 1331 1333
14
OFDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDT_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ORCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPC405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PULLDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PULLUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X2D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X4D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X4S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X8D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X8S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X4S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X8S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM128X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM128X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB4_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB4_Sm_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB16_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB16_Sm_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1337 1339 1343 1345 1349 1351 1353 1355 1357 1363 1367 1369 1385 1387 1389 1393 1397 1399 1403 1405 1409 1413 1417 1421 1425 1429 1433 1435 1439 1443 1447 1453 1457 1461 1465 1469 1473 1477 1481 1487 1497 1515
15
ROC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROCBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM32X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM64X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM128X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM256X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4CE, SR8CE, SR16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4CLE, SR8CLE, SR16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4CLED, SR8CLED, SR16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4RE, SR8RE, SR16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4RLE, SR8RLE, SR16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4RLED, SR8RLED, SR16RLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4CE, SRD8CE, SRD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4CLE, SRD8CLE, SRD16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4CLED, SRD8CLED, SRD16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4RE, SRD8RE, SRD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4RLE, SRD8RLE, SRD16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4RLED, SRD8RLED, SRD16RLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16E_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16E_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTBUF_architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOCBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XNOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XORCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XORCY_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XORCY_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1557 1559 1561 1563 1565 1567 1569 1571 1573 1577 1581 1587 1591 1595 1601 1605 1609 1613 1617 1621 1625 1629 1633 1637 1641 1645 1647 1651 1655 1657 1659 1663 1667 1671 1673 1675 1677 1679 1685 1691 1693 1695
16

This chapter describes the Unified Libraries and the applicable device architectures for each library. It also briefly discusses the contents of the other chapters, the general naming conventions, and performance issues. This chapter consists of the following major sections. Overview Applicable Architectures Functional Categories Design Elements Schematic Examples Naming Conventions Attributes and Constraints Carry Logic Flip-Flop, Counter, and Register Performance Unconnected Pins
Overview
Xilinx maintains software libraries with thousands of functional design elements (primitives and macros) for different device architectures. New functional elements are assembled with each release of development system software. The catalog of design elements is known as the Unified Libraries. Elements in these libraries are common to all Xilinx device architectures. This unified approach means that you can use your circuit design created with unified library elements across all current Xilinx device architectures that recognize the element you are using. Elements that exist in multiple architectures look and function the same, but their implementations might differ to make them more efficient for a particular architecture. A separate library still exists for each architecture (or architectural group) and common symbols are duplicated in each one, which is necessary for simulation (especially board level) where timing depends on a particular architecture. If you have active designs that were created with former Xilinx library primitives or macros, you may need to change references to the design elements that you were using to reflect the Unified Libraries elements. The Libraries Guide describes the primitive and macro logic elements available in the Unified Libraries for the Xilinx FPGA and CPLD devices. Common logic functions can be implemented with these elements and more complex functions can be built by combining macros and primitives. Several hundred design elements (primitives and
17
macros) are available across multiple device architectures, providing a common base for programmable logic designs. This libraries guide provides a functional selection guide and describes the design elements.
Applicable Architectures
Design elements for the Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex -II, Virtex-II Pro, Virtex-II Pro X, XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II libraries are included in the Xilinx Unified Libraries. Each library supports specific device architectures. For detailed information on the architectural families referenced below and the devices in each, see the current version of The Programmable Logic Data Book (an online version is available from the Xilinx web site, http://support.xilinx.com).
The functional categories list the available elements in each category along with a brief description of each element and an applicability table identifying which libraries (Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex -II, Virtex-II Pro, Virtex-II Pro X, XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II) contain the element.
Design Elements
Design elements are organized in alphanumeric order, with all numeric suffixes in ascending order. For example, FDR precedes FDRS, and ADD4 precedes ADD8, which precedes ADD16. The following information is provided for each library element, where applicable: Graphic symbol Applicability table (with primitive versus macro identification) Functional description Truth table Schematic for macros VHDL and Verilog instantiation and inference code Commonly used constraints
Schematic Examples
Schematics are included for each library if the implementation differs. Design elements with bussed or multiple I/O pins (2-, 4-, 8-, 16-bit versions) typically include just one schematic -- generally the 8-bit version. When only one schematic is included, implementation of the smaller and larger elements differs only in the number of sections. In cases where an 8-bit version is very large, an appropriate smaller element serves as the schematic example.
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Naming Conventions
Naming Conventions
Examples of the general naming conventions for the unified library elements are shown in the following figures.
Example 1 FUNCTION
Counter, Binary
SIZE
4-Bit
CONTROL PINS
Clear (Asynchronous)
Load
Clock Enable Bi-Directional
CB4CLED
Precedence of Control Pins
Example 2 FUNCTION
Flip-Flop, D-type
SIZE
16-Bit
CONTROL PINS
Reset (Synchronous) Clock Enable
FD16RE
X7764 Precedence of Control Pins
Naming Conventions
AND3B2
Logic Function Number of Inputs Inverting (Bubble) Inputs Number of Inverting Inputs
X4316
Combinatorial Naming Conventions
Attributes and Constraints

Attributes and constraints are instructions placed on components or nets to indicate their placement, implementation, naming, directionality, and so forth. The Constraints Guide provides information on all attributes and constraints.
Carry Logic
The Spartan-II, Spartan-IIE, Virtex, and Virtex-II architectures include dedicated carry logic components.
Spartan-II, Spartan-IIE, Virtex, and Virtex-E

Carry Logic for Spartan-II, Spartan-IIE, Virtex, and Virtex-E is a simple structure associated with each look-up table. The design entry library contains the following dedicated carry logic primitives: MULT_AND, MUXCY, MUXCY_D, MUXCY_L, XORCY, XORCY_D, and XORCY_L. The function performed is determined by their
19
connectivity and the contents of the look-up table. For an example of how to use carry logic, see CC8CE, CC16CE. For detailed information on Carry Logic in Virtex and Spartan-II, see The Programmable Logic Data Book available on the Xilinx web site, http:// support.xilinx.com.
Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3

The dedicated carry logic primitives for Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3 are MULT_AND, MUXCY, MUXCY_D, MUXCY_L, XORCY, XORCY_D, and XORCY_L. ORCY can only be used exclusively with Virtex-II, Virtex-II Pro, and Virtex-II Pro X. For detailed information on Carry Logic in Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3, see The Programmable Logic Data Book available on the Xilinx web site, http:/ /support.xilinx.com.
Flip-Flop, Counter, and Register Performance

All counter, register, and storage functions derived from the flip-flops are available in the Configurable Logic Blocks (CLBs). The D flip-flop is the basic building block for all architectures. Differences occur from the availability of asynchronous Clear (CLR) and Preset (PRE) inputs, and the source of the synchronous control signals, such as Clock Enable (CE), Clock (C), Load enable (L), synchronous Reset (R), and synchronous Set (S). The basic flip-flop configuration for each architecture follows. The basic XC9000 flip-flops have both Clear and Preset inputs.
PRE
FDCP
Q
CLR X4397
Virtex and Spartan-II have two basic flip-flop types. One has both Clear and Preset inputs and one has both asynchronous and synchronous control functions.
PRE
D CE C
FDCPE
Q
CLR X4389
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Flip-Flop, Counter, and Register Performance
D CE C
FDRSE
X3732
The asynchronous and synchronous control functions, when used, have a priority that is consistent across all devices and architectures. These inputs can be either activeHigh or active-Low as defined by the macro. The priority, from highest to lowest, is as follows. Asynchronous Clear (CLR) Asynchronous Preset (PRE) Synchronous Set (S) Synchronous Reset (R) Clock Enable (CE)
Note: The asynchronous CLR and PRE inputs, by definition, have priority over all the synchronous control and clock inputs. For FPGA families, the Clock Enable (CE) function is implemented using two different methods in the Xilinx Unified Libraries; both are shown in the following figure. In method 1, CE is implemented by connecting the CE pin of the macro directly to the dedicated Enable Clock (EC) pin of the internal Configurable Logic Block (CLB) flip-flop. This allows one CE per CLB. CE takes precedence over the L, S, and R inputs. All flip-flops with asynchronous clear or preset use this method. In method 2, CE is implemented using function generator logic. This allows two CEs per CLB. CE has the same priority as the L, S, and R inputs. All flip-flops with synchronous set or reset use this method.
The method used in a particular macro is indicated by the inclusion of asynchronous clear, asynchronous preset, synchronous set, or synchronous reset in the macro's description.
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CE
C1 C1 C2
Function Generator
X Function Generator
D C
D EC C
C2 CE
X=(CE * C2)+(CE * C1)
C1 C2
Function Generator
D EC C
C1 C2 CE
Function Generator
D C
Y=(CE * C1)+(CE * C2)
Method 1
CE implemented using dedicated EC pin.
Method 2
CE implemented as a function generator input. X4675
Clock Enable Implementation Methods
Unconnected Pins
Xilinx recommends that you always connect input pins in your designs. This ensures that front end simulation functionally matches back end timing simulation. If an input pin is left unconnected, mapper errors may result. If an output pin is left unconnected in your design, the corresponding function is trimmed. If the component has only one output, the entire component is trimmed. If the component has multiple outputs, the portion that drives the output is trimmed. As an example of the latter case, if the overflow pin (OFL) in an adder macro is unconnected, the logic that generates that term is trimmed, but the rest of the adder is retained (assuming all of the sum outputs are connected).
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Slice Count
This chapter contains the following sections. About Configurable Logic Blocks (CLBs) Slice Count for FPGA Components
About Configurable Logic Blocks (CLBs)

Configurable Logic Blocks (CLBs) implement most of the logic in an FPGA. Each Virtex, Virtex-E and Spartan-II, Spartan-IIE CLB contains two slices. Each Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X CLB contains four slices. In the following table, the numbers for Spartan-II, Spartan-IIE, Virtex, Virtex-E, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X are the number of slices required to implement the component. The Slice Count table lists FPGA design elements in alphanumeric order with the number of CLBs or slices needed for their implementation in each applicable library. Note: This information is for reference only. The actual count could vary, depending upon the switch settings of the implementation tools; for example, the effort level in PAR (Place and Route) or usage of the components with other components. The asterisk for the RAM16X1D and RAM16X1D_1 in the Spartan-3, Virtex-II, VirtexII Pro, and Virtex-II Pro X columns indicates that these design elements consume 1/2 of two slices. The double asterisks for design elements indicate that these primitives cannot be used by themselves. However, there is only one available per slice.
Slice Count for FPGA Components

Spartan-II, Spartan-IIE Name ACC4 ACC8 ACC16 ADD4 ADD8 ADD16 ADSU4 ADSU8 ADSU16 5 9 17 3 5 9 3 5 9 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 6 10 18 3 5 9 3 5 9 5 9 17 3 5 9 3 5 9 6 10 18 3 5 9 3 5 9
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Slice Count

Spartan-II, Spartan-IIE Name AND2 AND3 AND4 AND5 AND6 AND7 AND8 AND9 AND12 AND16 BRLSHFT4 BRLSHFT8 BSCAN_SPARTAN2 BSCAN_VIRTEX BSCAN_VIRTEX2 BUF BUF4 BUF8 BUF16 BUFCF BUFE BUFE4 BUFE8 BUFE16 BUFG BUFGCE BUFGCE_1 BUFGDLL BUFGMUX BUFGMUX_1 BUFGP BUFT BUFT4 BUFT8 BUFT16 CAPTURE_SPARTAN2 CAPTURE_VIRTEX 1 1 1 1 1 1 2 2 2 2 8 12 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 1 1 1 1 2 2 2 2 4 12 1 1 1 1 1 1 2 2 2 2 8 12 1 1 1 1 1 1 2 2 2 2 4 12 -
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Spartan-II, Spartan-IIE Name CAPTURE_VIRTEX2 CB2CE CB2CLE CB2CLED CB2RE CB4CE CB4CLE CB4CLED CB4RE CB8CE CB8CLE CB8CLED CB8RE CB16CE CB16CLE CB16CLED CB16RE CC8CE CC8CLE CC8CLED CC8RE CC16CE CC16CLE CC16CLED CC16RE CD4CE CD4CLE CD4RE CD4RLE CJ4CE CJ4RE CJ5CE CJ5RE CJ8CE CJ8RE CLKDLL CLKDLLE 2 3 3 2 3 5 6 3 6 9 12 6 13 18 24 13 8 9 9 9 16 17 17 17 3 5 3 7 2 2 3 3 4 4 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 3 3 3 3 4 5 7 4 7 10 12 7 14 19 25 14 5 9 17 9 9 17 33 17 4 5 4 7 4 4 5 5 4 4 2 3 3 2 3 5 6 3 6 9 12 6 13 18 24 13 8 9 9 9 16 17 17 17 3 5 3 7 2 2 3 3 4 4 3 3 3 3 4 5 7 4 7 10 12 7 14 19 25 14 5 9 17 9 9 17 33 17 4 5 4 7 4 4 5 5 4 4 -
25
Slice Count

Spartan-II, Spartan-IIE Name CLKDLLHF COMP2 COMP4 COMP8 COMP16 COMPM2 COMPM4 COMPM8 COMPM16 COMPMC8 COMPMC16 CR8CE CR16CE D2_4E D3_8E D4_16E DCM DEC_CC4 DEC_CC8 DEC_CC16 DECODE4 DECODE8 DECODE16 DECODE32 DECODE64 FD FD_1 FD4CE FD4RE FD8CE FD8RE FD16CE FD16RE FDC FDC_1 FDCE FDCE_1 1 2 3 6 1 5 11 24 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 2 2 4 4 8 8 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 2 4 9 2 5 13 32 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 4 4 4 4 8 8 1 1 1 1 1 2 3 6 1 5 11 24 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 2 2 4 4 8 8 1 1 1 1 1 2 4 9 2 5 13 32 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 4 4 4 4 8 8 1 1 1 1
26

Spartan-II, Spartan-IIE Name FDCP FDCP_1 FDCPE FDCPE_1 FDDRCPE FDDRRSE FDE FDE_1 FDP FDP_1 FDPE FDPE_1 FDR FDR_1 FDRE FDRE_1 FDRS FDRS_1 FDRSE FDRSE_1 FDS FDS_1 FDSE FDSE_1 FJKC FJKCE FJKP FJKPE FJKRSE FJKSRE FMAP FTC FTCE FTCLE FTCLEX FTP FTPE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
27
Slice Count

Spartan-II, Spartan-IIE Name FTPLE FTRSE FTRSLE FTSRE FTSRLE GND GT_AURORA_n GT_CUSTOM_n GT_ETHERNET_n GT_FIBRE_CHAN_n GT_INFINIBAND_n GT_XAUI_n GT10_AURORA_n GT10_AURORAX_n GT10_CUSTOM_n GT10_INFINIBAND_n GT10_XAUI_n GT10_10GE_n GT10_10GFC_n GT10_OC48_n GT10_OC192_n IBUF IBUF4 IBUF8 IBUF16 IBUF_selectIO IBUFDS IBUFG IBUFG_selectIO IBUFGDS IBUFGDS_DIFF_OUT ICAP_VIRTEX2 IFD IFD_1 IFD4 IFD8 IFD16 1 1 2 1 2 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 1 1 2 1 1 2 1 2 1 1 1 1 2 -
28

Spartan-II, Spartan-IIE Name IFDDRCPE IFDDRRSE IFDI IFDI_1 IFDX IFDX4 IFDX8 IFDX16 IFDX_1 IFDXI IFDXI_1 ILD ILD_1 ILD4 ILD8 ILD16 ILDI ILDI_1 ILDX ILDX4 ILDX8 ILDX16 ILDX_1 ILDXI ILDXI_1 INV INV4 INV8 INV16 IOBUF IOBUF_selectIO IOPAD IOPAD4 IOPAD8 IOPAD16 IPAD IPAD4 1 1 2 4 8 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 2 4 8 1 1 1 1 1 1 2 4 8 1 1 1 1 1 1 2 4 8 1 1 1 1 -
29
Slice Count

Spartan-II, Spartan-IIE Name IPAD8 IPAD16 JTAGPPC KEEPER LD LD_1 LD4 LD8 LD16 LD4CE LD8CE LD16CE LDC LDC_1 LDCE LDCE_1 LDCP LDCP_1 LDCPE LDCPE_1 LDE LDE_1 LDP LDP_1 LDPE LDPE_1 LUT1 LUT2 LUT3 LUT4 LUT1_D LUT2_D LUT3_D LUT4_D LUT1_L LUT2_L LUT3_L 1 1 2 4 8 2 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 4 4 8 4 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 8 2 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 8 4 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
30

Spartan-II, Spartan-IIE Name LUT4_L M2_1 M2_1B1 M2_1B2 M2_1E M4_1E M8_1E M16_1E MULT_AND ** MULT18X18 MULT18X18S MUXCY ** MUXCY_D ** MUXCY_L ** MUXF5 ** MUXF5_D ** MUXF5_L ** MUXF6 ** MUXF6_D ** MUXF6_L ** MUXF7 ** MUXF7_D ** MUXF7_L ** MUXF8 ** MUXF8_D ** MUXF8_L ** NAND2 NAND3 NAND4 NAND5 NAND6 NAND7 NAND8 NAND9 NAND12 NAND16 NOR2 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1
31
Slice Count

Spartan-II, Spartan-IIE Name NOR3 NOR4 NOR5 NOR6 NOR7 NOR8 NOR9 NOR12 NOR16 OBUF OBUF4 OBUF8 OBUF16 OBUF_selectIO OBUFDS OBUFE OBUFE4 OBUFE8 OBUFE16 OBUFT OBUFT4 OBUFT8 OBUFT16 OBUFT_selectIO OBUFTDS OFD OFD_1 OFD4 OFD8 OFD16 OFDDRCPE OFDDRRSE OFDDRTCPE OFDDRTRSE OFDE OFDE_1 OFDE4 1 1 1 1 1 2 2 2 2 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 1 1 1 2 2 2 2 1 1 1 1 1 2 2 2 2 1 1 1 1 1 2 2 2 2 -
32

Spartan-II, Spartan-IIE Name OFDE8 OFDE16 OFDI OFDI_I OFDT OFDT_1 OFDT4 OFDT8 OFDT16 OFDX OFDX4 OFDX8 OFDX16 OFDX_1 OFDXI OFDXI_I OPAD OPAD4 OPAD8 OPAD16 OR2 OR3 OR4 OR5 OR6 OR7 OR8 OR9 OR12 OR16 ORCY ** PPC405 PULLDOWN PULLUP RAM16X1D RAM16X1D_1 RAM16X1S 1 1 1 1 1 1 2 2 2 2 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 1 1 1 1 2 2 2 2 2* 2* 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 2 2 2 2 2* 2* 1
33
Slice Count

Spartan-II, Spartan-IIE Name RAM16X1S_1 RAM16X2D RAM16X2S RAM16X4D RAM16X4S RAM16X8D RAM16X8S RAM32X1D RAM32X1D_1 RAM32X1S RAM32X1S_1 RAM32X2S RAM32X4S RAM32X8S RAM64X1D RAM64X1D_1 RAM64X1S RAM64X1S_1 RAM64X2S RAM128X1S RAM128X1S_1 RAMB4_Sn RAMB4_Sm_Sn RAMB16_Sn RAMB16_Sm_Sn ROM16X1 ROM32X1 ROM64X1 ROM128X1 ROM256X1 SOP3 SOP4 SR4CE SR4CLE SR4CLED SR4RE SR4RLE 1 2 2 4 4 8 8 1 1 2 8 1 1 2 1 1 2 3 5 2 3 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 4 2 8 3 16 5 2 2 1 1 2 3 6 4 4 2 2 4 4 4 1 1 2 4 8 1 1 4 3 5 4 3 1 2 2 4 4 8 8 1 1 2 8 1 1 2 1 1 2 3 5 2 3 1 4 2 8 3 16 5 2 2 1 1 2 3 6 4 4 2 2 4 4 4 1 1 2 4 8 1 1 4 3 5 4 3
34

Spartan-II, Spartan-IIE Name SR4RLED SR8CE SR8CLE SR8CLED SR8RE SR8RLE SR8RLED SR16CE SR16CLE SR16CLED SR16RE SR16RLE SR16RLED SRL16 SRL16_1 SRL16E SRL16E_1 SRLC16 SRLC16_1 SRLC16E SRLC16E_1 STARTUP_SPARTAN2 STARTUP_VIRTEX STARTUP_VIRTEX2 UPAD VCC XNOR2 XNOR3 XNOR4 XNOR5 XNOR6 XNOR7 XNOR8 XNOR9 XOR2 XOR3 XOR4 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1
35
Slice Count

Spartan-II, Spartan-IIE Name XOR5 XOR6 XOR7 XOR8 XOR9 XORCY ** XORCY_D ** XORCY_L ** 1 1 1 2 2 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X
Number of Slices to Implement 1 1 1 2 2 1 1 1 2 2 1 1 1 2 2 -
* The RAM16X1D and RAM16X1D_1 consume 1/2 of two slices. ** These primitives cannot be used by themselves. However, there is only one available per slice.
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The following sections list the design elements that can be used with supported architectures. Spartan-II and Spartan-IIE Spartan-3 Virtex and Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500/XV/XL CoolRunner XPLA3 CoolRunner-II
To access lists of the constraints associated with each of these architectures, see "Architecture Specific Constraints," in the Xilinx Constraints Guide.
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38
Spartan-II and Spartan-IIE

The following table indicates the supported design elements for Spartan-II and Spartan-IIE. For a complete description of these architectures, see the Product Data Sheets (http://www.xilinx.com/partinfo/databook.htm#spartan). Spartan-II, Spartan-IIE Design Elements
ACC4, 8, 16 AND2-9 BSCAN_SPARTAN2 BUFE, 4, 8, 16 BUFGP CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE CLKDLLHF COMPMC8, 16 D3_8E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDE_1 FDPE FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE IBUF, 4, 8, 16 IFD, 4, 8, 16 IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16 ADD4, 8, 16 AND12, 16 BUF BUFG BUFT, 4, 8, 16 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDP FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE IBUF_selectIO IFD_1 IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1 ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGDLL CAPTURE_SPARTAN2 CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLE, CC16CLE CD4CE CD4RLE CLKDLL, CLKDLLE (Spartan-IIE only) COMPM2, 4, 8, 16 D2_4E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDE FDP_1 FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND IBUFG, IBUFG_selectIO IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ILDXI
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Spartan-II, Spartan-IIE Design Elements

ILDXI_1 IOPAD, 4, 8, 16 LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MUXCY_D MUXF5_D MUXF6_D NAND12, 16 OBUF, 4, 8, 16 OBUFT, 4, 8, 16 OFD_1 OFDI OFDT_1 OFDXI OR2-9 PULLUP RAM16X1S RAM16X2S RAM16X8D RAM32X1S_1 RAM32X8S ROC ROM32X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 STARTBUF_architecture TOCBUF XNOR2-9 XORCY_D INV, 4, 8, 16 IPAD, 4, 8, 16 LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY_L MUXF5_L MUXF6_L NOR2-9 OBUF_selectIO OBUFT_selectIO OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 RAM16X1D RAM16X1S_1 RAM16X4D RAM16X8S RAM32X2S RAMB4_Sn ROCBUF SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E STARTUP_SPARTAN2 UPAD XOR2-9 XORCY_L IOBUF, IOBUF_selectIO KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MUXCY MUXF5 MUXF6 NAND2-9 NOR12, 16 OBUFE, 4, 8, 16 OFD, 4, 8, 16 OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 PULLDOWN RAM16X1D_1 RAM16X2D RAM16X4S RAM32X1S RAM32X4S RAMB4_Sm_Sn ROM16X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 TOC VCC XORCY
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Spartan-3
The table below indicates the supported design elements for Spartan-3. Spartan-3 Design Elements
ACC4, 8, 16 AND2-9 BSCAN_SPARTAN3 BUFG BUFGDLL BUFGP CB2RE, CB4RE, CB8RE, CB16RE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE COMPMC8, 16 D3_8E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDDRCPE FDE_1 FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE IBUFDS IFD, 4, 8, 16 IFDDRRSE IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1 ADD4, 8, 16 AND12, 16 BUF BUFGCE BUFGMUX CAPTURE_SPARTAN3 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CLE, CC16CLE CD4CE CD4RLE COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDDRRSE FDP FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND IBUFG, IBUFG_selectIO IFD_1 IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ILDXI ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGCE_1 BUFGMUX_1 CB2CE, CB4CE, CB8CE, CB16CE CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D2_4E DCM DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDE FDP_1 FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE IBUF, 4, 8, 16 IBUFGDS IFDDRCPE IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16
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Spartan-3 Design Elements

ILDXI_1 IOBUFDS LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY MUXF5 MUXF6 MUXF7 MUXF8 NOR2-9 OBUF_selectIO OBUFTDS OFDDRCPE OFDDRTRSE OFDI OFDT_1 OFDXI OR2-9 PULLUP RAM16X1S RAM16X4S RAM32X1S_1 RAM64X1S_1 ROC ROM32X1 ROM256X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 SRLC16 SRLC16E_1 TOC INV, 4, 8, 16 KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MULT18X18 MUXCY_D MUXF5_D MUXF6_D MUXF7_D NAND2-9 NOR12, 16 OBUFDS OFD, 4, 8, 16 OFDDRRSE OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 RAM16X1D RAM16X1S_1 RAM16X8S RAM32X2S RAMB16_Sn ROCBUF ROM64X1 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E SRLC16_1 STARTBUF_architecture TOCBUF IOBUF, IOBUF_selectIO LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MULT18X18S MUXCY_L MUXF5_L MUXF6_L MUXF7_L NAND12, 16 OBUF, 4, 8, 16 OBUFT, 4, 8, 16 OFD_1 OFDDRTCPE OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 PULLDOWN RAM16X1D_1 RAM16X2S RAM32X1S RAM64X1S RAMB16_Sm_Sn ROM16X1 ROM128X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 SRLC16E STARTUP_SPARTAN3 VCC
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Spartan-3 Design Elements

XNOR2-9 XORCY_D XOR2-9 XORCY_L XORCY
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Virtex and Virtex-E

The table below indicates the supported design elements for Virtex and Virtex-E. For a complete description, see the Product Data Sheets (http://www.xilinx.com/partinfo/ databook.htm#virtex). Virtex, Virtex-E Design Elements
ACC4, 8, 16 AND2-9 BSCAN_VIRTEX BUFE, 4, 8, 16 BUFGP CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE CLKDLLE COMPM2, 4, 8, 16 D2_4E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDE FDP_1 FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND IBUFG, IBUFG_selectIO IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ADD4, 8, 16 AND12, 16 BUF BUFG BUFT, 4, 8, 16 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE CLKDLLHF COMPMC8, 16 D3_8E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDE_1 FDPE FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE IBUF, 4, 8, 16 IFD, 4, 8, 16 IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16 ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGDLL CAPTURE_VIRTEX CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLE, CC16CLE CD4CE CD4RLE CLKDLL COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDP FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE IBUF_selectIO IFD_1 IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1
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Virtex, Virtex-E Design Elements

ILDXI IOBUF, IOBUF_selectIO KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MUXCY MUXF5 MUXF6 NAND2-9 NOR12, 16 OBUFE, 4, 8, 16 OFD, 4, 8, 16 OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 PULLDOWN RAM16X1D_1 RAM16X2D RAM16X4S RAM32X1S RAM32X4S RAMB4_Sm_Sn ROM16X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 TOC VCC XORCY ILDXI_1 IOPAD, 4, 8, 16 LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MUXCY_D MUXF5_D MUXF6_D NAND12, 16 OBUF, 4, 8, 16 OBUFT, 4, 8, 16 OFD_1 OFDI OFDT_1 OFDXI OR2-9 PULLUP RAM16X1S RAM16X2S RAM16X8D RAM32X1S_1 RAM32X8S ROC ROM32X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 STARTBUF_architecture TOCBUF XNOR2-9 XORCY_D INV, 4, 8, 16 IPAD, 4, 8, 16 LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY_L MUXF5_L MUXF6_L NOR2-9 OBUF_selectIO OBUFT_selectIO OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 RAM16X1D RAM16X1S_1 RAM16X4D RAM16X8S RAM32X2S RAMB4_Sn ROCBUF SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E STARTUP_VIRTEX UPAD XOR2-9 XORCY_L
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Virtex-II, Virtex-II Pro, Virtex-II Pro X

The table below indicates the supported design elements for Virtex-II, Virtex-II Pro, and Virtex-II Pro X. For a complete description of Virtex-II, see the Product Data Sheets (http://www.xilinx.com/partinfo/databook.htm#vtwo). Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements
ACC4, 8, 16 AND2-9 BSCAN_VIRTEX2 BUFE, 4, 8, 16 BUFGCE_1 BUFGMUX_1 CAPTURE_VIRTEX2 CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLE, CC16CLE CD4CE CD4RLE COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDDRRSE FDP FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE GT_CUSTOM (Virtex-II Pro only) GT10_AURORAX_n (Virtex-II Pro X only) ADD4, 8, 16 AND12, 16 BUF BUFG BUFGDLL BUFGP CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D2_4E DCM DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDE FDP_1 FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND GT_ETHERNET_n (Virtex-II Pro only) GT10_CUSTOM (Virtex-II Pro X only) ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGCE BUFGMUX BUFT, 4, 8, 16 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE COMPMC8, 16 D3_8E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDDRCPE FDE_1 FDPE FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE GT_AURORA_n (Virtex-II Pro only) GT_FIBRE_CHAN_n (Virtex-II Pro only) GT10_AURORA_n (Virtex-II Pro X only) GT10_INFINIBAND_n (Virtex-II Pro X only)
GT_INFINIBAND_n (Virtex-II Pro only) GT_XAUI_n (Virtex-II Pro only)
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Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements

GT10_XAUI_n (Virtex-II Pro X only) GT10_OC48_n (Virtex-II Pro X only) IBUF_selectIO IBUFGDS IFD, 4, 8, 16 IFDDRRSE IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1 INV, 4, 8, 16 IOPAD, 4, 8, 16 KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MULT18X18 MUXCY_D MUXF5_D MUXF6_D MUXF7_D NAND2-9 NOR2-9 OBUF_selectIO OBUFT, 4, 8, 16 OFD, 4, 8, 16 OFDDRRSE OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 PULLDOWN RAM16X1D_1 GT10_10GE_n (Virtex-II Pro X only) GT10_OC192_n (Virtex-II Pro X only) IBUFDS IBUFGDS_DIFF_OUT IFD_1 IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ILDXI IOBUF, IOBUF_selectIO IPAD, 4, 8, 16 LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MULT18X18S MUXCY_L MUXF5_L MUXF6_L MUXF7_L NAND12, 16 NOR12, 16 OBUFDS OBUFT_selectIO OFD_1 OFDDRTCPE OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 ORCY PULLUP RAM16X1S OBUF, 4, 8, 16 OBUFE, 4, 8, 16 OBUFTDS OFDDRCPE OFDDRTRSE OFDI OFDT_1 OFDXI OR2-9 PPC405 (Virtex-II Pro only) RAM16X1D RAM16X1S_1 GT10_10GFC_n (Virtex-II Pro X only) IBUF, 4, 8, 16 IBUFG, IBUFG_selectIO ICAP_VIRTEX2 IFDDRCPE IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16 ILDXI_1 IOBUFDS JTAGPPC (Virtex-II Pro only) LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY MUXF5 MUXF6 MUXF7 MUXF8
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Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements

RAM16X2D RAM16X4S RAM32X1D RAM32X1S_1 RAM32X8S RAM64X1S RAM128X1S RAMB16_Sm_Sn ROM16X1 ROM128X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 SRLC16E STARTUP_VIRTEX2 UPAD XOR2-9 XORCY_L RAM16X2S RAM16X8D RAM32X1D_1 RAM32X2S RAM64X1D RAM64X1S_1 RAM128X1S_1 ROC ROM32X1 ROM256X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 SRLC16 SRLC16E_1 TOC VCC XORCY RAM16X4D RAM16X8S RAM32X1S RAM32X4S RAM64X1D_1 RAM64X2S RAMB16_Sn ROCBUF ROM64X1 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E SRLC16_1 STARTBUF_architecture TOCBUF XNOR2-9 XORCY_D
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XC9500/XV/XL
The table below indicates the supported design elements for XC95000/XV/XL. For a complete description, see the Product Data Sheets (http://www.xilinx.com/partinfo/ databook.htm#cpld). XC9500/XV/XL Design Elements
ACC1 ADD4, 8, 16 AND2-9 BUF4, 8, 16 BUFGSR CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CB2X2, CB4X2, CB8X2, CB16X2 CD4RE CJ4RE, CJ5RE, CJ8RE CR8CE, CR16CE D4_16E FD4CE, FD8CE, FD16CE FDCE FDP FDRE FDS FDSRE FJKCP FJKPE FTC FTCP FTDCP FTPLE FTSRE IBUF, 4, 8, 16 IPAD, 4, 8, 16 LDC M2_1 M2_1E M16_1E OBUF, 4, 8, 16 OPAD, 4, 8, 16 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE VCC ACC4, 8, 16 ADSU1 BRLSHFT4, 8 BUFE, 4, 8, 16 BUFGTS CB2CLE, CB4CLE, CB8CLE, CB16CLE CB2RLE, CB4RLE, CB8RLE, CB16RLE CD4CE CD4RLE COMP2, 4, 8, 16 D2_4E FD FD4RE, FD8RE, FD16RE FDCP FDPE FDRS FDSE FJKC FJKCPE FJKRSE FTCE FTCPE FTP FTRSE FTSRLE INV, 4, 8, 16 LD LDCP M2_1B1 M4_1E NAND2-9 OBUFE, 4, 8, 16 OR2-9 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE XNOR2-9 ADD1 ADSU4, 8, 16 BUF BUFG BUFT, 4, 8, 16 CB2CLED, CB4CLED, CB8CLED, CB16CLED CB2X1, CB4X1, CB8X1, CB16X1 CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D3_8E FD4, 8, 16 FDC FDCPE FDR FDRSE FDSR FJKCE FJKP FJKSRE FTCLE FTCPLE FTPE FTRSLE GND IOPAD, 4, 8, 16 LD4, 8, 16 LDP M2_1B2 M8_1E NOR2-9 OBUFT, 4, 8, 16 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED XOR2-9
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CoolRunner XPLA3
The table below indicates the supported design elements for CoolRunner XPLA3. For a complete description, see the Product Data Sheets (http://www.xilinx.com/ partinfo/databook.htm#coolrunner). CoolRunner XPLA3 Design Elements
ACC1 ADD4, 8, 16 AND2-9 BUF4, 8, 16 BUFT, 4, 8, 16 CB2CLED, CB4CLED, CB8CLED, CB16CLED CB2X1, CB4X1, CB8X1, CB16X1 CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D3_8E FD4, 8, 16 FDC FDCPE FDR FDRSE FDSR FJKCE FJKP FJKSRE FTCLE FTCPLE FTPE FTRSLE GND IOPAD, 4, 8, 16 LD4, 8, 16 LDP M2_1B2 M8_1E NOR2-9 OBUFT, 4, 8, 16 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED XOR2-9 ACC4, 8, 16 ADSU1 BRLSHFT4, 8 BUFE, 4, 8, 16 CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CB2X2, CB4X2, CB8X2, CB16X2 CD4RE CJ4RE, CJ5RE, CJ8RE CR8CE, CR16CE D4_16E FD4CE, FD8CE, FD16CE FDCE FDP FDRE FDS FDSRE FJKCP FJKPE FTC FTCP FTDCP FTPLE FTSRE IBUF, 4, 8, 16 IPAD, 4, 8, 16 LDC M2_1 M2_1E M16_1E OBUF, 4, 8, 16 OPAD, 4, 8, 16 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE VCC ADD1 ADSU4, 8, 16 BUF BUFG CB2CLE, CB4CLE, CB8CLE, CB16CLE CB2RLE, CB4RLE, CB8RLE, CB16RLE CD4CE CD4RLE COMP2, 4, 8, 16 D2_4E FD FD4RE, FD8RE, FD16RE FDCP FDPE FDRS FDSE FJKC FJKCPE FJKRSE FTCE FTCPE FTP FTRSE FTSRLE INV, 4, 8, 16 LD LDCP M2_1B1 M4_1E NAND2-9 OBUFE, 4, 8, 16 OR2-9 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE XNOR2-9
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54
CoolRunner-II
The table below indicates the supported design elements for CoolRunner-II. For a complete description of CoolRunner-II, see the Product Data Sheets (http:// www.xilinx.com/partinfo/databook.htm#cooltwo). CoolRunner-II Design Elements
ACC1 ADD4, 8, 16 AND2-9 BUF4, 8, 16 BUFGTS CB2CLED, CB4CLED, CB8CLED, CB16CLED CB2X1, CB4X1, CB8X1, CB16X1 CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE CD4CE CD4RLE CDD4RE CJ4RE, CJ5RE, CJ8RE CLK_DIV2,4,6,8,10,12,14,16 CLK_DIV2,4,6,8,10,12,14,16SD CR8CE, CR16CE D3_8E FD4, 8, 16 FDC FDCPE FDD4CE, FDD8CE, FDD16CE FDDCE FDDP FDDRE FDDS FDDSRE FDR FDRSE FDSR FJKCE FJKP FJKSRE FTCLE FTCPLE FTDCLEX ACC4, 8, 16 ADSU1 BRLSHFT4, 8 BUFG CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CB2X2, CB4X2, CB8X2, CB16X2 CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED CBD2X1, CBD4X1, CBD8X1, CBD16X1 CD4CLE CDD4CE CDD4RLE CJD4CE, CJD5CE, CJD8CE CLK_DIV2,4,6,8,10,12,14,16R COMP2, 4, 8, 16 CRD8CE, CRD16CE D4_16E FD4CE, FD8CE, FD16CE FDCE FDD FDD4RE, FDD8RE, FDD16RE FDDCP FDDPE FDDRS FDDSE FDP FDRE FDS FDSRE FJKCP FJKPE FTC FTCP FTDCE FTDCP ADD1 ADSU4, 8, 16 BUF BUFGSR CB2CLE, CB4CLE, CB8CLE, CB16CLE CB2RLE, CB4RLE, CB8RLE, CB16RLE CBD2CE, CBD4CE, CBD8CE, CBD16CE CBD2RE, CBD4RE, CBD8RE, CBD16RE CBD2X2, CBD4X2, CBD8X2, CBD16X2 CD4RE CDD4CLE CJ4CE, CJ5CE, CJ8CE CJD4RE, CJD5RE, CJD8RE CLK_DIV2,4,6,8,10,12,14,16RSD COMPM2, 4, 8, 16 D2_4E FD FD4RE, FD8RE, FD16RE FDCP FDD4,8,16 FDDC FDDCPE FDDR FDDRSE FDDSR FDPE FDRS FDSE FJKC FJKCPE FJKRSE FTCE FTCPE FTDCLE FTDRSE
55
CoolRunner-II Design Elements

FTDRSLE FTPLE FTSRE IBUF, 4, 8, 16 IPAD, 4, 8, 16 LD4, 8, 16 LDG M2_1 M2_1E M16_1E OBUF, 4, 8, 16 OPAD, 4, 8, 16 PULLUP SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRD4CLE, SRD8CLE, SRD16CLE SRD4RLE, SRD8RLE, SRD16RLE XNOR2-9 FTP FTRSE FTSRLE INV, 4, 8, 16 KEEPER LDC LDG4, 8, 16 M2_1B1 M4_1E NAND2-9 OBUFE, 4, 8, 16 OR2-9 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRD4CLED, SRD8CLED, SRD16CLED SRD4RLED, SRD8RLED, SRD16RLED XOR2-9 FTPE FTRSLE GND IOPAD, 4, 8, 16 LD LDCP LDP M2_1B2 M8_1E NOR2-9 OBUFT, 4, 8, 16 PULLDOWN SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRD4CE, SRD8CE, SRD16CE SRD4RE, SRD8RE, SRD16RE VCC
56
This section categorizes, by function, the logic elements that are described in detail in the Design Elements sections. Each category is briefly described. Tables under each category identify all the available elements for the function and indicate which architectures are supported by each.
Arithmetic Functions Buffers Comparators Counters Decoders Edge Decoders Flip-Flops General Input Latches Input/Output Flip-Flops Input/Output Functions Latches Logic Primitives Map Elements Memory Elements Multiplexers Shifters Shift Registers
Elements are listed in alphanumeric order under each category. See the Xilinx Unified Libraries chapter for information on the specific device families that use each library. "No" column means that the element does not apply. The Xilinx libraries contain three types of elements. Primitives are basic logical elements such as AND2 and OR2 gates. Soft macros are schematics made by combining primitives and sometimes other soft macros. Relationally placed macros (RPMs) are soft macros that contain relative location constraint (RLOC) information, carry logic symbols, and FMAP symbols, where appropriate.
The last item mentioned above, RPMs, applies only to FPGA families. The relationally placed macro (RPM) library uses RLOC constraints to define the order and structure of the underlying design primitives. Because these macros are built upon standard schematic parts, they do not have to be translated before simulation. The components that are implemented as RPMs are listed in the Slice Count section. Designs created with RPMs can be functionally simulated. RPMs can, but need not, include all the following elements. FMAPs and CLB-grouping attributes to control mapping. FMAPs have pin-lock attributes, which allow better control over routing. Relative location (RLOC) constraints to provide placement structure. They allow positioning of elements relative to each other. Carry logic primitive symbols.
57
The RPM library offers the functionality and precision of the hard macro library with added flexibility. You can optimize RPMs and merge other logic within them. The elements in the RPM library allow you to access carry logic easily and to control mapping and block placement. Because RPMs are a superset of ordinary macros, you can design them in the normal design entry environment. They can include any primitive logic. The macro logic is fully visible to you and can be easily backannotated with timing information.
58
Arithmetic Functions
There are three types of arithmetic functions: accumulators (ACC), adders (ADD), and adder/subtracters (ADSU). With an ADSU, either unsigned binary or twoscomplement operations cause an overflow. If the result crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-out boundary, a carry-out is generated. The following figure shows the ADSU carry-out and overflow boundaries.
Overflow
-127
D
127 127
TW
128
NE
OS
SIG
CO
UN
ED BINAR Y IGN
E N T OR
MPL EMENT O R
SIGN
ED BIN
LEM
AR
MP
NS
CO
SI
0 0
-1
Carry-Out
X4720
ADSU Carry-Out and Overflow Boundaries

Design Element ACC1 Description 1-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 4-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 8-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 16-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 1-Bit Full Adder with Carry-In and Carry-Out 4-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow 8-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow 16-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow 1-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow 8-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow Spartan-II, IIE No No Spartan3 Virtex, E No Virtex II, Pro, Pro X No XC9500/XV/ XL Macro CR XPLA3 Macro CR-II Macro
ACC4
Macro
Macro
Macro
ACC8
Macro
Macro
Macro
ACC16
Macro
Macro
Macro
ADD1 ADD4 ADD8 ADD16 ADSU1 ADSU4
No Macro Macro Macro No Macro
ADSU8
Macro
Macro
Macro
ED
255
TW
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro Macro Macro Macro Macro Macro
Macro
Macro
Macro
Macro
59
Design Element ADSU16
Description 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow 18 x 18 Signed Multiplier 18 x 18 Signed Multiplier -- Registered Version
Spartan-II, IIE Macro
Spartan3 Macro
Virtex, E Macro
Virtex II, Pro, Pro X Macro
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
MULT18X18 MULT18X18S
No No
Primitive Primitive
No No
Primitive Primitive
No No
No No
No No
60
Buffers
The buffers in this section route high fanout signals, 3-state signals, and clocks inside a PLD device. The Input/Output Functions section covers off-chip interfaces.
Design Element BUF BUF4 BUF8 BUF16 BUFCF BUFE BUFE4 BUFE8 BUFE16 BUFG BUFGCE Description General Purpose Buffer 4-Bit General Purpose Buffer 8-Bit General Purpose Buffer 16-Bit General Purpose Buffer Fast Connect Buffer Internal 3-State Buffer with Active High Enable. Internal 3-State Buffer with Active High Enable. Internal 3-State Buffer with Active High Enable. Internal 3-State Buffer with Active High Enable. Global Clock Buffer Global Clock MUX with Clock Enable and Output State 0 Global Clock MUX Buffer with Clock Enable and Output State 1 Clock Delay Locked Loop Buffer Global Clock MUX Buffer with Output State 0 Global Clock MUX with Output State 1 Primary Global Buffer for Driving Clocks or Longlines (Four per PLD Device) Global Set/Reset Input Buffer Global 3-State Input Buffer Internal 3-State Buffer with Active-Low Enable. Internal 3-State Buffer with Active-Low Enable. Internal 3-State Buffer with Active-Low Enable. Internal 3-State Buffer with Active-Low Enable. Spartan-II, IIE Primitive No No No Primitive Primitive Macro Macro Macro Primitive No Spartan3 Primitive No No No Primitive No No No No Primitive Primitive Virtex, E Primitive No No No Primitive Primitive Macro Macro Macro Primitive No Virtex II, Pro, Pro X Primitive No No No Primitive Primitive Macro Macro Macro Primitive Primitive XC9500 /XV/XL Primitive Macro Macro Macro No Primitive Macrob Macroc Macrod Primitive No
a
CR XPLA3 Primitive Macro Macro Macro No No No No No Primitive No
CR-II Primitive Macro Macro Macro No No No No No Primitive No
BUFGCE_1
No
Primitive
No
Primitive
No
No
No
BUFGDLL BUFGMUX BUFGMUX_1 BUFGP
Primitive No No Primitive
Primitive Primitive Primitive Primitive
Primitive No No Primitive
No No No No
No No No No
No No No No
BUFGSR BUFGTS BUFT BUFT4 BUFT8 BUFT16
No No Primitive Macro Macro Macro
No No No No No No
Primitive Primitive Primitivee Macrof Macrog Macroh
Primitive Primitive No No No No
Primitive Primitive No No No No
a.Not supported for XC9500XL and XC9500XV devices. b.Not supported for XC9500XL and XC9500XV devices. c.Not supported for XC9500XL and XC9500XV devices. d.Not supported for XC9500XL and XC9500XV devices. e.Not supported for XC9500XL and XC9500XV devices. f.Not supported for XC9500XL and XC9500XV devices.
61
g.Not supported for XC9500XL and XC9500XV devices. h.Not supported for XC9500XL and XC9500XV devices.
62
Comparators
Following is a list of comparators.
Design Element COMP2 COMP4 COMP8 COMP16 COMPM2 COMPM4 COMPM8 COMPM16 COMPMC8 COMPMC16 Description 2-Bit Identity Comparator 4-Bit Identity Comparator 8-Bit Identity Comparator 16-Bit Identity Comparator 2-Bit Magnitude Comparator 4-Bit Magnitude Comparator 8-Bit Magnitude Comparator Spartan-II, IIE Macro Macro Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro XC9500/XV/ XL Macro Macro Macro Macro Macro Macro Macro Macro No No CR XPLA3 Macro Macro Macrob Macro Macro Macro Macro Macro No No CR-II Macro Macro Macro Macro Macro Macro Macro Macro No No
16-Bit Magnitude Comparator Macro 8-Bit Magnitude Comparator Macro
16-Bit Magnitude Comparator Macro
63
Counters
There are six types of counters with various synchronous and asynchronous inputs. The name of the counter defines the modulo or bit size, the counter type, and which control functions are included. The counter naming convention is shown in the following figure.
CB16CLED
Counter Binary (B) BCD (D) Binary, Carry Logic (C) Johnson (J) Ripple (R) Modulo (Bit Size) Synchronous Reset (R) Asynchronous Clear (C) Loadable Clock Enable Directional
X4577
Counter Naming Convention A carry-lookahead design accommodates large counters without extra gating. On TTL 7400-type counters with trickle clock enable (ENT), parallel clock enable (ENP), and ripple carry-out (RCO), both the ENT and ENP inputs must be High to count. ENT is propagated forward to enable RCO, which produces a High output with the approximate duration of the QA output. The following figure illustrates a carrylookahead design.
RCO ENP ENT
RCO ENP ENT
Vcc ENP ENT
RCO
Vcc RCO ENP CE ENT
X4719
Carry-Lookahead Design
64
The RCO output of the first stage of the ripple carry is connected to the ENP input of the second stage and all subsequent stages. The RCO output of the second stage and all subsequent stages is connected to the ENT input of the next stage. The ENT of the second stage is always enabled/tied to VCC. CE is always connected to the ENT input of the first stage. This cascading method allows the first stage of the ripple carry to be built as a prescaler. In other words, the first stage is built to count very fast. Note: For counters, do not use TC (or any other gated signal) as a clock. Possible glitches may not always allow for a proper setup time when using gated signals.
Design Element CB2CE Description 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 4-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset Spartan-II, IIE Macro Spartan-3 Macro Virtex, E Macro Virtex II, Pro, Pro X Macro XC9500/XV/ XL Macro CR XPLA3 Macro CR-II Macro
CB4CE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CB8CE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CB16CE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CB2CLE
No
No
No
No
Macro
Macro
Macro
CB4CLE
No
No
No
No
Macro
Macro
Macro
CB8CLE
No
No
No
No
Macro
Macro
Macro
CB16CLE
No
No
No
No
Macro
Macro
Macro
CB2CLED
No
No
No
No
Macro
Macro
Macro
CB4CLED
No
No
No
No
Macro
Macro
Macro
CB8CLED
No
No
No
No
Macro
Macro
Macro
CB16CLED
No
No
No
No
Macro
Macro
Macro
CB2RE
Macro
Macro
Macro
Macro
Macro Macro Macro Macro
CB4RE
Macro
Macro
Macro
Macro
CB8RE
Macro
Macro
Macro
Macro
CB16RE
Macro
Macro
Macro
Macro
65
Design Element CB2RLE
Description 2-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 2-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 2-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 2-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
Spartan-II, IIE No
Spartan-3 No
Virtex, E No
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
CB4RLE
No
No
No
Macro
Macro
Macro
Macro
CB8RLE
No
No
No
Macro
Macro
Macro
Macro
CB16RLE
No
No
No
Macro
Macro
Macro
Macro
CB2X1
No
No
No
Macro
Macro
Macro
Macro
CB4X1
No
No
No
Macro
Macro
Macro
Macro
CB8X1
No
No
No
Macro
Macro
Macro
Macro
CB16X1
No
No
No
Macro
Macro
Macro
Macro
CB2X2
No
No
No
Macro
Macro
Macro
Macro
CB4X2
No
No
No
Macro
Macro
Macro
Macro
CB8X2
No
No
No
Macro
Macro
Macro
Macro
CB16X2
No
No
No
Macro
Macro
Macro
Macro
CBD2CE
No
No
No
No
No
No
Macro
CBD4CE
No
No
No
No
No
No
Macro
CBD8CE
No
No
No
No
No
No
Macro
CBD16CE
No
No
No
No
No
No
Macro
CBD2CLE
No
No
No
No
No
No
Macro
66
Design Element CBD4CLE
Description 4-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 2-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear
Spartan-II, IIE No
Spartan-3 No
Virtex, E No
Virtex II, Pro, Pro X No
XC9500/XV/ XL No
CR XPLA3 No
CR-II Macro
CBD8CLE
No
No
No
No
No
No
Macro
CBD16CLE
No
No
No
No
No
No
Macro
CBD2CLED
No
No
No
No
No
No
Macro
CBD4CLED
No
No
No
No
No
No
Macro
CBD8CLED
No
No
No
No
No
No
Macro
CBD16CLED
No
No
No
No
No
No
Macro
CBD2RE
No
No
No
No
No
No
Macro
CBD4RE
No
No
No
No
No
No
Macro
CBD8RE
No
No
No
No
No
No
Macro
CBD16RE
No
No
No
No
No
No
Macro
CBD2RLE
No
No
No
No
No
No
Macro
CBD4RLE
No
No
No
No
No
No
Macro
CBD8RLE
No
No
No
No
No
No
Macro
CBD16RLE
No
No
No
No
No
No
Macro
CBD2X1
No
No
No
No
No
No
Macro
67
Design Element CBD4X1
Description 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear
Spartan-II, IIE No
Spartan-3 No
Virtex, E No
XC9500/XV/ XL No
CR XPLA3 No
CR-II Macro
CBD8X1
No
No
No
No
No
No
Macro
CBD16X1
No
No
No
No
No
No
Macro
CBD2X2
No
No
No
No
No
No
Macro
CBD4X2
No
No
No
No
No
No
Macro
CBD8X2
No
No
No
No
No
No
Macro
CBD16X2
No
No
No
No
No
No
Macro
CC8CE
Macro
Macro
Macro
Macro
No
No
No
CC16CE
Macro
Macro
Macro
Macro
No
No
No
CC8CLE
Macro
Macro
Macro
Macro
No
No
No
CC16CLE
Macro
Macro
Macro
Macro
No
No
No
CC8CLED
Macro
Macro
Macro
Macro
No
No
No
CC16CLED
Macro
Macro
Macro
Macro
No
No
No
CC8RE
Macro
Macro
Macro
Macro
No
No
No
CC16RE
Macro
Macro
Macro
Macro
No
No
No
CD4CE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CD4CLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CDD4CE
No
No
No
No
No
No
Macro
68
Design Element CD4RE
Description 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable BCD Counter with Clock Enable And Synchronous Reset 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset 4-Bit Johnson Counter with Clock Enable and Synchronous Reset 5-Bit Johnson Counter with Clock Enable and Synchronous Reset 8-Bit Johnson Counter with Clock Enable and Synchronous Reset 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear
Spartan-3 Macro
Virtex, E Macro
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
CD4RLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CDD4CLE
No
No
No
No
No
No
Macro
CDD4RE
No
No
No
No
No
No
Macro
CDD4RLE
No
No
No
No
No
No
Macro
CD4RE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CD4RLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
CJ4CE CJ5CE CJ8CE CJD4CE
Macro Macro Macro No
CJD5CE
No
No
No
No
No
No
Macro
CJD8CE
No
No
No
No
No
No
Macro
CJD4RE
No
No
No
No
No
No
Macro
CJD5RE
No
No
No
No
No
No
Macro
CJD8RE
No
No
No
No
No
No
Macro
CJ4RE CJ5RE CJ8RE CR8CE
CR16CE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
69
Design Element CRD8CE
Description 8-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear 16-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear
Spartan-II, IIE No
Spartan-3 No
Virtex, E No
XC9500/XV/ XL No
CR XPLA3 No
CR-II Macro
CRD16CE
No
No
No
No
No
No
Macro
70
Decoders
Decoder names, shown in the following figure, indicate the number of inputs and outputs and whether or not an enable is available. Decoders with an enable can be used as multiplexers.
D2_4E
Decoder Number of Inputs Number of Outputs Output Enable
X4619
Decoder Naming Convention

Design Element D2_4E D3_8E D4_16E DEC_CC4 DEC_CC8 DEC_CC16 Description 2- to 4-Line Decoder/ Demultiplexer with Enable 3- to 8-Line Decoder/ Demultiplexer with Enable 4- to 16-Line Decoder/ Demultiplexer with Enable 4-Bit Active Low Decoder 8-Bit Active Low Decoder 16-Bit Active Low Decoder Spartan-II, IIE Macro Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro XC9500/XV/ XL Macro Macro Macro No No No CR XPLA3 Macro Macro Macro No No No CR-II Macro Macro Macro No No No
71
Edge Decoders
Edge decoders are open-drain wired AND gates that are available in different bit sizes.
Design Element DECODE4 DECODE8 DECODE16 DECODE32 DECODE64 Description 4-Bit Active-Low Decoder 8-Bit Active-Low Decoder 16-Bit Active-Low Decoder 32-Bit Active-Low Decoder 64-Bit Active-Low Decoder Spartan-II, IIE Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro No No No No No XC9500/XV/ XL CR XPLA3 No No No No No CR-II No No No No No
72
Flip-Flops
There are three types of flip-flops (D, J-K, toggle) with various synchronous and asynchronous inputs. Some are available with inverted clock inputs and/or the ability to set in response to global set/reset rather than reset. The naming convention shown in the following figure provides a description for each flip-flop. D-type flip-flops are available in multiples of up to 16 in one macro.
FDPE_1
Flip-Flop D-Type (D) JK-Type (JK) Toggle-Type (T) Asynchronous Preset (P) Asynchronous Clear (C) Synchronous Set (S) Synchronous Reset (R) Clock Enable Inverted Clock
X4579
Design Element FD FD_1 FD4 FD8 FD16 FD4CE FD8CE FD16CE FD4RE FD8RE FD16RE FDC FDC_1 FDCE FDCE_1
Description D Flip-Flop D Flip-Flop with Negative-Edge Clock Multiple D Flip-Flop Multiple D Flip-Flop Multiple D Flip-Flop 4-Bit Data Register with Clock Enable and Asynchronous Clear 8-Bit Data Register with Clock Enable and Asynchronous Clear 16-Bit Data Register with Clock Enable and Asynchronous Clear 4-Bit Data Register with Clock Enable and Synchronous Reset 8-Bit Data Register with Clock Enable and Synchronous Reset 16-Bit Data Register with Clock Enable and Synchronous Reset D Flip-Flop with Asynchronous Clear D Flip-Flop with Negative-Edge Clock and Asynchronous Clear D Flip-Flop with Clock Enable and Asynchronous Clear D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Clear D Flip-Flop with Asynchronous Preset and Clear D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and Clear
Spartan-II, IIE Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive
Spartan-3 Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive
Virtex, E Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive
Virtex II, Pro, Pro X Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive
XC9500/XV/ XL Macro No Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro No Primitive No
CR XPLA3 Macro No Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro No Primitive No
CR-II Macro No Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro No Primitive No
FDCP FDCP_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive No
Primitive No
Primitive No
73
Design Element FDCPE
Description D Flip-Flop with Clock Enable and Asynchronous Preset and Clear D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop Multiple Dual Edge Triggered D Flip-Flop Multiple Dual Edge Triggered D Flip-Flop Multiple Dual Edge Triggered D Flip-Flop 4-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear 8-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear 16-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset 8-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset 16-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset D Dual Edge Triggered Flip-Flop with Asynchronous Clear Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear Dual Edge Triggered D Flip-Flop Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop with Asynchronous Preset Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset Dual Edge Triggered D Flip-Flop with Synchronous Reset Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop with Clock Enable and Synchronous Reset Dual Data Rate D Flip-Flop with Clock Enable and Synchronous Reset and Set Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set
Spartan-II, IIE Primitive
Spartan-3 Primitive
Virtex, E Primitive
Virtex II, Pro, Pro X Primitive
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Primitive
FDCPE_1
Primitive
Primitive
Primitive
Primitive
No
No
No
FDD FDD4 FDD8 FDD16 FDD4CE
No No No No No
No No No No No
No No No No No
No No No No No
No No No No No
No No No No No
Macro Macro Macro Macro Macro
FDD8CE
No
No
No
No
No
No
Macro
FDD16CE
No
No
No
No
No
No
Macro
FDD4RE
No
No
No
No
No
No
Macro
FDD8RE
No
No
No
No
No
No
Macro
FDD16RE
No
No
No
No
No
No
Macro
FDDC FDDCE
No No
No No
No No
No No
No No
No No
Macro Primitive
FDDCP FDDCPE
No No
No No
No No
No No
No No
No No
Primitive Primitive
FDDP FDDPE
No No
No No
No No
No No
No No
No No
Macro Primitive
FDDR FDDRCPE
No No
No Primitive
No No
No Primitive
No No
No No
Macro No
FDDRE
No
No
No
No
No
No
Macro
FDDRRSE
No
Primitive
No
Primitive
No
No
No
FDDRS
No
No
No
No
No
No
Macro
74
Design Element FDDRSE
Description Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set and Clock Enable Dual Edge Triggered D Flip-Flop with Synchronous Set D Flip-Flop with Clock Enable and Synchronous Set Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset and Clock Enable D Flip-Flop with Clock Enable D Flip-Flop with Negative-Edge Clock and Clock Enable D Flip-Flop with Asynchronous Preset D Flip-Flop with Negative-Edge Clock and Asynchronous Preset D Flip-Flop with Clock Enable and Asynchronous Preset D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset D Flip-Flop with Synchronous Reset D Flip-Flop with Negative-Edge Clock and Synchronous Reset D Flip-Flop with Clock Enable and Synchronous Reset D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset D Flip-Flop with Synchronous Reset and Set D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set D Flip-Flop with Synchronous Reset and Set and Clock Enable D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set, and Clock Enable D Flip-Flop with Synchronous Set D Flip-Flop with Negative-Edge Clock and Synchronous Set D Flip-Flop with Clock Enable and Synchronous Set D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set D Flip-Flop with Synchronous Set and Reset D Flip-Flop with Synchronous Set and Reset and Clock Enable J-K Flip-Flop with Asynchronous Clear
Spartan-II, IIE No
Spartan-3 No
Virtex, E No
XC9500/XV/ XL No
CR XPLA3 No
CR-II Macro
FDDS FDDSE FDDSR FDDSRE
No No No No
No No No No
No No No No
No No No No
No No No No
No No No No
FDE FDE_1 FDP FDP_1 FDPE FDPE_1
Primitive Primitive Primitive Primitive Primitive Primitive
No No Macro No Primitive No
FDR FDR_1 FDRE FDRE_1
Macro No Macro No
Macro No Macro No
Macro No Macro No
FDRS FDRS_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
Macro No
Macro No
Macro No
FDRSE FDRSE_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
Macro No
Macro No
Macro No
FDS FDS_1 FDSE FDSE_1
Primitive Primitive Primitive No
Macro No Macro No
Macro No Macro No
Macro No Macro No
FDSR FDSRE FJKC
No No Macro
No No Macro
No No Macro
No No Macro
Macro Macro Macro
Macro Macro Macro
Macro Macro Macro
75
Design Element FJKCE FJKCP FJKCPE
Description J-K Flip-Flop with Clock Enable and Asynchronous Clear J-K Flip-Flop with Asynchronous Clear and Preset J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable J-K Flip-Flop with Asynchronous Preset J-K Flip-Flop with Clock Enable and Asynchronous Preset J-K Flip-Flop with Clock Enable and Synchronous Reset and Set J-K Flip-Flop with Clock Enable and Synchronous Set and Reset Toggle Flip-Flop with Toggle Enable and Asynchronous Clear Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset Loadable Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset
Spartan-II, IIE Macro No No
Spartan-3 Macro No No
Virtex, E Macro No No
Virtex II, Pro, Pro X Macro No No
XC9500/XV/ XL Macro Macro Macro
CR XPLA3 Macro Macro Macro
CR-II Macro Macro Macro
FJKP FJKPE FJKRSE FJKSRE FTC FTCE
FTCLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
FTCLEX
Macro
Macro
Macro
Macro
Macro
Macro
Macro
FTCP
No
No
No
No
Primitive
Primitive
Primitive
FTCPE
No
No
No
No
Macro
Macro
Macro
FTCPLE
No
No
No
No
Macro
Macro
Macro
FTDCE
Dual Edge Triggered Toggle Flip- No Flop with Toggle and Clock Enable and Asynchronous Clear Dual Edge Triggered Toggle/ Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Dual Edge Triggered Toggle/ Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset No
No
No
No
No
No
Macro
FTDCLE
No
No
No
No
No
Macro
FTDCLEX
No
No
No
No
No
No
Macro
FTDCP
No
No
No
No
Primitive
Primitive
Primitive
FTDRSE
Dual Edge Triggered Toggle Flip- No Flop with Toggle and Clock Enable and Synchronous Reset and Set Dual Edge Triggered Toggle/ Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set Macro
No
No
No
No
No
Macro
FTDRSLE
Macro
Macro
Macro
Macro
Macro
Macro
FTP FTPE
Toggle Flip-Flop with Toggle Macro Enable and Asynchronous Preset Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Preset Macro
Macro Macro
Macro Macro
Macro Macro
Macro Macro
Macro Macro
Macro Macro
76
Design Element FTPLE
Description Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Preset Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset
Spartan-3 Macro
Virtex, E Macro
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
FTRSE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
FTRSLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
FTSRE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
FTSRLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
77
General
General elements include FPGA configuration functions, oscillators, boundary scan logic, and other functions not classified in other sections.
Design Element BSCAN_SPARTAN2 BSCAN_SPARTAN3 BSCAN_VIRTEX BSCAN_VIRTEX2 CAPTURE_SPARTA N2 CAPTURE_SPARTA N3 CAPTURE_VIRTEX Description Spartan-II Boundary Scan Logic Control Circuit. Spartan-3 Boundary Scan Logic Control Circuit Virtex Boundary Scan Logic Control Circuit. Virtex2 Boundary Scan Logic Control Circuit Spartan-II Register State Capture for Bitstream Readback Spartan-3 Register State Capture for Bitstream Readback Virtex Register State Capture for Bitstream Readback Virtex-II Register State Capture for Bitstream Readback Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Spartan-II, IIE Primitivea No Primitiveb No Primitive No Primitive No No No Spartan3 Virtex, E No No Primitive No No Virtex II, Pro, Pro X No No No Primitive No No No No No No XC9500/XV/ XL CR XPLA3 No No No No No CR-II No No No No No
No
Primitive
No
No
No
No
No
No
No
Primitive
No
No
No
No
CAPTURE_VIRTEX2
No
No
No
Primitive
No
No
No
CLK_DIV2 CLK_DIV4 CLK_DIV6 CLK_DIV8 CLK_DIV10 CLK_DIV12 CLK_DIV14 CLK_DIV16 CLK_DIV2R CLK_DIV4R CLK_DIV6R CLK_DIV8R CLK_DIV10R CLK_DIV12R CLK_DIV14R CLK_DIV16R CLK_DIV2RSD
No No No No No No No No No No No No No No No No No
Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive
CLK_DIV4RSD
No
No
No
No
No
No
Primitive
78
Design Element CLK_DIV6RSD
Description Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Clock Delay Locked Loop. Clock Delay Locked Loop with Expanded Output. High Frequency Clock Delay Locked Loop. Digital Clock Manager Ground-Connection Signal Tag User Interface to Virtex-II Internal Configuration Access Port JTAG Primitive for the Power PC. KEEPER Symbol 1-Bit Look-Up-Table with General Output 2-Bit Look-Up-Table with General Output 3-Bit Look-Up-Table with General Output 4-Bit Look-Up-Table with General Output 1-Bit Look-Up-Table with Dual Output
Spartan-II, IIE No
Spartan3 No
Virtex, E No
XC9500/XV/ XL No
CR XPLA3 No
CR-II Primitive
CLK_DIV8RSD
No
No
No
No
No
No
Primitive
CLK_DIV10RSD
No
No
No
No
No
No
Primitive
CLK_DIV12RSD
No
No
No
No
No
No
Primitive
CLK_DIV14RSD
No
No
No
No
No
No
Primitive
CLK_DIV16RSD
No
No
No
No
No
No
Primitive
CLK_DIV2SD CLK_DIV4SD CLK_DIV6SD CLK_DIV8SD CLK_DIV10SD CLK_DIV12SD CLK_DIV14SD CLK_DIV16SD CLKDLL CLKDLLE CLKDLLHF DCM GND ICAP_VIRTEX2
No No No No No No No No Primitive Primitivec Primitive No Primitive No
No No No No No No No No No No No Primitive Primitive No
No No No No No No No No Primitive Primitived Primitivee No Primitive No
No No No No No No No No No No No Primitive Primitive Primitive
No No No No No No No No No No No No Primitive No
No No No No No No No No No No No No Primitive No
Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive No No No No Primitive No
JTAGPPC KEEPER LUT1 LUT2 LUT3 LUT4 LUT1_D
No Primitive Primitive Primitive Primitive Primitive Primitive
Primitivef Primitive Primitive Primitive Primitive Primitive Primitive
No Nog No No No No No
No No No No No No No
No Primitive No No No No No
79
Design Element LUT2_D LUT3_D LUT4_D LUT1_L LUT2_L LUT3_L LUT4_L PPC405 PULLDOWN PULLUP
Description 2-Bit Look-Up-Table with Dual Output 3-Bit Look-Up-Table with Dual Output 4-Bit Look-Up-Table with Dual Output 1-Bit Look-Up-Table with Local Output 2-Bit Look-Up-Table with Local Output 3-Bit Look-Up-Table with Local Output 4-Bit Look-Up-Table with Local Output Primitive for the Power PC Core. Resistor to GND for Input Pads Resistor to VCC for Input PADs, Open-Drain, and 3State Outputs Reset On Configuration VHDL Simulation of FPGA Designs Spartan-II User Interface to Global Clock, Reset, and 3State Controls. Spartan-3 User Interface to Global Clock, Reset, and 3State Controls Virtex User Interface to Global Clock, Reset, and 3State Controls. Virtex-II User Interface to Global Clock, Reset, and 3State Controls Three-State On Configuration Three-State On Configuration Buffer VCC-Connection Signal Tag
Spartan-II, IIE Primitive Primitive Primitive Primitive Primitive Primitive Primitive No Primitive Primitive
Spartan3 Primitive Primitive Primitive Primitive Primitive Primitive Primitive No Primitive Primitive
Virtex, E Primitive Primitive Primitive Primitive Primitive Primitive Primitive No Primitive Primitive
Virtex II, Pro, Pro X Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitiveh Primitive Primitive
XC9500/XV/ XL No No No No No No No No No No
CR XPLA3 No No No No No No No No No Primitive
CR-II No No No No No No No No No Primitive
ROC STARTBUF_ architecture STARTUP_SPARTA N2 STARTUP_SPARTA N3 STARTUP_VIRTEX
Primitive Primitive Primitivei
Primitive Primitive No
No No No
No No No
No No No
No
Primitive
No
No
No
No
No
Primitivej
No
Primitive
No
No
No
No
STARTUP_VIRTEX2
No
No
No
Primitive
No
No
No
TOC TOCBUF VCC
Primitive Primitive Primitive
No No Primitive
No No Primitive
No No Primitive
a.Primitive is supported for Spartan-II, but not for Spartan-IIE, which is supported by BSCAN_VIRTEX b.Primitive is supported for Spartan-IIE, but not for Spartan-II, which is supported by BSCAN_SPARTAN2. c. Supported for Spartan-IIE and Virtex-E devices only. d. Supported for Spartan-IIE and Virtex-E devices only. e.For Virtex E, use CLKDLLHF in HF mode. In LF mode, both the separate CLKDLLE and CLKDLL primitive can be used. f.Not supported for Virtex-II. Supported for Virtex-II PRO only. g.Under XC9500, the Primitive implementation applies only to XC9500XL/XV. h.The Primitive in the Virtex-II field is supported for Virtex-II PRO only. i.The Primitive in the field marked Spartan IIE is supported only for Spartan-II but not for Spartan-IIE, the latter of which is supported by STARTUP_VIRTEX. j.The Primitive in the Spartan IIE field is supported for Spartan-IIE, but not for Spartan-II, which is supported by STARTUP_SPARTAN2.
80
Input Latches
Single and multiple input latches can hold transient data entering a chip. Input latches use the same naming convention as I/O flip-flops.
Design Element ILD ILD4 ILD8 ILD16 ILD_1 ILDI Description Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch with Inverted Gate Transparent Input Data Latch (Asynchronous Preset) Transparent Input Data Latch with Inverted Gate (Asynchronous Preset) Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch with Inverted Gate Transparent Input Data Latch (Asynchronous Preset) Transparent Input Data Latch with Inverted Gate (Asynchronous Preset) Spartan-II, IIE Macro Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro No No No No No No XC9500/XV/ XL CR XPLA3 No Nob No No No No CR-II No No No No No No
ILDI_1
Macro
Macro
Macro
Macro
No
No
No
ILDX ILDX4 ILDX8 ILDX16 ILDX_1 ILDXI
No No No No No No
No No No No No No
No No No No No No
ILDXI_1
Macro
Macro
Macro
Macro
No
No
No
81
Input/Output Flip-Flops
Input/Output flip-flops are configured in IOBs. They include flip-flops whose outputs are enabled by 3-state buffers, flip-flops that can be set upon global set/reset rather than reset, and flip-flops with inverted clock inputs. The naming convention specifies each flip-flop function and is illustrated in the following figure.
OFDEI_1
Output (O), Input (I) Flip-Flop D-Type Active High Enable (E) Active Low Enable (T) Inverse of Normal Initial State Inverted Clock
X4580
Input/Output Flip-Flop Naming Convention

Design Element IFD IFD_1 IFD4 IFD8 IFD16 IFDDRCPE Description Single- and Multiple-Input D Flip-Flop Input D Flip-Flop with Inverted Clock Single- and Multiple-Input D Flip-Flop Single- and Multiple-Input D Flip-Flop Single- and Multiple-Input D Flip-Flop Dual Data Rate Input D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Data Rate Input D Flip-Flop with Synchronous Reset and Set and Clock Enable Input D Flip-Flop (Asynchronous Preset) Input D Flip-Flop with Inverted Clock (Asynchronous Preset) Single- and Multiple-Input D Flip-Flop with Clock Enable Input D Flip-Flop with Inverted Clock and Clock Enable Single- and Multiple-Input D Flip-Flop with Clock Enable Single- and Multiple-Input D Flip-Flop with Clock Enable Single- and Multiple-Input D Flip-Flops with Clock Enable Spartan-II, IIE Macro Macro Macro Macro Macro No Spartan3 Macro Macro Macro Macro Macro Primitive Virtex, E Macro Macro Macro Macro Macro No Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Primitive No No No No No No XC9500/XV/ XL CR XPLA3 No No No No No No CR-II No No No No No No
IFDDRRSE
No
Primitive
No
Primitive
No
No
No
IFDI IFDI_1
Macro Macro
Macro Macro
Macro Macro
Macro Macro
No No
No No
No No
IFDX
Macro
Macro
Macro
Macro
No
No
No
IFDX_1
Macro
Macro
Macro
Macro
No
No
No
IFDX4
Macro
Macro
Macro
Macro
No
No
No
IFDX8
Macro
Macro
Macro
Macro
No
No
No
IFDX16
Macro
Macro
Macro
Macro
No
No
No
82
Design Element IFDXI
Description Input D Flip-Flop with Clock Enable (Asynchronous Preset) Single- and MultipleOutput D Flip-Flops Single- and MultipleOutput D Flip-Flops Single- and MultipleOutput D Flip-Flops Single- and MultipleOutput D Flip-Flops Output D Flip-Flop with Inverted Clock Dual Data Rate Output D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Data Rate Output D Flip-Flop with Synchronous Reset and Set and Clock Enable Dual Data Rate D Flip-Flop with Active-Low 3--State Output Buffer, Clock Enable, and Asynchro-nous Preset and Clear Dual Data Rate D Flip-Flop with Active -Low 3-State Output Buffer, Synchronous Reset and Set, and Clock Enable
Spartan3 Macro
Virtex, E Macro
XC9500/XV/ XL No
CR XPLA3 No
CR-II No
OFD OFD4 OFD8 OFD16 OFD_1 OFDDRCPE
Macro Macro Macro Macro Macro No
Macro Macro Macro Macro Macro Primitive
Macro Macro Macro Macro Macro No
Macro Macro Macro Macro Macro Primitive
No No No No No No
No No No No No No
No No No No No No
OFDDRRSE
No
Primitive
No
Primitive
No
No
No
OFDDRTCPE
No
Primitive
No
Primitive
No
No
No
OFDDRTRSE
No
Primitive
No
Primitive
No
No
No
OFDE OFDE4 OFDE8 OFDE16 OFDE_1
D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveHigh Enable Output Buffer and Inverted Clock Output D Flip-Flop (Asynchronous Preset) Output D Flip-Flop with Inverted Clock (Asynchronous Preset) Single and Multiple D FlipFlop with Active-Low 3State Output Buffers Single and Multiple D FlipFlop with Active-Low 3State Output Buffers Single and Multiple D FlipFlop with Active-Low 3State Output Buffers Single and Multiple D FlipFlop with Active-Low 3State Output Buffers D Flip-Flop with ActiveLow 3-State Output Buffer and Inverted Clock Macro
No No No No No
No No No No No
No No No No No
OFDI OFDI_1
Macro Macro
Macro Macro
Macro Macro
Macro Macro
No No
No No
No No
OFDT
Macro
Macro
Macro
Macro
No
No
No
OFDT4
Macro
Macro
Macro
Macro
No
No
No
OFDT8
Macro
Macro
Macro
Macro
No
No
No
OFDT16
Macro
Macro
Macro
Macro
No
No
No
OFDT_1
Macro
Macro
Macro
Macro
No
No
No
83
Design Element OFDX
Description Single- and MultipleOutput D Flip-Flop with Clock Enable Single- and MultipleOutput D Flip-Flop with Clock Enable Single- and MultipleOutput D Flip-Flop with Clock Enable Single- and MultipleOutput D Flip-Flop with Clock Enable Output D Flip-Flop with Inverted Clock and Clock Enable Output D Flip-Flop with Clock Enable (Asynchronous Preset) Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
Spartan3 Macro
Virtex, E Macro
XC9500/XV/ XL No
CR XPLA3 No
CR-II No
OFDX4
Macro
Macro
Macro
Macro
No
No
No
OFDX8
Macro
Macro
Macro
Macro
No
No
No
OFDX16
Macro
Macro
Macro
Macro
No
No
No
OFDX_1
Macro
Macro
Macro
Macro
No
No
No
OFDXI
Macro
Macro
Macro
Macro
No
No
No
OFDXI_1
Macro
Macro
Macro
Macro
No
No
No
84
Input/Output Functions
Input/Output Block (IOB) resources are configured into various I/O primitives and macros for convenience, such as output buffers (s) and output buffers with an enable (OBUFEs). Pads used to connect the circuit to PLD device pins are also included. Virtex, Virtex-E, Spartan-II, Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro, and VirtexII Pro X have multiple variants (Primitives) to choose from for each SelectIO buffer. The I/O interface for each variant corresponds to a specific I/O standard.
Design Element GT_AURORA_n GT_CUSTOM GT_ETHERNET_n GT_FIBRE_CHAN_n GT_INFINIBAND_n GT_XAUI_n GT10_10GE_n GT10_10GFC_n GT10_AURORA_n GT10_AURORAX_n GT10_CUS-TOM GT10_OC48_n GT10_OC192_n GT10_PCI_EXPRESS_n GT10_XAUI_n IBUF IBUF4 IBUF8 IBUF16 IBUF_ selectIO IBUFDS Description Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. Single- and MultipleInput Buffer Single- and MultipleInput Buffer Single- and MultipleInput Buffer Single- and MultipleInput Buffer Single Input Buffer with Selectable I/O Interface (multiple primitives) Differential Signaling Input Buffer with Selectable I/O Interface Dedicated Input Buffer with Selectable I/O Interface Spartan-II, IIE No No No No No No No No No No No No No No No Primitive Macro Macro Macro Primitive Spartan-3 No No No No No No No No No No No No No No No Primitive No No No Primitive Virtex, E No No No No No Primitive No Primitive No No No No No Primitive No Primitive Macro Macro Macro Primitive Virtex II, Pro, Pro X Primitive Primitive Primitive Primitive Primitive No Primitive No Primitive Primitive Primitive Primitive Primitive No Primitive Primitive Macro Macro Macro Primitive No No No No No No No No No No No No No No No Primitive Macro Macro Macro No XC9500/XV/ XL CR XPLA3 No No No No No No No No No No No No No No No Primitive Macro Macro Macro No CR-II No No No No No No No No No No No No No No No Primitive Macro Macro Macro No
No
Primitive
No
Primitive
No
No
No
IBUFG
Primitive
Primitive
Primitive
Primitive
No
No
No
85
Design Element IBUFG_selectIO
Description Dedicated Input Buffer with Selectable I/O Interface (multiple primitives) Dedicated Differential Signaling Input Buffer with Selectable I/O Interface Differential I/O Input Buffer with Differential Outputs Bi-Directional Buffer with Selectable I/0 Interface (multiple primitives) Bi-Directional Buffer with Selectable I/0 Interface (multiple primitives) 3-State Differential Signaling I/O Buffer with Active Low Output Enable Single- and MultipleInput/Output Pad Single- and MultipleInput/Output Pad Single- and MultipleInput/Output Pad Single- and MultipleInput/Output Pad Single- and MultipleInput Pad Single- and MultipleInput Pad Single- and MultipleInput Pad Single- and MultipleInput Pad Single 3-State Output Buffer with Active-Low Output Enable and Selectable I/O Interface (multiple primitives) Single- and MultipleOutput Buffer Single- and MultipleOutput Buffer Single- and MultipleOutput Buffer Single- and MultipleOutput Buffer Differential Signaling Output Buffer with Selectable I/O Interface 3-State Output Buffers with Active-High Output Enable 3-State Output Buffers with Active-High Output Enable
Spartan-3 Primitive
Virtex, E Primitive
XC9500/XV/ XL No
CR XPLA3 No
CR-II No
IBUFGDS
No
Primitive
No
Primitive
No
No
No
IBUFGDS_DIFF_OUT
No
Primitive
No
Primitive
No
No
No
IOBUF
Primitive
Primitive
Primitive
Primitive
No
No
No
IOBUF_selectIO
Primitive
Primitive
Primitive
Primitive
No
No
No
IOBUFDS
No
Primitive
No
Primitive
No
No
No
IOPAD IOPAD4 IOPAD8 IOPAD16 IPAD IPAD4 IPAD8 IPAD16 OBUF_selectIO
Primitive Macro Macro Macro Primitive Macro Macro Macro Primitive
Primitive Macro Macro Macro Primitive Macro Macro Macro No
OBUF OBUF4 OBUF8 OBUF16 OBUFDS
Primitive Macro Macro Macro No
Primitive Macro Macro Macro Primitive
OBUFE
Macro
No
Macro
Macro
Primitive
Primitive
Primitive
OBUFE4
Macro
No
Macro
Macro
Macro
Macro
Macro
86
Design Element OBUFE8
Description 3-State Output Buffers with Active-High Output Enable 3-State Output Buffers with Active-High Output Enable Single and Multiple 3State Output Buffer with Active Low Output Enable Single 3-State Output Buffer with Active-Low Output Enable and Selectable I/O Interface (multiple primitives) Single and Multiple 3State Output Buffer with Active Low Output Enable Single and Multiple 3State Output Buffer with Active Low Output Enable Single and Multiple 3State Output Buffer with Active Low Output Enable 3-State Output Buffer with Differential Signaling, Active-Low Output Enable, and Selectable I/O Interface Single- and MultipleOutput Pad Multiple-Output Pad Multiple-Output Pad Multiple-Output Pad Connects the I/O Node of an IOB to the Internal PLD Circuit
Spartan-3 No
Virtex, E Macro
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
OBUFE16
Macro
No
Macro
Macro
Macro
Macro
Macro
OBUFT
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OBUFT_selectIO
Primitive
Primitive
Primitive
Primitive
No
No
No
OBUFT4
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OBUFT8
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OBUFT16
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OBUFTDS
No
Primitive
No
Primitive
No
No
No
OPAD OPAD4 OPAD8 OPAD16 UPAD
87
Latches
Latches (LD) are available for all architectures.
Design Element LD LD_1 LD4 LD8 LD16 LD4CE Description Transparent Data Latch Transparent Data Latch with Inverted Gate Multiple Transparent Data Latch Multiple Transparent Data Latch Multiple Transparent Data Latch Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear Transparent Data Latch with Asynchronous Clear and Inverted Gate Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear, Gate Enable, and Inverted Gate Transparent Data Latch with Asynchronous Clear and Preset Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate Spartan-II, IIE Primitive Primitive Macro Macro Macro Macro Spartan-3 Primitive Primitive Macro Macro Macro Macro Virtex, E Primitive Primitive Macro Macro Macro Macro Virtex II, Pro, Pro X Primitive Primitive Macro Macro Macro Macro XC9500/XV/ XL Macro No Macro Macro Macro No CR XPLA3 Primitive No Macro Macro Macro No CR-II Primitive No Macro Macro Macro No
LD8CE
Macro
Macro
Macro
Macro
No
No
No
LD16CE
Macro
Macro
Macro
Macro
No
No
No
LDC LDC_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
Macro No
Primitive No
Primitive No
LDCE
Primitive
Primitive
Primitive
Primitive
No
No
No
LDCE_1
Primitive
Primitive
Primitive
Primitive
No
No
No
LDCP
Primitive
Primitive
Primitive
Primitive
Macro
Primitive
Primitive
LDCP_1
Primitive
Primitive
Primitive
Primitive
No
No
No
LDCPE
Transparent Data Latch Primitive with Asynchronous Clear and Preset and Gate Enable Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable, and Inverted Gate Transparent Data Latch with Gate Enable Transparent Data Latch with Gate Enable and Inverted Gate Primitive
Primitive
Primitive
Primitive
No
No
No
LDCPE_1
Primitive
Primitive
Primitive
No
No
No
LDE LDE_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
No No
No No
No No
LDG LDG4 LDG8 LDG16
Transparent Datagate Latch No Multiple Transparent Datagate Latch Multiple Transparent Datagate Latch Multiple Transparent Datagate Latch No No No
No No No No
No No No No
No No No No
No No No No
No No No No
Primitive Macro Macro Macro
88
Design Element LDP LDP_1
Description Transparent Data Latch with Asynchronous Preset Transparent Data Latch with Asynchronous Preset and Inverted Gate Transparent Data Latch with Asynchronous Preset and Gate Enable Transparent Data Latch with Asynchronous Preset, Gate Enable, and Inverted Gate
Spartan-II, IIE Primitive Primitive
Spartan-3 Primitive Primitive
Virtex, E Primitive Primitive
Virtex II, Pro, Pro X Primitive Primitive
XC9500/XV/ XL Macro No
CR XPLA3 Macro No
CR-II Macro No
LDPE
Primitive
Primitive
Primitive
Primitive
No
No
No
LDPE_1
Primitive
Primitive
Primitive
Primitive
No
No
No
89
Logic Primitives
Combinatorial logic gates that implement the basic Boolean functions are available in all architectures with up to five inputs in all combinations of inverted and noninverted inputs, and with six to nine inputs non-inverted.
Design Element AND2 Description 2-Input AND Gate with Inverted and Non-Inverted Inputs 2-Input AND Gate with Inverted and Non-Inverted Inputs 2-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs Spartan-II, IIE Primitive Spartan-3 Primitive Virtex, E Primitive Virtex II, Pro, Pro X Primitive XC9500/XV/ XL Primitive CR XPLA3 Primitive CR-II Primitive
AND2B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND2B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND3
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
AND3B1
Macro
Macro
Macro
Macro
Macro
Macro
Macro
AND3B2
Macro
Macro
Macro
Macro
Macro
Macro
Macro
AND3B3
Macro
Macro
Macro
Macro
Macro
Macro
Macro
AND4
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
AND4B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND4B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND4B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND4B4
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND5
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
AND5B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND5B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND5B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND5B4
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
AND5B5
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
90
Design Element AND6
Description 6-Input AND Gate with Inverted and Non-Inverted Inputs 7-Input AND Gate with Inverted and Non-Inverted Inputs 8-Input AND Gate with Inverted and Non-Inverted Inputs 9-Input AND Gate with Inverted and Non-Inverted Inputs 12- Input AND Gate with Non-Inverted Inputs 16- Input AND Gate with Non-Inverted Inputs
Spartan-3 Macro
Virtex, E Macro
XC9500/XV/ XL Primitive
CR XPLA3 Primitive
CR-II Primitive
AND7
Macro
Macro
Macro
Macro
Primitive
Primitive
Primitive
AND8
Macro
Macro
Macro
Macro
Primitive
Primitive
Primitive
AND9
Macro
Macro
Macro
Macro
Primitive
Primitive
Primitive
AND12 AND16 INV INV4 INV8 INV16 MULT_AND NAND2
Macro Macro
Macro Macro Primitive Macro Macro Macro Primitive Primitive
No No Primitive Macro Macro Macro No Primitive
Single and Multiple Inverters Primitive Single and Multiple Inverters Macro Single and Multiple Inverters Macro Single and Multiple Inverters Macro Fast Multiplier AND 2-Input NAND Gate with Inverted and Non-Inverted Inputs. 2-Input NAND Gate with Inverted and Non-Inverted Inputs. 2-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. Primitive Primitive
NAND2B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND2B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND3
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
NAND3B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND3B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND3B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND4
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
NAND4B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND4B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND4B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND4B4
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND5
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
91
Design Element NAND5B1
Description 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 6-Input NAND Gate with Inverted and Non-Inverted Inputs. 7-Input NAND Gate with Inverted and Non-Inverted Inputs. 8-Input NAND Gate with Inverted and Non-Inverted Inputs. 9-Input NAND Gate with Inverted and Non-Inverted Inputs. 12- Input NAND Gate with Non-Inverted Inputs. 16- Input NAND Gate with Non-Inverted Inputs. 2- Input NOR Gate with Inverted and Non-Inverted Inputs. 3- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 6- Input NOR Gate with Inverted and Non-Inverted Inputs 7- Input NOR Gate with Inverted and Non-Inverted Inputs 8- Input NOR Gate with Inverted and Non-Inverted Inputs 9- Input NOR Gate with Inverted and Non-Inverted Inputs 12-Input NOR Gate with Non-Inverted Inputs 16-Input NOR Gate with Non-Inverted Inputs 2- Input NOR Gate with Inverted and Non-Inverted Inputs
Spartan-3 Primitive
Virtex, E Primitive
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
NAND5B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND5B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND5B4
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND5B5
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NAND6
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NAND7
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NAND8
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NAND9
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NAND12 NAND16 NOR2
Macro Macro Primitive
No No Primitive
No No Primitive
No No Primitive
NOR3
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
NOR4
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
NOR5
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
NOR6
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NOR7
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NOR8
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NOR9
Macro
Macro
Macro
Macro
Macro
Macro
Macro
NOR12 NOR16 NOR2B1
No No Macro
No No Macro
No No Macro
92
Design Element NOR2B2
Description 2- Input NOR Gate with Inverted and Non-Inverted Inputs 3- Input NOR Gate with Inverted and Non-Inverted Inputs 3- Input NOR Gate with Inverted and Non-Inverted Inputs 3- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 2-Input OR Gate with Inverted and Non-Inverted Inputs 2-Input OR Gate with Inverted and Non-Inverted Inputs 2-Input OR Gate with Inverted and Non-Inverted Inputs 3-Input OR Gate with Inverted and Non-Inverted Inputs 3-Input OR Gate with Inverted and Non-Inverted Inputs 3-Input OR Gate with Inverted and Non-Inverted Inputs 3Input OR Gate with Inverted and Non-Inverted Inputs 4-Input OR Gate with Inverted and Non-Inverted Inputs
Spartan-3 Primitive
Virtex, E Primitive
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
NOR3B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR3B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR3B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR4B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR4B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR4B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR4B4
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR5B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR5B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR5B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR5B4
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
NOR5B5
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
OR2
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR2B1
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR2B2
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR3
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR3B1
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR3B2
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR3B3
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR4
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
93
Design Element OR4B1
Description 4-Input OR Gate with Inverted and Non-Inverted Inputs 4-Input OR Gate with Inverted and Non-Inverted Inputs 4-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 12-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 6-Input OR Gate with Inverted and Non-Inverted Inputs 6-Input OR Gate with Inverted and Non-Inverted Inputs 8-Input OR Gate with Inverted and Non-Inverted Inputs 9-Input OR Gate with Inverted and Non-Inverted Inputs 12-Input OR Gate with Inverted and Non-Inverted Inputs 16-Input OR Gate with Inverted and Non-Inverted Inputs OR with Carry Logic Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products 2-Input XNOR Gate with Non-Inverted Inputs
Spartan-3 Primitive
Virtex, E Primitive
XC9500/XV/ XL Primitive
CR XPLA3 Primitive
CR-II Primitive
OR4B2
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR4B3
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
Primitive
OR5B1
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
OR5B2
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
OR5B3
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
OR5B4
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
OR5B5
Primitive
Primitive
Primitive
Primitive
Macro
Macro
Macro
OR6
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OR7
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OR8
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OR9
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OR12
Macro
Macro
Macro
Macro
No
No
No
OR16
Macro
Macro
Macro
Macro
No
No
No
ORCY SOP3 SOP3B1A SOP3B1B SOP3B2A SOP3B2B SOP3B3 SOP4 SOP4B3 SOP4B4 SOP4B1 SOP4B2A SOP4B2B XNOR2
Primitive Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Primitive
No No No No No No No No No No No No No Primitive
94
Design Element XNOR3 XNOR4 XNOR5 XNOR6 XNOR7 XNOR8 XNOR9 XOR2 XOR3 XOR4 XOR5 XOR6 XOR7 XOR8 XOR9 XORCY XORCY_D XORCY_L
Description 3-Input XNOR Gate with Non-Inverted Inputs 4-Input XNOR Gate with Non-Inverted Inputs 5-Input XNOR Gate with Non-Inverted Inputs 6-Input XNOR Gate with Non-Inverted Inputs 7-Input XNOR Gate with Non-Inverted Inputs 8-Input XNOR Gate with Non-Inverted Inputs 9-Input XNOR Gate with Non-Inverted Inputs 2-Input XOR Gate with NonInverted Inputs 3-Input XOR Gate with NonInverted Inputs 4-Input XOR Gate with NonInverted Inputs 5-Input XOR Gate with NonInverted Inputs 6-Input XOR Gate with NonInverted Inputs 7-Input XOR Gate with NonInverted Inputs 8-Input XOR Gate with NonInverted Inputs 9-Input XOR Gate with NonInverted Inputs XOR for Carry Logic with General Output XOR for Carry Logic with Dual Output XOR for Carry Logic with Local Output
Spartan-II, IIE Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive
Spartan-3 Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive
Virtex, E Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive
Virtex II, Pro, Pro X Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive
XC9500/XV/ XL Primitive Primitive Macro Macro Macro Macro Macro Primitive Primitive Primitive Macro Macro Macro Macro Macro No No No
CR XPLA3 Primitive Primitive Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro Macro No No No
CR-II Primitive Primitive Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro Macro No No No
95
Map Elements
Map elements are used in conjunction with logic symbols to constrain the logic to particular CLBs or particular F function generators.
Design Element FMAP Description F Function Generator Partitioning Control Symbol Spartan-II, IIE Primitive Spartan-3 Primitive Virtex, E Primitive Virtex II, Pro, Pro X Primitive XC9500/XV/ XL No CR XPLA3 No CR-II No
96
Memory Elements
In the Virtex, Virtex-E, Spartan-II, and Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X architectures, a number of static RAMs are defined as primitives. These 16- or 32-word RAMs are 1, 2, 4, and 8 bits wide. The Virtex, Virtex-E, Spartan-II, and Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X architectures have dedicated blocks of on-chip 4096-bit single-port and dual-port synchronous RAM. Each port is configured to a specific data width. There are five single-port block RAM primitives and 30 dual-port block RAM primitives.
Design Element RAM16X1D RAM16X1D_1 Description 16-Deep by 1-Wide Static Dual Port Synchronous RAM 16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock 16-Deep by 1-Wide Static Synchronous RAM 16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 16-Deep by 2-Wide Static Dual Port Synchronous RAM 16-Deep by 2-Wide Static Synchronous RAM 16-Deep by 4-Wide Static Dual Port Synchronous RAM 16-Deep by 4-Wide Static Synchronous RAM 16-Deep by 8-Wide Static Dual Port Synchronous RAM 16-Deep by 8-Wide Static Synchronous RAM 32-Deep by 1-Wide Static Dual Static Port Synchronous RAM 32-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock 32-Deep by 1-Wide Static Synchronous RAM 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 32-Deep by 2-Wide Static Synchronous RAM 32-Deep by 4-Wide Static Synchronous RAM 32-Deep by 8-Wide Static Synchronous RAM 64-Deep by 1-Wide Dual Port Static Synchronous RAM 64-Deep by 1-Wide Dual Port Static Synchronous RAM with Negative-Edge Clock 64-Deep by 1-Wide Static Synchronous RAM Spartan-II, IIE Primitive Primitive Spartan-3 Primitive Primitive Virtex, E Primitive Primitive Virtex II, Pro, Pro X Primitive Primitive No No XC9500/XV/ XL CR XPLA3 No No CR-II No No
RAM16X1S RAM16X1S_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
No No
No No
No No
RAM16X2D RAM16X2S RAM16X4D RAM16X4S RAM16X8D RAM16X8S RAM32X1D RAM32X1D_1
Macro Macro Macro Macro Macro Macro No No
No Primitive No Primitive No No No No
Macro Macro Macro Macro Macro Macro No No
Macro Primitive Macro Primitive Macro Primitive Primitive Primitive
No No No No No No No No
RAM32X1S RAM32X1S_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
No No
No No
No No
RAM32X2S RAM32X4S RAM32X8S RAM64X1D RAM64X1D_1
Macro Macro Macro No No
Primitive No No No No
Macro Macro Macro No No
Primitive Primitive Primitive Primitive Primitive
No No No No No
No No No No No
No No No No No
RAM64X1S
No
Primitive
No
Primitive
No
No
No
97
Design Element RAM64X1S_1
Description 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 64-Deep by 2-Wide Static Synchronous RAM 128-Deep by 1-Wide Static Synchronous RAM 128-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 4096-Bit Dual-Port Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 8, or 16 Bits 4096-Bit Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 8, or 16 Bits
Spartan-II, IIE No
Spartan-3 Primitive
Virtex, E No
XC9500/XV/ XL No
CR XPLA3 No
CR-II No
RAM64X2S RAM128X1S RAM128X1S_1
No No No
No No No
No No No
No No No
No No No
No No No
RAMB4_Sm_Sn
Primitive
No
Primitive
No
No
No
No
RAMB4_Sn
Primitive
No
Primitive
No
No
No
No
RAMB16_Sm_Sn
16384-Bit Data Memory and No 2048-Bit Parity Memory, DualPort Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 9, 18, or 36 Bits 16384-Bit Data Memory and 2048-Bit Parity Memory, Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 9, 18, or 36 Bits Reset On Configuration No
Primitive
No
Primitive
No
No
No
RAMB16_Sn
Primitive
No
Primitive
No
No
No
ROC ROCBUF ROM16X1 ROM32X1 ROM64X1 ROM128X1 ROM256X1
Primitive
Primitive Primitive Primitive Primitive Primitive Primitive Primitive
Primitive Primitive Primitive Primitive No No No
Primitive Primitive Primitive Primitive Primitive Primitive Primitive
Reset On Configuration Buffer Primitive 16-Deep by 1-Wide ROM 32-Deep by 1-Wide ROM 64-Deep by 1-Wide ROM 128-Deep by 1-Wide ROM 256-Deep by 1-Wide ROM Primitive Primitive No No No
98
Multiplexers
The multiplexer naming convention shown in the following figure indicates the number of inputs and outputs and whether or not an enable is available.
M8_1E
Multiplexer Number of Inputs Number of Outputs Output Enable
X4620
Multiplexer Naming Convention

Design Element M2_1 M2_1B1 M2_1B2 M2_1E M4_1E M8_1E M16_1E MUXCY MUXCY_D MUXCY_L MUXF5 Description 2-to-1 Multiplexer 2-to-1 Multiplexer with D0 Inverted 2-to-1 Multiplexer with D0 and D1 Inverted 2-to-1 Multiplexer with Enable 4-to-1 Multiplexer with Enable 8-to-1 Multiplexer with Enable 16-to-1 Multiplexer with Enable 2-to-1 Multiplexer for Carry Logic with General Output 2-to-1 Multiplexer for Carry Logic with Dual Output 2-to-1 Multiplexer for Carry Logic with Local Output 2-to-1 Lookup Table Multiplexer with General Output 2-to-1 Lookup Table Multiplexer with Dual Output 2-to-1 Lookup Table Multiplexer with Local Output 2-to-1 Lookup Table Multiplexer with General Output 2-to-1 Lookup Table Multiplexer with Dual Output 2-to-1 Lookup Table Multiplexer with Local Output 2-to-1 Lookup Table Multiplexer with General Output 2-to-1 Lookup Table Multiplexer with Dual Output 2-to-1 Lookup Table Multiplexer with Local Output 2-to-1 Lookup Table Multiplexer with General Output Spartan-II, IIE Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Spartan-3 Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Virtex, E Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive XC9500/XV/ XL Macro Macro Macro Macro Macro Macro Macro No No No No CR XPLA3 Macro Macro Macro Macro Macro Macro Macro No No No No CR-II Macro Macro Macro Macro Macro Macro Macro No No No No
MUXF5_D MUXF5_L MUXF6
No No No
No No No
No No No
No No No
No No No
No No No
No No No
No No No
No No No
No No No
No No No
99
Shifters
Shifters are barrel shifters (BRLSHFT) of four and eight bits.
Design Element BRLSHFT4 BRLSHFT8 Description 4-Bit Barrel Shifter 8-Bit Barrel Shifter Spartan-II, IIE Macro Macro Spartan-3 Macro Macro Virtex, E Macro Macro Virtex II, Pro, Pro X Macro Macro XC9500/XV/ XL Macro Macro CR XPLA3 Macro Macro CR-II Macro Macro
100
Shift Registers
Shift registers are available in a variety of sizes and capabilities. The naming convention shown in the following figure illustrates available features.
SR8RLED
Shift Register Bit Size Synchronous Reset (R) Asynchronous Clear (C) Loadable Clock Enable Directional
X4578
Shift Register Naming Convention

Design Element SR4CE Description 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 4-Bit Shift Register with Clock Enable and Asynchronous Clear 8-Bit Shift Register with Clock Enable and Asynchronous Clear 16-Bit Shift Register with Clock Enable and Asynchronous Clear 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset Spartan-II, IIE Macro Spartan-3 Macro Virtex, E Macro Virtex II, Pro, Pro X Macro XC9500/XV/ XL Macro CR XPLA3 Macro CR-II Macro
SR8CE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR16CE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR4CLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR8CLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR16CLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR4CLED SR8CLED SR16CLED SR4RE
SR8RE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR16RE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR4RLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
101
Design Element SR8RLE
Description 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 4-Bit Shift Register with Clock Enable and Synchronous Reset 8-Bit Shift Register with Clock Enable and Synchronous Reset 16-Bit Shift Register with Clock Enable and Synchronous Reset 4-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 8-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 4-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 8-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 8-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 16-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 4-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 8-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 4-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset
Spartan-3 Macro
Virtex, E Macro
XC9500/XV/ XL Macro
CR XPLA3 Macro
CR-II Macro
SR16RLE
Macro
Macro
Macro
Macro
Macro
Macro
Macro
SR4RLED SR8RLED SR16RLED SRD4CE
SRD8CE
No
No
No
No
No
No
Macro
SRD16CE
No
No
No
No
No
No
Macro
SRD4CLE
No
No
No
No
No
No
Macro
SRD8CLE
No
No
No
No
No
No
Macro
SRD16CLE
No
No
No
No
No
No
Macro
SRD4CLED
No
No
No
No
No
No
Macro
SRD8CLED
No
No
No
No
No
No
Macro
SRD16CLED
No
No
No
No
No
No
Macro
SRD4RE
No
No
No
No
No
No
Macro
SRD8RE
No
No
No
No
No
No
Macro
SRD16RE
No
No
No
No
No
No
Macro
SRD4RLE
No
No
No
No
No
No
Macro
102
Design Element SRD8RLE
Description 8-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 4-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 8-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Shift Register Look-UpTable (LUT) 16-Bit Shift Register Look-UpTable (LUT) with Negative-Edge Clock 16-Bit Shift Register Look-UpTable (LUT) with Clock Enable 16-Bit Shift Register Look-UpTable (LUT) with Negative-Edge Clock and Clock Enable 16-Bit Shift Register Look-UpTable (LUT) with Carry 16-Bit Shift Register Look-UpTable (LUT) with Carry and Negative-Edge Clock 16-Bit Shift Register Look-UpTable (LUT) with Carry and Clock Enable
Spartan-II, IIE No
Spartan-3 No
Virtex, E No
XC9500/XV/ XL No
CR XPLA3 No
CR-II Macro
SRD16RLE
No
No
No
No
No
No
Macro
SRD4RLED
No
No
No
No
No
No
Macro
SRD8RLED
No
No
No
No
No
No
Macro
SRD16RLED
No
No
No
No
No
No
Macro
SRL16 SRL16_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
No No
No No
No No
SRL16E SRL16E_1
Primitive Primitive
Primitive Primitive
Primitive Primitive
Primitive Primitive
No No
No No
No No
SRLC16 SRLC16_1
No No
Primitive Primitive
No No
Primitive Primitive
No No
No No
No No
SRLC16E
No
Primitive
No
Primitive
No
No
No
SRLC16E_1
16-Bit Shift Register Look-UpNo Table (LUT) with Carry, NegativeEdge Clock, and Clock Enable
Primitive
No
Primitive
No
No
No
103
104
Design Elements
The remaining sections in this book describe each design element that can be used with the supported architectures. Design elements are organized in alphanumeric order, with all numeric suffixes in ascending order. For example, FDR precedes FDRS, and ADD4 precedes ADD8, which precedes ADD16. The following information is provided for each library element, where applicable Graphic symbol Applicability table (with primitive versus macro identification) Functional description Truth table Schematic for macros VHDL and Verilog instantiation and inference code Commonly used constraints
105
Design Elements
106
ACC1
ACC1
1-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
Architectures Supported
ACC1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro
Virtex-II, Virtex-II Pro, Virtex-II Pro X No
CI B0 D0 L ADD CE C
ACC1
Q0 CO
X3862
ACC1 can add or subtract a 1-bit unsigned-binary word to or from the contents of a 1bit data register and store the results in the register. The register can be loaded with a 1-bit word. The synchronous reset (R) has priority over all other inputs and, when High, causes the output to go to logic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clock enable (CE) is Low. The accumulator is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Load
When the load input (L) is High, CE is ignored and the data on the input D0 is loaded into the 1-bit register during the Low-to-High clock (C) transition.
Add
When control inputs ADD and CE are both High, the accumulator adds a 1-bit word (B0) and carry-in (CI) to the contents of the 1-bit register. The result is stored in the register and appears on output Q0 during the Low-to-High clock transition. The carry-out (CO) is not registered synchronously with the data output. CO always reflects the accumulation of input B0 and the contents of the register, which allows cascading of ACC1s by connecting CO of one stage to CI of the next stage. In add mode, CO acts as a carry-out, and CO and CI are active-High.
Subtract
When ADD is Low and CE is High, the 1-bit word B0 and CI are subtracted from the contents of the register. The result is stored in the register and appears on output Q0 during the Low-to-High clock transition. The carry-out (CO) is not registered synchronously with the data output. CO always reflects the accumulation of input B0 and the contents of the register, which allows cascading of ACC1s by connecting CO of one stage to CI of the next stage. In subtract mode, CO acts as a borrow, and CO and CI are active-Low.
107
ACC1
VCC
CE CI ADD L
OR2 GND AND2
INV INV
B0
INV AND6
INV INV INV INV INV AND6
OR4
INV INV INV AND6
INV INV INV AND6
D0 FD
AND3B1 OR2 XOR2 D C Q
Q0
AND3B2
Q0
AND3
AND3
CO
AND3B2 OR5
AND3B2
AND2
X7688
ACC1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
108
ACC1
Usage
ACC is schematic and inference only-- not instantiated.
VHDL Inference Code

Following is some "basic" code for inference of the ACC modules.
architecture Behavioral of acc1 is begin process(C, R) begin if (R = '1') then Q <= (others => '0'); elsif (C'event and C = '1') then if (L = '1') then Q <= D; elsif (CE = '1') then if (ADD = '1') then Q <= Q + B; else Q <= Q - B; end if; end if; end if; end process; end Behavioral;
Verilog Inference Code

always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) end if (ADD) Q <= Q + B; else Q <= Q - B; end
Commonly Used Constraints

None
109
ACC1
110
ACC4, 8, 16
ACC4, 8, 16
4-, 8-, 16-Bit Loadable Cascadable Accumulators with Carry-In, CarryOut, and Synchronous Reset
ACC4, ACC8, ACC16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro
CI B0 B1 B2 B3 D0 D1 D2 D3 L ADD CE C
ACC4
Q0 Q1 Q2 Q3 CO OFL
ACC4, ACC8, ACC16 can add or subtract a 4-, 8-, 16-bit unsigned-binary, respectively or twos-complement word to or from the contents of a 4-, 8-, 16-bit data register and store the results in the register. The register can be loaded with the 4-, 8-, 16-bit word. The synchronous reset (R) has priority over all other inputs, and when High, causes all outputs to go to logic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clock enable (CE) is Low. The accumulator is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
X3863
CI B[7:0] D[7:0] L ADD CE C
ACC8
Q[7:0] CO OFL
Load
X4374
CI B[15:0] D[15:0] L ADD CE C
ACC16
Q[15:0] CO OFL
When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during the Low-to-High clock (C) transition. ACC4 loads the data on inputs D3 D0 into the 4-bit register. ACC8 loads the data on D7 D0 into the 8-bit register. ACC16 loads the data on inputs D15 D0 into the 16-bit register.
Unsigned Binary Versus Twos Complement

ACC4, ACC8, ACC16 can operate, respectively, on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twoscomplement operation is how they determine when overflow occurs. Unsigned
X4375
111
ACC4, 8, 16
binary uses CO, while twos complement uses OFL to determine when overflow occurs.
Unsigned Binary Operation

For unsigned binary operation, ACC4 can represent numbers between 0 and 15, inclusive; ACC8 between 0 and 255, inclusive; and ACC16 between 0 and 65535, inclusive. In add mode, CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) is not registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs (B3 B0 for ACC4, B7 B0 for ACC8, B15 B0 for ACC16) and the contents of the register. This allows cascading of ACC4s, ACC8s, or ACC16s by connecting CO of one stage to CI of the next stage. An unsigned binary overflow that is always activeHigh can be generated by gating the ADD signal and CO as follows.
unsigned overflow = CO XOR ADD
Ignore OFL in unsigned binary operation.
Twos-Complement Operation
For twos-complement operation, ACC4 can represent numbers between -8 and +7, inclusive; ACC8 between -128 and +127, inclusive; ACC16 between -32768 and +32767, inclusive. If an addition or subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is not registered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B3 B0 for ACC4, B7 B0 for ACC8, B15 B0 for ACC16) and the contents of the register, which allows cascading of ACC4s, ACC8s, or ACC16s by connecting OFL of one stage to CI of the next stage. Ignore CO in twos-complement operation.
112
ACC4, 8, 16
Q[7:0] CI CI A[7:0] B[7:0] B[7:0] ADD CO ADD RLOC=R0C0 D[7:0] M2_1 S0 D0 D0 D1 S0 O SD0 SD0 AND2B1 R_SD0 D Q CE C CLR FDCE Q0 OFL OFL CO S[7:0] S[7:0]
ADSU8
Q0 FMAP
RLOC=R3C0.S0 FMAP R S3 D3 L M2_1 I4 I3 I2 I1 O R_SD3 S1 D1 D0 D1 S0 O SD1 SD1 AND2B1 R_SD1 D Q CE C CLR FDCE Q1 R S7 D7 L I4 I3 I2 I1
R_SD7
Q1 RLOC=R0C0.S0
RLOC=R2C0.S0 RLOC=R3C0.S0 M2_1 S2 D2 FMAP R S2 D2 L I4 I3 I2 I1 D0 D1 S0 FDCE O SD2 SD2 AND2B1 O R_SD2 RLOC=R2C0.S0 M2_1 S3 D3 D0 D1 S0 O SD3 SD3 AND2B1 FMAP R S1 D1 L I4 I3 I2 I1 M2_1 O R_SD1 S4 D4 D0 D1 S0 O SD4 SD4 AND2B1 RLOC=R3C0.S0 R_SD4 R_SD3 FDCE D Q CE C CLR Q3 R_SD2 D Q CE C CLR Q2
FMAP Q2 R S6 D6 L I4 I3 I2 I1
R_SD6
RLOC=R2C0.S0
RLOC=R0C0.S0
Q3 FMAP R S5 D5 L I4 I3 I2 I1
RLOC=R2C0.S0 FDCE D Q CE C CLR Q4
R_SD5
Q4
RLOC=R1C0.S0
RLOC=R1C0.S0 M2_1 FMAP R S0 D0 L I4 I3 I2 I1 S5 D5 D0 D1 S0 O SD5 SD5 AND2B1 O R_SD0 R_SD5 FDCE D Q CE C CLR Q5 FMAP Q5 R S4 D4 L I4 I3 I2 I1
R_SD4
RLOC=R1C0.S0 M2_1 S6 D6 D0 D1 S0 O SD6 SD6 AND2B1 R_SD6
RLOC=R3C0.S0
FDCE D Q CE C CLR Q6
RLOC=R1C0.S0
Q6
RLOC=R0C0.S0 M2_1 S7 D7 D0 D1 S0 O SD7 SD7 AND2B1 L CE R C OR3 R_L_CE RLOC=R0C0.S0 R_SD7 FDCE D Q CE C CLR Q7
Q7
X8689 GND
ACC8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
113
ACC4, 8, 16
Q [7:0]
CI
ADSU8
CI A [7:0] S [7:0] S [7:0] B [7:0] OFL CO ADD OFL CO RLOC=X1Y0
B [7:0]
ADD D [7:0]
M2_1
S0 D0 D0 D1 S0 SD0 AND2B1 O SD0 R_SD0 D
FDCE
Q Q0 CE C CLR Q0
M2_1 FMAP
R S3 D3 L I4 I3 I2 I1 O R_SD3 S1 D1 D0 D1 S0 SD1 AND2B1 O SD1 R_SD1
RLOC=X0Y0
FDCE
D CE C CLR Q1 Q Q1 R S7 D7 L I4 I3 I2 I1
FMAP
R_SD7
M2_1
RLOC=X0Y1 S2 D2 D0 D1 S0 SD2 AND2B1 O R_SD2 O SD2 R_SD2
RLOC=X0Y0
FDCE
D CE C R CLR Q2 S6 D6 L Q Q3 Q Q2
RLOC=X0Y3
FMAP
R S2 D2 L I4 I3 I2 I1 RLOC=X0Y1
FMAP
I4 I3 I2 I1 RLOC=X0Y3 O R_SD6
M2_1
S3 D3 D0 D1 S0 SD3 AND2B1 O SD3 R_SD3
RLOC=X0Y1
FDCE
D CE C CLR Q3
FMAP
R S1 D1 L I4 I3 I2 I1 RLOC=X0Y0 O R_SD1 S4 D4 D0 D1 S0 SD4 AND2B1
FMAP
R S5 D5 Q Q4 L I4 I3 I2 I1 RLOC=X0Y2 O R_SD5
M2_1
O SD4 R_SD4
RLOC=X0Y1
FDCE
D CE C CLR Q4
FMAP
R S0 D0 L I4 I3 I2 I1 RLOC=X0Y0 O R_SD0
M2_1
RLOC=X0Y2
FMAP
R I4 I3 I2 I1 RLOC=X0Y2 O R_SD4 Q5 S4 D4 L
FDCE
D CE C CLR Q5 Q
M2_1
RLOC=X0Y2
FDCE
D CE C CLR Q6 Q Q6
M2_1
S7 D7 L CE R C OR3 D0 D1 S0 SD7 AND2B1 R_L_CE O SD7 R_SD7
RLOC=X0Y3
FDCE
D CE C CLR Q7 RLOC=X0Y3 Q Q7
GND
X9301
ACC8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
114
ACC4, 8, 16
AND4B2 OFL_NEG_ADD CI AND2 CI_0 AND4B1 OFL_OUT OFL OR4 R OR2 R_0 Q3 S3 B3 ADD_1 L_0 OR2 GND VCC CE ADD AND2 AND2 CE_1 ADD_1 NOR2 AND3B2 AND2 Q0
C
AND4B2 OFL_POS_SUB
AND4B3 OFL_NEG_SUB
S0
D
FD
Q0
AND3 D0 AND3B2 AND3 AND3B1 KEEP X0 OR4 NOR2 OR2
S1
D
FD
Q1
NOR2
Q1
AND4B2
B0 XNOR2
AND3 BX0 S2
D
FD
Q2
AND4
OR3
NOR2
Q2
AND4 D1 AND3B2
AND3B1
KEEP X1 OR4 NOR2 AND3
AND4B2
B1 AND4 BX1 XNOR2 OR4 AND5 AND3B2
S3
D
FD
Q3
NOR2
Q3
D2
AND3B1
KEEP X2
AND5
AND4B2
OR4
NOR2 AND3
B2 XNOR2
BX2
AND4
CO AND5 OR5
D3
AND3B2 AND6 AND3B1 KEEP X3 OR4 NOR2
AND4B2
AND6 B3 C XNOR2 BX3
X7607
ACC4 Implementation XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II
115
ACC4, 8, 16
ACC4X2
CI B0 B1 B2 B[7:0] B3 D0 D1 D2 D3 CI B0 B1 B2 B3 D0 D1 D2 D3 L ADD CE C R QO Q1 Q2 Q3 CO QO Q1 Q2 Q3
Q3_0
C3 Q[7:0]
ACC4
B4 B5 B6 B7 D4 D[7:0] L ADD CE C R D5 D6 D7 CI B0 B1 B2 B3 D0 D1 D2 D3 L ADD CE C R X7766 QO Q1 Q2 Q3 CO Q4 Q5 Q6 Q7 CO OFL
Q7_4 OFL
ACC8 Implementation XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II
Usage
ACC is schematic and inference only -- not instantiated.
VHDL Inference Code (ACC4)

Following is some "basic" code for inference of the ACC modules.
architecture Behavioral of acc4 is begin process(C) begin if (R = '1') then Q <= (others => '0'); elsif (C'event and C = '1') then if (L = '1') then Q <= D; elsif (CE = '1') then if (ADD = '1') then Q <= Q + B; else Q <= Q - B; end if; end if; end if;
116
ACC4, 8, 16
end process; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) end if (ADD) Q <= Q + B; else Q <= Q - B; end

None
117
ACC4, 8, 16
118
ADD1
ADD1
1-Bit Full Adder with Carry-In and Carry-Out
ADD1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CI A0 S0 B0 CO X4034
No No No Macro Macro Macro
ADD1 is a cascadable 1-bit full adder with carry-in and carry-out. It adds two 1-bit words (A and B) and a carry-in (CI), producing a binary sum (S0) output and a carryout (CO).
Inputs A0 0 1 0 1 0 1 0 1 B0 0 0 1 1 0 0 1 1 CI 0 0 0 0 1 1 1 1 S0 0 1 1 0 1 0 0 1
Outputs CO 0 0 0 1 0 1 1 1
119
ADD1
A0 B0 CI AND2B1 OR2 AND2B1 XOR2
S0
AND2 CO AND2 OR3
AND2
X7689
ADD1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
This design element is schematic or inference only -- no instantiation.
VHDL Inference Code

architecture Behavioral of ADD is signal sum: std_logic_vector(WIDTH downto 0); signal zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process (CI, A, B, sum) begin sum <= ('0' & A) + ('0' & B) + (zeros & CI); S <= sum(WIDTH-1 downto 0); CO <= sum(WIDTH); end process; end Behavioral;

always @ (A or B or CI) begin {CO,S} <= A + B + CI; end

None
120
ADD4, 8, 16
ADD4, 8, 16
4-, 8-, 16-Bit Cascadable Full Adders with Carry-In, Carry-Out, and Overflow
ADD4, ADD8, ADD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CI A0 A1 A2 A3 B0 B1 B2 B3
ADD4 S0 S1 S2 S3
ADD4, ADD8, and ADD16 add two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADD4 adds A3 A0, B3 B0, and CI producing the sum output S3 S0 and CO (or OFL). ADD8 adds A7 A0, B7 B0, and CI, producing the sum output S7 S0 and CO (or OFL). ADD16 adds A15 A0, B15 B0 and CI, producing the sum output S15 S0 and CO (or OFL).
OFL CO

ADD4, ADD8, ADD16 can operate on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers, respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twoscomplement operation is how they determine when overflow occurs. Unsigned binary uses CO, while twos-complement uses OFL to determine when overflow occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret the inputs as twos complement, follow the OFL output.
X4376
CI A[7:0] ADD8 B[7:0] OFL CO X4377 S[7:0]
CI A[15:0] ADD16 S[15:0] B[15:0] OFL CO X4378

For unsigned binary operation, ADD4 can represent numbers between 0 and 15, inclusive; ADD8 between 0 and 255, inclusive; ADD16 between 0 and 65535, inclusive. CO is active (High) when the sum exceeds the bounds of the adder. OFL is ignored in unsigned binary operation.
For twos-complement operation, ADD4 can represent numbers between -8 and +7, inclusive; ADD8 between -128 and +127, inclusive; ADD16 between -32768 and +32767, inclusive. OFL is active (High) when the sum exceeds the bounds of the adder. CO is ignored in twos-complement operation.
121
ADD4, 8, 16
CO OFL
XOR2 O
B7 A7
XOR2
RLOC=R0C0.S1
I7
S MUXCY 0 1 CI DI
LI CI
FMAP
I4
O XORCY
S7
B7 A7
I3 I2 I1
I7
C6
RLOC=R0C0.S1
LO
O 1 CI
B6 A6
XOR2
RLOC=R0C0.S1
I6
MUXCY_D
FMAP
I4
0 DI
LI CI
O XORCY
S6
B6 A6
I3 I2 I1
I6
C5
RLOC=R0C0.S1
LO
B5 A5
XOR2
RLOC=R1C0.S1
1 CI
LI CI
I5
MUXCY_L 0 DI
FMAP
I4
B5 A5
O XORCY
I3 I2 I1
I5
S5
RLOC=R1C0.S1
C4
LO
B4 A4
XOR2
RLOC=R1C0.S1 B4 A4
LI CI
FMAP
I4 I3 I2 I1 0
I4
S MUXCY_L 0 1 CI DI
I4
O XORCY
S4 RLOC=R1C0.S1
C3
LO
B3 A3
XOR2
RLOC=R2C0.S1
1 CI
LI CI
FMAP
I4
I3
MUXCY_L 0 DI
B3 A3
O XORCY
I3 I2 I1
I3
S3
RLOC=R2C0.S1
C2
FMAP
LO
B2 A2
XOR2
RLOC=R2C0.S1
1 CI
LI CI
I2
MUXCY_L 0 DI
I4
B2 A2
O XORCY
I3 I2 I1
I2
S2
RLOC=R2C0.S1
C1
FMAP
LO
B1 A1
XOR2
RLOC=R3C0.S1
1 CI
LI CI
I4
I1
MUXCY_L 0 DI
B1 A1
O XORCY
I3 I2 I1
I1
S1
RLOC=R3C0.S1
C0
FMAP
B0 A0
XOR2
I0
LO MUXCY_L 0 DI 1 CI
RLOC=R3C0.S1 B0 A0
LI CI
I4 I3 I2 I1 0
I0
RLOC=R3C0.S1
O XORCY
A[7:0] B[7:0]
S0 S[7:0]
CI
X8687
ADD8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
122
ADD4, 8, 16
CO
OFL O B7 I7 A7 XOR2 S RLOC=X0Y3 MUXCY 0 1 DI CI I4 LI O CI C6 C6O XORCY S7 B7 A7 I3 I2 I1 RLOC=X0Y3 LO B6 I6 A6 XOR2 S O RLOC=X0Y3 MUXCY_D 0 1 DI CI LI O CI XORCY C5 LO B5 I5 A5 XOR2 S RLOC=X0Y2 MUXCY_L 0 1 DI CI LI O CI XORCY C4 LO B4 I4 A4 XOR2 S RLOC=X0Y2 MUXCY_L 0 1 DI CI LI O CI XORCY C3 LO B3 I3 A3 XOR2 S RLOC=X0Y1 MUXCY_L 0 1 DI CI LI O CI RLOC=X0Y1 XORCY C2 LO B2 I2 A2 XOR2 S RLOC=X0Y1 MUXCY_L 0 1 DI CI LI O CI XORCY C1 LO B1 I1 A1 XOR2 S RLOC=X0Y0 MUXCY_L 0 1 DI CI LI O CI XORCY C0 LO B0 I0 A0 A [7:0] B [7:0] XOR2 S RLOC=X0Y0 MUXCY_L 0 1 DI CI LI O CI XORCY S [7:0] CI S0 RLOC=X0Y0 B0 A0 I4 I3 I2 I1 O I0 S1 RLOC=X0Y0 B1 A1 I4 I3 I2 I1 O I1 S2 B2 A2 I4 I3 I2 I1 RLOC=X0Y1 O I2 S3 B3 A3 I4 I3 I2 I1 O I3 S4 B4 A4 I4 I3 I2 I1 RLOC=X0Y2 O I4 S5 B5 A5 I4 I3 I2 I1 RLOC=X0Y2 O I5 RLOC=X0Y3 S6 B6 A6 I4 I3 I2 I1 O I6 O I7 XOR2
FMAP
FMAP
FMAP
FMAP
FMAP
FMAP
FMAP
FMAP
X9302
ADD8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
123
ADD4, 8, 16
S3 A3 B3
AND3B2 OR2
OFL
AND3B1
S0
XOR2
S1
AND2 OR2 XOR2
AND2
AND2
S2
AND3 OR3 XOR2
CI
OR2
CI_ORO
AND3 GND
A0 KEEP X0 B0
XOR2 AND3 XOR2 OR4 AND2
S3
A1 KEEP X1 B1
XOR2 AND4 AND4
A2 KEEP X2
XOR2 AND2
B2
AND3
CO
AND4
OR5
A3 KEEP X3
XOR2 AND5
B3
AND5
X7613
124
ADD4, 8, 16
S3_0 CI A0 A1 A2 A3 B0 B1 B2 B3
ADD4X2
CI A0 A1 A2 A3 B0 B1 B2 B3
S[7:0]
S0 S1 S2 S3
A[7:0]
S0 S1 S2 S3
B[7:0]
CO
C3
ADD4
CI
A4 A5 A6 A7 B4 B5 B6 B7
A0 A1 A2 A3 B0 B1 B2 B3
S0 S1 S2 S3
S4 S5 S6 S7
CO
CO
OFL CO
X7771
S7_4
Usage
This design element is schematic or inference only -- no instantiation.
VHDL Inference Code (ADD4)

architecture Behavioral of ADD is signal sum: std_logic_vector(WIDTH-1 downto 0); signal zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process (CI, A, B, sum) begin sum <= ('0' & A) + ('0' & B) + (zeros & CI); S <= sum(WIDTH-1 downto 0); CO <= sum(WIDTH); end process; end Behavioral;
Verilog Inference Code (ADD4)

always @ (A or B or CI) begin {CO,sum} <= A + B + CI; end
125
ADD4, 8, 16

None
126
ADSU1
ADSU1
1-Bit Cascadable Adder/Subtracter with Carry-In and Carry-Out
ADSU1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CI A0 S0 B0 ADD CO X4035
When the ADD input is High, two 1-bit words (A0 and B0) are added with a carry-in (CI), producing a 1-bit output (S0) and a carry-out (CO). When the ADD input is Low, B0 is subtracted from A0, producing a result (S0) and borrow (CO). In add mode, CO represents a carry-out, and CO and CI are active-High. In subtract mode, CO represents a borrow, and CO and CI are active-Low. Add Function, ADD=1
Inputs A0 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 CI 0 0 0 0 1 1 1 1 S0 0 1 1 0 1 0 0 1 Outputs CO 0 0 0 1 0 1 1 1
Subtract Function, ADD=0

Inputs A0 0 0 1 1 0 B0 0 1 0 1 0 CI 0 0 0 0 1 S0 1 0 0 1 0 Outputs CO 0 0 1 0 1
127
ADSU1
Subtract Function, ADD=0

Inputs A0 0 1 1
A0 B0 ADD AND3 CI
Outputs CI 1 1 1 S0 1 1 0 CO 0 1 1
B0 1 0 1
AND3
CO AND3B2 OR5
AND3B2
AND2 SO XOR2
AND3B3
AND3B1
OR4 AND3B1
AND3B1
X8144
ADSU1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
For HDL, this design element is inferred rather than instantiated.
VHDL Inference Code

architecture Behavioral of adsu4 is begin
128
ADSU1
process (A0,ADD,B0) begin if (ADD='1') then S <= A0 + B0; else S <= A0 - B0; end if; end process; end Behavioral;

always @ (A0 or ADD or B0) begin if (ADD) S0 <= A0 + B0; else S0 <= A0 - B0; end
VHDL Instantiation Template

-- Component Declaration for ADSU1 should be placed -- after architecture statement but before begin keyword component ADSU1 port (CO : out STD_ULOGIC; S0 : out STD_ULOGIC; A0 : in STD_ULOGIC; ADD: in STD_ULOGIC; B0 : in STD_ULOGIC; CI : in STD_ULOGIC); end component; -- Component Attribute specification for ADSU1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for ADSU1 should be placed -- in architecture after the begin keyword ADSU1_INSTANCE_NAME : ADSU1 -- synthesis translate_off generic map (CDS_ACTION => "string_value") -- synthesis translate_on port map (CO =>user_CO, S0 => user_SO, A0 => user_A0, ADD => user_ADD, B0 => user_B0, CI => user_CI);
Verilog Instantiation Template

ADSU1 instance_name (.CO (user_CO),
129
ADSU1
.S0 (user_SO), .A0 (user_A0), .ADD(user_ADD), .B0 (user_B0), .CI (user_CI));

None
130
ADSU4, 8, 16
ADSU4, 8, 16
4-, 8-, 16-Bit Cascadable Adders/Subtracters with Carry-In, Carry-Out, and Overflow
ADSU4, ADSU8, ADSU16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CI A0 A1 A2 A3 B0 B1 B2 B3 ADD OFL CO X4379 ADSU4 S0 S1 S2 S3
When the ADD input is High, ADSU4, ADSU8, and ADSU16 add two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADSU4 adds two 4-bit words (A3 A0 and B3 B0) and a CI, producing a 4-bit sum output (S3 S0) and CO or OFL. ADSU8 adds two 8-bit words (A7 A0 and B7 B0) and a CI producing, an 8-bit sum output (S7 S0) and CO or OFL. ADSU16 adds two 16-bit words (A15 A0 and B15 B0) and a CI, producing a 16-bit sum output (S15 S0) and CO or OFL. When the ADD input is Low, ADSU4, ADSU8, and ADSU16 subtract Bz B0 from Az A0, producing a difference output and CO or OFL. ADSU4 subtracts B3 B0 from A3 A0, producing a 4-bit difference (S3 S0) and CO or OFL. ADSU8 subtracts B7 B0 from A7 A0, producing an 8-bit difference (S7 S0) and CO or OFL. ADSU16 subtracts B15 B0 from A15 A0, producing a 16-bit difference (S15 S0) and CO or OFL. In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High in add and subtract modes. ADSU4, ADSU8, and ADSU16 CI and CO pins do not use the CPLD carry chain.
CI A[7:0] ADSU8 S[7:0] B[7:0] ADD OFL CO X4380

ADSU4, ADSU8, ADSU16 can operate, respectively, on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twos-complement operation is how they determine when overflow occurs. Unsigned binary uses CO, while twos complement uses OFL to determine when overflow occurs. With adder/subtracters, either unsigned binary or twos-complement operations cause an overflow. If the result crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-out boundary, a carry-out is generated. The following figure shows the ADSU carry-out and overflow boundaries.
CI A[15:0] ADSU16 B[15:0] OFL ADD CO X4381 S[15:0]
131
ADSU4, 8, 16
Overflow
-127
E N T OR SIG NE D ED BINAR GN Y SI
127 127
TW
128
OS
CO
UN
MPL EMENT O R
SIGN
ED BIN
LEM
AR
MP
CO
SI
G
0 0
-1
Carry-Out
X4720
ADSU Carry-Out and Overflow Boundaries

For unsigned binary operation, ADSU4 can represent numbers between 0 and 15, inclusive; ADSU8 between 0 and 255, inclusive; ADSU16 between 0 and 65535, inclusive. In add mode, CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low when the difference exceeds the bounds. An unsigned binary overflow that is always active-High can be generated by gating the ADD signal and CO as follows.
unsigned overflow = CO XOR ADD
OFL is ignored in unsigned binary operation.
For twos-complement operation, ADSU4 can represent numbers between -8 and +7, inclusive; ADSU8 between -128 and +127, inclusive; ADSU16 between -32768 and +32767, inclusive. If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignored in twos-complement operation.
132
ED
255
TW
ADSU4, 8, 16
CO OFL
XOR2 SUB7 O
RLOC=R0C0.S1
B7 A7
INV XOR3
I7
S MUXCY_L 0 1 DI CI LI CI
FMAP
ADD B7 A7
I4 I3 I2 I1 0
I7
S7
C6
XORCY
RLOC=R0C0.S1
SUB6
LO
O 1 CI
RLOC=R0C0.S1 ADD B6 A6
B6 A6
INV XOR3
I6
MUXCY_D
FMAP
I4 I3 I2 I1 0
0 DI
I6
LI CI
S6
C5
XORCY
RLOC=R0C0.S1
SUB5
LO
RLOC=R1C0.S1
1 CI LI CI
B5 A5
INV XOR3
I5
MUXCY_L 0 DI
FMAP
ADD B5 A5
I4 I3 I2 I1 0
I5
S5
RLOC=R1C0.S1
C4
XORCY
SUB4
LO
RLOC=R1C0.S1 ADD B4 A4
LI CI O
FMAP
I4 I3 I2 I1 0
B4 A4
INV XOR3
I4
S MUXCY_L 0 1 CI DI
I4
S4 RLOC=R1C0.S1
C3
XORCY
SUB3
LO
RLOC=R2C0.S1
1 CI LI CI
FMAP
ADD B3 A3
I4 I3 I2 I1 0
B3 A3
INV XOR3
I3
MUXCY_L 0 DI
I3
S3
RLOC=R2C0.S1
C2
XORCY
FMAP
SUB2 LO
RLOC=R2C0.S1
1 CI LI CI
B2 A2
INV XOR3
I2
MUXCY_L 0 DI
ADD B2 A2
O
I4 I3 I2 I1 0
I2
S2
RLOC=R2C0.S1
C1
XORCY
FMAP
SUB1 LO
RLOC=R3C0.S1
1 CI LI CI
B1 A1
INV XOR3
I1
MUXCY_L 0 DI
ADD B1 A1 S1
I4 I3 I2 I1 0
I1
RLOC=R3C0.S1
C0
XORCY
FMAP
SUB0
B0 A0 A[7:0] B[7:0] ADD CI
INV XOR3
I0
LO MUXCY_L 0 DI 1 CI
RLOC=R3C0.S1
ADD B0 A0
I4 I3 I2 I1 0
I0
RLOC=R3C0.S1
LI CI XORCY O
S0 S[7:0]
X8686
ADSU8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
133
ADSU4, 8, 16
CO
OFL XOR2 O SUB7 B7 A7 XOR3 INV I7 S MUXCY 0 1 DI CI I4 LI O CI XORCY C6 C6O RLOC=X1Y3 LO SUB6 B6 A6 XOR3 INV I6 S MUXCY_D 0 1 DI CI LI O CI XORCY C5 S6 ADD B6 A6 I4 I3 I2 I1 RLOC=X1Y3 O I6 O RLOC=X1Y3 S7 ADD B7 A7 I3 I2 I1 O I7 RLOC=X1Y3
FMAP
FMAP
LO SUB5 B5 A5 XOR3 INV I5 S MUXCY_L 0 1 DI CI ADD LI O CI XORCY C4 RLOC=X1Y2 S5 B5 A5 I4 I3 I2 I1 O I5 RLOC=X1Y2
FMAP
LO SUB4 B4 A4 XOR3 INV I4 S MUXCY_L 0 1 DI CI LI O CI XORCY C3 S4 ADD B4 A4 RLOC=X1Y2 I4 I3 I2 I1 RLOC=X1Y2 O I4
FMAP
LO SUB3 B3 A3 XOR3 INV I3 S MUXCY_L 0 1 DI CI LI O CI XORCY C2 S3 ADD B3 A3 RLOC=X1Y1 I4 I3 I2 I1 RLOC=X1Y1 O I3
FMAP
LO SUB2 B2 A2 XOR3 INV I2 S MUXCY_L 0 1 DI CI LI O CI XORCY C1 S2 RLOC=X1Y1 I4 ADD B2 A2 I3 I2 I1
FMAP
I2
RLOC=X1Y1
LO SUB1 B1 A1 XOR3 INV I1 S MUXCY_L 0 1 DI CI LI O CI XORCY C0 S1 RLOC=X1Y0 ADD B1 A1 I4 I3 I2 I1
FMAP
I1
RLOC=X1Y0
FMAP
LO SUB0 B0 A0 XOR3 A [7:0] LI O B [7:0] CI XORCY ADD S [7:0] S0 INV I0 S MUXCY_L 0 1 DI CI RLOC=X1Y0 I4 ADD B0 A0 I3 I2 I1 RLOC=X1Y0 O I0
CI
X9303
ADSU8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
134
ADSU4, 8, 16
CI A0 B0
ADSU1
CI A0 S0 B0 ADD CO
S0
S0
ADSU1 A1 B1
CI A0 S0 B0 ADD CO
S1
S1
ADSU1 A2 B2
CI A0 S0 B0 ADD CO
S2
OFL_POS_ADD
S2
AND4B2
ADSU1 A3 B3
CI A0 S0 B0 ADD CO
OFL_NEG_ADD OFL_OUT
AND4B1 OR4
S3
OFL
S3
CO
AND4B2
OFL_POS_SUB
ADD
AND4B3
OFL_NEG_SUB
X7615

S3_0 CI A0 A1 A2 A3 B0 B1 B2 B3
ADSU4X2
CI A0 A1 A2 A3 B0 B1 B2 B3 CO ADD
S[7:0]
S0 S1 S2 S3
A[7:0]
S0 S1 S2 S3
B[7:0]
C3
ADSU4
CI
A4 A5 A6 A7 B4 B5 B6 B7 ADD
A0 A1 A2 A3 B0 S0 S1 S2 S3
S4 S5 S6 S7
B1 B2 OFL B3 CO ADD
OFL CO
X7774
S7_4
135
ADSU4, 8, 16
Usability
For HDL, these design elements are inferred rather than instantiated.
VHDL Inference Code

architecture Behavioral of adsu4 is begin process (A,ADD,B) begin if (ADD='1') then S <= A + B; else S <= A - B; end if; end process; end Behavioral;

always @ (A or ADD or B) begin if (ADD) S <= A + B; else S <= A - B; end
136
AND2-9
AND2-9
2- to 9-Input AND Gates with Inverted and Non-Inverted Inputs
AND2, AND3, AND4, AND5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive Primitive
AND2B1, AND2B2, AND4B1, AND4B2, AND4B3, AND4B4, AND5B1, AND5B2, AND5B3, AND5B4, AND5B5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II AND3B1, AND3B2, AND3B3, Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II AND6, AND7, AND8, AND9 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Primitive Primitive Primitive Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro
137
AND2-9
I1 I0
I2 I1 I0
I3 O I2 I1 I0 O
I4 I3 I2 I1 I0 O
I5 I4 I3 I2 I1 I0 AND5 I6 I5 I4 O I3 I2 I1 I0 O AND6 O
AND2
AND3
AND4
I4 I1 I0 O I2 I1 I0 I3 O I2 I1 I0 O I3 I2 I1 I0
AND2B1
AND3B1
AND4B1 I4 I3 O I2 I1 I0 AND4B2 I3 I4 I3 O I2 I1 I0 AND4B3 I4 I3 O I2 I1 I0 AND4B4
AND5B1
AND7
I1 I0
I2 I1 I0
I3 O I2 I1 I0
O I7 I6 I5 AND5B2 I4 I3 I2 O I1 I0
AND2B2
AND3B2
I2 I1 I0
I2 I1 I0
AND3B3
AND5B3
AND8
I3 I2 I1 I0
O I8 I7 AND5B4 I6 I5 I4 O I3 I2 O I1 I0
I4 I3 I2 I1 I0 AND5B5
AND9 X9461
AND Gate Representations AND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. AND functions of six to nine inputs are available with only noninverting inputs. To make some or all inputs inverting, use external inverters. Because each input uses a CLB resource in Spartan-II, Spartan-3, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X replace functions with unused inputs with functions having the appropriate number of inputs. See AND12, 16 for information on additional AND functions for Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3.
138
AND2-9
FMAP
I4 I3 S1 S0 I7 I6 I5 I4 AND4 I7 O AND2 I3 I2 I1 I0 AND4 S0 I6 I5 I4 S1 I2 I1 RLOC=R0C0.S0 O O
FMAP
I4 I3 I2 I1 RLOC=R0C0.S1 O S1
FMAP
I3 I2 I1 I0 X8702 I4 I3 I2 I1 RLOC=R0C0.S1 O S0
AND8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
FMAP
I4 I7 I6 I5 I4 AND4 O RLOC=X0Y1 S1 S1 S0 I3 I2 I1 O O
FMAP
AND2 I3 I2 I1 I0 AND4 S0 I7 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1
FMAP
I3 I2 I1 I0 I4 I3 I2 I1 RLOC=X0Y0 O S0
X9304
AND8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
139
AND2-9
Usage
If possible, it is recommended that these design elements be inferred rather than instantiated.
VHDL Inference Code

AND2 example:
process (I0, I1) begin O <= I0 and I1; end process;
AND5B3 example:
process (I0, I1, I2, I3, I4) begin O <= (not I0) and (not I1) and (not I2) and I3 and I4; end process;

AND2:
always @ (I0 or I1) begin O <= I0 && I1; end
AND5B3:
always @ (I0 or I1 or I2 or I3 or I4) begin O <= !I0 && !I1 && !I2 && I3 && I4; end
VHDL Instantiation Template for AND2, AND2B1, or AND2B2

-- Component Declaration for AND2, AND2B1, or AND2B2 should -- be placed after architecture statement but before begin -- keyword component {AND2|AND2B1|AND2B2} port (O : out STD_ULOGIC; I1 : in STD_ULOGIC; I0 : in STD_ULOGIC); end component; -- Component Attribute specification for AND2, AND2B1, or -- AND2B2 should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here
-- Component Instantiation for AND2, AND2B1, or AND2B2 -- should be placed in architecture after the begin -- keyword
140
AND2-9
INSTANCE_NAME : {AND2|AND2B1|AND2B2} port map (O => user_O, I0 => user_I0, I1 => user_I1);
Verilog Instantiation Template for AND2, AND2B1, or AND2B2

ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1));
VHDL Instantiation Template for AND3 Through AND3B3

-- Component Declaration for AND3 through AND3B3 should -- be placed after architecture statement but before begin -- keyword component {AND3|AND3B1|AND3B2|AND3B3} port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC); end component; -- Component Attribute specification for AND3 through AND3B3 -- should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here -- Component Instantiation for AND3 through AND3B3 -- should be placed in architecture after the begin -- keyword INSTANCE_NAME : {AND3|AND3B1|AND3B2|AND3B3} port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2);
Verilog Instantiation Template for AND3 Through AND3B3

ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2));
141
AND2-9

-- Component Declaration for AND4 through AND4B4 should -- be placed after architecture statement but before begin -- keyword component {AND4|AND4B1|AND4B2|AND4B3|AND4B4} port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component; -- Component Attribute specification for AND4 through AND4B4 -- should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here -- Component Instantiation for AND4 through AND4B4 -- should be placed in architecture after the begin -- keyword INSTANCE_NAME : AND4_thru_AND4B4 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3);
Verilog Instantiation Template for AND4 through AND4B4

ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3));
142
AND2-9

-- Component Declaration for AND5 through AND5B5 should -- be placed after architecture statement but before begin -- keyword component {AND5|AND5B1|AND5B2|AND5B3|AND5B4|AND5B5} port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC; I4 : in STD_ULOGIC); end component; -- Component Attribute specification for AND5 through AND5B5 -- should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here -- Component Instantiation for AND5 through AND5B5 -- should be placed in architecture after the begin -- keyword INSTANCE_NAME : AND5_thru_AND5B5 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4);
Verilog Instantiation Template for AND5 through AND5B5

ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4));

None
143
AND2-9
144
AND12, 16
AND12, 16
12- and 16-Input AND Gates with Non-Inverted Inputs
AND12, AND16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 AND12
AND12 and AND16 functions are performed in the Configurable Logic Block (CLB) function generator.
O
The 12- and 16-input AND functions are available only with non-inverting inputs. To invert all of some inputs, use external inverters. See AND2-9 for information on more AND functions.
FMAP
S2 S1 S0 I4 I3 I2 I1 RLOC=R0C0.S0 O O
X9459
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 AND16
I11 I10 I9 I8 AND4 I7 I6 I5 I4 AND4 I3 I2 I1 I0 AND4 S0
FMAP
S2 I11 I10 I9 I8 I4 I3 I2 I1 RLOC=R0C0.S0 O S2
S1 AND3
FMAP
I7 I6 I5 I4 I4 I3 I2 I1 RLOC=R0C0.S1 O S1
X9460
FMAP
145
AND12, 16
FMAP
I11 I10 I9 I8 AND4 S2 S2 S1 S0 I4 I3 I2 I1 RLOC=X0Y1 O O
FMAP
I11 I7 I6 I5 I4 AND4 AND3 S1 O I10 I9 I8 I4 I3 I2 I1 RLOC=X0Y1 O S2
FMAP
I7 I3 I2 I1 I0 AND4 S0 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1
FMAP
I3 I2 I1 I0 I4 I3 I2 I1 RLOC=X0Y0 X9305 O S0

O
FMAP I15 I14 I13 I12 AND4 RLOC=R0C0.S1 C2 FMAP I11 I10 I9 I8 AND4 RLOC=R0C0.S1 C1 FMAP I7 I6 I5 I4 AND4 C0 RLOC=R1C0.S1 S1 LO MUXCY_L S 0 DI 1 CI I4 RLOC=R1C0.S1 I7 I6 I5 I4 I3 O I2 I1 S1 S2 LO MUXCY_L S 0 DI 1 CI RLOC=R0C0.S1 I11 I10 I9 I8 I4 I3 O I2 I1 S2 S3 S 0 DI 1 CI I12 O MUXCY RLOC=R0C0.S1 I15 I14 I13 I4 I3 O I2 I1 S3
FMAP I3 I2 I1 I0 AND4 S0 LO MUXCY_L S 0 DI 1 CI RLOC=R1C0.S1 I3 I2 I1 I0 I4 I3 O I2 I1 RLOC=R1C0.S1 S0
CIN GND VCC
X8708
146
AND12, 16
FMAP
I15 I14 I13 I12 AND4 C2 RLOC=X0Y1 S3 S O MUXCY 0 1 DI CI RLOC=X0Y1 I15 I14 I13 I12 I4 I3 I2 I1 O S3
I11 I10 I9 I8 AND4 S2 S
LO MUXCY_L 0 1 DI CI RLOC=X0Y1
FMAP
I11 I10 I9 I8 C1 I4 I3 I2 I1 RLOC=X0Y1 O S2
I7 I6 I5 I4 AND4 S1 S
LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I7 I6 I5 I4 C0
FMAP
I4 I3 I2 I1 RLOC=X0Y0 O S1
I3 I2 I1 I0 AND4 S0 S
LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I3 I2 I1 I0 CIN GND VCC
FMAP
I4 I3 I2 I1 RLOC=X0Y0 O S0
X9306
Usage
For HDL, it is recommended that these design elements be inferred rather than instantiated.
VHDL Inference Code

architecture Behavioral of and12 is begin process (I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11) begin O <= I0 and I1 and I2 and I3 and I4 and I5 and I6 and I7 and I8 and I9 and I10 and I11; end process;
end Behavioral;
147
AND12, 16

always @ (I0 or I1 or I2 or I3 or or I6 or I7 or I8 or I9 or I10 begin O <= I0 && I1 && I2 && I3 && I4 && I6 && I7 && I8 && I9 && I10 end I4 or I5 or I11) && I5 && I11;

None
148
BRLSHFT4, 8
BRLSHFT4, 8
4-, 8-Bit Barrel Shifters
BRLSHFT4, BRLSHFT8 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
I0 I1 I2 I3 S0 S1
BRLSHFT4
O0 O1 O2 O3
BRLSHFT4, a 4-bit barrel shifter, can rotate four inputs (I3 I0) up to four places. The control inputs (S1 and S0) determine the number of positions, from one to four, that the data is rotated. The four outputs (O3 O0) reflect the shifted data inputs. BRLSHFT8, an 8-bit barrel shifter, can rotate the eight inputs (I7 I0) up to eight places. The control inputs (S2 S0) determine the number of positions, from one to eight, that the data is rotated. The eight outputs (O7 O0) reflect the shifted data inputs.
X3856
I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2
BRLSHFT8 O0
O1 O2 O3 O4 O5 O6 O7
BRLSHFT4 Truth Table

Inputs S1 0 0 1 1 S0 0 1 0 1 I0 a a a a I1 b b b b I2 c c c c I3 d d d d O0 a b c d Outputs O1 b c d a O2 c d a b O3 d a b c
X3857

Inputs S2 S1 S0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 I0 a a a a a a I1 b b b b b b I2 c c c c c c I3 d d d d d d I4 e e e e e e I5 f f f f f f I6 g g g g g g I7 h h h h h h Outputs O0 O1 O2 O3 O4 O5 O6 O7 a b c d e f b c d e f g c d e f g h d e f g h a e f g h a b f g h a b c g h a b c d h a b c d e
149
BRLSHFT4, 8

Inputs S2 S1 S0 1 1 1 1 0 1 I0 a a I1 b b I2 c c I3 d d I4 e e I5 f f I6 g g I7 h h Outputs O0 O1 O2 O3 O4 O5 O6 O7 g h h a a b b c c d d e e f f g
150
BRLSHFT4, 8
I0
D0 D1 S0
M2_1
O M01 M01 D0 D1 S0
M2_1
O MO0 MO0 D0 D1 S0
M2_1
O O0 O0
I1
D0 D1 S0
M2_1
O M12 M12 D0 D1 S0
M2_1
O MO1 MO1 D0 D1 S0
M2_1
O O1 O1
I2
D0 D1 S0
M2_1
O M23 M23 D0 D1 S0
M2_1
O MO2 MO2 D0 D1 S0
M2_1
O O2 O2
I3
D0 D1 S0
M2_1
O M34 M34 D0 D1 S0
M2_1
O MO3 MO3 D0 D1 S0
M2_1
O O3 O3
I4
M2_1
D0 D1 S0 O M45 M45 D0 D1 S0
M2_1
O MO4 MO4 D0 D1 S0
M2_1
O O4 O4
I5
D0 D1 S0
M2_1
O M56 M56 D0 D1 S0
M2_1
O MO5 MO5 D0 D1 S0
M2_1
O O5 O5
I6
D0 D1 S0
M2_1
O M67 M67 D0 D1 S0
M2_1
O MO6 MO6 D0 D1 S0
M2_1
O O6 O6
I7 S0 S1 S2
D0 D1 S0
M2_1
O M70 M70 D0 D1 S0
M2_1
O MO7 MO7 D0 D1 S0
M2_1
O O7 X8143 O7
BRLSHFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
151
BRLSHFT4, 8
Usage
VHDL Inference Code

architecture Behavioral of brlshft4 is begin process (I,S) begin case S is when "00" => O <= I; when "01" => O(3) <= I(0); O(2 downto 0) when "10" => O(3 downto 2) O(1 downto 0) when "11" => O(3 downto 1) O(0) <= I(3); when others => O <= I; end case; end process; end Behavioral;
<= I(3 downto 1); <= I(1 downto 0); <= I(3 downto 2); <= I(2 downto 0);

always @(I or S) begin case (S) 2'b00 2'b01 2'b10 2'b11 endcase end : : : : O O O O <= <= <= <= I; {I[0],I[3:1]}; {I[1:0],I[3:2]}; {I[2:0],I[3]};
152
BSCAN_SPARTAN2
BSCAN_SPARTAN2
Spartan-II Boundary Scan Logic Control Circuit
BSCAN_SPARTAN2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No No No No No
* Supported for Spartan-II, but not for SpartanIIE, which is supported by BSCAN_VIRTEX.
BSCAN_SPARTAN2
UPDATE SHIFT RESET TDI SEL1 DRCK1 TDO1 TDO2 SEL2 DRCK2
The BSCAN_SPARTAN2 symbol creates internal boundary scan chains in a Spartan-II device. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Spartan-II. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_SPARTAN2 symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, and SHIFT pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain. Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Book.
X8894
Usage
This design element is supported for instantiation and schematics but not for inference.

-- Component Declaration for BSCAN_SPARTAN2 should be placed -- after architecture statement but before begin keyword component BSCAN_SPARTAN2 port (DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC;
153
BSCAN_SPARTAN2
SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC; TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_SPARTAN2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BSCAN_SPARTAN2 should be -- placed in architecture after the begin keyword BSCAN_SPARTAN2_INSTANCE_NAME : BSCAN_SPARTAN2 port map (DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

BSCAN_SPARTAN2 instance_name (.DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

None
154
BSCAN_SPARTAN3
BSCAN_SPARTAN3
Spartan-3 Boundary Scan Logic Control Circuit
BSCAN_SPARTAN3 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
BSCAN_SPARTAN3 UPDATE SHIFT RESET TDI SEL1 DRCK1 TD01 TD02 SEL2 DRCK2 CAPTURE
BSCAN_SPARTAN3 provides access to the BSCAN sites on a Spartan-3 device. It is used to create internal boundary scan chains. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Spartan-3. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_SPARTAN3 symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain.
X9930
Usage
This design element is instantiated rather than inferred.

-- Component Declaration for BSCAN_SPARTAN3 should be placed -- after architecture statement but before begin keyword component BSCAN_SPARTAN3 port (CAPTURE : out STD_ULOGIC; DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC;
155
BSCAN_SPARTAN3
TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_SPARTAN3 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BSCAN_SPARTAN3 should be -- placed in architecture after the begin keyword BSCAN_SPARTAN3_INSTANCE_NAME : BSCAN_SPARTAN3 port map (CAPTURE => user_CAPTURE, DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

BSCAN_SPARTAN3 instance_name (.CAPTURE (user_CAPTURE), .DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

None.
156
BSCAN_VIRTEX
BSCAN_VIRTEX
Virtex Boundary Scan Logic Control Circuit
BSCAN_VIRTEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No Primitive No No No No
* Supported for Spartan-IIE, but not for Spartan-II, which is supported by BSCAN_SPARTAN2.
BSCAN_VIRTEX
UPDATE SHIFT RESET TDI SEL1 DRCK1 TDO1 TDO2 SEL2 DRCK2
The BSCAN_VIRTEX symbol is used to create internal boundary scan chains in a Virtex or Virtex- E device. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Virtex and Virtex-E. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_VIRTEX symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. Note: For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, see BSCAN_VIRTEX2. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, and SHIFT pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain. Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Book.
X8679
Usage
This design element is supported for instantiation and schematics but not for inferrence.

-- Component Declaration for BSCAN_VIRTEX should be placed -- after architecture statement but before begin keyword component BSCAN_VIRTEX port (DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC;
157
BSCAN_VIRTEX
RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC; TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_VIRTEX -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BSCAN_VIRTEX should be -- placed in architecture after the begin keyword BSCAN_VIRTEX_INSTANCE_NAME : BSCAN_VIRTEX port map (DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

BSCAN_VIRTEX instance_name (.DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

None
158
BSCAN_VIRTEX2
BSCAN_VIRTEX2
Virtex-II Boundary Scan Logic Control Circuit
BSCAN_VIRTEX2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive
BSCAN_VIRTEX2 UPDATE SHIFT RESET TDI SEL1 DRCK1 TD01 TD02 SEL2 DRCK2 CAPTURE
BSCAN_VIRTEX2 provides access to the BSCAN sites on a Virtex-II, Virtex-II Pro, or Virtex-II Pro X device. It is used to create internal boundary scan chains. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Virtex-II, Virtex-II Pro, and Virtex-II Pro X. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_VIRTEX2 symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. Note: For Virtex and Virtex-E, see BSCAN_VIRTEX. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain. Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Book.
X9402
Usage
This design element is supported for instantiation and schematics but not for inference.

-- Component Declaration for BSCAN_VIRTEX2 should be placed -- after architecture statement but before begin keyword component BSCAN_VIRTEX2 port (CAPTURE : out STD_ULOGIC; DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC;
159
BSCAN_VIRTEX2
SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC; TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_VIRTEX2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BSCAN_VIRTEX2 should be -- placed in architecture after the begin keyword BSCAN_VIRTEX2_INSTANCE_NAME : BSCAN_VIRTEX2 port map (CAPTURE => user_CAPTURE, DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

BSCAN_VIRTEX2 instance_name (.CAPTURE (user_CAPTURE), .DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

None
160
BUF
BUF
General-Purpose Buffer
BUF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive
O X9444
BUF is a general purpose, non-inverting buffer. In Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, BUF is usually not necessary and is removed by the partitioning software (MAP). In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUF is usually removed, unless you inhibit optimization by applying the OPT=OFF attribute to the BUF symbol.
Usage
This design is supported in schematics and instantiation but not for inference.

-- Component Declaration for BUF should be placed -- after architecture statement but before begin keyword component BUF port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUF -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUF should be placed -- in architecture after the begin keyword BUF_INSTANCE_NAME : BUF port map (O => user_O, I => user_I);
161
BUF

BUF instance_name (.O (user_O), .I (user_I));

None
162
BUF4, 8, 16
BUF4, 8, 16
General-Purpose Buffers
BUF4, BUF8, BUF16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro
BUF4
BUF4, 8, 16 are general purpose, non-inverting buffers. In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUF4, BUF8, and BUF16 are usually removed, unless you inhibit optimization by applying the OPT=OFF attribute to the BUF4, BUF8, or BUF16 symbol or by using the LOGIC_OPT=OFF global attribute.
O [7:0] X4614 I0 0 BUF 1 BUF 2 BUF 3 BUF 4 BUF 5 BUF 6 BUF 7 BUF X 7776 O1
BUF8
I1
O1
I2 X4615
O2
I3
O3
I4
O4
BUF16
I5
O5
I6 X4616 I7 I[7:0]
O6
O7
BUF8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
These design elements are schematic only.
163
BUF4, 8, 16
164
BUFCF
BUFCF
Fast Connect Buffer
BUFCF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
O X9444
BUFCF is a single fast connect buffer used to connect the outputs of the LUTs and some dedicated logic directly to the input of another LUT. Using this buffer implies CLB packing. No more than four LUTs may be connected together as a group.
Usage
This design element is supported for schematics and instantiation but not for inferrence.

-- Component Declaration for BUFCF should be placed -- after architecture statement but before begin keyword component BUFCF port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFCF -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFCF should be placed -- in architecture after the begin keyword BUFCF_INSTANCE_NAME : BUFCF port map (O => user_O, I => user_I);
165
BUFCF

BUFCF instance_name (.O (user_O), .I (user_I));

None
166
BUFE, 4, 8, 16
BUFE, 4, 8, 16
Internal 3-State Buffers with Active High Enable
BUFE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II BUFE4, BUFE8, BUFE16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro Macro* No No Primitive No Primitive Primitive No No
*Not supported for XC9500XL and XC9500XV devices
BUFE
E
X3790
BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple 3-state buffers with inputs I, I3 I0, I7 I0, and I15 I0, respectively; outputs O, O3 O0, O7 O0, and O15 O0, respectively; and active-High output enable (E). When E is High, data on the inputs of the buffers is transferred to the corresponding outputs. When E is Low, the output is high impedance (Z state or Off). The outputs of the buffers are connected to horizontal longlines in FPGA architectures. The outputs of separate BUFE symbols can be tied together to form a bus or a multiplexer. Make sure that only one E is High at any one time. If none of the E inputs is active-High, a weak-keeper circuit (Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X) keeps the output bus from floating but does not guarantee that the bus remains at the last value driven onto it. For XC9500 devices, BUFE output nets assume the High logic level when all connected BUFE/BUFT buffers are disabled. For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, BUFE elements need a PULLUP element connected to their output. NGDBuild inserts a PULLUP element if one is not connected.
BUFE4
E
X3797
BUFE8
EE
BUFE16
X3809
X3821
167
BUFE, 4, 8, 16
Inputs E 0 1 1 I X 1 0
Outputs O Z 1 0
O[7:0] E I0 E I1 E I2 E I3 E I4 E I5 E I6 E I7 BUFE I[7:0] E X8119 BUFE O7 BUFE O6 BUFE O5 BUFE O4 BUFE O3 BUFE O2 BUFE O1 O0
BUFE8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
These design elements are supported for schematic, inference, and instantiation.
VHDL Inference Code

architecture Behavioral of bufe is begin process (I, E) begin if (E = '1') then O <= I; else O <= 'Z'; end if; end process; end Behavioral;
168
BUFE, 4, 8, 16

always @ (I or E) begin if (E) O <= I; else O <= 1'bZ; end

-- Component Declaration for BUFE should be placed -- after architecture statement but before begin keyword component BUFE port (O : out STD_ULOGIC; E : in STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFE should be placed -- in architecture after the begin keyword BUFE_INSTANCE_NAME : port map (O => E => I => BUFE user_O, user_E, user_I);

BUFE instance_name (.O (user_O), .E (user_E), .I (user_I));

None
169
BUFE, 4, 8, 16
170
BUFG
BUFG
Global Clock Buffer
BUFG Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive
O X9428
BUFG, an architecture-independent global buffer, distributes high fan-out clock signals throughout a PLD device. The Xilinx implementation software converts each BUFG to an appropriate type of global buffer for the target PLD device. To use a specific type of buffer, instantiate it manually. To use a BUFG in a schematic, connect the input of the BUFG symbol to the clock source. Depending on the target PLD family, the clock source can be an external PAD symbol, an IBUF symbol, or internal logic. For a negative-edge clock input, insert an INV (inverter) symbol between the BUFG output and the clock input. The inversion is implemented at the Configurable Logic Block (CLB) or Input Output Block (IOB) clock pin.
XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II

Consult the device data sheet for the number of available global pins. For these architectures BUFG is always implemented using an IOB. Connect the input of BUFG to an IPAD or an IOPAD that represents an external signal source. Each BUFG can drive any number of register clocks in a design. The output of a BUFG may also be used as an ordinary input signal to other logic elsewhere in the design.
Virtex, Virtex-E, Spartan-II, Spartan-IIE

In Virtex, Virtex-E, Spartan-II, and Spartan-IIE, the BUFG cannot be driven directly from a pad. It can be driven from an IBUFG to indicate to use the dedicated pin (GCLKIOB pin) or from an internal driver to create an internal clock. BUFG can also be driven with an IBUF to represent an externally driven clock that does not use the dedicated pin.
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, clock buffers are multiplexed clock buffers. In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, a BUFG is implemented using a BUFGMUX with the S_B input tied high, basically meaning the S input is tied low. I1 is unused. I0 is used.
171
BUFG
Usage
This design element is supported for schematic and instantiation. Synthesis tools usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the synthesis tool usually instantiates BUFGPs for the clocks that are most utilized. The BUFGP contains both a BUFG and an IBUFG.

-- Component Declaration for BUFG should be placed -- after architecture statement but before begin keyword component BUFG port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFG -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFG should be placed -- in architecture after the begin keyword BUFG_INSTANCE_NAME : BUFG port map (O => user_O, I => user_I);

BUFG instance_name (.O (user_O), .I (user_I));

LOC
172
BUFGCE
BUFGCE
Global Clock MUX Buffer with Clock Enable and Output State 0
BUFGCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
CE I O
BUFGCE is a global clock buffer with a single gated input. Its O output is "0" when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.
BUFGCE
X9384
Inputs I X I CE 0 1
Outputs O 0 I
BUFGMUX
I XGND CE INV GND X9307 CE_IN I0 I1 S O O
BUFGCE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This design element is supported for schematics and instantiations but not for inference.

-- Component Declaration for BUFGCE should be placed -- after architecture statement but before begin keyword component BUFGCE port (O : out STD_ULOGIC; CE : in STD_ULOGIC; I : in STD_ULOGIC); end component;
173
BUFGCE
-- Component Attribute specification for BUFGCE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFGCE should be placed -- in architecture after the begin keyword BUFGCE_INSTANCE_NAME : BUFGCE port map (O => user_O, CE => user_CE, I => user_I);

BUFGCE instance_name (.O (user_O), .CE (user_CE), .I (user_I));

LOC
174
BUFGCE_1
BUFGCE_1
Global Clock MUX Buffer with Clock Enable and Output State 1
BUFGCE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CE I O
No Primitive No No No No
BUFGCE_1
X9385
BUFGCE_1 is a multiplexed global clock buffer with a single gated input. Its O output is High (1) when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.
Inputs I X I CE 0 1
Outputs O 1 I
BUFGMUX_1
I XVCC CE INV VCC X9308 CE_IN I0 I1 S O O
BUFGCE_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage

-- Component Declaration for BUFGCE_1 should be placed -- after architecture statement but before begin keyword component BUFGCE_1 port (O : out STD_ULOGIC; CE : in STD_ULOGIC; I: in STD_ULOGIC); end component;
175
BUFGCE_1
-- Component Attribute specification for BUFGCE_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFGCE_1 should be placed -- in architecture after the begin keyword BUFGCE_1_INSTANCE_NAME : BUFGCE_1 port map (O => user_O, CE => user_CE, I => user_I);

BUGCE_1 instance_name (.O (user_O), .CE (user_CE), .I (user_I));

LOC
176
BUFGDLL
BUFGDLL
Clock Delay Locked Loop Buffer
BUFGDLL Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
BUFGDLL
RST I LOCKED O
BUFGDLL is a special purpose clock delay locked loop buffer for clock skew management. It is provided as a user convenience for the most frequently used configuration of elements for clock skew management. Internally, it consists of an IBUFG driving the CLKIN pin of a CLKDLL followed by a BUFG that is driven by the CLK0 pin of the CLKDLL. Because BUFGDLL already contains an input buffer (IBUFG), it can only be driven by a top-level port (IPAD). Any DUTY_CYCLE_CORRECTION attribute on a BUFGDLL applies to the underlying CLKDLL symbol.
X10033
Usage

-- Component Declaration for BUFGDLL should be placed -- after architecture statement but before begin keyword component BUFGDLL port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGDLL -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
177
BUFGDLL
-- Component Instantiation for BUFGDLL should be placed -- in architecture after the begin keyword BUFGDLL_INSTANCE_NAME : BUFGDLL port map (O => user_O, I => user_I);

BUFGDLL instance_name (.O (user_O), .I (user_I));

STARTUP_WAIT
178
BUFGMUX
BUFGMUX
Global Clock MUX Buffer with Output State 0
BUFGMUX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
BUFGMUX
I0 I1 S X9251 O
BUFGMUX is a multiplexed global clock buffer that can select between two input clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on I1 is selected for output. BUFGMUX and BUFGMUX_1 are distinguished by which state the output assumes when it switches between clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1 assumes output state 1. Using a BUFGMUX element in your design may cause inaccurate simulation if all the following conditions occur: both clock inputs (I0 and I1) are used, GSR is activated during simulation (after simulation time `0'), and the secondary clock input (I1) is selected before or while GSR is active. In this case, the primary clock input (I0) is incorrectly selected. This occurs because there is a cross-coupled register pair that ensures the BUFGMUX output does not inadvertently generate a clock edge. When GSR is asserted, these registers initialize to the default state of I0. To select the secondary clock, you must send a clock pulse to both the primary and secondary clock inputs while GSR is inactive. Note: BUFGMUX guarantees that when S is toggled, the state of the output will remain in the inactive state until the next active clock edge (either I0 or I1) occurs.
Inputs I0 I0 X X X I1 X I1 X X S 0 1
Outputs O I0 I1 0 0
Usage
179
BUFGMUX

-- Component Declaration for BUFGMUX should be placed -- after architecture statement but before begin keyword component BUFGMUX port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGMUX -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFGMUX should be placed -- in architecture after the begin keyword BUFGMUX_INSTANCE_NAME : BUFGMUX port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

BUFGMUX instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .S (user_S));

LOC
180
BUFGMUX_1
BUFGMUX_1
Global Clock MUX Buffer with Output State 1
BUFGMUX_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
BUFGMUX_1
I0 I1 S X9252 O
BUFGMUX_1 is a multiplexed global clock buffer that can select between two input clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on I1 is selected for output. BUFGMUX and BUFGMUX_1 are distinguished by which state the output assumes when it switches between clocks in response to a change in its select input. BUFGMUX assumes output state 0 and BUFGMUX_1 assumes output state 1. Using a BUFGMUX_1 element in your design may cause inaccurate simulation if all the following conditions occur: both clock inputs (I0 and I1) are used, GSR is activated during simulation (after simulation time `0'), and the secondary clock input (I1) is selected before or while GSR is active. In this case, the primary clock input (I0) is incorrectly selected. This occurs because there is a cross-coupled register pair that ensures the BUFGMUX_1 output does not inadvertently generate a clock edge. When GSR is asserted, these registers initialize to the default state of I0. To select the secondary clock, you must send a clock pulse to both the primary and secondary clock inputs while GSR is inactive.
Inputs I0 I0 X X X I1 X I1 X X S 0 1
Outputs O I0 I1 1 1
Usage
181
BUFGMUX_1

-- Component Declaration for BUFGMUX_1 should be placed -- after architecture statement but before begin keyword component BUFGMUX_1 port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGMUX_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFGMUX should be placed -- in architecture after the begin keyword BUFGMUX_1_INSTANCE_NAME : BUFGMUX_1 port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

BUFGMUX_1 instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .S (user_S));

LOC
182
BUFGP
BUFGP
Primary Global Buffer for Driving Clocks or Longlines (Four per PLD Device)
BUFGP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
BUFGP, a primary global buffer, is used to distribute high fan-out clock or control signals throughout PLD devices.
X3902
In Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, BUFGP is equivalent to an IBUFG driving a BUFG. In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUFGP is treated like BUFG. A BUFGP provides direct access to Configurable Logic Block (CLB) and Input Output Block (IOB) clock pins and limited access to other CLB inputs. The input to a BUFGP comes only from a dedicated IOB. Because of its structure, a BUFGP can always access a clock pin directly. However, it can access only one of the F3, G1, C3, or C1 pins, depending on the corner in which the BUFGP is placed. When the required pin cannot be accessed directly from the vertical line, PAR feeds the signal through another CLB and uses general purpose routing to access the load pin. To use a BUFGP in a schematic, connect the input of the BUFGP element directly to the PAD symbol. Do not use any IBUFs, because the signal comes directly from a dedicated IOB. The output of the BUFGP is then used throughout the schematic. For a negative-edge clock, insert an INV (inverter) element between the output of the BUFGP and the clock input. This inversion is performed inside each CLB or IOB. A Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, or Spartan-3 BUFGP must be sourced by an external signal.
Usage
This design element is supported for schematic and instantiation. Synthesis tools usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the synthesis tool usually instantiates BUFGPs for the clocks that are most utilized.
183
BUFGP

-- Component Declaration for BUFGP should be placed -- after architecture statement but before begin keyword component BUFGP port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGP -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFGP should be placed -- in architecture after the begin keyword BUFGP_INSTANCE_NAME : BUFGP port map (O => user_O, I => user_I);

BUFGP instance_name (.O (user_O), .I (user_I));

HBLKNM
184
BUFGSR
BUFGSR
Global Set/Reset Input Buffer
BUFGSR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I O X9428
No No No Primitive Primitive Primitive
BUFGSR distributes global set/reset signals throughout selected flip-flops of an XC9500/XV/XL, CoolRunner XPLA3, or CoolRunner-II device. Global Set/Reset (GSR) control pins are available on these CPLD devices. Consult device data sheets for availability. BUFGSR always acts as an input buffer. To use it in a schematic, connect the input of the BUFGSR symbol to an IPAD or an IOPAD representing the GSR signal source. GSR signals generated on-chip must be passed through an OBUF-type buffer before they are connected to BUFGSR. For global set/reset control, the output of BUFGSR normally connects to the CLR or PRE input of a flip-flop symbol, like FDCP, or any registered symbol with asynchronous clear or preset. The global set/reset control signal may pass through an inverter to perform an active-low set/reset. The output of BUFGSR may also be used as an ordinary input signal to other logic elsewhere in the design. Each BUFGSR can control any number of flip-flops in a design.
Usage

-- Component Declaration for BUFGSR should be placed -- after architecture statement but before begin keyword component BUFGSR port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGSR -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
185
BUFGSR
-- Component Instantiation for BUFGSR should be placed -- in architecture after the begin keyword
BUFGSR_INSTANCE_NAME : BUFGSR port map (O => user_O, I => user_I);

BUFGSR instance_name (.O (user_O), .I (user_I));
186
BUFGTS
BUFGTS
Global 3-State Input Buffer
BUFGTS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I O X9428
BUFGTS distributes global output-enable signals throughout the output pad drivers of an XC9500/XV/XL, CoolRunner XPLA3, or CoolRunner-II device. Global ThreeState (GTS) control pins are available on these CPLD devices. Consult device data sheets for availability. BUFGTS always acts as an input buffer. To use it in a schematic, connect the input of the BUFGTS symbol to an IPAD or an IOPAD representing the GTS signal source. GTS signals generated on-chip must be passed through an OBUF-type buffer before they are connected to BUFGTS. For global 3-state control, the output of BUFGTS normally connects to the E input of a 3-state output buffer symbol, OBUFE. The global 3-state control signal may pass through an inverter or control an OBUFT symbol to perform an active-low outputenable. The same 3-state control signal may even be used both inverted and noninverted to enable alternate groups of device outputs. The output of BUFGTS may also be used as an ordinary input signal to other logic elsewhere in the design. Each BUFGTS can control any number of output buffers in a design.
Usage

-- Component Declaration for BUFGTS should be placed -- after architecture statement but before begin keyword component BUFGTS port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGTS -- should be placed after architecture declaration but -- before the begin keyword
187
BUFGTS
-- Enter attributes here -- Component Instantiation for BUFGTS should be placed -- in architecture after the begin keyword
BUFGTS_INSTANCE_NAME : BUFGTS port map (O => user_O, I => user_I);

BUFGTS instance_name (.O (user_O), .I (user_I));
188
BUFT, 4, 8, 16
BUFT, 4, 8, 16
Internal 3-State Buffers with Active-Low Enable
BUFT Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II BUFT4, BUFT8, BUFT16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro Macro* No No Primitive No Primitive Primitive* No No
*Not supported for XC9500XL and XC9500XV devices.
BUFT T
X3789
BUFT, BUFT4, BUFT8, and BUFT16 are single or multiple 3-state buffers with inputs I, I3 I0, I7 I0, and I15 10, respectively; outputs O, O3 O0, O7 O0, and O15 O0, respectively; and active-Low output enable (T). When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, the output is high impedance (Z state or off). The outputs of the buffers are connected to horizontal longlines in FPGA architectures. The outputs of separate BUFT symbols can be tied together to form a bus or a multiplexer. Make sure that only one T is Low at one time. For XC9500 devices, BUFT output nets assume the High logic level when all connected BUFE/BUFT buffers are disabled.
BUFT4 T
X3796
For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, when all BUFTs on a net are disabled, the net is High. For correct simulation of this effect, a PULLUP element must be connected to the net. NGDBuild inserts a PULLUP element if one is not connected so that back-annotation simulation reflects the true state of the device.
BUFT8 T
X3808
189
BUFT, 4, 8, 16
BUFT16 T
X3820
Inputs T 1 0 0 I X 1 0
O[7:0] T I0 T I1 T I2 T I3 T I4 T I5 T I6 T I7 BUFT I[7:0] T X8118 BUFT O7 BUFT O6 BUFT O5 BUFT O4 BUFT O3 BUFT O2 BUFT O1 O0
Outputs O Z 1 0
BUFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
These design elements are supported for schematics, instantiations, or inferences.
VHDL Inference Code

architecture Behavioral of buft is begin process (I, T) begin if (T = '0') then O <= I; else O <= 'Z'; end if; end process; end Behavioral;
190
BUFT, 4, 8, 16

always @ (I or T) begin if (!T) O <= I; else O <= 1'bZ; end

-- Component Declaration for BUFT should be placed -- after architecture statement but before begin keyword component BUFT port (O : out STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for BUFT -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for BUFT should be placed -- in architecture after the begin keyword BUFT_INSTANCE_NAME : port map (O => I => T => BUFT user_O, user_I, user_T);

BUFT instance_name (.O (user_O), .I (user_I), .T (user_T));

BLKNM HBLKNM HU_SET LOC U_SET
191
BUFT, 4, 8, 16
192
CAPTURE_SPARTAN2
CAPTURE_SPARTAN2
Spartan-II Register State Capture for Bitstream Readback
CAPTURE_SPARTAN2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CAPTURE_SPARTAN2
CAP
Primitive No No No No No
CLK
CAPTURE_SPARTAN2 provides user control over when to capture register (flip-flop and latch) information for readback. Spartan-II and Spartan-IIE devices provide the readback function through dedicated configuration port instructions. The CAPTURE_SPARTAN2 symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available. Note: Spartan-II and Spartan-IIE devices only allow for capturing register (flip-flop and latch)
states. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured.
X8895
An asserted High CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_SPARTAN2. See the Constraints Guide for information on the ONESHOT attribute. Note: For details on the Spartan-II and Spartan-IIE readback functions, see The Programmable Logic Data Book.
Usage

-- Component Declaration for CAPTURE_SPARTAN2 should be -- placed after architecture statement but before -- begin keyword component CAPTURE_SPARTAN2 port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_SPARTAN2 -- should be placed after architecture declaration but
193
CAPTURE_SPARTAN2
-- before the begin keyword -- Enter attributes here
-- Component Instantiation for CAPTURE_SPARTAN2 should be -- placed in architecture after the begin keyword CAPTURE_SPARTAN2_INSTANCE_NAME : CAPTURE_SPARTAN2 port map (CAP => user_CAP, CLK => user_CLK);

CAPTURE_SPARTAN2 instance_name (.CAP (user_CAP), .CLK (user_CLK));

ONESHOT
194
CAPTURE_SPARTAN3
CAPTURE_SPARTAN3
Spartan-3 Register State Capture for Bitstream Readback
CAPTURE_SPARTAN3 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
CAPTURE_SPARTAN3 CAP
CAPTURE_SPARTAN3 provides user control over when to capture register (flip-flop and latch) information for readback. Spartan-3 devices provide the readback function through dedicated configuration port instructions. The CAPTURE_SPARTAN3 symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available.
CLK
X9931
Spartan-3 allows for capturing register (flip-flop and latch) states only. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured. An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_SPARTAN3. See the Constraints Guide for information on the ONESHOT attribute.
Usage
This design element is instantiated rather than inferred.

-- Component Declaration for CAPTURE_SPARTAN3 should be -- placed after architecture statement but before -- begin keyword component CAPTURE_SPARTAN3 port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_SPARTAN3 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
195
CAPTURE_SPARTAN3
-- Component Instantiation for CAPTURE_SPARTAN3 should be -- placed in architecture after the begin keyword
CAPTURE_SPARTAN3_INSTANCE_NAME : CAPTURE_SPARTAN3 port map (CAP => user_CAP, CLK => user_CLK);

CAPTURE_SPARTAN3 instance_name (.CAP (user_CAP), .CLK (user_CLK));

ONESHOT
196
CAPTURE_VIRTEX
CAPTURE_VIRTEX
Virtex Register State Capture for Bitstream Readback
CAPTURE_VIRTEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CAPTURE_VIRTEX
CAP
No No Primitive No No No
CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and latch) information for readback. Virtex and Virtex-E devices provide the readback function through dedicated configuration port instructions. The CAPTURE_VIRTEX symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available. Note: Virtex and Virtex-E allow for capturing register (flip-flop and latch) states only. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured. An asserted High CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_VIRTEX. See the Constraints Guide for information on the ONESHOT attribute. For details on the Virtex and Virtex-E readback functions, see the Virtex datasheets on the Xilinx web site, http://support.xilinx.com.
CLK
X8681
Usage

-- Component Declaration for CAPTURE_VIRTEX should be -- placed after architecture statement but before -- begin keyword component CAPTURE_VIRTEX port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_VIRTEX -- should be placed after architecture declaration but -- before the begin keyword
197
CAPTURE_VIRTEX
-- Enter attributes here
-- Component Instantiation for CAPTURE_VIRTEX should be -- placed in architecture after the begin keyword CAPTURE_VIRTEX_INSTANCE_NAME : CAPTURE_VIRTEX port map (CAP => user_CAP, CLK => user_CLK);

CAPTURE_VIRTEX instance_name (.CAP (user_CAP), .CLK (user_CLK));

ONESHOT
198
CAPTURE_VIRTEX2
CAPTURE_VIRTEX2
Virtex-II Register State Capture for Bitstream Readback
CAPTURE_VIRTEX2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
CAPTURE_VIRTEX2 CAP
CLK
CAPTURE_VIRTEX2 provides user control over when to capture register (flip-flop and latch) information for readback. Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices provide the readback function through dedicated configuration port instructions. The CAPTURE_VIRTEX2 symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available. Virtex-II, Virtex-II Pro, and Virtex-II Pro X allow for capturing register (flip-flop and latch) states only. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured. An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_VIRTEX2. See the Constraints Guide for information on the ONESHOT attribute. The GRDBK (internal capture signal) is asserted at the rising edge of the Capture clock when the Capture signal is high. The capture memory cell is continuously updated if the value of the FF is continuously changing. The final value of the capture memory cell occurs at the rising edge of the Capture clock when the Capture signal is low. For details on the Virtex-II, Virtex-II Pro, and Virtex-II Pro X readback functions, see The Programmable Logic Data Book.
X9397
Usage

-- Component Declaration for CAPTURE_VIRTEX2 should be -- placed after architecture statement but before -- begin keyword
199
CAPTURE_VIRTEX2
component CAPTURE_VIRTEX2 port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_VIRTEX2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for CAPTURE_VIRTEX2 should be -- placed in architecture after the begin keyword CAPTURE_VIRTEX2_INSTANCE_NAME : CAPTURE_VIRTEX2 port map (CAP => user_CAP, CLK => user_CLK);

CAPTURE_VIRTEX2 instance_name (.CAP (user_CAP), .CLK (user_CLK));

None
200
CB2CE, CB4CE, CB8CE, CB16CE

2-, 4-, 8-,16-Bit Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CB2CE, CB4CE, CB8CE, CB16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CB2CE
Q0 Q1 CEO TC
CE C
CLR
X4353
CB2CE, CB4CE, CB8CE, and CB16CE are, respectively, 2-, 4-, 8-, and 16-bit (stage), asynchronous, clearable, cascadable binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, outputs Low, when power is applied.
CB4CE
Q0 Q1 Q2 Q3
CE C
CEO TC
CLR X4357
CB8CE
CE C
Q[7:0] CEO TC
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs Outputs C X X Qz-Q0 0 No Chg TC 0 No Chg CEO 0 0
CLR
X4361
CB16CE
CE C
Q[15:0] CEO TC
CLR
X4365
CLR 1 0
CE X 0
201
Inputs CLR 0 CE 1 C Qz-Q0 Inc
Outputs TC TC CEO CEO
z= 1 for CB2CE; z = 3 for CB4CE; z = 7 for CB8CE; z = 15 for CB16CE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
202
VCC
Q[7:0] FTCE
T CE C CLR Q
Q0
Q0
FTCE
T CE C Q
Q1 T2
CLR
Q1
AND2
FTCE
T CE C Q
Q2 T3
CLR
Q2
AND3
FTCE
T CE C Q
Q3 T4
CLR
Q3
AND4
FTCE
T CE C Q
Q4 T5
CLR
Q4
AND2
FTCE
T CE C Q
Q5 T6
CLR
Q5
AND3
FTCE
T CE C Q
Q6 T7
CLR
Q6
AND4
FTCE
CE C CLR T CE C Q
Q7
CLR
TC Q7
AND5
CEO X8136
AND2
CB8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,
203

VCC
CE AND2 Q0 Q1
FDC
D XOR2 C CLR Q0 AND3 Q CEO
TC AND2
FDC
D AND2 C CLR XOR2 C CLR Q1
X7779
CB2CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
204
CB2CE
Q0 CE C Q1 CE C CEO TC CLR CLR CB0 Q0 Q1
CB2CE
Q0 Q1 CE C CEO TC CLR CB2 Q2 Q3
CB2CE
CB2CE
Q0 Q1 CE C CEO TC CLR CB6 Q6 Q7 CEO
TC
X7783
AND4
CB8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cb2ce is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then
205
if (CE='1') then Q <= Q+1; end if; end if; end process; process (Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (CE or TC) begin CE0 <= TC && CE; end
206
CB2CLE, CB4CLE, CB8CLE, CB16CLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CB2CLE, CB4CLE, CB8CLE, CB16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No Macro Macro Macro
D0 D1 L CE C
CB2CLE
Q0 Q1
CEO TC
CLR X4354
D0 D1 D2 D3 L CE C
CB4CLE
Q0 Q1 Q2 Q3
CB2CLE, CB4CLE, CB8CLE, and CB16CLE are, respectively, 2-, 4-, 8-, and 16-bit (stage) synchronously loadable, asynchronously clearable, cascadable binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock transition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied.
CEO TC
CLR
X4358
D[7:0]
CB8CLE
Q[7:0]
L CE C CEO TC
CLR
X4362
D[15:0]
CB16CLE
Q[15:0]
L CE C CEO TC
CLR
X4366
207
Inputs CLR 1 0 0 0 L X 1 0 0 CE X X 0 1 C X X Dz D0 X Dn X X Qz Q0 0 Dn No Chg Inc
Outputs TC 0 TC No Chg TC CEO 0 CEO 0 CEO
z= 1 for CB2CLE; z = 3 for CB4CLE; z = 7 for CB8CLE; z = 15 for CB16CLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC
FTCLEX
D0 D L T CE C CLR Q
Q[7:0] Q0
Q0 FTCLEX
D1 D L T CE C
Q1 T2
CLR
Q1 FTCLEX
D2 D L T CE C
AND2
Q2 T3
CLR
Q2 FTCLEX
D3 D L T CE C
AND3
Q3 T4
CLR
Q3
AND4
FTCLEX
D4 D L T CE C
Q4 T5
CLR
Q4 FTCLEX
D5 D L T CE C
AND2
Q5 T6
CLR
Q5 FTCLEX
D6 D L T CE C
AND3
Q6 T7
CLR
Q6
AND4
D[7:0] D7
L CE C CLR
FTCLEX
D L T CE C Q
Q7
CLR
TC Q7
AND5
OR_CE_L OR2
CEO
AND2
X8135
CB8CLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
208
VCC
CE AND2 Q0 Q1 CEO
FDC
OR2 GND AND2B1 OR2 D0 AND2 AND2B1 D XOR2 C CLR Q0 Q AND2 AND3 TC
AND2B1 D XOR2 AND3B1 OR2 D1 C CLR AND2 C
FDC
Q
CLR Q1
X7780
CB2CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

CB2CLE
D0 D1 L CE C D0 D1 Q0 Q1 CEO TC CLR CLR CB0 Q0 Q1
L
CE C
CB2CLE
D2 D3 D0 D1 Q0 Q1 CEO TC CLR CB2 Q2 Q3
L
CE C
D[7:0]
Q[7:0]
CB2CLE
D4 D5 D0 D1 Q0 Q1 CEO TC CLR CB4 Q4 Q5
L
CE C
CB2CLE
D6 D7 D0 D1 Q0 Q1 CEO TC CLR CB6 Q6 Q7 CEO
L
CE C
TC
X8130
AND4
CB8CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
209
Usage
VHDL Inference Code

architecture Behavioral of cb2cle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (L = '1') then Q <= D; elsif (CE='1') then Q <= COUNT+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; TC <= TC_INT; CEO <= TC and CE; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0;
210
end always @ (TC or CE) begin CEO <= TC & CE; end
211
212
CB2CLED, CB4CLED, CB8CLED, CB16CLED

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No Macro Macro Macro
D0 D1 UP L CE C
CB2CLED Q0
Q1
CEO TC
CLR
X4355
CB2CLED, CB4CLED, CB8CLED, and CB16CLED are, respectively, 2-, 4-, 8- and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-toHigh clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low. For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. To cascade counters, the CEO output of each counter is connected to the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, see CB2X1, CB4X1, CB8X1, CB16X1 for high-performance cascadable, bidirectional counters. The counter is asynchronously cleared, output Low, when power is applied.
D0 D1 D2 D3 UP L CE C
CB4CLED Q0
Q1 Q2 Q3
CEO TC
CLR
X4359
D[7:0]
CB8CLED
Q[7:0]
UP L CE C CEO TC
CLR
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted with an inverter in front of the GSR input of STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2.
X4363
213
D[15:0] CB16CLED Q[15:0] UP L CE C CEO TC
Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 C X X UP X X X 1 0 Dz D0 X Dn X X X Qz Q0 0 Dn No Chg Inc Dec
Outputs TC TC No Chg TC TC CEO *CE CEO 0 CEO CEO
CLR
X4367
z = 1 for CB2CLED; z = 3 for CB4CLED; z = 7 for CB8CLED; z = 15 for CB16CLED TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP) CEO = TCCE
214
D[7:0] D0 VCC
FTCLEX D L T Q CE C CLR Q0 FTCLEX D L T Q CE C CLR Q1 Q1 T2_DN M2_1 AND2B2 T2_UP AND2 FTCLEX D L Q T CE C CLR Q2 Q2 T3_DN M2_1 AND3B3 T3_UP AND3 D0 D1 S0 O T3 T3 D0 D1 S0 O T2 T2 Q0 D0 D1 S0 M2_1B1 O T1 T1
D1
D2
D3
FTCLEX D L T Q CE C CLR Q3 Q3 T4_DN M2_1 AND4B4 T4_UP AND4 D0 D1 S0 O T4 T4
D4
FTCLEX D L T Q CE C CLR Q4
Q4 T5_DN M2_1 AND2B1 T5_UP AND2 D0 D1 S0 O T5 T5
D5
FTCLEX D L T Q CE C CLR Q5
Q5 T6_DN M2_1 AND3B2 D0 D1 S0 O T6 T6
T6_UP AND3 D6 FTCLEX D L Q T CE C CLR Q6
Q6 T7_DN M2_1 AND4B3 T7_UP AND4 D0 D1 S0 O T7 T7
D7 L CE C CLR
FTCLEX D L Q T CE C CLR Q7
Q7 Q[7:0] TC_DN M2_1 D0 O D1 S0 TC AND2 TC CEO
AND5B4 OR_CE_L OR2 TC_UP AND5 UP
X4046
CB8CLED Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
215
VCC
CE
AND2
UP
OR2 GND
AND3B2
FDC
D AND3B1 OR2 OR3 XOR2 C CLR Q
Q0
GND
D0
AND2
Q0
AND2B1
AND4B3
FDC
D AND4B1 OR3 XOR2 C CLR Q
Q1
D1
AND2
Q1
AND2B1
AND5B4
FDC
D OR3 AND5B1 XOR2 C CLR Q
Q2
D2
AND2
Q2
AND2B1
FDC
INV OR3 AND6 XOR2 D C CLR Q
Q3
Q3 D3
AND2
AND2B1
AND5 OR2
TC
AND5B5
INV INV INV INV INV
AND6 OR2
CEO
AND6
C CLR
X7625
CB4CLED Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
216
VHDL Inference Code

architecture Behavioral of cb2cled is constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif C'event and C='1' then if (L = '1') then Q <= D; elsif (CE='1') then if (UP='1') then Q <= Q+1; elsif (UP='0') then Q <= Q-1; end if; end if; end if; end process; process(Q, UP) begin if (((Q = TERMINAL_COUNT_UP) and (UP = '1')) or ((Q = TERMINAL_COUNT_DOWN) and (UP = '0'))) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (UP) Q <= Q + 1; else if (!UP) Q <= Q - 1; end end
217
always @ (Q or UP) begin if ((Q == TERMINAL_COUNT_UP && UP) || (Q == TERMINAL_COUNT_DOWN && !UP)) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
218
CB2RE, CB4RE, CB8RE, CB16RE

2-, 4-, 8-, 16-Bit Cascadable Binary Counters with Clock Enable and Synchronous Reset
CB2RE, CB4RE, CB8RE, CB16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CB2RE
Q0 Q1 CEO TC
CE C
X4356
CB2RE, CB4RE, CB8RE, and CB16RE are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, resettable, cascadable binary counters. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero during the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when both Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied.
CB4RE
Q0 Q1 Q2 Q3
CE C
CEO TC
X4360
CB8RE
CE C
Q[7:0] CEO TC
Inputs R 1 0 CE X 0 C X Qz Q0 0 No Chg Outputs TC 0 No Chg CEO 0 0
X4364
CB16RE
CE C
Q[15:0] CEO TC
X4368
219
Inputs R 0 CE 1 C Qz Q0 Inc
z = 1 for CB2RE; z = 3 for CB4RE; z = 7 for CB8RE; z = 15 for CB16RE TC = QzQ(z-1)Q(z-2)...Q0) CEO = TCCE
FTRSE
T CE C S Q
VCC
Q[7:0] Q0
Q0
FTRSE
T CE C S Q
Q1 T2
Q1
AND2
FTRSE
T CE C S Q
Q2 T3
Q2
AND3
FTRSE
T CE C S Q
Q3 T4
Q3
AND4
FTRSE
T CE C S Q
Q4 T5
Q4
AND2
FTRSE
T CE C S Q
Q5 T6
Q5
AND3
FTRSE
T CE C S Q
Q6 T7
Q6
AND4
FTRSE
T CE C S Q
Q7
CE C R
TC Q7
GND
AND5
CEO X8137
AND2
CB8RE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
220
VCC
CE AND2 R CEO AND3
FD
D AND2B1 XOR2 C Q0 AND2B1 Q AND2 TC
FD
D AND3B1 XOR2 C Q1 C AND2B1 Q
Q0 Q1
X7781
CB2RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

CB2RE
Q0 CE C Q1 CE C R R CB0 CEO TC Q0 Q1
CB2RE
Q0 Q1 CE C R CB2 CEO TC Q2 Q3
CB2RE
CB2RE
Q0 Q1 CE C R CB6 CEO TC Q6 Q7 CEO Q[7:0]
TC X8129 AND4
CB8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cb2re is
221
constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C) begin if (C'event and C='1') then if (R='1') then Q <= (others => '0'); elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
222
CB2RLE, CB4RLE, CB8RLE, CB16RLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Synchronous Reset
CB2RLE, CB4RLE, CB8RLE, CB16RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro Macro
D0 D1
CB2RLE
Q0 Q1
L CE C CEO TC
CB2RLE, CB4RLE, CB8RLE, and CB16RLE are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, loadable, resettable, cascadable binary counters. The synchronous reset (R) is the highest priority input. The synchronous R, when High, overrides all other inputs and resets the Q outputs, terminal count (TC), and clock enable out (CEO) outputs to Low on the Low-to-High clock (C) transition. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of CE. The Q outputs increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. The CEO output is High when all Q outputs and CE are High to allow direct cascading of counters. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and by connecting the C, L, and R inputs in parallel. The maximum length of the counter is determined by the accumulated CE-to-CEO propagation delays versus the clock period. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
X4513
D0 D1 D2 D3 L CE C
CB4RLE
Q0 Q1 Q2 Q3
CEO TC
X4514
D[7:0]
CB8RLE
Q[7:0]
L CE C CEO TC
X4515
Inputs
D[15:0]
Outputs C X Dz D0 X Dn X Qz Q0 0 Dn No Chg TC 0 TC No Chg CEO 0 CEO 0
CB16RLE Q[15:0]
R 1
L X 1 0
CE X X 0
L CE C CEO TC
0 0
X4516
223
Inputs R 0 L 0 CE 1 C Dz D0 X Qz Q0 Inc
z = 1 for CB2RLE; z = 3 for CB4RLE; z = 7 for CB8RLE; z = 15 for CB16RLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC
CE AND2 L OR2 GND
CEO AND3
Q1 AND3B2 D0 Q0
OR2 AND3B1 XOR2 C D
FD
TC Q AND2
Q0 AND3B2
AND4B2 D1
OR2 AND3B1 XOR2 C D
FD
Q
Q1 AND3B2 C
X7782
CB2RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
CB2RLE
D0 D1 L CE C R Q0 D0 Q1 D1 L CE CEO TC C R CB0 Q0 Q1
CB2RLE
D2 D3 Q0 D0 D1 Q1 L CE CEO C TC R CB2 Q2 Q3
CB2RLE
D4 D5 Q0 D0 Q1 D1 L CE CEO TC C R CB4 Q4 Q5
CB2RLE
D6 D7 D0 Q0 Q1 D1 L CE CEO C TC R CB6 Q6 Q7 CEO
D[7:0] Q[7:0]
TC AND4
X7621
CB8RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
224
Usage
VHDL Inference Code

architecture Behavioral of cb2rle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C) begin if (C'event and C='1') then if (R='1') then Q <= (others => '0'); elsif (L='1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
225
226
CB2X1, CB4X1, CB8X1, CB16X1

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
CB2X1, CB4X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II CB8X1, CB16X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro No No No Macro Macro Macro
D0 D1 L CEU CED C
CB2X1
QO Q1 TCU TCD CEOU CEOD
CB2X1, CB4X1, CB8X1, and CB16X1 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronously loadable, asynchronously clearable, bidirectional binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support high-speed cascading in XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU and CEOD go to Low and High, respectively, independent of clock transitions. The data on the D inputs loads into the counter on the Low-to-High clock (C) transition when the load enable input (L) is High, independent of the CE inputs. The Q outputs increment when CEU is High, provided CLR and L are Low, during the Low-to-High clock transition. The Q outputs decrement when CED is High, provided CLR and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are
CLR
X4194
D0 D1 D2 D3 CEU CED L C
CB4X1
Q0 Q1 Q2 Q3 TCU TCD CEOU CEOD
CLR
X4196
227
D[7:0]
CB8X1
Q[7:0] TCU
connected directly to the CEU and CED inputs, respectively, of the next stage. The clock, L, and CLR inputs are connected in parallel. The maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
L CEU CED C
TCD CEOU CEOD
CLR
X4198
D[15:0]
CB16X1
Q[15:0] TCU
L CEU CED C
TCD CEOU CEOD
CLR
X4200
Inputs CLR 1 0 0 0 0 0 L X 1 0 0 0 0 CEU X X 0 1 0 1 CED X X 0 0 1 1 C X X DzD0 X Dn X X X X QzQ0 0 Dn No Chg Inc Dec Inc TCU 0 TCU No Chg TCU TCU TCU
Outputs TCD 1 TCD No Chg TCD TCD TCD CEOU 0 CEOU 0 CEOU 0 Invalid CEOD CEOD CEOD 0 0 CEOD Invalid
z = 1 for CB2X1; z = 3 for CB4X1; z = 7 for CB8X1; z = 15 for CB16X1 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED
228
L
OR2
CEU
OR2
AND2B1
FDC CED
OR2 AND2B1 GND D AND3B2 OR3 XOR2 C CLR Q
Q0
Q0
D0
AND2
AND4B3
FDC
D AND3B1 OR3 XOR2 C CLR AND2B1 Q
Q1
Q1
D1
AND2
AND5B4
FDC
D AND4B1 OR3 XOR2 C CLR Q
Q2
Q2
AND2B1
D2
AND2
FDC
D OR3 AND5B1 XOR2 C CLR Q
Q3
Q3
AND2B1
D3
AND2
TCU
AND4 INV INV INV INV INV INV INV AND7
INV INV INV INV INV AND7 NOR4 D C CLR
FDC
Q
TCDINV
TCDINV
AND5B4
AND3B1
CEQU
AND2
CEQD
AND3B1
TCD
INV
C CLR
X7624
CB4X1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
229
VHDL Inference Code

architecture Behavioral of cb2x1 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif ((C'event) and (C='1')) then if (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process (Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU <= '1'; TCD <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU <= TCU and CEU; CEOD <= TCD and CED; end Behavioral;
230

always @ (posedge C or posedge CLR) begin if (CLR) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @ (TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end
231
232

2-, 4-, 8-, and 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Synchronous Reset
CB2X2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II CB4X2, CB8X2, CB16X2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro No No No Macro Macro Macro
D0 D1 L CEU CED C
CB2X2
CB2X2, CB4X2, CB8X2, and CB16X2 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, loadable, resettable, bidirectional binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support high-speed cascading in CPLD architectures. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, and clock enable outputs CEOU and CEOD go to Low and High, respectively, on the Low-to-High clock (C) transition. The data on the D inputs loads into the counter on the Low-to-High clock (C) transition when the load enable input (L) is High, independent of the CE inputs. All Q outputs increment when CEU is High, provided R and L are Low during the Low-to-High clock transition. All Q outputs decrement when CED is High, provided R and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are, respectively, connected directly to the CEU and CED inputs of the next stage. The C, L, and R inputs are connected in parallel.
X4195
D0 D1 D2 D3 L CEU CED C
CB4X2
X4197
D[7:0]
CB8X2
Q[7:0] TCU
L CEU CED C
TCD CEOU CEOD
X4199
233
D[15:0]
CB16X2
Q[15:0] TCU
L CEU CED C
TCD CEOU CEOD
The maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
X4201
Inputs R 1 0 0 0 0 0 L X 1 0 0 0 0 CEU X X 0 1 0 1 CED X X 0 0 1 1 C X Dz D0 X Dn X X X X Qz Q0 0 Dn No Chg Inc Dec Inc TCU 0 TCU No Chg TCU TCU TCU
Outputs TCD 1 TCD No Chg TCD TCD TCD CEOU 0 CEOU 0 CEOU 0 Invalid CEOD CEOD CEOD 0 0 CEOD Invalid
z = 1 for CB2X2; z = 3 for CB4X2; z = 7 for CB8X2; z = 15 for CB16X2 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED
234
L
OR2
Q3 Q2 Q1 Q0
CED
OR2
TCU
AND4B3 AND4
R TCD
INV
FD
AND3B2 OR3 XOR2 C AND3B2 D Q AND3B1
CEQD
CEQU
D0
Q0
AND2
AND3B1
CEU
OR2
GND
AND5B4
FD
AND4B2 OR3 D XOR2 C Q
AND3B2
Q1
D1
AND3B1
OR3 AND5B2 XOR2 D C
FDC
Q
AND3B2
Q2
D2
AND3B1
INV INV INV INV INV INV AND7
INV INV OR3 AND6 XOR2 D C
FDC
Q
AND3B2
Q3
D3
AND3B1 INV INV INV INV INV INV INV AND7
INV INV INV INV INV AND7 D C
FDC
Q
NOR5 INV
TCDINV
AND6
AND5B4
CB4X2 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
235
Usage
VHDL Inference Code

architecture Behavioral of cb2x2 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C) begin if ((C'event) and (C='1'))then if (R='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process(Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU <= '1'; TCD <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU<=TCU and CEU; CEOD<=TCD and CED;
236
end Behavioral;

always @ (posedge C) begin if (R) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @(TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end
237
238
CBD2CE, CBD4CE, CBD8CE, CBD16CE

2-, 4-, 8-,16-Bit Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
CBD2CE, CBD4CE, CBD8CE, CBD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CBD2CE
No No No No No No Macro
Q0 Q1 CEO TC
CE C
CLR
X9621
CBD4CE
CBD2CE, CBD4CE, CBD8CE, and CBD16CE are, respectively, 2-, 4-, 8-, and 16-bit (stage), asynchronous, clearable, cascadable dual edge triggered binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Q0 Q1 Q2 Q3
CE C
CEO TC
CLR
X9622
CBD8CE
CE C
Q[7:0] CEO TC
CLR
X9623
CBD16CE
CE C
Q[15:0] CEO TC
CLR
X9624
239
VCC
CE AND2 Q0 Q1
FDDC
D XOR2 C CLR Q0 AND3 Q CEO
TC AND2
FDDC
D AND2 C CLR XOR2 C CLR Q1
X9625
CBD2CE Implementation CoolRunner-II

CBD2CE
Q0 CE C Q1 CE C CEO TC CLR CLR CB0 Q0 Q1
CBD2CE
CBD2CE
CBD2CE
Q0 Q1 CE C CEO TC CLR CB6 TC Q6 Q7 CEO
AND4
X9626
CBD8CE Implementation CoolRunner-II
240
Usage
For HDL, these design elements are supported for inference but not instantiation.
VHDL Inference Code

architecture Behavioral of cbd2ce is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif C'event then if (CE='1') then Q <= Q+1; end if; end if; end process; process (Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
241
242
CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro
D0 D1 L CE C
CBD2CLE
Q0 Q1
CEO TC
CLR
X9627
D0 D1 D2 D3 L CE C
CBD4CLE
Q0 Q1 Q2 Q3
CBD2CLE, CBD4CLE, CBD8CLE, and CBD16CLE are, respectively, 2-, 4-, 8-, and 16bit (stage) synchronously loadable, asynchronously clearable, cascadable dual edge triggered binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock transition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
CEO TC
CLR D[7:0]
X9628
CBD8CLE
Q[7:0]
L CE C CEO TC
CLR
X9629
Inputs CLR L X 1 1 0 CE X X X 0 C X X Dz D0 X Dn Dn X Qz Q0 0 Dn Dn No Chg
Outputs TC 0 TC TC No Chg CEO 0 CEO CEO 0
D[15:0]
CBD16CLE
Q[15:0]
1 0
CEO TC
L CE C
0 0
CLR
X9630
243
Inputs CLR 0 0 L 0 0 CE 1 1 C Dz D0 X X Qz Q0 Inc Inc
Outputs TC TC TC CEO CEO CEO
z= 1 for CBD2CLE; z = 3 for CBD4CLE; z = 7 for CBD8CLE; z = 15 for CBD16CLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC
CE AND2 Q0 Q1 CEO
FDDC
OR2 GND AND2B1 OR2 D0 AND2 AND2B1 D XOR2 C CLR Q0 Q AND2 AND3 TC
AND2B1 D XOR2 AND3B1 OR2 D1 C CLR AND2 C
FDDC
Q
CLR Q1
X9631
CBD2CLE Implementation CoolRunner-II
244
CBD2CLE
D0 D1 L CE C D0 D1 L CE C CEO TC CLR CLR CB0 Q0 Q1 Q0 Q1
CBD2CLE
D2 D3 D0 D1 L CE C D[7:0] Q0 Q1 CEO TC CLR CB2 Q[7:0] Q2 Q3
CBD2CLE
D4 D5 D0 D1 L CE C Q0 Q1 CEO TC CLR CB4 Q4 Q5
CBD2CLE
D6 D7 D0 D1 L CE C Q0 Q1 CEO TC CLR CB6 Q6 Q7 CEO
TC
AND4
X9632
CBD8CLE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cbd2cle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then
245
Q <= (others => '0'); elsif C'event then if (L = '1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
246
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro
D0 D1 UP L CE C
CBD2CLED Q0
Q1
CEO TC
CLR
X9633
D0 D1 D2 D3 UP L CE C
CBD4CLED Q0
Q1 Q2 Q3
CBD2CLED, CBD4CLED, CBD8CLED, and CBD16CLED are, respectively, 2-, 4-, 8and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional dual edge triggered binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-to-High and High-to-Low clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low. For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. To cascade counters, the CEO output of each counter is connected to the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. For CoolRunner-II, see CB2X1, CB4X1, CB8X1, CB16X1 for high-performance cascadable, bidirectional counters. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
CEO TC
CLR
X9634
D[7:0]
CBD8CLED
Q[7:0]
UP L CE C CEO TC
CLR
X9635
D[15:0] CBD16CLED Q[15:0] UP L CE C CEO TC
CLR
X9636
247
Inputs CLR 1 0 0 0 0 0 0 0 L X 1 1 0 0 0 0 0 CE X X X 0 1 1 1 1 C X X UP X X X X 1 1 0 0 Dz D0 X Dn Dn X X X X X Qz Q0 0 Dn Dn No Chg Inc Inc Dec Dec
Outputs TC 0 TC TC No Chg TC TC TC TC CEO 0 CEO CEO 0 CEO CEO CEO CEO
z = 1 for CBD2CLED; z = 3 for CBD4CLED; z = 7 for CBD8CLED; z = 15 for CBD16CLED TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP) CEO = TCCE
248
VCC
CE
AND2
UP
OR2 GND
AND3B2
FDDC
D AND3B1 OR2 OR3 XOR2 C CLR Q0 AND2 Q Q0
GND
D0
AND2B1
AND4B3
FDDC
D AND4B1 OR3 XOR2 C CLR Q1 AND2 Q Q1
D1
AND2B1
AND5B4
FDDC
D OR3 AND5B1 XOR2 C CLR Q2 AND2 Q Q2
D2
AND2B1
FDDC
INV OR3 AND6 XOR2 D C CLR Q3 Q Q3
D3
AND2
AND2B1
AND5 OR2
TC
AND5B5
INV INV INV INV INV
AND6 OR2
CEO
AND6
C CLR
X9637
CBD4CLED Implementation CoolRunner-II
249
Usage
VHDL Inference Code

architecture Behavioral of cbd2cled is constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event) then if (L = '1') then Q <= D; elsif (CE='1') then if (UP='1') then Q <= Q+1; elsif (UP='0') then Q <= Q-1; end if; end if; end if; end process; process(Q, UP) begin if (((Q = TERMINAL_COUNT_UP) and (UP = '1')) or ((Q = TERMINAL_COUNT_DOWN) and (UP = '0'))) then TC <='1'; else TC <='0'; end if; end process; CEO <=TC and CE; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (UP) Q <= Q + 1;
250
else if (!UP) Q <= Q - 1; end end always @ (Q or UP) begin if ((Q == TERMINAL_COUNT_UP && UP) || (Q == TERMINAL_COUNT_DOWN && !UP)) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
251
252
CBD2RE, CBD4RE, CBD8RE, CBD16RE

2-, 4-, 8-, 16-Bit Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Synchronous Reset
CBD2RE, CBD4RE, CBD8RE, CBD16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro
CBD2RE
Q0 Q1 CEO TC
CE C
X9638
CBD4RE
Q0 Q1 Q2 Q3
CBD2RE, CBD4RE, CBD8RE, and CBD16RE are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, resettable, cascadable dual edge triggered binary counters. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero during the Low-to-High or High-to-Low clock transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when both Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
CE C
CEO TC
R
X9639
CBD8RE
CE C
Q[7:0] CEO TC
R
X9640
Inputs
CBD16RE
CE C Q[15:0] CEO TC
Outputs C X Qz Q0 0 0 No Chg Inc TC 0 0 No Chg TC CEO 0 0 0 CEO
R 1 1 0 0
CE X X 0 1
X9641
253
z = 1 for CBD2RE; z = 3 for CBD4RE; z = 7 for CBD8RE; z = 15 for CBD16RE TC = QzQ(z-1)Q(z-2)...Q0) CEO = TCCE
VCC
CE AND2 R CEO AND3
FDD
D AND2B1 XOR2 C Q0 AND2B1 Q AND2 TC
FDD
D AND3B1 XOR2 C Q1 C AND2B1 Q
Q0 Q1
X9642
CBD2RE Implementation CoolRunner-II
254
CBD2RE
Q0 CE C Q1 CE C R R CB0 CEO TC Q0 Q1
CBD2RE
CBD2RE
CBD2RE
Q0 Q1 CE C R CB6 CEO TC Q6 Q7 CEO Q[7:0]
TC
AND4
X9643
CBD8RE Implementation CoolRunner-II
Usage
255
VHDL Inference Code

architecture Behavioral of cbd2re is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, R) begin if (C'event) then if (R='1') then Q <= (others => '0'); elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
256
CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

2-, 4-, 8-, 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Synchronous Reset
CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
D0 D1
No No No No No No Macro
CBD2RLE
Q0 Q1
L CE C CEO TC
X9644
CBD2RLE, CBD4RLE, CBD8RLE, and CBD16RLE are, respectively, 2-, 4-, 8-, and 16bit (stage), synchronous, loadable, resettable, cascadable dual edge triggered binary counters. The synchronous reset (R) is the highest priority input. The synchronous R, when High, overrides all other inputs and resets the Q outputs, terminal count (TC), and clock enable out (CEO) outputs to Low on the Low-to-High or High-to-Low clock (C) transition. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High and High-to-Low clock (C) transition, independent of the state of CE. The Q outputs increment when CE is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. The CEO output is High when all Q outputs and CE are High to allow direct cascading of counters. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and by connecting the C, L, and R inputs in parallel. The maximum length of the counter is determined by the accumulated CE-to-CEO propagation delays versus the clock period. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
D0 D1 D2 D3 L CE C
CBD4RLE
Q0 Q1 Q2 Q3
CEO TC
X9645
D[7:0]
CBD8RLE
Q[7:0]
L CE C CEO TC
X9646
D[15:0]
CBD16RLE
Q[15:0]
L CE C CEO TC
X9647
257
Inputs R 1 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 C X Dz D0 X X Dn Dn X X X Qz Q0 0 0 Dn Dn No Chg Inc Inc
Outputs TC 0 0 TC TC No Chg TC TC CEO 0 0 CEO CEO 0 CEO CEO
z = 1 for CBD2RLE; z = 3 for CBD4RLE; z = 7 for CBD8RLE; z = 15 for CBD16RLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC
CE AND2 L OR2 GND
CEO AND3
Q1 AND3B2 D0 Q0
OR2 AND3B1 XOR2 C D
FDD
TC Q AND2
Q0 AND3B2
AND4B2 D1
OR2 AND3B1 XOR2 C D
FDD
Q
Q1 AND3B2 C
X9648
CBD2RLE Implementation CoolRunner-II
258
CBD2RLE
D0 D1 L CE C R Q0 D0 Q1 D1 L CE CEO TC C R CB0 Q0 Q1
CBD2RLE
D2 D3 D0 Q0 D1 Q1 L CE CEO C TC R CB2 Q2 Q3
CBD2RLE
D4 D5 Q0 D0 Q1 D1 L CE CEO TC C R CB4 Q4 Q5
CBD2RLE
D6 D7 D0 Q0 D1 Q1 L CE CEO C TC R D[7:0] Q[7:0] TC CB6 Q6 Q7 CEO
AND4
X9649
CBD8RLE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cbd2rle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, R) begin if (C'event) then if (R='1') then Q <= (others => '0'); elsif (L='1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin
259
if (Q = TERMINAL_COUNT) then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
260
CBD2X1, CBD4X1, CBD8X1, CBD16X1

2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
CBD2X1, CBD4X1, CBD8X1, CBD16X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro
D0 D1 L CEU CED C
CBD2X1
CBD2X1, CBD4X1, CBD8X1, and CBD16X1 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronously loadable, asynchronously clearable, bidirectional dual edge triggered binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support highspeed cascading in the CoolRunner-II architecture. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU and CEOD go to Low and High, respectively, independent of clock transitions. The data on the D inputs loads into the counter on the Low-to-High and High-to-Low clock (C) transition when the load enable input (L) is High, independent of the CE inputs. The Q outputs increment when CEU is High, provided CLR and L are Low, during the Low-to-High and High-to-Low clock transition. The Q outputs decrement when CED is High, provided CLR and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are connected directly to the CEU and CED inputs, respectively, of the next stage. The clock, L, and CLR inputs are connected in parallel. In CoolRunner-II, the maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable
CLR
X9650
D0 D1 D2 D3 CEU CED L C
CBD4X1
CLR
X9651
D[7:0]
CBD8X1
Q[7:0] TCU
L CEU CED C
TCD CEOU CEOD
CLR
X9652
261
D[15:0]
CBD16X1
Q[15:0] TCU
AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
L CEU CED C
TCD CEOU CEOD
CLR
X9653
Inputs CLR 1 0 0 0 0 0 0 0 0 0 L X 1 1 0 0 0 0 0 0 0 CEU X X X 0 1 1 0 0 1 1 CED X X X 0 0 0 1 1 1 1 C X X DzD0 X Dn Dn X X X X X X X QzQ0 0 Dn Dn No Chg Inc Inc Dec Dec Inc Inc TCU 0 TCU TCU No Chg TCU TCU TCU TCU TCU TCU
Outputs TCD 1 TCD TCD No Chg TCD TCD TCD TCD TCD TCD CEOU 0 CEOU CEOU 0 CEOU CEOU 0 0 Invalid Invalid CEOD CEOD CEOD CEOD 0 0 0 CEOD CEOD Invalid Invalid
z = 1 for CBD2X1; z = 3 for CBD4X1; z = 7 for CBD8X1; z = 15 for CBD16X1 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED
CBD4X1 Implementation CoolRunner-II
Usage
262
VHDL Inference Code

architecture Behavioral of cbd2x1 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif C'event then if (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process(Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU_INT <= '1'; TCD_INT <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU <= TCU and CEU; CEOD <= TCD and CED; end Behavioral;
263

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @ (TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end
264

2-, 4-, 8-, and 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counters with Clock Enable and Synchronous Reset
CBD2X2, CBD4X2, CBD8X2, CBD16X2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro
D0 D1 L CEU CED C
CBD2X2
CBD2X2, CBD4X2, CBD8X2, and CBD16X2 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, loadable, resettable, bidirectional dual edge triggered binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support high-speed cascading in the CoolRunner-II architecture. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, and clock enable outputs CEOU and CEOD go to Low and High, respectively, on the Low-to-High and High-to-Low clock (C) transition. The data on the D inputs loads into the counter on the Low-to-High and High-to-Low clock (C) transition when the load enable input (L) is High, independent of the CE inputs. All Q outputs increment when CEU is High, provided R and L are Low during the Low-to-High and High-to-Low clock transition. All Q outputs decrement when CED is High, provided R and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are, respectively, connected directly to the CEU and CED inputs of the next stage. The C, L, and R inputs are connected in parallel. In CoolRunner-II, the maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable
X9655
D0 D1 D2 D3 L CEU CED C
CBD4X2
R
X9656
D[7:0]
CBD8X2
Q[7:0] TCU
L CEU CED C
TCD CEOU CEOD
X9657
D[15:0]
CBD16X2
Q[15:0] TCU
L CEU CED C
TCD CEOU CEOD
X9658
265
AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 0 0 0 0 0 L X X 1 1 0 0 0 0 0 0 0 CEU X X X X 0 1 1 0 0 1 1 CED X X X X 0 0 0 1 1 1 1 C X Dz D0 X X Dn Dn X X X X X X X Qz Q0 0 0 Dn Dn No Chg Inc Inc Dec Dec Inc Inc TCU 0 0 TCU TCU No Chg TCU TCU TCU TCU TCU TCU
Outputs TCD 1 1 TCD TCD No Chg TCD TCD TCD TCD TCD TCD CEOU 0 0 CEOU CEOU 0 CEOU CEOU 0 0 Invalid Invalid CEOD CEOD CEOD CEOD CEOD 0 0 0 CEOD CEOD Invalid Invalid
z = 1 for CBD2X2; z = 3 for CBD4X2; z = 7 for CBD8X2; z = 15 for CBD16X2 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED
266
L OR2
Q3 Q2 Q1 Q0
CED OR2 R AND4B3 AND4 TCD INV TCU
FDD
AND3B2 OR3 XOR2 C AND3B2 D0 Q0 AND2 CEQD D Q AND3B1 CEQU
AND3B1 CEU OR2
GND
AND5B4
FDD
AND4B2 OR3 D XOR2 C Q1 Q
AND3B2 D1
AND3B1
OR3 AND5B2 XOR2 D C
FDDC
Q
AND3B2 D2
Q2
AND3B1
INV INV INV INV INV INV AND7
INV INV OR3 AND6 XOR2 D C Q3
FDDC
Q
AND3B2 D3
AND3B1 INV INV INV INV INV INV INV AND7
INV INV INV INV INV AND7 D C TCDINV
FDDC
Q
NOR5 INV
AND6
AND5B4 C
X9659
CBD4X2 Implementation CoolRunner-II
Usage
267
VHDL Inference Code

architecture Behavioral of cbd2x2 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C) begin if (C'event) then if (R='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process(Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU_INT <= '1'; TCD_INT <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU <= TCU and CEU; CEOD <= TCD and CED; end Behavioral;

always @ (posedge C or negedge C)
268
begin if (R) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @ (TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end
269
270
CC8CE, CC16CE
CC8CE, CC16CE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CC8CE, CC16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
CC8CE
CE C
Q[7:0] CEO TC
CLR
X4290
CC16CE
CE C
Q[15:0] CEO TC
CC8CE and CC16CE are, respectively, 8- and 16-bit (stage), asynchronous clearable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, with Low outputs, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 CE X 0 C X X Qz Q0 0 No Chg Outputs TC 0 No Chg CEO 0 0
CLR X4286
271
CC8CE, CC16CE
Inputs CLR 0 CE 1 C Qz Q0 Inc
z = 7 for CC8CE; z = 15 for CC16CE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
TC CEO AND2 Q[7:0]
Q7
MUXCY O RLOC=R0C0.S1 S 0 1 CI DI LI CI C7 XORCY
FMAP FDCE O TQ7 D Q CE C CLR RLOC=R0C0.S0 FDCE O TQ6 D Q CE C CLR RLOC=R0C0.S0 FDCE O TQ5 D Q CE C CLR RLOC=R1C0.S0 FDCE O TQ4 D Q CE C CLR RLOC=R1C0.S0 FMAP FDCE O TQ3 D Q CE C CLR RLOC=R2C0.S0 FDCE O TQ2 D Q CE C CLR RLOC=R2C0.S0 FDCE O TQ1 D Q CE C CLR RLOC=R3C0.S0 FDCE O TQ0 D Q CE C CLR RLOC=R3C0.S0 Q0 C0 Q0 Q1 C1 Q1 Q2 C2 Q2 Q3 C3 Q3 I4 I3 I2 I1 TQ3 Q4 C4 Q4 Q5 C5 Q5 Q6 C6 Q6 Q7 C7 Q7 I4 I3 I2 I1 TQ7
Q6
MUXCY_L LO S RLOC=R0C0.S1 0 1 DI CI LI CI C6 XORCY
RLOC=R0C0.S0 FMAP I4 I3 I2 I1 TQ6
Q5
MUXCY_L LO RLOC=R1C0.S1 S 0 1 CI DI LI CI C5 XORCY
Q4
MUXCY_L LO S RLOC=R1C0.S1 0 1 CI DI LI CI C4 XORCY
Q3
MUXCY_L LO RLOC=R2C0.S1 S 0 1 CI DI LI CI C3 XORCY
RLOC=R1C0.S0
Q2
MUXCY_L LO S RLOC=R2C0.S1 0 1 DI CI LI CI C2 XORCY
Q1
Q0
GND VCC
RLOC=R3C0.S0
CE C CLR
X8890
CC8CE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
272
CC8CE, CC16CE
TC
CEO AND2 Q[7:0]
O Q7 S MUXCY 0 DI 1 CI LI O TQ7 CI XORCY C7 LO Q6 S MUXCY_L 0 DI 1 CI LI O TQ6 CI XORCY C6 LO Q5 S MUXCY_L 0 1 DI CI LI O TQ5 CI XORCY C5 LO Q4 S MUXCY_L 0 DI 1 CI LI O TQ4 CI XORCY C4 LO Q3 S MUXCY_L 0 DI 1 CI LI O TQ3 CI XORCY C3 LO Q2 S MUXCY_L 0 1 DI CI LI O TQ2 CI XORCY C2 LO Q1 S MUXCY_L 0 1 DI CI LI O TQ1 CI XORCY C1 LO Q0 S MUXCY_L 0 DI 1 CI LI O TQ0 CI XORCY GND VCC C0 D CE C CLR RLOC=X0Y0 RLOC=X0Y0 D CE C CLR RLOC=X0Y0 RLOC=X0Y1 D CE C CLR RLOC=X0Y1 RLOC=X0Y1 D CE C CLR RLOC=X0Y1 RLOC=X0Y2 D CE C CLR RLOC=X0Y2 RLOC=X0Y2 D CE C CLR RLOC=X0Y2 RLOC=X0Y3 D CE C CLR RLOC=X0Y3 RLOC=X0Y3 D CE C CLR RLOC=X0Y3
FDCE
Q Q7
FDCE
Q Q6
FDCE
Q Q5
FDCE
Q Q4
FDCE
Q Q3
FDCE
Q Q2
FDCE
Q Q1
FDCE
Q Q0
RLOC=X0Y0 CE C CLR X9309
CC8CE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
273
CC8CE, CC16CE
Usage
VHDL Inference Code

architecture Behavioral of cc8ce is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (CE='1') then Q <= Q+1; end if; end if; end process; process (Q) begin if (Q = TERMINAL_COUNT) then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end
274
CC8CE, CC16CE
always @ (TC or CE) begin CEO <= TC & CE; end
275
CC8CE, CC16CE
276
CC8CLE, CC16CLE
CC8CLE, CC16CLE
8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
CC8CLE, CC16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D[7:0]
CC8CLE
Q[7:0] CEO
L CE C
TC
CC8CLE and CC16CLE are, respectively, 8- and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, with Low output, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
CLR
X4289
D[15:0]
CC16CLE Q[15:0]
CEO TC
L CE C
CLR
X4284
277
CC8CLE, CC16CLE
GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 L X 1 0 0 CE X X 0 1 C X X Dz D0 X Dn X X Qz Q0 0 Dn No Chg Inc Outputs TC 0 TC No Chg TC CEO 0 CEO 0 CEO
z = 7 for CC8CLE; z = 15 for CC16CLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
278
CC8CLE, CC16CLE
TC CEO AND2 MUXCY S 0 DI O 1 CI RLOC=R0C0.S1 L LI CI M2_1 O TQ7 D7 XORCY RLOC=R0C0.S1 RLOC=R0C0.S0 CI LI CI C6 MUXCY_L Q5 S DI 0 LO 1 CI RLOC=R1C0.S1 LI CI M2_1 O TQ5 D5 XORCY RLOC=R1C0.S1 1 CI LI CI M2_1 O TQ4 D4 XORCY D0 D1 S0 O MD4 RLOC=R1C0.S0 FDCE D Q CE C CLR RLOC=R1C0.S0 M2_1 O TQ3 D3 XORCY RLOC=R2C0.S1 0 DI 1 CI LI CI M2_1 O TQ2 D2 XORCY D0 D1 S0 O MD2 RLOC=R2C0.S0 FDCE D Q CE C CLR RLOC=R2C0.S0 M2_1 O TQ1 D1 XORCY RLOC=R3C0.S1 RLOC=R3C0.S0 CI LI CI M2_1 O TQ0 D0 XORCY C0 VCC D0 D1 S0 O MD0 FDCE Q0 D Q CE C CLR RLOC=R3C0.S0 D[7:0] L CE C CLR OR2 X8891 L_CE L D0 TQ0 D0 D1 S0 O MD1 D Q CE C CLR FDCE Q1 L D1 TQ1 Q2 L D2 TQ2 FMAP I4 I3 I2 I1 RLOC=R2C0.S0 FMAP I4 I3 I2 I1 RLOC=R3C0.S0 FMAP I4 I3 I2 I1 RLOC=R3C0.S0 O MD0 O MD1 O MD2 D0 D1 S0 O MD3 FDCE D Q CE C CLR Q3 L D3 TQ3 Q4 L D4 TQ4 RLOC=R1C0.S0 FMAP I4 I3 I2 I1 RLOC=R1C0.S0 FMAP I4 I3 I2 I1 RLOC=R2C0.S0 O MD3 O MD4 D0 D1 S0 O MD5 O TQ6 D6 XORCY D0 D1 S0 M2_1 O MD6 FDCE D Q CE C CLR RLOC=R0C0.S0 FDCE D Q CE C CLR Q5 L D5 TQ5 Q6 L D6 TQ6 D0 D1 S0 O MD7 FDCE D Q CE C CLR Q7 D7 TQ7 FMAP I4 I3 I2 I1 RLOC=R0C0.S0 FMAP I4 I3 I2 I1 RLOC=R0C0.S0 FMAP I4 I3 I2 I1 O MD5 O MD6 O MD7 Q[7:0]
Q7
C7 Q6 MUXCY_L S 0 DI LO 1
C5 Q4 MUXCY_L S 0 DI LO
C4 MUXCY_L Q3 S DI 0 LO 1 CI
RLOC=R2C0.S1 LI CI
C3 MUXCY_L Q2 S LO
C2 Q1 MUXCY_L S 0 DI LO
RLOC=R3C0.S1 1 CI LI CI C1
MUXCY_L Q0 S DI 0
LO 1
GND
CC8CLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
279
CC8CLE, CC16CLE
TC
CEO AND2 Q[7:0]
O Q7 S MUXCY 0 1 DI CI LI O CI D7 XORCY C7 LO Q6 S MUXCY_L 0 1 DI CI LI O CI D6 XORCY S0 C6 LO Q5 S MUXCY_L 0 1 DI CI LI O CI D5 XORCY C5 LO Q4 S MUXCY_L 0 1 DI CI LI O CI D4 XORCY S0 C4 LO Q3 S MUXCY_L 0 1 DI CI LI O CI D3 XORCY C3 LO Q2 S MUXCY_L 0 1 DI CI LI O CI D2 XORCY S0 C2 LO Q1 S MUXCY_L 0 1 DI CI LI O CI D1 XORCY C1 LO Q0 S MUXCY_L 0 1 DI CI LI O CI D0 XORCY GND VCC C0 S0 D1 TQ0 D0 O MD0 D CE C CLR Q Q0 TQ0 RLOC=X0Y0 RLOC=X1Y0 L I4 I3 O I2 I1 RLOC=X1Y0 MD0 S0 D1 TQ1 D0 O MD1 D CE C CLR Q Q1 TQ1 RLOC=X0Y0 RLOC=X1Y1 L D1 TQ2 D0 O MD2 D CE C CLR Q Q2 TQ2 RLOC=X0Y1 RLOC=X1Y1 L I4 I3 O I2 I1 RLOC=X1Y1 MD2 S0 D1 TQ3 D0 O MD3 D CE C CLR Q Q3 TQ3 RLOC=X0Y1 RLOC=X1Y2 L D1 TQ4 D0 O MD4 D CE C CLR Q Q4 TQ4 RLOC=X0Y2 RLOC=X1Y2 L I4 I3 O I2 I1 RLOC=X1Y2 MD4 S0 D1 TQ5 D0 O MD5 D CE C CLR Q Q5 TQ5 RLOC=X0Y2 RLOC=X1Y3 L D1 TQ6 D0 O MD6 D CE C CLR Q Q6 TQ6 RLOC=X0Y3 RLOC=X1Y3 L I4 I3 O I2 I1 RLOC=X1Y3 MD6 S0 D1 TQ7 D0 O MD7 D CE C CLR Q Q7 TQ7 RLOC=X0Y3
FMAP
L
M2_1
FDCE
I4 I3 O I2 I1 RLOC=X1Y3 MD7
D7
FMAP
M2_1
FDCE
D6
FMAP
M2_1
FDCE
D5
FMAP
M2_1
FDCE
D4
FMAP
M2_1
FDCE
D3
FMAP
M2_1
FDCE
D2
FMAP
M2_1
FDCE
D1
FMAP
M2_1
FDCE
D0
RLOC=X1Y0 D[7:0] L L_CE CE C CLR OR2 X9310
CC8CLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
280
CC8CLE, CC16CLE
Usage
VHDL Inference Code

architecture Behavioral of cc8cle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (L = '1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end
281
CC8CLE, CC16CLE
always @ (TC or CE) begin CEO <= TC & CE; end
282
CC8CLED, CC16CLED
CC8CLED, CC16CLED
8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
CC8CLED, CC16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D[7:0]
CC8CLED Q[7:0]
CEO TC
UP L CE C
CC8CLED and CC16CLED are, respectively, 8- and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional binary counters. These counters are implemented using carry logic with relative location constraints, which assures most efficient logic placement. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-to-High clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low. For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. To cascade counters, the count enable out (CEO) output of each counter is connected to the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, outputs Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
CLR
X4287
D[15:0] CC16CLED Q[15:0] CEO UP L CE C TC
CLR
X4285
283
CC8CLED, CC16CLED
Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 C X X UP X X X 1 0 Dz D0 X Dn X X X Qz Q0 0 Dn No Chg Inc Dec
Outputs TC 0 TC No Chg TC TC CEO 0 CEO 0 CEO CEO
z = 7 for CC8CLED; z = 15 for CC16CLED TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP) CEO = TCCE
284
CC8CLED, CC16CLED
TC CEO
AND2
Q[7:0]
INV DN7 Q7 XOR2
O SQ7 S
MUXCY
RLOC=R0C0.S1
0 DI
1 CI LI CI XORCY C7 LO
FMAP
I4 I3 I2 I1 O SQ7
TQ7 D7
M2_1
D0 D1 S0 O MD7
FDCE
D Q CE C CLR RLOC=R0C0.S0 Q7
FMAP
L I4 D7 I3 TQ7 I2 I1 O MD7
UP Q7
RLOC=R0C0.S1 Q6
INV DN6 XOR2
RLOC=R0C0.S1
RLOC=R0C0.S0
SQ6
MUXCY_L
FMAP
I4 I3 I2 I1 O SQ6
0 DI
1 CI LI CI XORCY C6
FMAP M2_1
O TQ6 D6 D0 D1 S0 O MD6
FDCE
UP Q6
L I4 D6 I3 TQ6 I2 I1
O MD6
RLOC=R0C0.S1 INV DN5 Q5 XOR2 O SQ5 LO SQ5 S

MUXCY_L
RLOC=R0C0.S0
RLOC=R1C0.S1
FMAP
I4 I3 I2 I1
0 DI
FMAP M2_1
O XORCY TQ5 D5 D0 D1 S0 O MD5 L I4 D5 I3 TQ5 I2 I1 O MD5
1 CI LI CI
UP Q5
FDCE
RLOC=R1C0.S1 C5
RLOC=R1C0.S0
FMAP
I4 I3 I2 I1 INV DN4 Q4 O SQ4 XOR2 SQ4 S 0 DI
LO
MUXCY_L
RLOC=R1C0.S1
FMAP
L I4 D4 I3 TQ4 I2 I1 Q4 O MD4
UP Q4
1 CI LI CI XORCY TQ4 D4
M2_1
D0 D1 S0 O MD4
FDCE
D Q CE C CLR RLOC=R1C0.S0
RLOC=R1C0.S1
RLOC=R1C0.S0
FMAP
I4 I3 I2 I1 O SQ3 Q3 XOR2 INV DN3 LO SQ3 S
C4
FMAP
RLOC=R2C0.S1
UP Q3
MUXCY_L
0 DI
1 CI LI CI XORCY C3 TQ3 D3
RLOC=R2C0.S1
M2_1
D0 D1 S0 O MD3
FDCE
RLOC=R2C0.S0
FMAP
I4 I3 I2 I1 O SQ2 INV DN2 Q2 RLOC=R2C0.S1 XOR2 SQ2 S
FMAP
UP Q2
LO
MUXCY_L
RLOC=R2C0.S1
0 DI
1 CI LI CI XORCY
RLOC=R2C0.S0
M2_1
FDCE
FMAP
I4 I3 I2 I1 O SQ1 LO SQ1 XOR2 S
MUXCY_L
FMAP
UP Q1
C2 RLOC=R3C0.S1
RLOC=R3C0.S1 Q1
INV DN1
RLOC=R3C0.S0
0 DI
1 CI LI CI
FMAP
I4 I3 I2 I1 O XORCY C1 RLOC=R3C0.S1 INV DN0 Q0 XOR2 SQ0 S LO
MUXCY_L
M2_1
TQ1 D1 D0 D1 S0 O MD1
FDCE
FMAP
UP Q0
O SQ0
RLOC=R3C0.S0
RLOC=R3C0.S1
0 DI
1 CI LI CI XORCY
M2_1
FDCE
GND VCC UP
C0
D[7:0] L CE C CLR OR2 X8892 L_CE
CC8CLED Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
285
CC8CLED, CC16CLED
TC
CEO AND2 Q[7:0]
FMAP
I4 I3 UP Q7 O I2 I1 RLOC=X0Y3 DN7 SQ7 Q7 INV XOR2 SQ7 S O MUXCY 0 1 DI CI RLOC=X0Y3
FMAP
L LI O CI D7 D1 S0 XORCY TQ7 D0 O MD7 D CE C CLR RLOC=X0Y3 RLOC=X1Y3 L LI Q Q7 TQ7
M2_1
FDCE
D7
FMAP
I4 I3 UP Q6 O I2 I1 RLOC=X0Y3 DN6 SQ6 Q6 INV XOR2 SQ6 S LO
C7
MUXCY_L 0 1 DI CI
FMAP
I4 I3 O I2 I1 MD6 D6
M2_1
O TQ6 D6 XORCY D0 O D1 S0 MD6 D
FDCE
Q Q6
CI
TQ6
CE C CLR
FMAP
C6
RLOC=X1Y3
MUXCY_L 0 1 DI CI
RLOC=X0Y2 RLOC=X1Y3 L LI O CI D5 D1 S0 XORCY TQ5 D0 O MD5 D CE C CLR RLOC=X0Y2 RLOC=X1Y2 L LI Q Q5 TQ5
FMAP
I4 I3 O I2 I1 RLOC=X1Y2 MD5 D5
M2_1
FDCE
FMAP
C5
MUXCY_L 0 1 DI CI
FMAP
I4 I3 O I2 I1 MD4 D4
M2_1
O TQ4 D4 D0 O D1 S0 XORCY MD4 D
FDCE
Q Q4
CI C4 LO
TQ4
CE C CLR
FMAP
I4 I3 UP Q3 O I2 I1 RLOC=X0Y1 SQ3 Q3 INV XOR2 DN3 SQ3 S
RLOC=X1Y2
MUXCY_L 0 1 DI CI
RLOC=X0Y1 RLOC=X1Y2
FMAP
L Q3 D3 TQ3 I4 I3 O I2 I1 MD3
LI CI C3 LO XORCY O TQ3 D3 D0 D1 S0
M2_1
O MD3 D
FDCE
Q
CE C CLR
FMAP
MUXCY_L 0 1 DI CI
RLOC=X0Y1 RLOC=X1Y1
RLOC=X1Y1
FMAP
L D2 Q2 TQ2 I4 I3 O I2 I1 MD2
LI O CI D2 XORCY C2 LO D1 S0 TQ2 D0
M2_1
O MD2 D
FDCE
Q
CE C CLR RLOC=X1Y1
FMAP
MUXCY_L 0 1 DI CI
RLOC=X0Y0 RLOC=X1Y1
FMAP
LI O CI D1 D1 S0 XORCY TQ1 D0 O MD1 D CE I1 C CLR RLOC=X0Y0 RLOC=X1Y0 RLOC=X1Y0 Q Q1 TQ1
M2_1
FDCE
L D1
I4 I3 O I2 MD1
C1
FMAP
I4 I3 UP Q0 O I2 I1 RLOC=X0Y0 Q0 SQ0 XOR2 INV DN0 SQ0 S
LO MUXCY_L 0 1 DI CI
FMAP
L D0 Q0 TQ0 I4 I3 O I2 I1 MD0
LI O CI D0 XORCY C0 VCC UP D[7:0] L GND D1 S0 TQ0 D0
M2_1
O MD0 D
FDCE
Q
CE C CLR RLOC=X1Y0 RLOC=X1Y0
L_CE CE C CLR OR2 X9311
CC8CLED Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
286
CC8CLED, CC16CLED
VHDL Inference Code

architecture Behavioral of cc8cled is constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (L = '1') then Q <= D; elsif (CE='1') then if (UP='1') then Q <= Q+1; elsif (UP='0') then Q <= Q-1; end if; end if; end if; end process; process(Q, UP) begin if (((Q = TERMINAL_COUNT_UP) and (UP = '1')) or ((Q = TERMINAL_COUNT_DOWN) and (UP = '0'))) then TC<='1'; else TC<='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (UP) Q <= Q + 1; else if (!UP) Q <= Q - 1;
287
CC8CLED, CC16CLED
end end always @ (Q or UP) begin if ((Q == TERMINAL_COUNT_UP && UP) || (Q == TERMINAL_COUNT_DOWN && !UP)) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end
288
CC8RE, CC16RE
CC8RE, CC16RE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and Synchronous Reset
CC8RE, CC16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
CC8RE
CE C
Q[7:0] CEO TC
X4288
CC16RE
CE C
Q[15:0] CEO TC
CC8RE and CC16RE are, respectively, 8- and 16-bit (stage), synchronous resettable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs and CE are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, with Low outputs, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 CE X 0 C X Qz Q0 0 No Chg Outputs TC 0 No Chg CEO 0 0
X4283
289
CC8RE, CC16RE
z = 7 for CC8RE; z = 15 for CC16RE TC = QzQ(z-1)Q(z-2)...Q0CE CEO = TCCE
290
CC8RE, CC16RE
TC CEO AND2 Q[7:0]
O MUXCY Q7 S 0 DI 1 CI LI CI C7 LO XORCY INV RLOC=R0C0.S1 0 DI 1 CI LI CI C6 LO MUXCY_L Q5 S 0 DI 1 CI LI CI C5 LO MUXCY_L Q4 S 0 DI 1 CI LI CI C4 LO MUXCY_L Q3 S 0 DI 1 CI LI CI C3 LO MUXCY_L Q2 S 0 DI 1 CI LI CI C2 LO MUXCY_L Q1 S 0 DI 1 CI LI CI C1 MUXCY_L Q0 S 0 DI 1 CI LI CI XORCY GND VCC C0 INV O LO RLOC=R3C0.S1 XORCY INV RLOC=R3C0.S1 RLOC=R2C0.S0 CE Q1 TQ1 Q Q1 R XORCY INV RLOC=R2C0.S1 XORCY INV O RLOC=R2C0.S1 RLOC=R1C0.S0 CE Q3 O CE_M3 TQ3 Q Q3 R XORCY INV O RLOC=R1C0.S1 XORCY INV O TQ5 Q5 RLOC=R1C0.S1 RLOC=R0C0.S0 CE Q5 O CE_M5 TQ5 Q Q5 R XORCY INV O TQ7 Q7 RLOC=R0C0.S1 VCC
FMAP
M2_1
D0 D1 S0 CEB7 O CE_M7 CE Q7 I4 I3 I2 I1 RLOC=R0C0.S0 CLR RLOC=R0C0.S0 CE Q6 TQ6 Q Q6 R R_TQ7 O
FDCE
R_TQ7 AND2B1 D CE C Q Q7
TQ7 R
MUXCY_L Q6 S
FMAP
I4 I3 I2 I1 RLOC=R0C0.S0 O R_TQ6
M2_1
O TQ6 Q6 D0 D1 S0 CEB6 AND2B1 O CE_M6
FDCE
R_TQ6 D CE C CLR
FMAP
M2_1
D0 D1 S0 CEB5 I4 I3 I2 I1 RLOC=R1C0.S0 CLR RLOC=R1C0.S0 CE Q4 O CE_M4 TQ4 Q Q4 R R_TQ5 O
FDCE
R_TQ5 AND2B1 D CE C
FMAP
I4 I3 I2 I1 RLOC=R1C0.S0 R_TQ4 O
M2_1
TQ4 Q4 D0 D1 S0 CEB4 AND2B1
FDCE
R_TQ4 D CE C CLR
FMAP
I4 I3 I2 I1 RLOC=R2C0.S0 CLR RLOC=R2C0.S0 CE Q2 O CE_M2 TQ2 Q Q2 R R_TQ3 O
M2_1
TQ3 Q3 D0 D1 S0 CEB3 AND2B1 R_TQ3
FDCE
D CE C
FMAP
M2_1
O TQ2 Q2 D0 D1 S0 CEB2 AND2B1
FDCE
R_TQ2 D CE C CLR
FMAP
I4 I3 I2 I1 RLOC=R3C0.S0 CLR RLOC=R3C0.S0 CE Q0 O CE_M0 TQ0 Q Q0 R R_TQ1 O
M2_1
O TQ1 Q1 D0 D1 S0 CEB1 AND2B1 O CE_M1 R_TQ1
FDCE
D CE C
FMAP
M2_1
TQ0 Q0 D0 D1 S0 CEB0 AND2B1 R_TQ0
FDCE
D CE C CLR RLOC=R3C0.S0
CE R C GND
X8893
CC8RE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
291
CC8RE, CC16RE
TC
CEO AND2 Q[7:0]
O Q7 S MUXCY 0 1 DI CI LI O CI Q7 XORCY C7 LO Q6 S MUXCY_L 0 1 DI CI RLOC=X1Y3 INV S0 AND2B1 CEB7 D1 TQ7 D0 O RLOC=X1Y3
VCC
FMAP
CE
M2_1
CE_M7 R_TQ7 D CE C
I4 I3 O I2 I1 RLOC=X0Y3 R_TQ7
FDCE
Q Q7
Q7 TQ7 R
CLR
FMAP
RLOC=X0Y3 CE LI O CI Q6 XORCY S0 D1 AND2B1 CEB6 TQ6 D0 O
M2_1
CE_M6 R_TQ6 D CE C
I4 I3 O I2 I1 RLOC=X0Y3 R_TQ6
FDCE
Q Q6
Q6 TQ6 R
C6 LO Q5 S MUXCY_L 0 1 DI CI RLOC=X1Y2
INV
CLR
RLOC=X0Y3 CE LI O CI Q5 XORCY D1 S0 INV RLOC=X1Y2 AND2B1 CEB5 TQ5 D0 O
FMAP
I4 I3 O I2 I1 RLOC=X0Y2 R_TQ5 Q5 TQ5 Q5 R
M2_1
CE_M5 R_TQ5 D CE C
FDCE
Q
C5 LO Q4 S MUXCY_L 0 1 DI CI LI O CI Q4 XORCY C4 LO Q3 S MUXCY_L 0 1 DI CI RLOC=X1Y1 TQ4
CLR
RLOC=X0Y2 CE
FMAP
M2_1
D0 O D1 S0 INV AND2B1 CEB4 CE_M4 R_TQ4 D CE C
FDCE
Q
CLR
RLOC=X0Y2 CE LI O CI Q3 XORCY D1 S0 INV RLOC=X1Y1 AND2B1 CEB3 TQ3 D0 O
FMAP
M2_1
CE_M3 R_TQ3 D CE C
FDCE
Q
C3 LO Q2 S MUXCY_L 0 1 DI CI LI O CI Q2 XORCY C2 LO Q1 S MUXCY_L 0 1 DI CI LI O CI Q1 XORCY C1 LO Q0 S MUXCY_L 0 1 DI CI RLOC=X1Y0 INV TQ1 RLOC=X1Y0 TQ2
CLR
RLOC=X0Y1 CE
FMAP
M2_1
D0 O D1 S0 INV AND2B1 CEB2 CE_M2 R_TQ2 D CE C
FDCE
Q
CLR
RLOC=X0Y1 CE
FMAP
M2_1
D0 O D1 S0 AND2B1 CEB1 CE_M1 R_TQ1 D CE C
FDCE
Q
CLR
RLOC=X0Y0 CE LI O CI Q0 XORCY S0 D1 AND2B1 INV CEB0 TQ0 D0 O
FMAP
M2_1
CE_M0 R_TQ0 D CE C
FDCE
Q
GND VCC C0
CLR
RLOC=X0Y0 CE R C X9312
GND
CC8RE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
292
CC8RE, CC16RE
Usage
VHDL Inference Code

architecture Behavioral of cc8re is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, R) begin if (C'event and C='1') then if (R='1') then Q <= (others => '0'); elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC<='1'; else TC<='0'; end if; end process; CEO<=TC and CE; end Behavioral;

always @(posedge C) begin if (R) Q <= 0; else if (CE) Q <= Q + 1; end always @(Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end
293
CC8RE, CC16RE
always @(TC or CE) begin CEO <= TC & CE; end
294
CD4CE
CD4CE
4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear
CD4CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CD4CE
Q0 Q1 Q2 Q3
CE C
CEO TC
CLR X4369
CD4CE is a 4-bit (stage), asynchronous clearable, cascadable binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when clock enable (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.
X2355
Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage.
295
CD4CE
When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse to the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0
CEO = TCCE
Outputs C X X X Q3 0 Inc No Chg 1 Q2 0 Inc No Chg 0 Q1 0 Inc No Chg 0 Q0 0 Inc No Chg 1 TC 0 TC TC 1 CEO 0 CEO 0 1
CE X 1 0 1
TC = Q3!Q2!Q1Q0
FDCE
D0 INV D CE C CLR Q0 Q Q0
AX1 AND2B1 XOR2
FDCE
D1 D CE C CLR Q1 Q Q1
AX2 AND2 AO3B AND3 XOR2
FDCE
AO3A AND2 OR2
OX3 XOR2
FDCE
C CLR AND4B2 CE AND2 X7784
TC
CEO
CD4CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
296
CD4CE
VCC
CE
AND2
CLR C Q0 Q1 Q2 Q3
AND3B2
FDC
D OR3 AND4B3 C CLR Q
Q0
AND5B2
FDC Q0
AND4B2 D Q
Q2 CEO
AND2B1 OR4 AND4B2

AND4B2
CLR
Q2
AND5B2
FDC
D OR3
AND4B2
Q1
AND2B1 AND4B2
TC
CLR
Q1
AND2B1 AND5B1
FDC
D
OR3 AND5B3
Q3
CLR
Q3
AND2B1
X7629
CD4CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
For HDL, this design element can be inferred.
VHDL Inference Code

architecture Behavioral of cd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C'event and C = '1') then if (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1;
297
CD4CE
end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC_INT <= '1'; else TC_INT <= '0'; end if; end process; TC <= TC; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end
298
CD4CLE
CD4CLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous Clear
CD4CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D0 D1 D2 D3 L CE C
CD4CLE
Q0 Q1 Q2 Q3
CEO TC
CLR
X4370
CD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, binarycoded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition. The Q outputs increment when clock enable input (CE) is High during the Low- to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.
0 1 2 3 4
X2355
Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the
299
CD4CLE
clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 1 0 1 D3 D0 X D3 D0 X X X C X X X Q3 0 D3 Inc No Chg 1 Q2 0 D2 Inc No Chg 0 Outputs Q1 0 D1 Inc No Chg 0 Q0 0 D0 Inc No Chg 1 TC 0 TC TC TC 1 CEO 0 CEO CEO 0 1
TC = Q3!Q2!Q1Q0 CEO = TCCE

FTCLEX
D0 L D L Q T CE C CLR Q0
C CLR
Q0
FTCLEX
D1 T1 AND2B1 OR_CE_L OR2 D2 D L Q T CE C CLR Q1 Q1
FTCLEX
D L Q T CE C CLR Q2
Q2
FTCLEX
D3 T2 AND2 TQ03 AND2 AND2 TQ2 OR2 T3 D L Q T CE C CLR Q3 Q3 TC
AND4B2 CE AND2 CEO
X7785
CD4CLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
300
CD4CLE
Q0 Q1 Q2 Q3
INV INV AND5B4 INV AND6
FDC
AND4B3 OR4 AND3B2 D C Q
AND5B2
CEO
AND5B3
CLR D0
AND2 AND5B3 OR5
Q0
D C
FDC
Q
AND4B2
TC
CLR
Q2
AND3B2 AND5B3
D2
AND2
FDC
AND5B3 OR4 AND3B2
INV Q
CLR Q1
INV AND6
D1
AND2
INV INV INV INV

AND6 OR4 AND3B2
VCC
FDC
D Q
CE L
CLR Q3
GRD
D3
AND2
C CLR
X7628
CD4CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cd4cle is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C'event and C = '1') then if (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then
301
CD4CLE
Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC_INT <= '1'; else TC_INT <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @(TC or CE) begin CEO <= TC && CE; end
302
CD4RE
CD4RE
4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset
CD4RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CD4RE
Q0 Q1 Q2 Q3
CE C
CEO TC
X4371
CD4RE is a 4-bit (stage), synchronous resettable, cascadable binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.
X2355
Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
303
CD4RE
cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0
CEO = TCCE
Outputs C X X Q3 0 Inc No Chg 1 Q2 0 Inc No Chg 0 Q1 0 Inc No Chg 0 Q0 0 Inc No Chg 1 TC 0 TC TC 1 CEO 0 CEO 0 1
CE X 1 0 1
TC = Q3!Q2!Q1Q0
FDRE
D0 INV D CE C R Q0 Q Q0
AX1 AND2B1
FDRE
D1 XOR2 D CE C R Q1 Q Q1
AX2 AND2 A03B
FDRE
AND3
AO3A OR2 AND2
OX3
FDRE
C R CE AND4B2 AND2
TC
CEO
X9315
CD4RE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
304
CD4RE
R Q0 Q1 Q2 Q3
INV
AND5B4
FD
D OR3 AND4B3 C Q
INV INV
AND6
CEO FD Q0
AND5B3
Q
AND5B2
AND3B2 OR4 C
Q2
AND5B3
TC
AND4B2
AND5B3
FD
D OR3 AND5B3 C Q INV
AND3B2
Q1
INV AND3B2 AND6
INV INV INV INV VCC

AND6 OR3
FD
D Q
Q3 CE
AND2
AND3B2
X7627
CD4RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cd4re is begin process (C) begin if (C'event and C = '1') then if (R = '1') then Q <= "0000"; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if;
305
CD4RE
end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @(TC or CE) begin CEO <= TC && CE; end
306
CD4RLE
CD4RLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset
CD4RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D0 D1 D2 D3 L CE C
CD4RLE
Q0 Q1 Q2 Q3
CEO TC
R X4372
CD4RLE is a 4-bit (stage), synchronous loadable, resettable, binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.
0 1 2 3 4
X2355
Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When
307
CD4RLE
cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 L X 1 0 0 0 CE X X 1 0 1 D3 D0 X D3 D0 X X X C X X Q3 0 D3 Inc No Chg 1 Q2 0 D Inc No Chg 0
Outputs Q1 0 D Inc No Chg 0 Q0 0 D0 Inc No Chg 1 TC 0 TC TC TC 1 CEO 0 CEO CEO 0 1
308
CD4RLE
FTRSLE
D0 L D S L T Q CE C R Q0
C R
Q0
FTRSLE
D1 T1 AND2B1 D S L T Q CE C R Q1 Q1
FTRSLE
D2 D S L T Q CE C R Q2
Q2
FTRSLE
D3 T2 AND2 TQ03 AND2 AND2 TQ2 OR2 T3 D S L T Q CE C R Q3 Q3 TC
AND4B2 CE AND2 CEO
GND
X7787
CD4RLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
309
CD4RLE
Q1 Q2 Q3
AND2
INV INV INV OR2 INV INV AND5B2 AND6
CEO
D AND4B2 Q
TC
FD
AND5B4 OR4 C D
Q0
AND4B3
D0
AND3B1
INV INV INV INV
AND6
INV INV INV INV AND6 OR4 C D
FD
Q
Q1
AND4B3
D1
AND3B1
INV INV
INV INV
AND7
INV INV INV INV AND6
FD
INV INV INV INV AND6 D OR5 C Q
Q2
AND4B3
D2
AND3B1
INV INV
INV
AND7
INV INV INV INV INV AND7 OR4 C
FD
D Q
Q3
AND4B3
CD4RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
310
CD4RLE
Usage
For HDL, this design element can be inferred but not instantiated.
VHDL Inference Code

architecture Behavioral of cd4rle is begin process (C) begin if (C'event and C = '1') then if (R = '1') then Q <= "0000"; elsif (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000;
311
CD4RLE
else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end
312
CDD4CE
CDD4CE
4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear
CDD4CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
CDD4CE
Q0 Q1 Q2 Q3
CE C
CEO TC
CLR
X9734
CDD4CE is a 4-bit (stage), asynchronous clearable, cascadable dual edge triggered Binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when clock enable (CE) is High during the Low-to-High and High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse to the PRLD global net.
Inputs CLR 1 0 0 0 CE X 1 1 0 C X X Q3 0 Inc Inc No Chg Q2 0 Inc Inc No Chg
Outputs Q1 0 Inc Inc No Chg Q0 0 Inc Inc No Chg TC 0 TC TC TC CEO 0 CEO CEO 0
313
CDD4CE
Inputs CLR 0
CEO = TCCE
Outputs C X Q3 1 Q2 0 Q1 0 Q0 1 TC 1 CEO 1
CE 1
TC = Q3!Q2!Q1Q0
VCC
CE AND2 CLR C Q0 Q1 Q2 Q3
AND3B2
FDDC
D OR3 AND4B3 C CLR Q0 AND2B1 Q Q0
AND5B2
FDDC
AND4B2 D Q Q2 CEO
OR4 AND4B2 AND4B2
CLR Q2 AND5B2
FDDC
D OR3 AND4B2 C CLR Q1 AND2B1 AND5B1 Q Q1 AND2B1 AND4B2
TC
FDDC
D OR3 AND5B3 C CLR Q3 AND2B1
X9735
Q3
CDD4CE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cdd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C'event) then if (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110";
314
CDD4CE
elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end
315
CDD4CE
316
CDD4CLE
CDD4CLE
4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear
CDD4CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D0 D1 D2 D3 L CE C
CDD4CLE
Q0 Q1 Q2 Q3
CEO TC
CLR
X9736
CDD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, dual edge triggered Binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High and High-to-Low clock (C) transitions. The Q outputs increment when clock enable input (CE) is High during the Low- to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 L X 1 1 0 CE X X X 1 D3 D0 X D3 D0 D3 D0 X C X Q3 0 D3 D3 Inc Q2 0 D2 D2 Inc
Outputs Q1 0 D1 D1 Inc Q0 0 D0 D0 Inc TC 0 TC TC TC CEO 0 CEO CEO CEO
317
CDD4CLE
Inputs CLR 0 0 0 L 0 0 0 CE 1 0 1 D3 D0 X X X C X X Q3 Inc No Chg 1 Q2 Inc No Chg 0
Outputs Q1 Inc No Chg 0 Q0 Inc No Chg 1 TC TC TC 1 CEO CEO 0 1
Q0 Q1 Q2 Q3
INV INV AND5B4 INV AND6 CEO
FDDC
AND4B3 OR4 AND3B2 D0 AND2 AND5B3 OR5 D C CLR Q0 D C CLR Q2 Q AND5B2 AND5B3
FDDC
Q AND4B2
TC
AND3B2 AND5B3 D2 AND2
FDDC
AND5B3 OR4 AND3B2 D1 AND2 VCC CE L D Q
INV
CLR Q1
INV AND6
INV INV INV INV AND6 OR4 AND3B2 D
FDDC
Q
CLR Q3
GRD C CLR
D3 AND2
X9737
CDD4CLE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cdd4cle is begin process (C, CLR) begin if (CLR = '1') then
318
CDD4CLE
Q <= "0000"; elsif (C'event) then if (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin
319
CDD4CLE
if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end
320
CDD4RE
CDD4RE
4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset
CDD4RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
CDD4RE
Q0 Q1 Q2 Q3
CE C
CEO TC
X9738
CDD4RE is a 4-bit (stage), synchronous resettable, cascadable dual edge triggered binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High or High-to-Low clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 CE X X 1 1 0 C X Q3 0 0 Inc Inc No Chg Q2 0 0 Inc Inc No Chg Outputs Q1 0 0 Inc Inc No Chg Q0 0 0 Inc Inc No Chg TC 0 0 TC TC TC CEO 0 0 CEO CEO 0
321
CDD4RE
Inputs R 0
CEO = TCCE
Outputs C X Q3 1 Q2 0 Q1 0 Q0 1 TC 1 CEO 1
CE 1
TC = Q3!Q2!Q1Q0
R Q0 Q1 Q2 Q3
INV
AND5B4
INV INV
FDD
D OR3 AND4B3 C Q0 AND3B2 Q
AND6
CEO
FDD
AND5B3 D Q AND5B2 OR4 C Q2 AND5B3 TC
AND5B3
AND4B2
FDD
D OR3 AND5B3 C Q1 INV AND3B2 Q INV
AND3B2
AND6
INV INV INV INV VCC AND6 OR3
FDD
D Q
C Q3
CE AND2 AND3B2
X9739
CDD4RE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cdd4re is begin process (C) begin if (C'event) then if (R = '1') then Q <= "0000"; elsif (CE = '1') then if (Q = "1001") then Q <= "0000";
322
CDD4RE
elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end
323
CDD4RE
always @ (TC or CE) begin CEO <= TC && CE; end
324
CDD4RLE
CDD4RLE
4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset
CDD4RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D0 D1 D2 D3 L CE C
CDD4RLE
Q0 Q1 Q2 Q3
CEO TC
R
X9740
CDD4RLE is a 4-bit (stage), synchronous loadable, resettable, dual edge triggered binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High or High-to-Low clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High and High-to-Low clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 L X X 1 1 0 CE X X X X 1 D3 D0 X X D3 D0 D3 D0 X C Q3 0 0 D3 D3 Inc Q2 0 0 D2 D2 Inc Outputs Q1 0 0 D1 D1 Inc Q0 0 0 D0 D0 Inc TC 0 0 TC TC TC CEO 0 0 CEO CEO CEO
325
CDD4RLE
Inputs R 0 0 0 L 0 0 0 CE 1 0 1 D3 D0 X X X C X X Q3 Inc No Chg 1 Q2 Inc No Chg 0
Outputs Q1 Inc No Chg 0 Q0 Inc No Chg 1 TC TC TC 1 CEO CEO 0 1
326
CDD4RLE
C Q0 VCC Q1 Q2 CE AND2 CEO Q3
R L OR2
INV INV INV INV INV AND5B2 AND6
GND AND4B2 Q
TC
FDD
AND5B4 OR4 C Q0 AND4B3 D0 AND3B1 D
INV INV INV INV
AND6
INV INV INV INV AND6 OR4 C D
FDD
Q
Q1 AND4B3 D1 AND3B1
INV INV
INV INV
AND7
INV INV INV INV AND6
FDD
INV INV INV INV AND6 Q2 D OR5 C Q
AND4B3 D2 AND3B1
INV INV
INV
AND7
INV INV INV INV INV AND7 OR4 C Q3 AND4B3 D3 AND3B1

X9741
FDD
D Q
CDD4RLE Implementation CoolRunner-II
Usage
327
CDD4RLE
VHDL Inference Code

architecture Behavioral of cdd4rle is begin process (C) begin if (C'event) then if (R = '1') then Q <= "0000"; elsif (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100;
328
CDD4RLE
else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end
329
CDD4RLE
330
CJ4CE, CJ5CE, CJ8CE
CJ4CE, CJ5CE, CJ8CE

4-, 5-, 8-Bit Johnson Counters with Clock Enable and Asynchronous Clear
CJ4CE, CJ5CE, CJ8CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CJ4CE
Q0 Q1 Q2 Q3
CE C
CLR
X4112
CJ4CE, CJ5CE, and CJ8CE are clearable Johnson/shift counters. The asynchronous clear (CLR) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero, independent of clock (C) transitions. The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High during the Low-to-High clock transition. Clock transitions are ignored when CE is Low. For CJ4CE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operation. For CJ5CE, the Q4 output is inverted and fed back to input Q0. For CJ8CE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. CJ4CE Truth Table
Inputs CLR 1 0 0 CE X 0 1 C X X Q0 0 No Chg !q3 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2
CJ5CE
Q0 Q1 Q2
CE C
Q3 Q4
CLR
X4114
CJ8CE
CE C
Q[7:0]
CLR
X4118
q = state of referenced output one setup time prior to active clock transition
331
CJ4CE, CJ5CE, CJ8CE
CJ5CE Truth Table

Inputs CLR 1 0 0 CE X 0 1 C X X Q0 0 No Chg !q4 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2 Q4 0 No Chg q3
CJ8CE Truth Table

Inputs CLR 1 0 0 CE X 0 1 C X X Q0 0 No Chg !q7 Outputs Q1 Q7 0 No Chg q0 q6
Q[7:0] Q7
FDCE FDCE
Q7B INV D CE C CLR Q0 Q Q0 Q3 D CE C CLR Q4 Q Q4
FDCE FDCE
D CE C CLR Q1 Q Q1 D CE C CLR Q5 Q Q5
FDCE FDCE
FDCE FDCE
D CE C CLR Q3 CE C CLR X7789 Q Q3 D CE C CLR Q7 Q Q7
CJ8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
332
CJ4CE, CJ5CE, CJ8CE
VHDL Inference Code

architecture Behavioral of cj4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= (others => '0'); elsif (C'event and C = '1') then if (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else begin if (CE) begin Q[0] <= !Q[WIDTH-1]; Q[WIDTH-1:1] <= Q[WIDTH-2:0]; end end end
333
CJ4CE, CJ5CE, CJ8CE
334
CJ4RE, CJ5RE, CJ8RE
CJ4RE, CJ5RE, CJ8RE

4-, 5-, 8-Bit Johnson Counters with Clock Enable and Synchronous Reset
CJ4RE, CJ5RE, CJ8RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CJ4RE
Q0 Q1 Q2 Q3
CE C
X4113
CJ4RE, CJ5RE, and CJ8RE are resettable Johnson/shift counters. The synchronous reset (R) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero during the Low-to-High clock (C) transition. The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High during the Low-to-High clock transition. Clock transitions are ignored when CE is Low. For CJ4RE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operations. For CJ5RE, the Q4 output is inverted and fed back to input Q0. For CJ8RE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. CJ4RE Truth Table
Inputs R 1 0 0 CE X 0 1 C X Q0 0 No Chg q3 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2
CJ5RE
Q0 Q1 Q2
CE C
Q3 Q4
X4115
CJ8RE
CE C
Q[7:0]
X4119
335
CJ4RE, CJ5RE, CJ8RE
CJ5RE Truth Table

Inputs R 1 0 0 CE X 0 1 C X Q0 0 No Chg q4 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2 Q4 0 No Chg q3
CJ8RE Truth Table

Inputs R 1 0 0 CE X 0 1 C X Q0 0 No Chg q7 Outputs Q1 Q7 0 No Chg q0 q6
Q[7:0] Q7
FDRE FDRE
Q7B INV D CE C R Q0 Q Q0 Q3 D CE C R Q4 Q Q4
FDRE FDRE
D CE C R Q1 Q Q1 D CE C R Q5 Q Q5
FDRE FDRE
FDRE FDRE
D CE C R Q3 CE C R X7790 Q Q3 D CE C R Q7 Q Q7
CJ8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
336
CJ4RE, CJ5RE, CJ8RE
Usage
VHDL Inference Code

architecture Behavioral of cj4re is begin process (C) begin if (C'event and C = '1') then if (R = '1') then Q <= (others => '0'); elsif (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else begin if (CE) begin Q[0] <= !Q[WIDTH-1]; Q[WIDTH-1:1] <= Q[WIDTH-2:0]; end end end
337
CJ4RE, CJ5RE, CJ8RE
338
CJD4CE, CJD5CE, CJD8CE

4-, 5-, 8-Bit Dual Edge Triggered Johnson Counters with Clock Enable and Asynchronous Clear
CJD4CE, CJD5CE, CJD8CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
CJD4CE
Q0 Q1 CE C Q2 Q3
CLR
X9742
CJD4CE, CJD5CE, and CJD8CE are dual edge triggered clearable Johnson/shift counters. The asynchronous clear (CLR) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero, independent of clock (C) transitions. The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. Clock transitions are ignored when CE is Low. For CJD4CE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operations. For CJD5CE, the Q4 output is inverted and fed back to input Q0. For CJD8CE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. CJD4CE Truth Table
CJD5CE
Q0 Q1 Q2
CE C
Q3 Q4
CLR
X9743
CJD8CE
CE C
Q[7:0]
Inputs CLR
X9744
Outputs C X X Q0 0 No Chg !q3 !q3 Q1 0 No Chg q0 q0 Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2
CE X 0 1 1
CLR
1 0 0 0
339
CJD5CE Truth Table

Inputs CLR 1 0 0 0 CE X 0 1 1 C X X Q0 0 No Chg !q4 !q4 Q1 0 No Chg q0 q0 Outputs Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2 Q4 0 No Chg q3 q3
CJD8CE Truth Table

Inputs CLR 1 0 0 0 CE X 0 1 1 C X X Q0 0 No Chg !q7 !q7 Outputs Q1 Q7 0 No Chg q0 q6 q0 q6
Usage
VHDL Inference Code

architecture Behavioral of cjd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= (others => '0'); elsif (C'event) then if (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;
340

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q_INT <= 0; else begin if (CE) begin Q_INT[0] <= !Q_INT[WIDTH-1]; Q_INT[WIDTH-1:1] <= Q_INT[WIDTH-2:0]; end end end always @ (Q_INT) begin Q <= Q_INT; end
341
342
CJD4RE, CJD5RE, CJD8RE

4-, 5-, 8-Bit Dual Edge Triggered Johnson Counters with Clock Enable and Synchronous Reset
CJD4RE, CJD5RE, CJD8RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
CJD4RE
Q0 Q1 Q2 Q3
CE C
X9745
CJD4RE, CJD5RE, and CJD8RE are resettable dual edge triggered Johnson/shift counters. The synchronous reset (R) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero during the Low-to-High and High-to-Low clock (C) transition. The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. Clock transitions are ignored when CE is Low. For CJD4RE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operations. For CJD5RE, the Q4 output is inverted and fed back to input Q0. For CJD8RE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. CJD4RE Truth Table
CJD5RE
Q0 Q1 Q2
CE C
Q3 Q4
X9746
CJD8RE
CE C
Q[7:0]
Inputs R 1 CE X 0 1 1 C X Q0 0 No Chg q3 q3 Q1 0
Outputs Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2
X9747
0 0 0
No Chg q0 q0
343
CJD5RE Truth Table

Inputs R 1 0 0 0 CE X 0 1 1 C X Q0 0 No Chg q4 q4 Q1 0 No Chg q0 q0 Outputs Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2 Q4 0 No Chg q3 q3
CJD8RE Truth Table

Inputs R 1 1 0 0 0 CE X X 0 1 1 C X Q0 0 0 No Chg q7 q7 Outputs Q1 Q7 0 0 No Chg q0 q6 q0 q6
Usage
VHDL Inference Code

architecture Behavioral of cjd4re is begin process (C) begin if (C'event) then if (R = '1') then Q <= (others => '0'); elsif (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;
344

always @ (posedge C or negedge C) begin if (R) Q <= 0; else begin if (CE) begin Q[0] <= !Q[WIDTH-1]; Q[WIDTH-1:1] <= Q[WIDTH-2:0]; end end end
345
346
CLK_DIV2,4,6,8,10,12,14,16
CLK_DIV2,4,6,8,10,12,14,16
Global Clock Divider
CLK_DIV2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLK_DIV4, CLK_DIV6, CLK_DIV8, CLK_DIV10, CLK_DIV12, CLK_DIV14, CLK_DIV16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLKIN
CLKDV
The CLK_DIV2,4,6,8,10,12,14,16 Global Clock Dividers divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 orXC2C64. The CLKIN input can only be connected to the device gclk<2> pin. The duty cycle of the CLKDV output is 50-50. The CLKDV output is reset low by power-on reset circuitry.
Usage
This design element is supported for schematics and instantiation but not for inference.

-- Component Declaration for CLK_DIVn should be placed -- after architecture statement but before begin keyword component CLK_DIVn port (CLKDV : out STD_ULOGIC; CLKIN : in STD_ULOGIC); end component; -- Component Instantiation for CLK_DIVn should be placed -- in architecture after the begin keyword
347
CLK_DIV2,4,6,8,10,12,14,16
CLK_DIVn_INSTANCE_NAME : CLK_DIVn port map (CLKDV => user_CLKDV, CLKIN => user_CLKIN);

CLK_DIVn CLK_DIVn_instance_name (.CLKDV (user_CLKDV), .CLKIN (user_CLKIN));
348
CLK_DIV2,4,6,8,10,12,14,16R
CLK_DIV2,4,6,8,10,12,14,16R
Global Clock Divider with Synchronous Reset
CLK_DIV2R Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLK_DIV4R, CLK_DIV6R, CLK_DIV8R, CLK_DIV10R, CLK_DIV12R, CLK_DIV14R, CLK_DIV16R Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLKIN CLKDV CDRST
The CLK_DIV2,4,6,8,10,12,14,16R Global Clock Dividers with Synchronous Reset divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN and CDRST inputs can only be connected to the device gclk<2> and CDRST pins. The duty cycle of the CLKDV output is 50-50. The CDRST input is an active High synchronous reset. If CDRST is input High when the CLKDV output is High, the CLKDV output remains High to complete the last clock pulse, and then goes Low. The CLKDV output is reset low by power-on reset circuitry.
Usage
For HDL, these design elements are supported for instantiation but not inference.

-- Component Declaration for CLK_DIVnR should be placed -- after architecture statement but before begin keyword component CLK_DIVnR port (CLDV : out STD_ULOGIC; CDRST : in STD_ULOGIC;
349
CLK_DIV2,4,6,8,10,12,14,16R
CLKIN : in STD_ULOGIC); end component; -- Component Instantiation for CLK_DIVnR should be placed -- in architecture after the begin keyword CLK_DIVnR_INSTANCE_NAME : port map (CLKDV => CDRST => CLKIN => CLK_DIVnR user_CLKDV, user_CDRST, user_CLKIN);

CLK_DIVnR CLK_DIVnR_instance_name (.CLKDV (user_CLKDV), .CDRST (user_CDRST), .CLKIN (user_CLKIN));
350
CLK_DIV2,4,6,8,10,12,14,16RSD
CLK_DIV2,4,6,8,10,12,14,16RSD
Global Clock Divider with Synchronous Reset and Start Delay
CLK_DIV2RSD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLK_DIV4RSD, CLK_DIV6RSD, CLK_DIV8RSD, CLK_DIV10RSD, CLK_DIV12RSD, CLK_DIV14RSD, CLK_DIV16RSD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLKIN CLKDV CDRST
The CLK_DIV2,4,6,8,10,12,14,16 Global Clock Dividers with Synchronous Reset and Start Delay divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN and CDRST inputs can only be connected to the device gclk<2> and CDRST pins. The duty cycle of the CLKDV output is 50-50. The CDRST input is an active High synchronous reset. If CDRST is input High when the CLKDV output is High, the CLKDV output remains High to complete the last clock pulse, and then goes Low. The start delay function delays the start of the CLKDV output by (n + 1) clocks, where n is the divisor for the clock divider. The CLKDV output is reset low by power-on reset circuitry.
Usage
For HDL, these design elements are supported for instantiation but not inference.

-- Component Declaration for CLK_DIVnRSD should be placed -- after architecture statement but before begin keyword
351
CLK_DIV2,4,6,8,10,12,14,16RSD
component CLK_DIVnRSD port (CLDV : out STD_ULOGIC; CDRST : in STD_ULOGIC; CLKIN : in STD_ULOGIC); end component; -- Component Instantiation for CLK_DIVnRSD should be placed -- in architecture after the begin keyword CLK_DIVnRSD_INSTANCE_NAME port map (CLKDV CDRST CLKIN : CLK_DIVnRSD => user_CLKDV, => user_CDRST, => user_CLKIN);

CLK_DIVnRSD CLK_DIVnRSD_instance_name (.CLKDV (user_CLKDV), .CDRST (user_CDRST), .CLKIN (user_CLKIN));
352
CLK_DIV2,4,6,8,10,12,14,16SD
CLK_DIV2,4,6,8,10,12,14,16SD
Global Clock Divider with Start Delay
CLK_DIV2SD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLK_DIV4SD, CLK_DIV6SD, CLK_DIV8SD, CLK_DIV10SD, CLK_DIV12SD, CLK_DIV14SD, CLK_DIV16SD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive
CLKIN
CLKDV
The CLK_DIV2,4,6,8,10,12,14,16SD Global Clock Dividers with Start Delay divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN input can only be connected to the device gclk<2> pin. The duty cycle of the CLKDV output is 50-50. The start delay function delays the CLKDV output (n + 1) clocks, where n is the divisor for the clock divider. The CLKDV output is reset low by power-on reset circuitry.
Usage
This design element is supported for schematics and instantiation but not for inference.

-- Component Declaration for CLK_DIVnSD should be placed -- after architecture statement but before begin keyword component CLK_DIVnSD port (CLKDV : out STD_ULOGIC; CLKIN : in STD_ULOGIC); end component;
353
CLK_DIV2,4,6,8,10,12,14,16SD
-- Component Instantiation for CLK_DIVnSD should be placed -- in architecture after the begin keyword CLK_DIVnSD_INSTANCE_NAME : CLK_DIVnSD port map (CLKDV => user_CLKDV, CLKIN => user_CLKIN);

CLK_DIVnSD CLK_DIVnSD_instance_name (.CLKDV (user_CLKDV), .CLKIN (user_CLKIN));
354
CLKDLL
CLKDLL
Clock Delay Locked Loop
CLKDLL Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II * Use CLKDLLE for Spartan-IIE and Virtex-E. Primitive* No Primitive* No No No No
CLKDLL
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV RST LOCKED
CLKDLL is a clock delay locked loop used to minimize clock skew. CLKDLL synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specific range of each other (see The Programmable Logic Data Book for the most current value). The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (see The Programmable Logic Data Book for the most current values). The CLKIN pin must be driven by an IBUFG or a BUFG. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the CLKDLL must be sourced from either the CLK0 or CLK2X outputs of the same CLKDLL. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X output can be used but not both. The CLK0 or CLK2X must be connected to the input of OBUF, an output buffer. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X and CLKDV outputs is always 50-50. The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for just 2ns.
X8678
355
CLKDLL
CLKDLL Outputs
Output CLK0 CLK180 CLK270 CLK2X CLK90 CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0 Clock at 1x CLKIN frequency, shifted 270o with regards to CLK0 Clock at 2x CLKIN frequency, in phase with CLK0 Clock at 1x CLKIN frequency, shifted 90o with regards to CLK0 Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. CLKDLL locked Description
Note: See the "PERIOD Specifications on CLKDLLs and DCM" section of the "Xilinx Constraints P" chapter in the Constraints Guide for additional information on using the TNM,
TNM_NET, and PERIOD attributes with CLKDLL components.
Usage
This component is generally instantiated in the code as it can not be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool's documentation. Generally, global buffers (IBUFG, BUFG) are instantiated with the CLKDLL component to construct the proper clocking circuit. See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the Xilinx Databook for more information on using the CLKDLL component.

-- Component Declaration for CLKDLL should be placed -- after architecture statement but before begin keyword
component CLKDLL -- synthesis translate_off generic (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0) DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLK270 : out STD_ULOGIC; CLK2X : out STD_ULOGIC; CLK90 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; LOCKED : out STD_ULOGIC;
356
CLKDLL
CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; RST : in STD_ULOGIC); end component;
-- Component Attribute specification for CLKDLL -- should be placed after architecture declaration but -- before the begin keyword
attribute CLKDV_DIVIDE : real; attribute DUTY_CYCLE_CORRECTION : boolean; attribute STARTUP_WAIT : boolean;
attribute CLKDV_DIVIDE of CLKDLL_instance_name: label is 2.0; -- 1.5,2,2.5,3,4, 5, 8, 16 are valid for CLKDV_DIVIDE attribute DUTY_CYCLE_CORRECTION of CLKDLL_instance_name: label is "TRUE"; -- TRUE, FALSE are valid for DUTY_CYCLE_CORRECTION attribute STARTUP_WAIT of CLKDLL_instance_name: label is "FALSE"; -(TRUE,FALSE)
-- Component Instantiation for CLKDLL should be placed -- in architecture after the begin keyword
CLKDLL_INSTANCE_NAME : CLKDLL -- synthesis translate_off generic map (CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) STARTUP_WAIT => boolean_value); -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLK270 => user_CLK270, CLK2X => user_CLK2X, CLK90 => user_CLK90, CLKDV => user_CLKDV,
357
CLKDLL
LOCKED => user_LOCKED, CLKFB => user_CLKFB, CLKIN0 => user_CLKIN, RST => user_RST);

CLKDLL CLKDLL_instance_name (.CLK0 (user_CLK0), .CLK180 (user_CLK180), .CLK270 (user_CLK270), .CLK2X (user_CLK2X), .CLK90 (user_CLK90), .CLKDV (user_CLKDV), .LOCKED (user_LOCKED), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .RST (user_RST));
defparam CLKDLL_instance_name.CLKDV_DIVIDE = integer_value; //(1.5,2,2.5,3,4,5,8,16) defparam CLKDLL_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;// (TRUE, FALSE) defparam CLKDLL_instance_name.STARTUP_WAIT = boolean_value; // (TRUE, FALSE) Note: Additional syntax may be necessary in order to pass the CLKDLL attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

STARTUP_WAIT, DUTY_CYCLE_CORRECTION, CLKDV_DIVIDE and LOC.
358
CLKDLLE
CLKDLLE
Virtex-E Clock Delay Locked Loop
CLKDLLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No Primitive* No No No No
* Supported for Spartan-IIE and Virtex-E devices only.
CLKDLLE CLK0 CLKIN CLKFB CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV RST LOCKED
CLKDLLE is a clock delay locked loop used to minimize clock skew for Virtex-E devices. CLKDLLE synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specific range of each other (see The Programmable Logic Data Book for the most current value). The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (see The Programmable Logic Data Book for the most current values). The CLKIN pin must be driven by an IBUFG or a BUFG. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG input can only be connected to the CLK0 or CLK2X output of CLKDLLE. The BUFG connected to the CLKFB input of the CLKDLLE must be sourced from either the CLK0 or CLK2X outputs of the same CLKDLLE. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X output can be used but not both. The CLK0 or CLK2X must be connected to the input of OBUF, an output buffer. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X, CLK2X180, and CLKDV outputs is always 50-50. The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. The master reset input (RST) resets CLKDLLE to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for just 2ns.
X9400
359
CLKDLLE
CLKDLLE Outputs
Output CLK0 CLK180 CLK270 CLK2X CLK2X180 CLK90 CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLK0 frequency, shifted 180o with regards to CLK0 Clock at 1x CLK0 frequency, shifted 270o with regards to CLK0 Clock at 2x CLK0 frequency, in phase with CLK0 Clock at 1x CLK2X frequency shifted 180o with regards to CLK2X Clock at 1x CLK0 frequency, shifted 90o with regards to CLK0 Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. CLKDLLE locked. CLKIN and CLKFB synchronized. Description
Usage
This component is generally instantiated in the code as it cannot be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool documentation. Generally, global buffers (IBUFG, BUFG) are instantiated with the CLKDLLE component to construct the proper clocking circuit. See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the Xilinx Databook for more information on using the CLKDLLE component.

-- Component Declaration for CLKDLLE should be placed -- after architecture statement but before begin keyword component CLKDLLE -- synthesis translate_off generic (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0) DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) STARTUP_WAIT :boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLK270 : out STD_ULOGIC; CLK2X : out STD_ULOGIC; CLK2X180: out STD_ULOGIC; CLK90 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; LOCKED : out STD_ULOGIC; CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; RST : in STD_ULOGIC); end component; -- Component Attribute specification for CLKDLLE -- should be placed after architecture declaration but -- before the begin keyword attribute CLKDV_DIVIDE : real;
360
CLKDLLE
attribute DUTY_CYCLE_CORRECTION : boolean; attribute STARTUP_WAIT : boolean; attribute CLKDV_DIVIDE of CLKDLLE_instance_name: label is 2.0; -- (1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.5, 8.0, 9.0, 10.0, 11.0, -- 12.0, 13.0, 14.0, 15.0, 16.0) are valid for CLKDV_DIVIDE attribute DUTY_CYCLE_CORRECTION of CLKDLLE_instance_name: label is TRUE; -- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION attribute STARTUP_WAIT of CLKDLLE_instance_name: label is FALSE; -- (TRUE,FALSE)
-- Component Instantiation for CLKDLLE should be placed -- in architecture after the begin keyword CLKDLLE_INSTANCE_NAME : CLKDLLE -- synthesis translate_off generic map (CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) STARTUP_WAIT => boolean_value); -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLK270 => user_CLK270, CLK2X => user_CLK2X, CLK2X180 => user_CLK2X, CLK90 => user_CLK90, CLKDV => user_CLKDV, LOCKED => user_LOCKED, CLKFB => user_CLKFB, CLKIN0 => user_CLKIN, RST => user_RST);

CLKDLLE CLKDLLE_instance_name (.CLK0 (user_CLK0), .CLK180 (user_CLK180), .CLK270 (user_CLK270), .CLK2X (user_CLK2X), .CLK2X180 (user_CLK2X180), .CLK90 (user_CLK90), .CLKDV (user_CLKDV), .LOCKED (user_LOCKED), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .RST (user_RST)); defparam CLKDLLE_instance_name.CLKDV_DIVIDE = integer_value; // 1.5,2,2.5,3,4,5,8,16 are valid for CLKDV_DIVIDE defparam CLKDLLE_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;// (TRUE,FALSE) defparam CLKDLLE_instance_name.STARTUP_WAIT = boolean_value; // (TRUE, FALSE)
361
CLKDLLE
Note: Additional syntax may be necessary in order to pass the CLKDLLE attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

STARTUP_WAIT, DUTY_CYCLE_CORRECTION, CLKDV_DIVIDE, and LOC
362
CLKDLLHF
CLKDLLHF
High Frequency Clock Delay Locked Loop
CLKDLLHF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive No Primitive* No No No No
*Use CLKDLLHF for the Virtex-E DLL in HF mode. In LF mode, both the separate CLKDLLE and CLKDLL primitive can be used.
CLKDLLHF
CLKIN CLKFB CLK180 CLK0
CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew. CLKDLLHF synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specific range of each other (see The Programmable Logic Data Book for the most current value). The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (see The Programmable Logic Data Book for the most current values). The CLKIN pin must be driven by an IBUFG or a BUFG. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG input can only be connected to the CLK0 output of CLKDLLHF. The BUFG connected to the CLKFB input of the CLKDLLHF must be sourced from the CLK0 output of the same CLKDLLHF. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Only the CLK0 output can be used. CLK0 must be connected to the input of OBUF, an output buffer. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted output (CLK180) is the same as that of the CLK0 output. The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. The master reset input (RST) resets CLKDLLHF to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for just 2ns.
CLKDV RST LOCKED
X8680
363
CLKDLLHF
CLKDLLHF Outputs
Output CLK0 CLK180 CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0 Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. CLKDLLHF locked Description
Note: See the "PERIOD Specifications on CLKDLLs and DCM" section of the "Xilinx Constraints P" chapter in the Constraints Guide for additional information on using the TNM,
TNM_NET, and PERIOD attributes with CLKDLLHF components.
Usage
This component is generally instantiated in the code as it cannot be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool documentation. Generally, global buffers (IBUFG, BUFG) are instantiated with the CLKDLLHF component to construct the proper clocking circuit. See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the Xilinx Databook for more information on using the CLKDLLHF component.

-- Component Declaration for CLKDLLHF should be placed -- after architecture statement but before begin keyword
component CLKDLLHF -- synthesis translate_off generic (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0) DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; LOCKED : out STD_ULOGIC; CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; RST : in STD_ULOGIC); end component;
-- Component Attribute specification for CLKDLLHF
364
CLKDLLHF
-- should be placed after architecture declaration but -- before the begin keyword
attribute CLKDV_DIVIDE : real; attribute DUTY_CYCLE_CORRECTION : boolean; attribute STARTUP_WAIT : boolean;
attribute CLKDV_DIVIDE of CLKDLLHF_instance_name: label is 2.0; -- (1.5,2,2.5,3,4, 5, 8, 16) are valid for CLKDV_DIVIDE attribute DUTY_CYCLE_CORRECTION of CLKDLLHF_instance_name: label is TRUE; -- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION attribute STARTUP_WAIT of CLKDLLHF_instance_name: label is FALSE; -(TRUE,FALSE)
-- Component Instantiation for CLKDLLHF should be placed -- in architecture after the begin keyword
CLKDLLHF_INSTANCE_NAME : CLKDLLHF -- synthesis translate_off generic map(CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) STARTUP_WAIT => boolean_value); -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLKDV => user_CLKDV, LOCKED => user_LOCKED, CLKFB => user_CLKFB, CLKIN => user_CLKIN, RST => user_RST); Verilog Instantiation Template CLKDLLHF CLKDLLHF_instance_name (.CLK0 (user_CLK0),
365
CLKDLLHF
.CLK180 (user_CLK180), .CLKDV (user_CLKDV), .LOCKED (user_LOCKED), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .RST (user_RST));
defparam CLKDLLHF_instance_name.CLKDV_DIVIDE = integer_value; // 1.5,2,2.5,3,4,5,8,16 are valid for CLKDV_DIVIDE defparam CLKDLLHF_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;// (TRUE,FALSE) defparam CLKDLLHF_instance_name.STARTUP_WAIT = boolean_value; // (TRUE, FALSE) Note: Additional syntax may be necessary in order to pass the CLKDLLHF attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

STARTUP_WAIT DUTY_CYCLE_CORRECTION CLKDV_DIVIDE LOC
366
COMP2, 4, 8, 16
COMP2, 4, 8, 16
2-, 4-, 8-, 16-Bit Identity Comparators
COMP2, COMP4, COMP8, COMP16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
A0 A1 B0 B1
COMP2
EQ
X4122
COMP2, COMP4, COMP8, and COMP16 are, respectively, 2-, 4-, 8-, and 16-bit identity comparators. The equal output (EQ) of the COMP2 2-bit, identity comparator is High when the two words A1 A0 and B1 B0 are equal. EQ is high for COMP4 when A3 A0 and B3 B0 are equal; for COMP8, when A7 A0 and B7 B0 are equal; and for COMP16, when A15 A0 and B15 B0 are equal. Equality is determined by a bit comparison of the two words. When any two of the corresponding bits from each word are not the same, the EQ output is Low.
A0 A1 A2 A3 B0 B1 B2 B3
COMP4
EQ
X4126
A[7:0]
COMP8
EQ
B[7:0]
X4131
A[15:0]
COMP16
EQ
B[15:0]
X4133
367
COMP2, 4, 8, 16
A0 B0 XNOR2 A1 B1 XNOR2 A2 B2 XNOR2 A3 B3 XNOR2 A4 B4 XNOR2 A5 B5 XNOR2 A6 B6 XNOR2 A7 B7 A[7:0] B[7:0] XNOR2
AB0
AB1 AB03 AB2 AND4
AB3 EQ AB4 AND2
AB5 AB47 AB6 AND4
AB7
X7791
COMP8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture behavioral of comp2 is begin process (A, B) begin If (A=B) then EQ <= '1'; else EQ <= '0'; end if; end process; end behavioral;
368
COMP2, 4, 8, 16

always @ begin if (A EQ <= else EQ <= end (A or B) == B) 1; 0;
369
COMP2, 4, 8, 16
370
COMPM2, 4, 8, 16
COMPM2, 4, 8, 16
2-, 4-, 8-, 16-Bit Magnitude Comparators
COMPM2, COMPM4, COMPM8, COMPM16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Macro
A0 A1 B0 B1
COMPM2
GT LT
COMPM2, COMPM4, COMPM8, and COMPM16 are, respectively, 2-, 4-, 8-, and 16bit magnitude comparators that compare two positive binary-weighted words. COMPM2 compares A1 A0 and B1 B0, where A1 and B1 are the most significant bits. COMPM4 compares A3 A0 and B3 B0, where A3 and B3 are the most significant bits. COMPM8 compares A7 A0 and B7 B0, where A7 and B7 are the most significant bits. COMPM16 compares A15 A0 and B15 B0, where A15 and B15 are the most significant bits. The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When the two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparing both outputs with a NOR gate. COMPM2 Truth Table
Inputs Outputs A0 0 1 0 1 0 1 0 1 X X B0 0 0 1 1 0 0 1 1 X X GT 0 1 0 0 0 1 0 0 1 0 LT 0 0 1 0 0 0 1 0 0 1
X4123
A0 A1 A2 A3 B0 B1 B2 B3
COMPM4
GT LT
X4127
A1 0
B1 0 0 0 0 1 1 1 1 0 1
A[7:0]
COMPM8
GT
0 0 0 1 1 1 1
GT LT
B[7:0]
X4132
A[15:0]
COMPM16
1 0
B[15:0]
LT
X4134
371
COMPM2, 4, 8, 16
COMPM4 Truth Table

Inputs A3, B3 A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2, B2 X X A2>B2 A2<B2 A2=B2 A2=B2 A2=A2 A2=B2 A2=B2 A1, B1 X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A0, B0 X X X X X X A0>B0 A0<B0 A0=B0 GT 1 0 1 0 1 0 1 0 0 Outputs LT 0 1 0 1 0 1 0 1 0
COMPM8 Truth Table (also representative of COMPM16)

Inputs A7, B7 A7>B7 A7<B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A6, B6 X X A6>B6 A6<B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A5, B5 X X X X A5>B5 A5<B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A4, B4 X X X X X X A4>B4 A4<B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A3, B3 X X X X X X X X A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2, B2 X X X X X X X X X X A2>B2 A2<B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A1, B1 X X X X X X X X X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A0, B0 X X X X X X X X X X X X X X A0>B0 A0<B0 A0=B0 Outputs GT 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 LT 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
372
COMPM2, 4, 8, 16
EQ_1 XNOR2 A0
LE0_1
LT0_1 OR2 AND4 GTA GT0_1 AND4 OR2 LTA
AND3B1 GE0_1
B0 AND3B1 A1 B1 AND2B1 LT_1 AND2B1 EQ_3 XNOR2 A2 GE2_3 B2 AND3B1 A3 A3 GT_3 AND2B1 LT_3 AND2B1 EQ_5 XNOR2 A4 GE4_5 B4 AND3B1 A5 B5 GT_5 AND2B1 LT_5 AND2B1 EQ_7 XNOR2 A6 GE6_7 B6 AND3B1 A[7:0] B[7:0] A7 B7 GT_7 AND2B1 LT_7 AND2B1 OR2 NOR2 LE6_7 OR2 GT4_5 NOR2 LE4_5 LT4_5 OR2 EQ4_5 OR2 GT2_3 NOR2 LE2_3 LT2_3 GT_1
LTB AND3B1 OR2 EQ2_3 AND3 OR4 GTB AND3
LT
LTC AND2
AND3B1
GTC AND2 OR4
GT
LTD OR2 EQ6_7
AND3B1
GTD
X7793
COMPM8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
373
COMPM2, 4, 8, 16
B0 A0
AND2B1
B1 A1
OR2B1
AND2 OR2
AND2 AND2B1
B2 A2
OR2B1 AND2 AND2B1 OR2
B3 A3
OR2B1 OR2
AND2 AND2B1
B4 A4
OR2B1 OR2
AND2B1
AND2
B5 A5
OR2B1 OR2
AND2 AND2B1
B6 A6
OR2B1 OR2
AND2B1
AND2 LT
B7 A7
OR2B1 OR2
AND2B1
A0 B0
AND2B1
A1 B1
OR2B1
AND2 OR2
AND2 AND2B1
A2 B2
OR2B1 AND2 AND2B1 OR2
A3 B3
OR2B1 OR2
AND2 AND2B1
A4 B4
OR2B1 OR2
AND2B1
AND2
A5 B5
OR2B1 OR2
AND2 AND2B1
A6 B6
OR2B1 OR2
AND2 AND2B1
A7 B7 A[7:0]
OR2B1 OR2
GT
B[7:0]
AND2B1 X7632
COMPM8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
374
COMPM2, 4, 8, 16
Usage
For HDL, these design elements are supported for inference rather than instantiation.
VHDL Inference Code

architecture Behavioral of compm2 is begin process (A,B) begin if (A>B) then GT <= '1'; LT <= '0'; elsif (A<B) then GT <= '0'; LT <= '1'; else GT <= '0'; LT <= '0'; end if; end process; end Behavioral;

always @ (A or B)
begin if (A > B) begin GT <= 1; LT <= 0; end else if (A < B) begin GT <= 0; LT <= 1; end else begin GT <= 0; LT <= 0; end end
375
COMPM2, 4, 8, 16
376
COMPMC8, 16
COMPMC8, 16
8-, 16-Bit Magnitude Comparators
COMPMC, COMPMC8, COMPMC16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
A[7:0]
COMPMC8
GT LT
B[7:0]
COMPMC8 is an 8-bit, magnitude comparator that compares two positive binaryweighted words A7 A0 and B7 B0, where A7 and B7 are the most significant bits. COMPMC16 is a 16-bit, magnitude comparator that compares two positive binaryweighted words A15 A0 and B15 B0, where A15 and B15 are the most significant bits. These comparators are implemented using carry logic with relative location constraints to ensure efficient logic placement. The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When the two words are equal, both GT and LT are Low. Equality can be flagged with this macro by connecting both outputs to a NOR gate. COMPMC8 Truth Table (also representative of COMPMC16)
Inputs A7, B7 A7>B7 A7<B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A6, B6 X X A6>B6 A6<B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A5, B5 X X X X A5>B5 A5<B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A4, B4 X X X X X X A4>B4 A4<B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A3, B3 X X X X X X X X A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A2, B2 X X X X X X X X X X A2>B2 A2<B2 A2=B2 A2=B2 A1, B1 X X X X X X X X X X X X A1>B1 A1<B1 A0, B0 X X X X X X X X X X X X X X Outputs GT 1 0 1 0 1 0 1 0 1 0 1 0 1 0 LT 0 1 0 1 0 1 0 1 0 1 0 1 0 1
X4264
A[15:0]
COMPMC16 GT
B[15:0]
LT
X4265
377
COMPMC8, 16
COMPMC8 Truth Table (also representative of COMPMC16)

Inputs A7, B7 A7=B7 A7=B7 A7=B7 A6, B6 A6=B6 A6=B6 A6=B6 A5, B5 A5=B5 A5=B5 A5=B5 A4, B4 A4=B4 A4=B4 A4=B4
LT LO RLOC=R0C0.S1 B7 A7 C8 B6 A6 XNOR2 LO MUXCY_L RLOC=R0C0.S1 I6 S 0 1 DI CI C7 MUXCY_L I5 XNOR2 S LO RLOC=R1C0.S1 B5 A5 C6 LO RLOC=R1C0.S1 B4 A4 C5 MUXCY_L B3 A3 XNOR2 I3 S DI LO RLOC=R2C0.S1 B3 A3 XNOR2 MUXCY_L I3G S DI XNOR2 MUXCY_L I4G S DI XNOR2 MUXCY_L I5G S DI MUXCY_L B6 A6 XNOR2 I6G S DI XNOR2 MUXCY I7G S DI LO RLOC=R0C0.S0 CI C8G LO RLOC=R0C0.S0 CI C7G LO RLOC=R1C0.S0 CI C6G LO RLOC=R1C0.S0 CI C5G LO RLOC=R2C0.S0 CI C4G MUXCY_L I2G XNOR2 S DI LO RLOC=R2C0.S0 CI C2G MUXCY_L B1 A1 XNOR2 I1G S DI LO RLOC=R3C0.S0 CI C1G RLOC=R3C0.S1 DI 0 1 CI C0 MUXCY_L B0 A0 XNOR2 I0G S DI LO RLOC=R3C0.S0 CI C0G
Outputs A2, B2 A2=B2 A2=B2 A2=B2 A1, B1 A1=B1 A1=B1 A1=B1 A0, B0 A0>B0 A0<B0 A0=B0
GT
A3, B3 A3=B3 A3=B3 A3=B3
GT 1 0 0
LT 0 1 0
MUXCY B7 A7 XNOR2 I7 S
0 1 DI CI
0 1
0 1
B5 A5
0 1 DI CI
0 1
B4 A4 XNOR2
MUXCY_L I4 S DI
0 1 CI
0 1
0 1 CI C4
0 1
B2 A2 XNOR2
MUXCY_L RLOC=R2C0.S1 S I2 0 1 DI CI C2 LO MUXCY_L RLOC=R3C0.S1 I1 S 0 1 CI DI C1 MUXCY_L LO
LO
B2 A2
0 1
B1 A1 XNOR2
0 1
B0 A0 XNOR2
I0
0 1
GND
GND
A[7:0] B[7:0]
X8713
COMPMC8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
378
COMPMC8, 16
LT
GT
O B7 I7 XNOR2 A7 C8 S MUXCY 0 1 DI CI
RLOC=X0Y3 B7 I7G XNOR2 A7 S
O RLOC=X1Y3 MUXCY 0 1 DI CI C8G
LO B6 I6 XNOR2 S MUXCY_L 0 1 DI CI A6 C7 RLOC=X0Y3 B6 I6G XNOR2 S
RLOC=X1Y3
A6
C7G LO B5 I5G XNOR2 A5 S MUXCY_L 0 1 DI CI
LO B5 I5 XNOR2 A5 C6 S MUXCY_L 0 1 DI CI
RLOC=X0Y2
RLOC=X1Y2
C6G
LO B4 I4 XNOR2 A4 S MUXCY_L 0 1 DI CI
RLOC=X0Y2 B4 I4G XNOR2 A4 C5 S
RLOC=X1Y2
C5G
RLOC=X1Y1
C4G
RLOC=X0Y1
LO B2 I2G XNOR2 A2 S MUXCY_L 0 1 DI CI
RLOC=X1Y1
C2
C2G
RLOC=X1Y0
C1G
RLOC=X1Y0
C0G
GND A[7:0]
GND
B[7:0] X9313
COMPMC8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
379
COMPMC8, 16
Usage
For HDL, these design elements are supported for inference rather than instantiation.
VHDL Inference Code

architecture Behavioral of compmc8 is begin process (A,B) begin if (A>B) then GT <= '1'; LT <= '0'; elsif (A<B) then GT <= '0'; LT <= '1'; else GT <= '0'; LT <= '0'; end if; end process; end Behavioral;

always @(A or B) begin if (A > B) begin GT <= 1; LT <= 0; end else if (A < B) begin GT <= 0; LT <= 1; end else begin GT <= 0; LT <= 0; end end
380
CR8CE, CR16CE
CR8CE, CR16CE
8-, 16-Bit Negative-Edge Binary Ripple Counters with Clock Enable and Asynchronous Clear
CR8CE, CR16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
CR8CE
CE C
Q[7:0]
CLR
X4116
CR8CE and CR16CE are 8-bit and 16-bit, cascadable, clearable, binary, ripple counters. The asynchronous clear (CLR), when High, overrides all other inputs and causes the Q outputs to go to logic level zero. The counter increments when the clock enable input (CE) is High during the High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. Larger counters can be created by connecting the last Q output (Q7 for CR8CE, Q15 for CR16CE) of the first stage to the clock input of the next stage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of a ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the time tC - Q is the C-to-Qz propagation delay of each stage. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0
z = 7 for CR8CE; z = 15 for CR16CE.
CR16CE
CE C
Q[15:0]
CLR
X4120
Outputs C X X Qz Q0 0 No Chg Inc
CE X 0 1
381
CR8CE, CR16CE
Q[7:0] Q7
FDCE_1
TQ0 CE C INV D CE C CLR Q0 Q Q0 Q3 TQ4 INV
FDCE_1
D CE C CLR Q4 Q Q4
FDCE_1
TQ1 INV D CE C CLR Q1 Q Q1 TQ5 INV
FDCE_1
D CE C CLR Q5 Q Q5
FDCE_1
TQ2 INV D CE C CLR Q2 Q Q2 TQ6 INV
FDCE_1
D CE C CLR Q6 Q Q6
FDCE_1
TQ3 INV D CE C CLR Q3 CLR Q Q3 TQ7 INV
FDCE_1
D CE C CLR Q7 Q Q7
VCC
X8142
CR8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
382
CR8CE, CR16CE
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Q[7:0]
VCC
FDC
D AND2 XOR2 C Q
CE
CLR Q0
FDC
D AND2 XOR2 C Q
CLR Q1
FDC
D AND3 XOR2 C Q
CLR Q2
FDC
D XOR2 AND4 C Q
CLR Q3
FDC
D XOR2 AND5 C Q
CLR Q4
FDC
D XOR2 AND6 C Q
CLR Q5
FDC
D XOR2 C Q
CLR
AND7
Q6
FDC
D XOR2 C Q
CLR
AND8
Q7
C CLR
INV
X7631
CR8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of cr8ce is begin
383
CR8CE, CR16CE
process (C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C' event and C='0') then if (CE='1') then Q <= Q + 1; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end
384
CRD8CE, CRD16CE
CRD8CE, CRD16CE
8-, 16-Bit Dual-Edge Triggered Binary Ripple Counters with Clock Enable and Asynchronous Clear
CRD8CE, CRD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
CRD8CE
CE C
Q[7:0]
CLR
X9748
CRD8CE and CRD16CE are dual edge triggered 8-bit and 16-bit, cascadable, clearable, binary, ripple counters. The asynchronous clear (CLR), when High, overrides all other inputs and causes the Q outputs to go to logic level zero. The counter increments when the clock enable input (CE) is High during the High-to-Low and Low-to-High clock (C) transitions. The counter ignores clock transitions when CE is Low. Larger counters can be created by connecting the last Q output (Q7 for CRD8CE, Q15 for CRD16CE) of the first stage to the clock input of the next stage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of a ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the time tC - Q is the C-to-Qz propagation delay of each stage. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0
z = 7 for CR8CE; z = 15 for CR16CE.
CRD16CE
CE C
Q[15:0]
CLR
X9749
Outputs C X X Qz Q0 0 No Chg Inc Inc
CE X 0 1 1
385
CRD8CE, CRD16CE
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Q[7:0]
VCC CE AND2 XOR2 D C
FDDC
Q
CLR Q0
FDDC
D AND2 XOR2 C CLR Q1 Q
FDDC
D AND3 XOR2 C CLR Q2 Q
FDDC
D XOR2 AND4 C CLR Q3 Q
FDDC
FDDC
FDDC
D XOR2 C CLR AND7 Q6 Q
FDDC
D XOR2 C CLR AND8 Q7 Q
C CLR INV
X9750
CRD8CE Implementation CoolRunner-II
386
CRD8CE, CRD16CE
Usage
VHDL Inference Code

architecture Behavioral of crd8ce is begin process (C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C' event) then if (CE='1') then Q <= Q + 1; end if; end if; end process; end Behavioral;

always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end
387
CRD8CE, CRD16CE
388
D2_4E
D2_4E
2- to 4-Line Decoder/Demultiplexer with Enable
D2_4E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
A0 A1 E
D2_4E
D0 D1 D2 D3
When the enable (E) input of the D2_4E decoder/demultiplexer is High, one of four active-High outputs (D3 D0) is selected with a 2-bit binary address (A1 A0) input. The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E input is the data input.
X3853
Inputs A1 X 0 0 1 1 A0 X 0 1 0 1 E 0 1 1 1 1 D3 0 0 0 0 1 D2 0 0 0 1 0
D0
AND3B2
Outputs D1 0 0 1 0 0 D0 0 1 0 0 0
D1
AND3B1
D2
AND3B1
E A0 A1
AND3
D3
X7794
D2_4E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
389
D2_4E
VHDL Inference Code

architecture Behavioral of d2_4e is begin process (A, E) begin if (E='0') then D <= "0000"; else case A is when "00" => D <= "0001"; when "01" => D <= "0010"; when "10" => D <= "0100"; when "11" => D <= "1000"; when others => D <= "0000"; end case; end if; end process; end Behavioral;

always @ (A or E) begin if (!E) D <= 4'b0000; else begin case (A) 2'b00 : D <= 2'b01 : D <= 2'b10 : D <= 2'b11 : D <= endcase end end
4'b0001; 4'b0010; 4'b0100; 4'b1000;
390
D3_8E
D3_8E
A0 A1 A2
D3_8E
D0 D1 D2 D3 D4 D5 D6
When the enable (E) input of the D3_8E decoder/demultiplexer is High, one of eight active-High outputs (D7 D0) is selected with a 3-bit binary address (A2 A0) input. The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E input is the data input.
D7
Inputs A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 E 0 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 0 1 0 D5 0 0 0 0 0 0 1 0 0
Outputs D4 0 0 0 0 0 1 0 0 0 D3 0 0 0 0 1 0 0 0 0 D2 0 0 0 1 0 0 0 0 0 D1 0 0 1 0 0 0 0 0 0 D0 0 1 0 0 0 0 0 0 0
X3854
391
D3_8E
D0
AND4B3
D1
AND4B2 D2
AND4B2 D3
AND4B1 D4
AND4B2 D5
AND4B1 D6
E A0 A1 A2
AND4B1 D7
AND4 X7795
Usage
VHDL Inference Code

architecture Behavioral of d3_8e is begin process (A, E) begin if (E='0') then D <= "00000000"; else case A is when "000" => D <= "00000001"; when "001" => D <= "00000010"; when "010" => D <= "00000100"; when "011" => D <= "00001000";
392
D3_8E
when "100" => D <= "00010000"; when "101" => D <= "00100000"; when "110" => D <= "01000000"; when "111" => D <= "10000000"; when others => D <= "00000000"; end case; end if; end process; end Behavioral;

always @ (A or E) begin if (!E) D <= 8'b00000000; else begin case (A) 3'b000 : D <= 8'b00000001; 3'b001 : D <= 8'b00000010; 3'b010 : D <= 8'b00000100; 3'b011 : D <= 8'b00001000; 3'b100 : D <= 8'b00010000; 3'b101 : D <= 8'b00100000; 3'b110 : D <= 8'b01000000; 3'b111 : D <= 8'b10000000; endcase end end
393
D3_8E
394
D4_16E
D4_16E
A0 A1 A2 A3
D4_16E
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
When the enable (E) input of the D4_16E decoder/demultiplexer is High, one of 16 active-High outputs (D15 D0) is selected with a 4-bit binary address (A3 A0) input. The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E input is the data input. See D3_8E for a representative truth table derivation.
D15
X3855
395
D4_16E
D0
AND5B4
D1
AND5B3
D2
AND5B3
D3
AND5B2
D4
AND5B3
D5
AND5B2
D6
AND5B2
D7
AND5B1
D8
AND5B3
D9
AND5B2
D10
AND5B2
D11
AND5B1
D12
AND5B2
D13
AND5B1
D14
AND5B1 E A0 A1 A2 A3 AND5 X7638
D15
Usage
VHDL Inference Code

architecture Behavioral of d4_16e is begin process (A, E) begin
396
D4_16E
if (E='0') then D <= "0000000000000000"; else case A is when "0000" => D <= "0000000000000001"; when "0001" => D <= "0000000000000010"; when "0010" => D <= "0000000000000100"; when "0011" => D <= "0000000000001000"; when "0100" => D <= "0000000000010000"; when "0101" => D <= "0000000000100000"; when "0110" => D <= "0000000001000000"; when "0111" => D <= "0000000010000000"; when "1000" => D <= "0000000100000000"; when "1001" => D <= "0000001000000000"; when "1010" => D <= "0000010000000000"; when "1011" => D <= "0000100000000000"; when "1100" => D <= "0001000000000000"; when "1101" => D <= "0010000000000000"; when "1110" => D <= "0100000000000000"; when "1111" => D <= "1000000000000000"; when others => D <= "0000000000000000"; end case; end if; end process; end Behavioral;

always @ (A or E) begin if (!E) D <= 16'b0000000000000000; else begin case (A) 4'b0000 : D <= 16'b0000000000000001; 4'b0001 : D <= 16'b0000000000000010; 4'b0010 : D <= 16'b0000000000000100; 4'b0011 : D <= 16'b0000000000001000; 4'b0100 : D <= 16'b0000000000010000;
397
D4_16E
4'b0101 4'b0110 4'b0111 4'b1000 4'b1001 4'b1010 4'b1011 4'b1100 4'b1101 4'b1110 4'b1111 endcase end end
: : : : : : : : : : :
D D D D D D D D D D D
<= <= <= <= <= <= <= <= <= <= <=
16'b0000000000100000; 16'b0000000001000000; 16'b0000000010000000; 16'b0000000100000000; 16'b0000001000000000; 16'b0000010000000000; 16'b0000100000000000; 16'b0001000000000000; 16'b0010000000000000; 16'b0100000000000000; 16'b1000000000000000;
398
DCM
DCM
Digital Clock Manager
DCM Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
DCM CLKIN CLKFB CLK0 CLK90 CLK180 RST DSSEN CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180
DCM is a digital clock manager that provides multiple functions. It can implement a clock delay locked loop, a digital frequency synthesizer, digital phase shifter, and a digital spread spectrum. Note: All unused inputs must be driven Low. The program will automatically tie the inputs Low if they are unused.
PSINCDEC PSEN PSCLK
Clock Delay Locked Loop (DLL)

DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other. See The Programmable Logic Data Book for the specified time value. DCM supports two frequency modes for the DLL. By default, the DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF) frequency range (MHz). See The Programmable Logic Data Book for the current DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF frequency range values. In Low frequency mode, the CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, and CLK2X180 outputs are available. When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data Book for the current DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF frequency range values. In High frequency mode, only the CLK0, CLK180, and CLKDV outputs are available. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the DCM must be sourced from either the CLK0 or CLK2X outputs of the same DCM. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X
LOCKED STATUS [7:0]
PSDONE X9469
399
DCM
output can be used but not both. The CLK0 or CLK2X must be connected to the input of OBUF, an output buffer. The CLK_FEEDBACK attribute controls whether the CLK0 output, the default, or the CLK2X output is the source of the CLKFB input. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X, CLK2X180, and CLKDV outputs is 50-50 unless CLKDV_DIVIDE is a non-integer and the DLL_FREQUENCY_MODE is High (see CLKDV_DIVIDE, in the Constraints Guide for details). The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. DCM Clock Delay Lock Loop Outputs
Output CLK0 CLK180 CLK270* CLK2X* CLK2X180* CLK90* CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLK0 frequency, shifted 180o with regards to CLK0 Clock at 1x CLK0 frequency, shifted 270o with regards to CLK0 Clock at 2x CLK0 frequency, in phase with CLK0 Clock at 2x CLK0 frequency shifted 180o with regards to CLK2X Clock at 1x CLK0 frequency, shifted 90o with regards to CLK0 Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. All enabled DCM features locked. Description
* The CLK90, CLK270, CLK2X, and CLK2X180 outputs are not available if the DLL_FREQUENCY_MODE is set to High.
Digital Frequency Synthesizer (DFS)

The CLKFX and CLKFX180 outputs in conjunction with the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes provide a frequency synthesizer that can be any multiple or division of CLKIN. CLKFX and CLKIN are in phase every CLKFX_MULTIPLY cycles of CLKFX and every CLKFX_DIVIDE cycles of CLKIN when a feedback is provided to the CLKFB input of the DLL. The frequency of CLKFX is defined by the following equation.
FrequencyCLKFX= (CLKFX_MULTIPLY_value/CLKFX_DIVIDE_value) * FrequencyCLKIN
Both the CLKFX or CLKFX180 output can be used simultaneously. CLKFX180 is 1x the CLKFX frequency, shifted 180o with regards to CLKFX. CLKFX and CLKFX180 always have a 50/50 duty cycle. The DFS_FREQUENCY_MODE attribute specifies the allowable input clock and output clock frequency ranges. The CLK_FEEDBACK attribute set to NONE will cause the DCM to be in the Digital Frequency Synthesizer mode. The CLKFX and CLKFX180 will be generated without phase correction with respect to CLKIN. See The Programmable Logic Data Book for the allowable frequency range of CLKFX.
400
DCM
Digital Phase Shifter (DPS)

The phase shift (skew) between the rising edges of CLKIN and CLKFB may be configured as a fraction of the CLKIN period with the PHASE_SHIFT attribute. This allows the phase shift to remain constant as ambient conditions change. The CLKOUT_PHASE_SHIFT attribute controls the use of the PHASE_SHIFT value. By default, the CLKOUT_PHASE_SHIFT attribute is set to NONE and the PHASE_SHIFT attribute has no effect. By creating skew between CLKIN and CLKFB, all DCM output clocks are phase shifted by the amount of the skew. When the CLKOUT_PHASE_SHIFT attribute is set to FIXED, the skew set by the PHASE_SHIFT attribute is used at configuration for the rising edges of CLKIN and CLKFB. The skew remains constant. When the CLKOUT_PHASE_SHIFT attribute is set to VARIABLE, the skew set at configuration is used as a starting point and the skew value can be changed dynamically during operation using the PS* signals. This digital phase shifter feature is controlled by a synchronous interface. The inputs PSEN (phase shift enable) and PSINCDEC (phase shift increment/decrement) are set up to the rising edge of PSCLK (phase shift clock). The PSDONE (phase shift done) output is clocked with the rising edge of PSCLK (the phase shift clock). PSDONE must be connected to implement the complete synchronous interface. The rising-edge skew between CLKIN and CLKFB may be dynamically adjusted after the LOCKED output goes High. The PHASE_SHIFT attribute value specifies the initial phase shift amount when the device is configured. Then the PHASE_SHIFT value is changed one unit when PSEN is activated for one period of PSCLK. The PHASE_SHIFT value is incremented when PSINCDEC is High and decremented when PSINCDEC is Low during the period that PSEN is High. When the DCM completes an increment or decrement operation, the PSDONE output goes High for a single PSCLK cycle to indicate the operation is complete. At this point the next change may be made. When RST (reset) is High, the PHASE_SHIFT attribute value is reset to the skew value set at configuration. If CLKOUT_PHASE_SHIFT is FIXED or NONE, the PSEN, PSINCDEC, and PSCLK inputs must be tied to GND. The program will automatically tie the inputs to GND if they are not connected by the user.
Digital Spread Spectrum (DSS)

The digital spread spectrum function of DCM broadens the frequency spectrum of the output clocks to help meet FCC requirements. Spread spectrum clocking is a simple method to lower electromagnetic interference (EMI). A digital system can create a severe EMI spike at the clock frequency. Spread spectrum clocking speeds up and slows down the clock within a few percent of the target frequency, thus flattening out the EMI peak by spreading it across a range of frequencies. When the DSS_MODE attribute is set to NONE, the DSSEN input has no effect. When DSS_MODE is set to a value other than NONE and DSSEN is High, the output clock frequency is modulated by the amount of spread specified by the DSS_MODE value. For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the DSS feature of the DCM has limited EMI reduction capability. For maximum EMI reduction an IP core available from Xilinx is recommended. Note: DSS is not supported in Spartan-3.
401
DCM
Additional Status Bits

The STATUS output bits return the following information. DCM Additional Status Bits
Bit 0 1 2 3 4 5 6 7 Description Phase Shift Overflow* 1 = |PHASE_SHIFT| > 255 DLL CLKIN stopped** 1 = CLKIN stopped toggling DLL CLKFX stopped 1 = CLKFX stopped toggling No No No No No
* Phase Shift Overflow will also go high if the end of the phase shift delay line is reached (see the product data sheet for the most current value of the maximum shifting delay). ** If only the DFS outputs are used (CLKFX & CLKFX180), this status bit will not go high if CLKIN stops.
LOCKED
When LOCKED is high, all enabled signals are locked.
RST
The master reset input (RST) resets DCM to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for 2ns.
Usage
This component is generally instantiated in the code as it cannot be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool documentation.

-- Component Declaration for DCM should be placed -- after architecture statement but before begin keyword
component DCM -- synthesis translate_off generic (CLK_FEEDBACK : string := "1X"; CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0) CLKFX_DIVIDE : integer := 1; -- (1 to 4096)
402
DCM
CLKFX_MULTIPLY : integer := 4; -- (1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 5.0, 5.5, -- 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0) CLKIN_DIVIDE_BY_2 : boolean := FALSE; -- (TRUE, FALSE) CLKOUT_PHASE_SHIFT : string := "NONE"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) PHASE_SHIFT : real := 0; STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLK270 : out STD_ULOGIC; CLK2X : out STD_ULOGIC; CLK2X180 : out STD_ULOGIC; CLK90 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; CLKFX : out STD_ULOGIC; CLKFX180 : out STD_ULOGIC; LOCKED : out STD_ULOGIC; PSDONE : out STD_ULOGIC; STATUS : out STD_LOGIC_VECTOR (7 downto 0); CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; DSSEN : in STD_ULOGIC; PSCLK : in STD_ULOGIC; PSEN : in STD_ULOGIC; PSINCDEC : in STD_ULOGIC; RST : in STD_ULOGIC); end component;
-- Component Attribute specification for DCM -- should be placed after architecture declaration but
403
DCM
-- before the begin keyword
attribute CLK_FEEDBACK : string; attribute CLKDV_DIVIDE : real; attribute CLKFX_DIVIDE : integer; attribute CLKFX_MULTIPLY : integer; attribute CLKIN_DIVIDE_BY_2 : string; attribute CLKOUT_PHASE_SHIFT : string; attribute DESKEW_ADJUST : string; attribute DFS_FREQUENCY_MODE : string; attribute DLL_FREQUENCY_MODE : string; attribute DSS_MODE : string; attribute DUTY_CYCLE_CORRECTION : string; attribute PHASE_SHIFT : real; attribute STARTUP_WAIT : boolean;
attribute CLK_FEEDBACK of DCM_instance_name: label is "1X"; attribute CLKDV_DIVIDE of DCM_instance_name: label is 2.0; -- (1.5,2,2.5,3,4, 5, 8, 16) are valid for CLKDV_DIVIDE attribute CLKFX_DIVIDE of DCM_instance_name: label is 1; attribute CLKFX_MULTIPLY of DCM_instance_name: label is 4; attribute CLKIN_DIVIDE_BY_2 of DCM_instance_name: label is "FALSE"; attribute CLKOUT_PHASE_SHIFT of DCM_instance_name: label is "NONE"; attribute DESKEW_ADJUST of DCM_instance_name : label is "SYSTEM_SYNCHRONOUS"; attribute DFS_FREQUENCY_MODE of DCM_instance_name: label is "LOW"; attribute DLL_FREQUENCY_MODE of DCM_instance_name: label is "LOW"; attribute DSS_MODE of DCM_instance_name: label is "NONE"; attribute DUTY_CYCLE_CORRECTION of DCM_instance_name: label is TRUE; -- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION attribute PHASE_SHIFT of DCM_instance_name: label is 0; attribute STARTUP_WAIT of DCM_instance_name: label is FALSE; -- (TRUE,FALSE)
-- Component Instantiation for DCM should be placed
404
DCM
-- in architecture after the begin keyword
DCM_INSTANCE_NAME : DCM -- synthesis translate_off generic map(CLK_FEEDBACK => "string_value", CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) CLKFX_DIVIDE => integer_value, CLKFX_MULTIPLY => integer_value, CLKIN_DIVIDE_BY_2 => boolean_value, -- (TRUE, FALSE) CLKOUT_PHASE_SHIFT => "string_value", DESKEW_ADJUST => "string_value", DFS_FREQUENCY_MODE => "string_value", DLL_FREQUENCY_MODE => "string_value", DSS_MODE => "string_value", DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) PHASE_SHIFT => integer_value, STARTUP_WAIT => boolean) -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLK270 => user_CLK270, CLK2X => user_CLK2X, CLK2X180 => user_CLK2X180, CLK90 => user_CLK90, CLKDV => user_CLKDV, CLKFX => user_CLKFX, CLKFX180 => user_CLKFX180, LOCKED => user_LOCKED) PSDONE => user_PSDONE, STATUS => user_STATUS, CLKFB => user_CLKFB, CLKIN => user_CLKIN, DSSEN => user_DSSEN, PSCLK => user_PSCLK, PSEN => user_PSEN, PSINCDEC => user_PSINCDEC,
405
DCM
RST => user_RST);

DCM DCM_instance_name (.CLK0 (user_CLK0), .CLK180 (user_CLK180), .CLK270 (user_CLK270), .CLK2X (user_CLK2X), .CLK2X180 (user_CLK2X180), .CLK90 (user_CLK90), .CLKDV (user_CLKDV), .CLKFX (user_CLKFX), .CLKFX180 (user_CLKFX180), .LOCKED (user_LOCKED), .PSDONE (user_PSDONE), .STATUS (user_STATUS), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .DSSEN (user_DSSEN), .PSCLK (user_PSCLK), .PSEN (user_PSEN), .PSINCDEC (user_PSINCDEC), .RST (user_RST));
defparam DCM_instance_name.CLK_FEEDBACK => "string_value"; defparam DCM_instance_name.CLKDV_DIVIDE = integer_value; //(1.5,2,2.5,3,4,5,8,16) defparam DCM_instance_name.CLKFX_DIVIDE => integer_value; defparam DCM_instance_name.CLKFX_MULTIPLY => integer_value; defparam DCM_instance_name.CLKIN_DIVIDE_BY_2 => boolean_value; // (TRUE, FALSE) defparam DCM_instance_name.CLKOUT_PHASE_SHIFT => "string_value"; defparam DCM_instance_name.DESKEW_ADJUST => "string_value"; defparam DCM_instance_name.DFS_FREQUENCY_MODE => "string_value"; defparam DCM_instance_name.DLL_FREQUENCY_MODE => "string_value"; defparam DCM_instance_name.DSS_MODE => "string_value"; defparam DCM_instance_name.DUTY_CYCLE_CORRECTION => "string_value";// (TRUE, FALSE)
406
DCM
defparam DCM_instance_name.PHASE_SHIFT => integer_value; defparam DCM_instance_name.STARTUP_WAIT => boolean_value; // (TRUE, FALSE) Note: Additional syntax may be necessary in order to pass the DCM attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

CLKDV_DIVIDE CLK_FEEDBACK CLKFX_DIVIDE CLKFX_MULTIPLY CLKIN_DIVIDE_BY_2 CLKOUT_PHASE_SHIFT DUTY_CYCLE_CORRECTION DFS_FREQUENCY_MODE DLL_FREQUENCY_MODE LOC PHASE_SHIFT STARTUP_WAIT DESKEW_ADJUST
407
DCM
408
DEC_CC4, 8, 16
DEC_CC4, 8, 16
4-, 8-, 16-Bit Active Low Decoders
DEC_CC4, DEC_CC8, DEC_CC16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
A0 A1 A2 A3 C_IN
DEC_CC4
X4927
These decoders are used to build wide-decoder functions. They are implemented by cascading CY_MUX elements driven by lookup tables (LUTs). The C_IN pin can only be driven by the output (O) of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all the inputs are High and the C_IN input is High, the output is High. You can decode patterns by adding inverters to inputs.
Inputs Outputs Az 1 X X X 0 C_IN 1 0 X X X O 1 0 0 0 0
A0 A1 A2 A3 A4 A5 A6 A7 C_IN
DEC_CC8
A0 1 X 0
O
A1 1 X X 0 X
1 X X X X
X X
X4928
z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16

O
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 C_IN
DEC_CC16
A3 A2 A1 A0 AND4 S0 MUXCY O S DI 0 1 CI
GND C_IN The C_IN pin can only be initialized by a CY_INIT or by the output of a previous decode stage.
X8717
DEC_CC4 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
X4929
409
DEC_CC4, 8, 16
DEC_CC4
A0 A1 A0 A3 A0 A1 A2 A3 C_IN O O
DEC_CC4
A4 A5 A6 A7 C_IN A0 A1 A2 A3 C_IN O
The C_IN pin can only be initialized by a CY_INIT or by the output of a previous decode stage. X6396
DEC_CC8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
DEC_CC4 cannot be directly inferred or instantiated. The proper way to use a DEC_CC4 is to infer the primitive components that make up the DEC_CC4.
410
DECODE4, 8, 16
DECODE4, 8, 16
4-, 8-, 16-Bit Active-Low Decoders
DECODE4, DECODE8, DECODE16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
A0 A1 A2 A3
DECODE4
A0 A1 O A2 A3 A4 A5 A6 A7
DECODE16
A0 A1 A2 A3 A4 A5 A6 A7
DECODE8
A8 A9 A10 A11 A12 A13 A14 O A15 O
X9807
DECODE Representations In Spartan-II, , Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X decoders are implemented using combinations of LUTs and MUXCYs.
Inputs A0 1 0 X X A1 1 X 0 X 1 X X X Az 1 X X 0
Outputs* O 1 0 0 0
z = 3 for DECODE4, z = 7 for DECODE8; z = 15 for DECODE16 *A pull-up resistor must be connected to the output to establish High-level drive current.
411
DECODE4, 8, 16
FMAP
I4 I3 S1 S0 A7 A6 A5 A4 AND4 A7 O AND2 A3 A2 A1 A0 AND4 S0 A6 A5 A4 S1 I2 I1 MAP=PUO RLOC=R0C0.S0 O O
FMAP
I4 I3 I2 I1 MAP=PUO RLOC=R0C0.S1 O S1
FMAP
A3 A2 A1 A0 X8703 I4 I3 I2 I1 MAP=PUO RLOC=R0C0.S1 O S0
DECODE8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4 I3 S1 S0 I2 I1 MAP=PUO RLOC=X0Y1 A7 A6 A5 A4 AND4 S1 O O
FMAP
A7 A6 A5 A4 O AND2 MAP=PUO RLOC=X0Y0 I4 I3 I2 I1 O S1
A3 A2 A1 A0 AND4 S0 A3 A2 A1 A0 I4 I3 I2 I1
FMAP
S0
MAP=PUO RLOC=X0Y0 X9316
DECODE8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, these design elements are inferrred rather than instantiated.
412
DECODE4, 8, 16
VHDL Inference Code

architecture Behavioral of decode4 is begin process (A) begin case A is when "1111" => O <= '1'; when others => O <= '0'; end case; end process; end Behavioral;

always @(A) begin case (A) 4'h0 : O <= 1; default : O <= 0; endcase end
413
DECODE4, 8, 16
414
DECODE32, 64
DECODE32, 64
32- and 64-Bit Active-Low Decoders
DECODE3, DECODE2, DECODE64 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
A[31:0] DECODE32 O
Macro Macro Macro No No No
DECODE32 and DECODE64 are 32- and 64-bit active-low decoders. These decoders are implemented using combinations of LUTs and MUXCYs. See DECODE4, 8, 16 for a representative schematic.
X8203
Inputs
A[63:0] DECODE64
Outputs 1 X X X Az 1 X X 0 O 1 0 0 0
A0
O
A1 1 X 0 X
1
X8204
0 X X
z = 31 for DECODE32, z = 63 for DECODE64
Usage
VHDL Inference Code

architecture Behavioral of decode32 is begin process (A) begin case A is when x"11111111" => O <= '1'; when others => O <= '0'; end case; end process; end Behavioral;
415
DECODE32, 64

always @(A) begin case (A) 32'h00000000 : O <= 1; default : O <= 0; endcase end
416
FD
FD
D Flip-Flop
FD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro
D C
FD
FD is a single D-type flip-flop with data input (D) and data output (Q). The data on the D inputs is loaded into the flip-flop during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.
X3715
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. See FD4, 8, 16 for information on multiple D flip-flops for XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II.
Inputs D 0 1
FDCP
D C PRE Q
Outputs C Q 0 1
D C
CLR Q
X7797 GND
FD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
417
FD
Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.
VHDL Inference Code

architecture Behavioral of fd is begin process (C) begin if C'event and C='1' then Q <= D; end if; end process; end Behavioral;

always @ (posedge C) begin Q <= D; end

-- Component Declaration for FD should be placed -- after architecture statement but before begin keyword component FD -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FD -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FD_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FD should be placed -- in architecture after the begin keyword FD_INSTANCE_NAME : FD -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D);
418
FD

FD FD_instance_name (.Q (user_Q), .C (user_C), .D (user_D)); defparam FD_instance_name.INIT = bit_value;

BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM
419
FD
420
FD_1
FD_1
D Flip-Flop with Negative-Edge Clock
FD_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D C
FD_1
FD_1 is a single D-type flip-flop with data input (D) and data output (Q). The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.
X3726
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs D 0 1 C Outputs Q 0 1
Usage
VHDL Inference Code

architecture Behavioral of fd_1 is begin process (C) begin if C' event and C = '0' then Q <= D; end if; end process; end Behavioral;
421
FD_1

always @ (negedge C) begin Q <= D; end

-- Component Declaration for FD_1 should be placed -- after architecture statement but before begin keyword component FD_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FD_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FD_1_instance_name : label is "0"; -- values can be (0 or 1)
begin FD_1_INSTANCE_NAME : FD_1 -- synthesis translate_off generic map ( INIT => bit_value) -- INIT value can be '0' or '1' -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D); end Behavioral

FD_1 FD_1_instance_name (.Q (user_Q), .C (user_C), .D (user_D)); defparam FD_1_instance_name.INIT = bit_value;

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM
422
FD4, 8, 16
FD4, 8, 16
Multiple D Flip-Flops
FD4, FD8, FD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro
D0 D1 D2 D3 C
FD4
Q0 Q1 Q2 Q3
FD4, FD8, FD16 are multiple D-type flip-flops with data inputs (D) and data outputs (Q). FD4, FD8, and FD16 are, respectively, 4-bit, 8-bit, and 16-bit registers, each with a common clock (C). The data on the D inputs is loaded into the flip-flop during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
X4608
D[7:0]
FD8
Q[7:0]
Inputs
C
Outputs C Qz Q0 0 1
Dz D0
X4609
0 1
z = 3 for FD4; z = 7 for FD8; z = 15 for FD16
D[15:0]
FD16
Q[15:0]
C X4610
423
FD4, 8, 16
Q[7:0] FD D0
D C Q
FD Q0 D4
D C Q
Q4
Q0 FD D1
D C Q
Q4 FD Q1 D5
D C Q
Q5
Q1 FD D2
D C Q
Q5 FD Q2 D6
D C Q
Q6
Q2 FD D3
D C Q
Q6 FD Q3 D7
D C Q
Q7
D[7:0] C
Q3
Q7
X8128
FD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fd4 is begin process (C) begin if C' event and C='1' then Q <= D; end if; end process; end Behavioral;

always @ (posedge C) begin Q <= D; end
424
FD4CE, FD8CE, FD16CE

4-, 8-, 16-Bit Data Registers with Clock Enable and Asynchronous Clear
FD4CE, FD8CE, FD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D0 D1 D2 D3 CE C
FD4CE
Q0 Q1 Q2 Q3
FD4CE, FD8CE, and FD16CE are, respectively, 4-, 8-, and 16-bit data registers with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputs and resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
CLR
X3733
D[7:0] CE C
FD8CE
Q[7:0]
CLR
X3850
D[15:0] CE C
FD16CE
Q[15:0]
Inputs CLR CE X 0 1 Dz D0 X X Dn C X X Outputs Qz Q0 0 No Chg Dn
CLR
X3736
1 0 0
z = 3 for FD4CE; z = 7 for FD8CE; z = 15 for FD16CE.
425
Q[7:0]
FDCE FDCE
D0 D CE C CLR Q0 Q Q0 D4 D CE C CLR Q4 Q Q4
FDCE FDCE
FDCE FDCE
FDCE FDCE
D3 D CE C CLR Q3 D[7:0] CE C CLR X7799 Q Q3 D7 D CE C CLR Q7 Q Q7
FD8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of fd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;
426

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 4'b0000; else begin if (CE) Q <= D; end end
427
428
FD4RE, FD8RE, FD16RE

4-, 8-, 16-Bit Data Registers with Clock Enable and Synchronous Reset
FD4RE, FD8RE, FD16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D0 D1 D2 D3 CE C
FD4RE
Q0 Q1 Q2 Q3
X3734
FD4RE, FD8RE, and FD16RE are, respectively, 4-, 8-, and 16-bit data registers. When the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during the Low-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q) Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied.
D[7:0] CE C
FD8RE
Q[7:0]
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
X3735
D[15:0] CE C
FD16RE
Q[15:0]
Inputs R CE X 0 1 Dz D0 X X Dn C X Outputs Qz Q0 0 No Chg Dn
X3737
1 0 0
z = 3 for FD4RE; z = 7 for FD8RE; z = 15 for FD16RE
429
Q[7:0]
FDRE
D0 D CE C R Q0 Q Q0 D4
FDRE
D CE C R Q4 Q Q4
FDRE
FDRE
D CE C R Q5 Q Q5
FDRE
FDRE
D CE C R Q6 Q Q6
FDRE
D3 D CE C R Q3 D[7:0] CE C R Q Q3 D7
FDRE
D CE C R Q7 Q Q7
X8195
FD8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of fd4re is begin process (C) begin if (C' event and C = '1') then if (R = '1') then Q <= "0000"; elsif (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;
430

always @ (posedge C) begin if (R) Q <= 4'b0000; else begin if (CE) Q <= D; end end
431
432
FDC
FDC
D Flip-Flop with Asynchronous Clear
FDC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro
D C
FDC
FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q). The asynchronous CLR, when High, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low on the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 D X 1 0
FDCP
D C CLR PRE Q
CLR
X3716
Outputs C X Q 0 1 0
D C
CLR Q
X7801 GND
FDC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
433
FDC
Usage
VHDL Inference Code

architecture Behavioral of fdc is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event and C = '1') then Q <= D; end if; end process; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else Q <= D; end

-- Component Declaration for FDC should be placed -- after architecture statement but before begin keyword component FDC -- synthesis translate_off generic (INIT : bit:= '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDC -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDC_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDC should be placed -- in architecture after the begin keyword FDC_INSTANCE_NAME : FDC -- synthesis translate_off
434
FDC
generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D);

FDC FDC_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D)); defparam FDC_instance_name.INIT = bit_value;

435
FDC
436
FDC_1
FDC_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
FDC_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D C
FDC_1
FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q). The asynchronous CLR, when active, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 D X 1 0 C X Outputs Q 0 1 0
CLR X3847
Usage
VHDL Inference Code

architecture Behavioral of fdc_1 is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event and C = '0') then Q <= D; end if;
437
FDC_1

always @ (negedge C or posedge CLR) begin if (CLR) Q <= 0; else Q <= D; end

-- Component Declaration for FDC_1 should be placed -- after architecture statement but before begin keyword component FDC_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDC_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDC_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDC_1 should be placed -- in architecture after the begin keyword FDC_1_INSTANCE_NAME : FDC_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D);

FDC_1 FDC_1_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D)); defparam FDC_1_instance_name.INIT = bit_value;
438
FDC_1

BLKNM, HBLKNM, U_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM
439
FDC_1
440
FDCE
FDCE
D Flip-Flop with Clock Enable and Asynchronous Clear
FDCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive
D CE C
FDCE
FDCE is a single D-type flip-flop with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of FDCE is transferred to the corresponding data output (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For XC9500XL and XC9500XV devices, logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDCE and FDPE flip-flops primitives may take advantage of the clock-enable p-term. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 CE X 0 1 1 D X X 1 0 C X X Outputs Q 0 No Chg 1 0
CLR
X3717
Usage
441
FDCE
VHDL Inference Code

architecture Behavioral of fdce is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge CLR or posedge C) begin if (CLR) Q <= 0; else if (CE) Q <= D; end

-- Component Declaration for FDCE should be placed -- after architecture statement but before begin keyword component FDCE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDCE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDCE should be placed -- in architecture after the begin keyword FDCE_INSTANCE_NAME : FDCE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C,
442
FDCE
CE => user_CE, CLR => user_CLR, D => user_D);

FDCE FDCE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D)); defparam FDCE_instance_name.INIT = bit_value;

443
FDCE
444
FDCE_1
FDCE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Clear
FDCE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D CE C
FDCE_1
CLR
X3727
FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q). The asynchronous CLR input, when High, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 0 No Chg 1 0
Usage
VHDL Inference Code

architecture Behavioral of fdce_1 is begin process (C, CLR) begin if (CLR = '1') then
445
FDCE_1
Q <= '0'; elsif (C' event and C = '0') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge CLR or negedge C) begin if (CLR) Q <= 0; else if (CE) Q <= D; end

-- Component Declaration for FDCE_1 should be placed -- after architecture statement but before begin keyword component FDCE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDCE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDCE_1 should be placed -- in architecture after the begin keyword FDCE_1_INSTANCE_NAME : FDCE_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D);
446
FDCE_1

FDCE_1 FDCE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D)); defparam FDCE_1_instance_name.INIT = bit_value;

447
FDCE_1
448
FDCP
FDCP
D Flip-Flop Asynchronous Preset and Clear
FDCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive
PRE
FDCP
Q
FDCP is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low on the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 PRE X 1 0 0 D X X 0 1 C X X Outputs Q 0 1 0 1
CLR X4397
Usage
VHDL Inference Code

architecture Behavioral of fdcp is begin process (C, CLR, PRE) begin if (CLR = '1') then
449
FDCP
Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then Q <= D; end if; end process; end Behavioral;

always @ (posedge CLR or posedge PRE or posedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else Q <= D; end

-- Component Declaration for FDCP should be placed -- after architecture statement but before begin keyword component FDCP -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCP_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDCP should be placed -- in architecture after the begin keyword FDCP_INSTANCE_NAME : FDCP -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D, PRE => user_PRE);
450
FDCP

FDCP FDCP_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCP_instance_name.INIT = bit_value;

451
FDCP
452
FDCP_1
FDCP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and Clear
FDCP_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
Primitive Primitive Primitive No No No
FDCP_1
Q
FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low on the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.
CLR X8357
Inputs CLR 1 0 0 0 PRE X 1 0 0 D X X 0 1 C X X Outputs Q 0 1 0 1
Usage
VHDL Inference Code

architecture Behavioral of fdcp_1 is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0';
453
FDCP_1
elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '0') then Q <= D; end if; end process; end Behavioral;

always @ (posedge CLR or posedge PRE or negedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else Q <= D; end

-- Component Declaration for FDCP_1 should be placed -- after architecture statement but before begin keyword component FDCP_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCP_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCP_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDCP_1 should be placed -- in architecture after the begin keyword FDCP_1_INSTANCE_NAME : FDCP_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D, PRE => user_PRE);
454
FDCP_1

FDCP_1 FDCP_1_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCP_1_instance_name.INIT = bit_value;

455
FDCP_1
456
FDCPE
FDCPE
D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
FDCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Macro Macro Primitive
PRE
D CE C
FDCPE
Q
FDCPE is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied.
CLR X4389
Inputs CLR 1 0 0 0 0 PRE X 1 0 0 0 CE X X 0 1 1 D X X X 0 1 C X X X Outputs Q 0 1 No Chg 0 1
457
FDCPE
VCC
CE AND2 AND2B1
D AND2 PRE OR2
FDCP
D PRE Q
C CLR
C CLR Q
X7804
FDCPE Implementation XC9500/XV/XL, CoolRunner XPLA3
Usage
VHDL Inference Code

architecture Behavioral of fdcpe is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge CLR or posedge PRE or posedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) Q <= D; end

-- Component Declaration for FDCPE should be placed -- after architecture statement but before begin keyword
458
FDCPE
component FDCPE -- synthesis translate_off generic (INIT : bit:= '1'); -- synthesis translate_on port(Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCPE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCPE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDCPE should be placed -- in architecture after the begin keyword FDCPE_INSTANCE_NAME : FDCPE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D, PRE => user_PRE);

FDCPE FDCPE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCPE_instance_name.INIT = bit_value;

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM.
459
FDCPE
460
FDCPE_1
FDCPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset and Clear
FDCPE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
PRE
D CE C
FDCPE_1
Q
FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied.
CLR X8360
Inputs CLR 1 0 0 0 0 PRE X 1 0 0 0 CE X X 0 1 1 D X X X 0 1 C X X X Outputs Q 0 1 No Chg 0 1
Usage
461
FDCPE_1
VHDL Inference Code

architecture Behavioral of fdcpe_1 is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '0') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge CLR or posedge PRE or negedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) Q <= D; end

-- Component Declaration for FDCPE_1 should be placed -- after architecture statement but before begin keyword component FDCPE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCPE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCPE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDCPE_1 should be placed -- in architecture after the begin keyword FDCPE_1_INSTANCE_NAME : FDCPE_1
462
FDCPE_1
-- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D, PRE => user_PRE);

FDCPE_1 FDCPE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCPE_1_instance_name.INIT = bit_value;

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM
463
FDCPE_1
464
FDD
FDD
Dual Edge Triggered D Flip-Flop
FDD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
FDD
No No No No No Macro
D C
FDD is a single dual edge triggered D-type flip-flop with data input (D) and data output (Q). The data on the D input is loaded into the flip-flop during the Low-toHigh and the High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net. See FDD4,8,16 for information on multiple D flip-flops for CoolRunner-II.
X9661
Inputs D 0 1 0 1
FDDCP
D C PRE Q
Outputs C Q 0 1 0 1
D C
CLR Q
GND
X9662
FDD Implementation CoolRunner-II
465
FDD
Usage
VHDL Inference Code

architecture Behavioral of fdd is begin process (C) begin if C' event then Q <= D; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin Q <= D; end

-- Component Declaration for FDD should be placed -- after architecture statement but before begin keyword component FDD -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDD -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDD_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDD should be placed -- in architecture after the begin keyword FDD_INSTANCE_NAME : FDD -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D);
466
FDD

FDD FDD_instance_name (.Q (user_Q), .C (user_C), .D (user_D)); defparam FDD_instance_name.INIT = bit_value;
467
FDD
468
FDD4,8,16
FDD4,8,16
Multiple Dual Edge Triggered D Flip-Flops
FDD4, FDD8, FDD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D0 D1 D2 D3 C
FDD4
Q0 Q1 Q2 Q3
FDD4, FDD8, FDD16 are multiple dual edge triggered D-type flip-flops with data inputs (D) and data outputs (Q). FDD4, FDD8, and FDD16 are, respectively, 4-bit, 8bit, and 16-bit registers, each with a common clock (C). The data on the D inputs is loaded into the flip-flop during the Low-to-High and High-to-Low clock (C) transitions. The flip-flops are asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
X9663
D[7:0]
FDD8
Q[7:0]
Inputs
X9664
Outputs C Qz Q0 0 1 0 1
Dz D0 0
D[15:0]
FDD16
Q[15:0]
1 0 1
X9665
z = 3 for FDD4; z = 7 for FDD8; z = 15 for FDD16
469
FDD4,8,16
Q[7:0]
FDD
D0 D C Q0 Q Q0 D4 D C
FDD
Q Q4
Q4
FDD
FDD
Q Q5
Q5
FDD
FDD
Q Q6
Q6
FDD
D3 D C D[7:0] Q3 Q Q3 D7 D C
FDD
Q Q7
Q7
X9666
FDD8 Implementation CoolRunner-II
Usage
For HDL, these deign elements are inferred rather than instantiated.
VHDL Inference Code

architecture Behavioral of fdd4 is begin process (C) begin if C' event then Q <= D; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin Q[3:0] <= D[3:0] ; end
470
FDD4CE, FDD8CE, FDD16CE

4-, 8-, 16-Bit Dual Edge Triggered Data Registers with Clock Enable and Asynchronous Clear
FDD4CE, FDD8CE, FDD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D0 D1 D2 D3 CE C
FDD4CE
Q0 Q1 Q2 Q3
FDD4CE, FDD8CE, and FDD16CE are, respectively, 4-, 8-, and 16-bit data registers with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q) during the Low-to-High and High-to-Low clock (C) transitions. When CLR is High, it overrides all other inputs and resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
CLR
X9667
D[7:0] CE C
FDD8CE
Q[7:0]
Inputs
CLR
X9668
Outputs Dz D0 X X Dn Dn C X X Qz Q0 0 No Chg Dn Dn
CLR 1
CE X 0 1 1
D[15:0] CE C
FDD16CE
Q[15:0]
0 0 0
CLR
X9669
z = 3 for FDD4CE; z = 7 for FDD8CE; z = 15 for FDD16CE.
471
Q[7:0]
FDDCE FDDCE
FDDCE FDDCE
FDDCE FDDCE
FDDCE FDDCE
D3 D CE C CLR Q3 D[7:0] CE C CLR
X9670
D7 Q Q3
D CE C CLR
Q7
Q7
FDD8CE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 4'b0; else if (CE) Q[3:0] <= D[3:0]; end
472
FDD4RE, FDD8RE, FDD16RE

4-, 8-, 16-Bit Dual Edge Triggered Data Registers with Clock Enable and Synchronous Reset
FDD4RE, FDD8RE, FDD16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D0 D1 D2 D3 CE C
FDD4RE
Q0 Q1 Q2 Q3
R
X9671
FDD4RE, FDD8RE, and FDD16RE are, respectively, 4-, 8-, and 16-bit data registers. When the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during the Low-to-High or High-to-Low clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q) Low on the Low-to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
D[7:0] CE C
FDD8RE
Q[7:0]
Inputs
R
X9672
Outputs Dz D0 X X X Dn Dn C X Qz Q0 0 0 No Chg Dn Dn
R
D[15:0] CE C
CE X X 0 1 1
FDD16RE
Q[15:0]
1 1 0 0 0
X9673
z = 3 for FDD4RE; z = 7 for FDD8RE; z = 15 for FDD16RE
473
Q[7:0]
FDDRE
FDDRE
D CE C R Q4 Q Q4
FDDRE
FDDRE
D CE C R Q5 Q Q5
FDDRE
FDDRE
D CE C R Q6 Q Q6
FDDRE
D3 D CE C R Q3 D[7:0] CE C R Q Q3 D7
FDDRE
D CE C R Q7 Q Q7
X9674
FDD8RE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdd4re is begin process (C) begin if (C' event) then if (CE = '1') then if (R = '1') then Q <= "0000"; else Q <= D; end if; end if; end if; end process; end Behavioral;
474

always @ (posedge C or negedge C) begin if (R) Q <= 4'b0; else if (CE) Q[3:0] <= D[3:0] ; end
475
476
FDDC
FDDC
D Dual Edge Triggered Flip-Flop with Asynchronous Clear
FDDC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D C
FDDC
CLR
X9675
FDDC is a single dual edge triggered D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q). The asynchronous CLR, when High, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low on the Low-to-High and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 D X 1 1 0 0
FDDCP
D C CLR PRE Q
Outputs C X Q 0 1 1 0 0
D C
CLR Q
GND
X9676
FDDC Implementation CoolRunner-II
477
FDDC
Usage
VHDL Inference Code

architecture Behavioral of fddc is begin process (C,CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event) then Q <= D; end if; end process; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 1'b0; else Q <= D ; end

-- Component Declaration for FDDC should be placed -- after architecture statement but before begin keyword component FDDC -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDDC -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDC_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDDC should be placed -- in architecture after the begin keyword FDDC_INSTANCE_NAME : FDDC
478
FDDC
-- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D);

FDDC FDDC_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D)); defparam FDDC_instance_name.INIT = bit_value;
479
FDDC
480
FDDCE
FDDCE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear
FDDCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Primitive
D CE C
FDDCE
CLR
X9677
FDDCE is a single dual edge triggered D-type flip-flop with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of FDDCE is transferred to the corresponding data output (Q) during the Low-to-High and High-to-Low clock (C) transitions. When CLR is High, it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net. Logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDDCE and FDDPE flip-flops primitives may take advantage of the clock-enable p-term.
Inputs CLR 1 0 0 0 0 0 CE X 0 1 1 1 1 D X X 1 0 1 0 C X X
Outputs Q 0 No Chg 1 0 1 0
Usage
481
FDDCE
VHDL Inference Code

architecture Behavioral of fddce is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 1'b0; else if (CE) Q <= D ; end

-- Component Declaration for FDDCE should be placed -- after architecture statement but before begin keyword component FDDCE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDDCE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for FDDCE should be placed -- in architecture after the begin keyword FDDCE_INSTANCE_NAME : FDDCE port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D);
482
FDDCE

FDDCE FDDCE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D));
483
FDDCE
484
FDDCP
FDDCP
Dual EdgeArchitectures Supported Triggered D Flip-Flop Asynchronous Preset and Clear
FDDCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
No No No No No Primitive
FDDCP
Q
FDDCP is a single dual edge triggered D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low on the Low-toHigh and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
CLR
X9678
Inputs CLR 1 0 0 0 0 0 PRE X 1 0 0 0 0 D X X 0 1 0 1 C X X
Outputs Q 0 1 0 1 0 1
Usage
VHDL Inference Code

architecture Behavioral of fddcp is begin process (C, CLR, PRE) begin if (CLR = '1') then
485
FDDCP
Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event) then Q <= D; end if; end process; end Behavioral;

always @ (posedge C or negedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 1'b0; else if (PRE) Q <= 1'b1; else Q <= D ; end

-- Component Declaration for FDDCP should be placed -- after architecture statement but before begin keyword component FDDCP -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDCP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDCP_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDDCP should be placed -- in architecture after the begin keyword FDDCP_INSTANCE_NAME : FDDCP -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D,
486
FDDCP
PRE => user_PRE);

FDDCP FDDCP_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDDCP_instance_name.INIT = bit_value;
487
FDDCP
488
FDDCPE
FDDCPE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
FDDCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Primitive
PRE
D CE C
FDDCPE
Q
FDDCPE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High and High-to-Low clock (C) transitions. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
CLR
X9679
Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 CE X X 0 1 1 1 1 D X X X 0 1 0 1 C X X X
Outputs Q 0 1 No Chg 0 1 0 1
489
FDDCPE
VCC
CE AND2 AND2B1
D AND2 PRE OR2
FDDCP
PRE Q
D C CLR C
CLR Q
X9680
FDDCPE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fddcpe is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 1'b0; else if (PRE) Q <= 1'b1; else if (CE) Q <= D ; end

-- Component Declaration for FDDCPE should be placed -- after architecture statement but before begin keyword
490
FDDCPE
component FDDCPE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDCPE -- should be placed after architecture declaration but -- before the begin keyword
-- Enter values here
-- Component Instantiation for FDDCPE should be placed -- in architecture after the begin keyword FDDCPE_INSTANCE_NAME : FDDCPE port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D, PRE => user_PRE);

FDDCPE FDDCPE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D), .PRE (user_PRE));
491
FDDCPE
492
FDDP
FDDP
Dual Edge Triggered D Flip-Flop with Asynchronous Preset
FDDP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D C
FDDP
FDDP is a single dual edge triggered D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the Low-to-High and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
X9681
Inputs PRE 1 0 0 0 0 C X D X 1 0 1 0
Outputs Q 1 1 0 1 0
PRE D C
FDDCP
PRE Q
D C
CLR Q
GND
X9682
FDDP Implementation CoolRunner-II
493
FDDP
Usage
For HDL, this design element can be inferred or instantiated.
VHDL Inference Code

architecture Behavioral of fddp is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event) then Q <= D; end if; end process; end Behavioral;

always @ (posedge C or negedge C or posedge PRE) begin if (PRE) Q <= 1'b1; else Q <= D ; end

-- Component Declaration for FDDP should be placed -- after architecture statement but before begin keyword component FDDP -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDP_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDDP should be placed -- in architecture after the begin keyword FDDP_INSTANCE_NAME : FDDP -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on
494
FDDP
port map (Q => user_Q, C => user_C, D => user_D, PRE => user_PRE);

FDDP FDDP_instance_name (.Q (user_Q), .C (user_C), .D (user_D), .PRE (user_PRE)); defparam FDDP_instance_name.INIT = bit_value;
495
FDDP
496
FDDPE
FDDPE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset
FDDPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
No No No No No Primitive
D CE C
FDDPE
FDDPE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the Low-toHigh and High-to-Low clock (C) transitions. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net. Logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDDCE and FDDPE flip-flops primitives may take advantage of the clock-enable p-term.
X9683
Inputs PRE 1 0 0 0 0 0 CE X 0 1 1 1 1 D X X 0 1 0 1 C X X
Outputs Q 1 No Chg 0 1 0 1
Usage
497
FDDPE
VHDL Inference Code

architecture Behavioral of fddpe is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C or posedge PRE) begin if (PRE) Q <= 1'b1; else if (CE) Q <= D ; end

-- Component Declaration for FDDPE should be placed -- after architecture statement but before begin keyword component FDDPE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDPE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here -- Component Instantiation for FDDPE should be placed -- in architecture after the begin keyword FDDPE_INSTANCE_NAME : FDDPE port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, PRE => user_PRE);

FDDPE FDDPE_instance_name (.Q (user_Q),
498
FDDPE
.C (user_C), .CE (user_CE), .D (user_D), .PRE (user_PRE)); defparam FDDPE_instance_name.INIT = bit_value;
499
FDDPE
500
FDDR
FDDR
Dual Edge Triggered D Flip-Flop with Synchronous Reset
FDDR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D C
FDDR
X9684
FDDR is a single dual edge triggered D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High and Highto-Low clock (C) transitions. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High or High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 D X X 1 0 1 0
FDD
D_R AND2B1 C
X9685
Outputs C Q 0 0 1 0 1 0
D R C
FDDR Implementation CoolRunner-II
Usage
501
FDDR
VHDL Inference Code

architecture Behavioral of fddr is begin process (C) begin if (C' event) then if (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else Q <= D ; end
502
FDDRCPE
FDDRCPE
Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
FDDRCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE D0 D1 CE C0 C1 CLR X9399 FDDRCPE Q
FDDRCPE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). It also has clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D0 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C1 clock transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. Use the INIT attribute to initialize FDDRCPE during configuration.
Inputs C0 X X X X X C1 X X X X X CE X X X 0 1 1 D0 X X X X D0 X D1 X X X X X D1 CLR 1 0 1 0 0 0 PRE 0 1 1 0 0 0
Outputs Q 0 1 0 No Chg D0 D1
Usage
For HDL, this design element is instantiated rather than inferred.
503
FDDRCPE

-- Component Declaration for FDDRCPE should be placed -- after architecture statement but before begin keyword component FDDRCPE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDRCPE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDRCPE_instance_name : label is "0"; -- values can be (0 or 1) -- Component Instantiation for FDDRCPE should be placed -- in architecture after the begin keyword FDDRCPE_INSTANCE_NAME : FDDRCPE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C0 => user_C0, C1 => user_C1, CE => user_CE, CLR => user_CLR, D0 => user_D0, D1 => user_D1, PRE => user_PRE);
504
FDDRCPE

FDDRCPE FDDRCPE_instance_name (.Q (user_Q), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .CLR (user_CLR), .D0 (user_D0), .D1 (user_D1), .PRE (user_PRE)); defparam FDDRCPE_instance_name.INIT = bit_value;
505
FDDRCPE
506
FDDRE
FDDRE
Dual Edge Triggered D Flip-Flop with Clock Enable and Synchronous Reset
FDDRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D CE C
FDDRE
X9686
FDDRE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High or High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High and High-toLow clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 0 CE X X 0 1 1 1 1 D X X X 1 0 1 0 C X Outputs Q 0 0 No Chg 1 0 1 0
507
FDDRE
VCC
CE AND2 R AND3B2
D D
FDD
OR2 AND3B1 Q Q
C Q
X9687
FDDRE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fddre is begin process (C) begin if (C event) then if (R = 1) then Q <= 0; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else if (CE) Q <= D ; end
508
FDDRRSE
FDDRRSE
Dual Data Rate D Flip-Flop with Clock Enable and Synchronous Reset and Set
FDDRRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S D0 D1 CE C0 C1 R X9254 FDDRRSE Q
FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). It also has synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during any Low-to-High clock transition (C0 or C1). (Reset has precedence over Set.) When the S input is High and R is Low, the flip-flop is set, output High, during a Low-to-High clock transition (C0 or C1). Data on the D0 input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High C1 clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Use the INIT attribute to initialize FDDRRSE during configuration.
Inputs C0 X X X X X C1 X X X X X CE X X X X X X 0 1 1 D0 X X X X X X X D0 X D1 X X X X X X X X D1 R 1 0 1 1 0 1 0 0 0 S 0 1 1 0 1 1 0 0 0
Outputs Q 0 1 0 0 1 0 No Chg D0 D1
Usage
509
FDDRRSE

-- Component Declaration for FDDRRSE should be placed -- after architecture statement but before begin keyword component FDDRRSE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDDRRSE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDRRSE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDDRRSE should be placed -- in architecture after the begin keyword FDDRRSE_INSTANCE_NAME : FDDRRSE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C0 => user_C0, C1 => user_C1, CE => user_CE, D0 => user_D0, D1 => user_D1, R => user_R, S => user_S);
510
FDDRRSE

FDDRRSE FDDRRSE_instance_name (.Q (user_Q), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .D0 (user_D0), .D1 (user_D1), .R (user_R), .S (user_S)); defparam FDDRRSE_instance_name.INIT = bit_value;
511
FDDRRSE
512
FDDRS
FDDRS
Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set
FDDRS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D C
FDDRS
X9688
FDDRS is a single dual edge triggered D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High or High-to-Low clock (C) transitions. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the Low-toHigh or High-to-Low clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High and High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 0 0 S X X 1 1 0 0 0 0 D X X X X 1 1 0 0 C Outputs Q 0 0 1 1 1 1 0 0
D R AND2B1 S AND2B1 C OR2 D C Q

X9689
FDD
Q Q
FDDRS Implementation CoolRunner-II
513
FDDRS
Usage
VHDL Inference Code

architecture Behavioral of fddrs is begin process (C) begin if (C' event) then if (R = '1') then Q <= '0'; elsif (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else if (S) Q <= 1'b1; else Q <= D ; end

-- Component Declaration for FDDRS should be placed -- after architecture statement but before begin keyword component FDDRS -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDDRS -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string;
514
FDDRS
attribute INIT of FDDRS_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDDRS should be placed -- in architecture after the begin keyword FDDRS_INSTANCE_NAME : FDDRS -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R, S => user_S);

FDDRS FDDRS_instance_name (.Q .C .D .R .S (user_Q), (user_C), (user_D), (user_R), (user_S));
defparam FDDRS_instance_name.INIT = bit_value;
515
FDDRS
516
FDDRSE
FDDRSE
Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set and Clock Enable
FDDRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D CE C
FDDRSE
X9690
FDDRSE is a single dual edge triggered D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High or High-to-Low clock transitions. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High or High-to-Low clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High and Highto-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 0 0 0 S X X 1 1 0 0 0 0 0 CE X X X X 0 1 1 1 1 D X X X X X 1 0 1 0 C X
Outputs Q 0 0 1 1 No Chg 1 0 1 0
517
FDDRSE
VCC CE AND2 S OR3 AND2B1
D AND2 R C AND2B1 C D
FDD
Q Q
X9691
FDDRSE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fddrse is begin process (C) begin if (C event) then if (R = 1) then Q <= 0; elsif (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else if (S) Q <= 1'b1; else if (CE) Q <= D ; end
518
FDDS
FDDS
Dual Edge Triggered D Flip-Flop with Synchronous Set
FDDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D C
FDDS
FDDS is a single dual edge triggered D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q output High on the Low-to-High or High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low during the Low-to-High and Highto-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
X9692
Inputs S 1 1 0 0 0 0 D X X 1 0 1 0 C
Outputs Q 1 1 1 0 1 0
D S C OR2 D
FDD
Q Q
C Q
X9693
FDDS Implementation CoolRunner-II
Usage
519
FDDS
VHDL Inference Code

architecture Behavioral of fdds is begin process (C) begin if (C' event) then if (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else Q <= D ; end
520
FDDSE
FDDSE
D Flip-Flop with Clock Enable and Synchronous Set
FDDSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D CE C
FDDSE
X9694
FDDSE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the Low-to-High or High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the Low-to-High and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs S 1 1 0 0 0 0 0 CE X X 0 1 1 1 1 D X X X 1 0 1 0 C X
Outputs Q 1 1 No Chg 1 0 1 0
521
FDDSE
D AND2 D C
FDD
Q Q Q
C Q
X9695
FDDSE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fddse is begin process (C) begin if (C event) then if (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else if (CE) Q <= D ; end
522
FDDSR
FDDSR
Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset
FDDSR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D C
FDDSR
R
X9696
FDDSR is a single dual edge triggered D-type flip-flop with data (D), synchronous reset (R) and synchronous set (S) inputs and data output (Q). When the set (S) input is High, it overrides all other inputs and sets the Q output High during the Low-to-High or High-to-Low clock transition. (Set has precedence over Reset.) When reset (R) is High and S is Low, the flip-flop is reset, output Low, on the Low-to-High or High-toLow clock transition. Data on the D input is loaded into the flip-flop when S and R are Low on the Low-to-High and High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs S 1 1 0 0 0 0 0 0 R X X 1 1 0 0 0 0 D X X X X 1 0 1 0 C
Outputs Q 1 1 0 0 1 0 1 0
D R AND2B1 S C OR2 C Q
X9697
FDD
D Q Q
FDDSR Implementation CoolRunner-II
523
FDDSR
Usage
VHDL Inference Code

architecture Behavioral of fddsr is begin process (C) begin if (C' event) then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else if (R) Q <= 1'b0; else Q <= D; end
524
FDDSRE
FDDSRE
Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset and Clock Enable
FDDSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D CE C
FDDSRE
R
X9698
FDDSRE is a single dual edge triggered D-type flip-flop with synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, it overrides all other inputs and sets the Q output High during the Low-to-High or High-to-Low clock transition. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low during the Low-to-High or High-to-Low clock transition. Data is loaded into the flipflop when S and R are Low and CE is High during the Low-to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs S 1 1 0 0 0 0 0 0 0 R X X 1 1 0 0 0 0 0 CE X X X X 0 1 1 1 1 D X X X X X 1 0 1 0 C X
Outputs Q 1 1 0 0 No Chg 1 0 1 0
525
FDDSRE
VCC
CE AND2 R AND3B2 S OR3 D C D
FDD
Q Q
AND3B1 C
X9699
FDDSRE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fddsre is begin process (C) begin if (C' event) then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; elsif (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else if (R) Q <= 1'b0; else if (CE) Q <= D; end
526
FDE
FDE
D Flip-Flop with Clock Enable
FDE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D CE C
FDE
Q
FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q). When clock enable is High, the data on the D input is loaded into the flipflop during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.
X8361
Inputs CE 0 1 1 D X 0 1 C X Outputs Q No Chg 0 1
Usage
VHDL Inference Code

architecture Behavioral of fde is begin process (C) begin if (C' event and C='1') then if (CE = '1') then Q <= D; end if; end if;
527
FDE

always @ (posedge C) begin if (CE) Q <= D; end

-- Component Declaration for FDE should be placed -- after architecture statement but before begin keyword component FDE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDE should be placed -- in architecture after the begin keyword FDE_INSTANCE_NAME : FDE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D);

FDE FDE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D)); defparam FDE_instance_name.INIT = bit_value;
528
FDE

529
FDE
530
FDE_1
FDE_1
D Flip-Flop with Negative-Edge Clock and Clock Enable
FDE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D CE C
FDE_1
Q
FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q). When clock enable is High, the data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.
X8362
Inputs CE 0 1 1 D X 0 1 C X Outputs Q No Chg 0 1
Usage
VHDL Inference Code

architecture Behavioral of fde_1 is begin process (C) begin if (C' event and C='0') then if (CE = '1') then Q <= D; end if; end if;
531
FDE_1

always @ (negedge C) begin if (CE) Q <= D; end

-- Component Declaration for FDE_1 should be placed -- after architecture statement but before begin keyword component FDE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDE_1 should be placed -- in architecture after the begin keyword FDE_1_INSTANCE_NAME : FDE_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D);

FDE_1 FDE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D)); defparam FDE_1_instance_name.INIT = bit_value;
532
FDE_1

BLKNM, HBLKNM, HU_SET,INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM
533
FDE_1
534
FDP
FDP
D Flip-Flop with Asynchronous Preset
FDP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
Primitive Primitive Primitive Macro Macro Macro
D C
FDP
FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the Low-to-High clock (C) transition. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 C X D X 1 0 Outputs Q 1 1 0
X3720
535
FDP
PRE D C
FDCP
PRE Q
D C
CLR Q
GND
X7805
FDP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdp is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then Q <= D; end if; end process; end Behavioral;

always @ (posedge PRE or posedge C) begin if (PRE) Q <= 1; else Q <= D; end

-- Component Declaration for FDP should be placed -- after architecture statement but before begin keyword component FDP -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDP
536
FDP
-- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDP_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDP should be placed -- in architecture after the begin keyword FDP_INSTANCE_NAME : FDP -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, PRE => user_PRE);

FDP FDP_instance_name (.Q (user_Q), .C (user_C), .D (user_D), .PRE (user_PRE)); defparam FDP_instance_name.INIT = bit_value;

537
FDP
538
FDP_1
FDP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
FDP_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D C
FDP_1
FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the High-to-Low clock (C) transition. The flip-flop is asynchronously preset, output High, when power is applied.
X3728
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 C X D X 1 0 Outputs Q 1 1 0
Usage
VHDL Inference Code

architecture Behavioral of fdp_1 is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event and C = '0') then Q <= D; end if;
539
FDP_1

always @ (posedge PRE or negedge C) begin if (PRE) Q <= 1; else Q <= D; end

-- Component Declaration for FDP_1 should be placed -- after architecture statement but before begin keyword component FDP_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDP_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDP_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDP_1 should be placed -- in architecture after the begin keyword FDP_1_INSTANCE_NAME : FDP_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, PRE => user_PRE);

FDP_1 FDP_1_instance_name (.Q (user_Q), .C (user_C), .D (user_D), .PRE (user_PRE)); defparam FDP_1_instance_name.INIT = bit_value;
540
FDP_1

541
FDP_1
542
FDPE
FDPE
D Flip-Flop with Clock Enable and Asynchronous Preset
FDPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D CE C
FDPE
FDPE is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For XC9500XL and XC9500XV devices, logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDCE and FDPE flip-flop primitives may take advantage of the clock-enable p-term. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. These devices simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 CE X 0 1 1 D X X 0 1 C X X Outputs Q 1 No Chg 0 1
X3721
543
FDPE
Usage
VHDL Inference Code

architecture Behavioral of fdpe is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge PRE or posedge C) begin if (PRE) Q <= 1; else if (CE) Q <= D; end

-- Component Declaration for FDPE should be placed -- after architecture statement but before begin keyword component FDPE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDPE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDPE_instance_name : label is "0"; -- values can be (0 or 1)
544
FDPE
-- Component Instantiation for FDPE should be placed -- in architecture after the begin keyword FDPE_INSTANCE_NAME : FDPE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, PRE => user_PRE);

FDPE FDPE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .PRE (user_PRE)); defparam FDPE_instance_name.INIT = bit_value;

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM
545
FDPE
546
FDPE_1
FDPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset
FDPE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
PRE
D CE C
FDPE_1
FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-III, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 CE X 0 1 1 D X X 1 0 C X X Outputs Q 1 No Chg 1 0
X3852
Usage
VHDL Inference Code

architecture Behavioral of fdpe_1 is begin process (C,PRE) begin if (PRE = '1') then
547
FDPE_1
Q <= '1'; elsif (C' event and C = '0') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge PRE or negedge C) begin if (PRE) Q <= 1; else if (CE) Q <= D; end

-- Component Declaration for FDPE_1 should be placed -- after architecture statement but before begin keyword component FDPE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDPE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDPE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDPE_1 should be placed -- in architecture after the begin keyword -FDPE_1_INSTANCE_NAME : FDPE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, PRE => user_PRE);
548
FDPE_1

FDPE_1 FDPE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .PRE (user_PRE)); defparam FDPE_1_instance_name.INIT = bit_value;

549
FDPE_1
550
FDR
FDR
D Flip-Flop with Synchronous Reset
FDR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro
D C
FDR
X3718
FDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 D X 1 0 C Outputs Q 0 1 0
Usage
VHDL Inference Code

architecture Behavioral of fdr is begin process (C) begin if (C' event and C = '1') then
551
FDR
if (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else Q <= D; end

-- Component Declaration for FDR should be placed -- after architecture statement but before begin keyword component FDR -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDR -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDR_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDR should be placed -- in architecture after the begin keyword FDR_INSTANCE_NAME : FDR -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R);
552
FDR

FDR FDR_instance_name (.Q .C .D .R (user_Q), (user_C), (user_D), (user_R));
defparam FDR_instance_name.INIT = bit_value;

553
FDR
554
FDR_1
FDR_1
D Flip-Flop with Negative-Edge Clock and Synchronous Reset
FDR_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
FDR_1
Q C
R X8363
FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the High-to-Low clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 D X 1 0 C Outputs Q 0 1 0
Usage
VHDL Inference Code

architecture Behavioral of fdr_1 is begin process (C) begin if (C' event and C = '0') then if (R = '1') then Q <= '0'; else
555
FDR_1
Q <= D; end if; end if; end process; end Behavioral;

always @ (negedge C) begin if (R) Q <= 0; else Q <= D; end

-- Component Declaration for FDR_1 should be placed -- after architecture statement but before begin keyword component FDR_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDR_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDR_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDR_1 should be placed -- in architecture after the begin keyword FDR_1_INSTANCE_NAME : FDR_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R);
556
FDR_1

FDR_1 FDR_1_instance_name (.Q .C .D .R (user_Q), (user_C), (user_D), (user_R));
defparam FDR_1_instance_name.INIT = bit_value;

557
FDR_1
558
FDRE
FDRE
D Flip-Flop with Clock Enable and Synchronous Reset
FDRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro
D CE C
FDRE
X3719
FDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 0 No Chg 1 0
559
FDRE
VCC
CE AND2 R AND3B2
D D
FD
OR2 AND3B1 Q Q
C Q
X7808
FDRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdre is begin process (C) begin if (C event and C = 1) then if (R = 1) then Q <= 0; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (CE) Q <= D; end

-- Component Declaration for FDRE should be placed -- after architecture statement but before begin keyword component FDRE -- synthesis translate_off generic (
560
FDRE
INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDRE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDRE should be placed -- in architecture after the begin keyword FDRE_INSTANCE_NAME : FDRE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R);

FDRE FDRE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R)); defparam FDRE_instance_name.INIT = bit_value;

561
FDRE
562
FDRE_1
FDRE_1
D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset
FDRE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
FDRE_1
Q
D CE C
R X8364
FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the High-to-Low clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 0 No Chg 1 0
Usage
VHDL Inference Code

architecture Behavioral of fdre_1 is begin process (C) begin if (C event and C = 0) then
563
FDRE_1
if (R = 1) then Q <= 0; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (negedge C) begin if (R) Q <= 0; else if (CE) Q <= D; end

-- Component Declaration for FDRE_1 should be placed -- after architecture statement but before begin keyword component FDRE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDRE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDRE_1 should be placed -- in architecture after the begin keyword FDRE_1_INSTANCE_NAME : FDRE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R);
564
FDRE_1

FDRE_1 FDRE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R)); defparam FDRE_1_instance_name.INIT = bit_value;

565
FDRE_1
566
FDRS
FDRS
D Flip-Flop with Synchronous Reset and Set
FDRS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D C
FDRS
X3731
FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flipflop is set, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 S X 1 0 0 D X X 1 0 C Outputs Q 0 1 1 0
567
FDRS
D R AND2B1 S AND2B1 C OR2 D C Q X7811
FD
Q Q
FDRS Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdrs is begin process (C) begin if (C' event and C = '1') then if (R = '1') then Q <= '0'; elsif (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else Q <= D; end

-- Component Declaration for FDRS should be placed -- after architecture statement but before begin keyword component FDRS -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC;
568
FDRS
C : in D : in R : in S : in end component;
STD_ULOGIC; STD_ULOGIC; STD_ULOGIC; STD_ULOGIC);
-- Component Attribute specification for FDRS -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRS_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDRS should be placed -- in architecture after the begin keyword FDRS_INSTANCE_NAME : FDRS -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R, S => user_S);

FDRS FDRS_instance_name (.Q .C .D .R .S (user_Q), (user_C), (user_D), (user_R), (user_S));
defparam FDRS_instance_name.INIT = bit_value;

569
FDRS
570
FDRS_1
FDRS_1
D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set
FDRS_1
Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
FDRS_1
Q
R X8365
FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Highto-Low clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the High-to-Low clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the High-toLow clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 S X 1 0 0 D X X 1 0 C Outputs Q 0 1 1 0
Usage
571
FDRS_1
VHDL Inference Code

architecture Behavioral of fdrs_1 is begin process (C) begin if (C' event and C = '0') then if (R = '1') then Q <= '0'; elsif (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else Q <= D; end

-- Component Declaration for FDRS_1 should be placed -- after architecture statement but before begin keyword component FDRS_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDRS_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRS_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDRS_1 should be placed -- in architecture after the begin keyword FDRS_1_INSTANCE_NAME : FDRS_1
572
FDRS_1
-- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R, S => user_S);

FDRS_1 FDRS_1_instance_name (.Q .C .D .R .S (user_Q), (user_C), (user_D), (user_R), (user_S));
defparam FDRS_1_instance_name.INIT = bit_value;

573
FDRS_1
574
FDRSE
FDRSE
D Flip-Flop with Synchronous Reset and Set and Clock Enable
FDRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro
D CE C
FDRSE
X3732
FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 S X 1 0 0 0 CE X X 0 1 1 D X X X 1 0 C X Outputs Q 0 1 No Chg 1 0
575
FDRSE
D AND2 R C AND2B1 C D
FD
Q Q
FDRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdrse is begin process (C) begin if (C event and C = 1) then if (R = 1) then Q <= 0; elsif (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE) Q <= D; end
576
FDRSE

-- Component Declaration for FDRSE should be placed -- after architecture statement but before begin keyword component FDRSE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDRSE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRSE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDRSE should be placed -- in architecture after the begin keyword FDRSE_INSTANCE_NAME : FDRSE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R, S => user_S);

FDRSE FDRSE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R), .S (user_S)); defparam FDRSE_instance_name.INIT = bit_value;

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET and XBLKNM
577
FDRSE
578
FDRSE_1
FDRSE_1
D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set, and Clock Enable
FDRSE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D CE C
FDRSE_1
Q
R X8366
FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the High-to-Low clock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the High-to-Low clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the High-to-Low clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 S X 1 0 0 0 CE X X 0 1 1 D X X X 1 0 C X Outputs Q 0 1 No Chg 1 0
Usage
579
FDRSE_1
VHDL Inference Code

architecture Behavioral of fdrse_1 is begin process (C) begin if (C event and C = 0) then if (R = 1) then Q <= 0; elsif (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else Q => D; end

-- Component Declaration for FDRSE_1 should be placed -- after architecture statement but before begin keyword component FDRSE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDRSE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRSE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDRSE_1 should be placed -- in architecture after the begin keyword
580
FDRSE_1
FDRSE_1_INSTANCE_NAME : FDRSE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R, S => user_S);

FDRSE_1 FDRSE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R), .S (user_S)); defparam FDRSE_1_instance_name.INIT = bit_value;

581
FDRSE_1
582
FDS
FDS
D Flip-Flop with Synchronous Set
FDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D C
FDS
FDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q output High on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low during the Low-to-High clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. For all other devices (XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II), the flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDS will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 D X 1 0 C Outputs Q 1 1 0
X3722
Usage
583
FDS
VHDL Inference Code

architecture Behavioral of fds is begin process (C) begin if (C' event and C = '1') then if (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) begin if (S) Q <= 1; else Q <= D; end

-- Component Declaration for FDS should be placed -- after architecture statement but before begin keyword component FDS -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDS -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDS_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDS should be placed -- in architecture after the begin keyword FDS_INSTANCE_NAME : FDS -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q,
584
FDS
C => user_C, D => user_D, S => user_S);

FDS FDS_instance_name (.Q .C .D .S (user_Q), (user_C), (user_D), (user_S));
defparam FDS_instance_name.INIT = bit_value;

585
FDS
586
FDS_1
FDS_1
D Flip-Flop with Negative-Edge Clock and Synchronous Set
FDS_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
FDS_1
Q
FDS_1 is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q output High on the High-to-Low clock (C) transition. The data on the D input is loaded into the flipflop when S is Low during the High-to-Low clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDS_1 will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 D X 1 0 C Outputs Q 1 1 0
X8367
Usage
VHDL Inference Code

architecture Behavioral of fds_1 is begin process (C) begin if (C' event and C = '0') then
587
FDS_1
if (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (negedge C) begin if (S) Q <= 1; else Q <= D; end

-- Component Declaration for FDS_1 should be placed -- after architecture statement but before begin keyword component FDS_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDS_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDS_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDS_1 should be placed -- in architecture after the begin keyword FDS_1_INSTANCE_NAME : FDS_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, S => user_S);
588
FDS_1

FDS_1 FDS_1_instance_name (.Q .C .D .S (user_Q), (user_C), (user_D), (user_S));
defparam FDS_1_instance_name.INIT = bit_value;

589
FDS_1
590
FDSE
FDSE
D Flip-Flop with Clock Enable and Synchronous Set
FDSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D CE C
FDSE
FDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the Low-to-High clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. For all other devices (XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II), the flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDSE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 1 No Chg 1 0
X3723
591
FDSE
D AND2 D C C
FD
Q Q Q
Q
X7815
FDSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdse is begin process (C) begin if (C event and C = 1) then if (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) begin if (S) Q <= 1; else if (CE) Q <= D; end
592
FDSE

-- Component Declaration for FDSE should be placed -- after architecture statement but before begin keyword component FDSE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDSE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDSE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDSE should be placed -- in architecture after the begin keyword FDSE_INSTANCE_NAME : FDSE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, S => user_S);

FDSE FDSE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .S (user_S)); defparam FDSE_instance_name.INIT = bit_value;
593
FDSE

594
FDSE_1
FDSE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set
FDSE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D CE C
FDSE_1
Q
FDSE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the High-toLow clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the High-to-Low clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDSE_1 will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 1 No Chg 1 0
X8368
Usage
595
FDSE_1
VHDL Inference Code

architecture Behavioral of fdse_1 is begin process (C) begin if (C event and C = 0) then if (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

always @ (negedge C) begin if (S) Q <= 1; else if (CE) Q <= D; end

-- Component Declaration for FDSE_1 should be placed -- after architecture statement but before begin keyword component FDSE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDSE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDSE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for FDSE_1 should be placed -- in architecture after the begin keyword
FDSE_1_INSTANCE_NAME : FDSE_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on
596
FDSE_1
port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, S => user_S);

FDSE_1 FDSE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .S (user_S)); defparam FDSE_1_instance_name.INIT = bit_value;

597
FDSE_1
598
FDSR
FDSR
D Flip-Flop with Synchronous Set and Reset
FDSR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D C
FDSR
X3729
FDSR is a single D-type flip-flop with data (D), synchronous reset (R) and synchronous set (S) inputs and data output (Q). When the set (S) input is High, it overrides all other inputs and sets the Q output High during the Low-to-High clock transition. (Set has precedence over Reset.) When reset (R) is High and S is Low, the flip-flop is reset, output Low, on the Low-to-High clock transition. Data on the D input is loaded into the flip-flop when S and R are Low on the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs S 1 0 0 0
D R AND2B1 S C OR2 C Q X7817 D
Outputs D X X 1 0 C Q 1 0 1 0
R X 1 0 0
FD
Q Q
FDSR Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
599
FDSR
VHDL Inference Code

architecture Behavioral of fdsr is begin process (C) begin if (C' event and C = '1') then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) if (S) Q <= else if (R) Q <= else Q <= end begin 1; 0; D;
600
FDSRE
FDSRE
D Flip-Flop with Synchronous Set and Reset and Clock Enable
FDSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D CE C
FDSRE
X3730
FDSRE is a single D-type flip-flop with synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, it overrides all other inputs and sets the Q output High during the Low-to-High clock transition. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low during the Low-to-High clock transition. Data is loaded into the flip-flop when S and R are Low and CE is High during the Low-to-high clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs S 1 0 0 0 0 R X 1 0 0 0 CE X X 0 1 1 D X X X 1 0 C X Outputs Q 1 0 No Chg 1 0
601
FDSRE
VCC
CE AND2 R AND3B2 S OR3 D C D
FD
Q Q
AND3B1 C
X7819
FDSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fdsre is begin process (C) begin if (C' event and C = '1') then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; elsif (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (posedge C) if (S) Q <= else if (R) Q <= else if (CE) Q <= end begin 1; 0; D;
602
FJKC
FJKC
J-K Flip-Flop with Asynchronous Clear
FJKC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
J K C
FJKC
Q
FJKC is a single J-K-type flip-flop with J, K, and asynchronous clear (CLR) inputs and data output (Q). The asynchronous clear (CLR) input, when High, overrides all other inputs and resets the Q output Low. When CLR is Low, the output responds to the state of the J and K inputs, as shown in the following truth table, during the Low-toHigh clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 J X 0 0 1 1 K X 0 1 0 1 C X Outputs Q 0 No Chg 0 1 Toggle
CLR
X3753
603
FJKC
AND3B2
A0 A1 A2 AD OR3
AND3B1 J K AND2B1 C CLR
FDC
D C CLR Q Q
X7820
FJKC Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
K AND2B1
FDC
J AND2B1 C CLR OR2 C CLR Q X7821 D Q Q
FJKC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fjkc is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q;
604
FJKC
end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end
605
FJKC
606
FJKCE
FJKCE
J-K Flip-Flop with Clock Enable and Asynchronous Clear
FJKCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
J K CE C
FJKCE
Q
CLR
X3756
FJKCE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous clear (CLR), when High, overrides all other inputs and resets the Q output Low. When CLR is Low and CE is High, Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 CE X 0 1 1 1 1 J X X 0 0 1 1 K X X 0 1 0 1 C X X X Outputs Q 0 No Chg No Chg 0 1 Toggle
607
FJKCE
AND3B2
A0 A1 A2 AD OR3
AND3B1 J K AND2B1
FDCE
D CE C CLR X7822 CE C CLR Q Q
FJKCE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X
VCC
CE AND2 AND2B1 J
FDC
AND3B1 K AND2B1 C CLR
X782
D OR3 C CLR
FJKCE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fjkce is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then
608
FJKCE
if (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end
609
FJKCE
610
FJKCP
FJKCP
J-K Flip-Flop with Asynchronous Clear and Preset
FJKCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
J K C
FJKCP
Q
CLR
FJKCP is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), and asynchronous preset (PRE) inputs and data output (Q). When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. The asynchronous preset (PRE), when High, and CLR set to Low overrides all other inputs and sets the Q output High. When CLR and PRE are Low, Q responds to the state of the J and K inputs during the Low-to-High clock transition, as shown in the following truth table. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 0 PRE X 1 0 0 0 0 J X X 0 0 1 1 K X X 0 1 0 1 C X X X Outputs Q 0 1 No Chg 0 1 Toggle
X4390
611
FJKCP
AND2B1 PRE
FDCP
PRE Q
D K OR2 AND2B1 C CLR C
CLR Q
X8124
FJKCP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fjkcp is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1;
612
FJKCP
else begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end
613
FJKCP
614
FJKCPE
FJKCPE
J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable
FJKCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
J K CE C
FJKCPE
Q
CLR X4391
FJKCPE is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), asynchronous preset (PRE), and clock enable (CE) inputs and data output (Q). When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. The asynchronous preset (PRE), when High, and CLR set to Low overrides all other inputs and sets the Q output High. When CLR and PRE are Low and CE is High, Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition. Clock transitions are ignored when CE is Low. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 CE X X 0 1 1 1 1 J X X 0 0 0 1 1 K X X X 0 1 0 1 C X X X X Outputs Q 0 1 No Chg No Chg 0 1 Toggle
615
FJKCPE
VCC 5
CE AND2B1 J AND2
FDCP
PRE D AND3B1 OR3 C CLR AND2B1 Q Q Q
K PRE C CLR
X7687
FJKCPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fjkcpe is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;
616
FJKCPE

always @(posedge C or posedge CLR begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) begin if (!J) begin if (K) Q end else begin if (!K) Q else Q end end end or posedge PRE)
<= 0;
<= 1; <= !Q;
617
FJKCPE
618
FJKP
FJKP
J-K Flip-Flop with Asynchronous Preset
FJKP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
J K C
FJKP
Q
FJKP is a single J-K-type flip-flop with J, K, and asynchronous preset (PRE) inputs and data output (Q). The asynchronous preset (PRE) input, when High, overrides all other inputs and sets the Q output High. When PRE is Low, the Q output responds to the state of the J and K inputs, as shown in the following truth table, during the Low-toHigh clock transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs PRE 1 0 0 0 0 J X 0 0 1 1 K X 0 1 0 1 C X X Outputs Q 1 No Chg 0 1 Toggle
X3754
619
FJKP
AND3B2
A0 A1 A2 AD OR3
AND3B1 J K AND2B1 PRE
FDP
D PRE Q
C RLOC=R0C0 X7824
FJKP Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
AND3B2
A0 A1 A2 AD
OR3
FDP
PRE D Q Q
C RLOC=X0Y0 X9317
FJKP Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

J
AND2B1 PRE
FDP
PRE Q
D K OR2 AND2B1 C C
X8125
FJKP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
620
FJKP
Usage
VHDL Inference Code

architecture Behavioral of fjkp is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end
621
FJKP
622
FJKPE
FJKPE
J-K Flip-Flop with Clock Enable and Asynchronous Preset
FJKPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
PRE
J K CE C
FJKPE
Q
FJKPE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous preset (PRE), when High, overrides all other inputs and sets the Q output High. When PRE is Low and CE is High, the Q output responds to the state of the J and K inputs, as shown in the truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs PRE 1 0 0 0 0 0 CE X 0 1 1 1 1 J X X 0 0 1 1 K X X 0 1 0 1 C X X X Outputs Q 1 No Chg No Chg 0 1 Toggle
X3757
623
FJKPE
AND3B2
A0 A1 A2 AD OR3
FDPE
D CE C RLOC=R0C0 X7825 PRE Q
CE C
FJKPE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
AND3B2
A0 A1 A2 AD OR3
FDPE
D PRE Q Q
CE C
CE C RLOC=X0Y0 X9318
FJKPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
624
FJKPE
VCC
CE AND2 K AND2B1 J AND3B1 OR3 C AND2B1
FDP
D PRE Q
C PRE
X7826
FJKPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of fjkpe is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (CE)
625
FJKPE
begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end
626
FJKRSE
FJKRSE
J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
FJKRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
J K CE C
FJKRSE
Q
FJKRSE is a single J-K-type flip-flop with J, K, synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). When synchronous reset (R) is High, all other inputs are ignored and output Q is reset Low. (Reset has precedence over Set.) When synchronous set (S) is High and R is Low, output Q is set High. When R and S are Low and CE is High, output Q responds to the state of the J and K inputs, according to the following truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 0 0 S X 1 0 0 0 0 0 CE X X 0 1 1 1 1 J X X X 0 0 1 1 K X X X 0 1 1 0 C X X Outputs Q 0 1 No Chg No Chg 0 Toggle 1
X3760
627
FJKRSE
AND3B2
A0 A1 A2 AD_S
AND3B1 J K AND2B1 S CE C R RLOC=R0C0 X7827 OR2 S_CE D CE C R OR4
FDRE
Q Q
FJKRSE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
AND3B2
A0 A1 A2 AD_S OR4
AND3B1 J K S CE C R AND2B1
FDRE
D S_CE OR2 CE C R RLOC=X0Y0 X9319 Q Q
FJKRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro

VCC
CE K S AND2
AND4B1
AND3B3 D J AND3B3 R NOR4 C
FD
Q Q
Q C
X8126
FJKRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
628
FJKRSE
VHDL Inference Code

architecture Behavioral of fjkrse is begin process (C) begin if (C'event and C='1') then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

always @(posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE) begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end
629
FJKRSE
630
FJKSRE
FJKSRE
J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
FJKSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
J K CE C
FJKSRE
Q
FJKSRE is a single J-K-type flip-flop with J, K, synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, all other inputs are ignored and output Q is set High. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low. When S and R are Low and CE is High, output Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FJKSRE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 0 0 0 R X 1 0 0 0 0 0 CE X X 0 1 1 1 1 J X X X 0 0 1 1 K X X X 0 1 0 1 C X X Outputs Q 1 0 No Chg No Chg 0 1 Toggle
X3759
631
FJKSRE
AND3B2
A0 A1 A2 AD OR3 AD_R AND2B1
AND3B1 J K S AND2B1
FDSE
S Q
R CE C OR2
R_CE
D CE C
X7828
FJKSRE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
AND3B2
A0 A1 A2 OR3 AD AD_R AND2B1
AND3B1 J K AND2B1 S R CE C
FDSE
S D R_CE OR2 CE C RLOC=X0Y0 X9320 Q Q
FJKSRE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC
CE AND2 K AND3 J R S C NAND2B1 C Q

X8127
AND2B2
AND2B2
OR4 D
FD
Q Q
FJKSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
632
FJKSRE
VHDL Inference Code

architecture Behavioral of fjksre is begin process (C) begin if (C'event and C='1') then if (S='1') then Q <= '1'; elsif (R='1') then Q <= '0'; elsif (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

always @(posedge C) begin if (S) Q <= 1; else if (R) Q <= 0; else if (CE) begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end
633
FJKSRE
634
FMAP
FMAP
F Function Generator Partitioning Control Symbol
FMAP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
I4 I3 I2 I1
FMAP
O
The FMAP symbol is used to map logic to the function generator of a slice. See the appropriate CAE tool interface user guide for information about specifying this attribute in your schematic design editor. The MAP=type parameter can be used with the FMAP symbol to further define how much latitude you want to give the mapping program. The following table shows MAP option characters and their meanings.
MAP Option Character P C L O U Pins. Closed Adding logic to or removing logic from the CLB is not allowed. Locked Locking CLB pins. Open Adding logic to or removing logic from the CLB is allowed. Unlocked No locking on CLB pins. Function
X4646
Possible types of MAP parameters for FMAP are MAP=PUC, MAP=PLC, MAP=PLO, and MAP=PUO. The default parameter is PUO. If one of the open parameters is used (PLO or PUO), only the output signals must be specified. Note: Currently, only PUC and PUO are observed. PLC and PLO are translated into PUC and PUO, respectively. The FMAP symbol can be assigned to specific CLB locations using LOC attributes.
Usage
FMAPs are generally inferred with the logic portions of the HDL code. Xilinx suggests that you instantiate FMAPs only if you have a need to implicitly specify the logic mapping, or if you need to manually place or relationally place the logic.
635
FMAP

-- Component Declaration for FMAP should be placed -- after architecture statement but before begin keyword component FMAP port (I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC; I4 : in STD_ULOGIC; O : in STD_ULOGIC); end component; -- Component Attribute specification for FMAP -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here
-- Component Instantiation for FMAP should be placed -- in architecture after the begin keyword FMAP_INSTANCE_NAME : FMAP port map (I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4, O => user_O);

FMAP FMAP_instance_name (.I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4), .O (user_O));

BEL BLKNM HBLKNM HU_SET LOC MAP U_SET
636
FTC
FTC
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear
FTC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
T C
FTC
FTC is a synchronous, resettable toggle flip-flop. The asynchronous clear (CLR) input, when High, overrides all other inputs and resets the data output (Q) Low. The Q output toggles, or changes state, when the toggle enable (T) input is High and CLR is Low during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 T X 0 1 C X X Outputs Q 0 No Chg Toggle
CLR
X3761
FDC
T C CLR X7830 XOR2 C CLR TQ D Q Q
FTC Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
637
FTC
FDC
T C CLR RLOC=X0Y0 X9321 XOR2 C CLR TQ D Q Q
FTC Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FTCP
T C CLR PRE Q
D C
CLR Q
X7831 GND
FTC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
For HDL, this design element can be instantiated or inferred.
VHDL Inference Code

architecture Behavioral of ftc is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (T) Q <= !Q; end
638
FTC

-- Component Declaration for FTC should be placed -- after architecture statement but before begin keyword component FTC port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTC -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for FTC should be placed -- in architecture after the begin keyword FTC_INSTANCE_NAME : FTC port map (Q => user_Q, C => user_C, CLR => user_CLR, T => user_T);

FTC FTC_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .T (user_T));

639
FTC
640
FTCE
FTCE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
FTCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
T CE C
FTCE
CLR
X3764
FTCE is a toggle flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the data output (Q) is reset Low. When CLR is Low and toggle enable (T) and clock enable (CE) are High, Q output toggles, or changes state, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 CE X 0 1 1 T X X 0 1 C X X X Outputs Q 0 No Chg No Chg Toggle
T CE C CLR XOR2
TQ D
FDCE
Q Q
CE C CLR
X7832
FTCE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
641
FTCE
T CE C CLR XOR2
TQ
FDCE
D CE C CLR X9322 Q Q
RLOC=X0Y0
FTCE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FTCP
T CE C CLR AND2 C CLR Q PRE Q
X7833 GND
FTCE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftce is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; Q <= Q; end Behavioral;
642
FTCE

always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (T) Q <= !Q; end

-- Component Declaration for FTCE should be placed -- after architecture statement but before begin keyword component FTCE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; PRE : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTCE -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for FTCE should be placed -- in architecture after the begin keyword FTCE_INSTANCE_NAME : FTCE port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, PRE => user_PRE, T => user_T);

FTCE FTCE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .PRE (user_PRE), .T (user_T));

BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM.
643
FTCE
644
FTCLE
FTCLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
FTCLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D L T CE C
FTCLE
CLR
X3769
FTCLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High and CLR is Low, clock enable (CE) is overridden and the data on data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 L X 1 1 0 0 0 CE X X X 0 1 1 T X X X X 0 1 D X 1 0 X X X C X X X Outputs Q 0 1 0 No Chg No Chg Toggle
645
FTCLE
T XOR2
TQ
D0 D L D1 S0
M2_1
O MD
FDCE
D CE C CLR Q Q
CE OR2
L_CE
C CLR RLOC=R0C0 X8147
FTCLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
T XOR2 D L
TQ
M2_1
D0 D1 S0 O MD
FDCE
CE C CLR RLOC=X0Y0 X9323 OR2 L_CE D CE C CLR Q Q
FTCLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC CE L AND3 AND3B2 OR2 GRD AND4B2 T AND3B2 OR4
FDC
D AND2 C C CLR CLR Q
X7561
FTCLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
646
FTCLE
Usage
VHDL Inference Code

architecture Behavioral of ftcle is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
647
FTCLE
648
FTCLEX
FTCLEX
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
FTCLEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D L T CE C
FTCLEX
CLR X7601
FTCLEX is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High, CLR is Low, and CE is High, the data on data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 L X 1 1 0 0 0 CE X 1 1 0 1 1 T X X X X 0 1 D X 1 0 X X X C X X X Outputs Q 0 1 0 No Chg No Chg Toggle
649
FTCLEX
TQ T XOR2 D L CE C CLR X6995 D0 D1 S0 M2_1 0 MD FDCE D CE C CLR Q Q
FTCLEX Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
T XOR2 D L
TQ
M2_1
D0 D1 S0 O MD
FDCE
CE D CE C CLR RLOC=X0Y0 X9324 C CLR Q Q
FTCLEX Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of ftclex is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (CE='1') then if (L='1') then Q <= D; elsif (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;
650
FTCLEX

always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
651
FTCLEX
652
FTCP
FTCP
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset
FTCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
FTCP
Q
FTCP is a toggle flip-flop with toggle enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the toggle enable input (T) is High and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 PRE X 1 0 0 T X X 0 1 C X X X Outputs Q 0 1 No Chg Toggle
CLR X4392
Usage
VHDL Inference Code

architecture Behavioral of ftcp is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then
653
FTCP
if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (T) Q <= !Q; end

-- Component Declaration for FTCP should be placed -- after architecture statement but before begin keyword component FTCP port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; PRE : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTCP -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for FTCP should be placed -- in architecture after the begin keyword FTCP_INSTANCE_NAME : FTCP port map (Q => user_Q, C => user_C, CLR => user_CLR, PRE => user_PRE, T => user_T);
654
FTCP

FTCP FTCP_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .PRE (user_PRE), .T (user_T));

655
FTCP
656
FTCPE
FTCPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset
FTCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
T CE C
FTCPE
Q
CLR X4393
FTCPE is a toggle flip-flop with toggle and clock enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the toggle enable input (T) and the clock enable input (CE) are High and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. Clock transitions are ignored when CE is Low. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0
PRE T CE C CLR AND2 C CLR Q X7681 T
Outputs T X X X 0 1 C X X X X Q 0 1 No Chg No Chg Toggle
PRE X 1 0 0 0
CE X X 0 1 1
FTCP
PRE Q Q
FTCPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
657
FTCPE
VHDL Inference Code

architecture Behavioral of ftcpe is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) if (T) Q <= !Q; end
658
FTCPLE
FTCPLE
Loadable Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset
FTCPLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro
PRE
D L T CE C
FTCPLE
CLR
X4394
FTCPLE is a loadable toggle flip-flop with toggle and clock enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the load input (L) is High, the clock enable input (CE) is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enable input (T) and the clock enable input (CE) are High and CLR, PRE, and L are Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. Clock transitions are ignored when CE is Low. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 T X X X X X 0 1 C X X X X D X X 0 1 X X X Outputs Q 0 1 0 1 No Chg No Chg Toggle
659
FTCPLE
VCC
CE AND2 L OR2 AND3B2
GND AND4B2 T
FDCP
AND3B2 PRE Q
D C
D AND2 PRE C CLR
OR4
CLR
X7845
FTCPLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftcple is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;
660
FTCPLE

always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
661
FTCPLE
662
FTDCE
FTDCE
Dual Edge Triggered Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
FTDCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
T CE C
FTDCE
CLR
X9751
FTDCE is a dual edge triggered toggle flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the data output (Q) is reset Low. When CLR is Low and toggle enable (T) and clock enable (CE) are High, Q output toggles, or changes state, during the Low-to-High and High-to-Low clock (C) transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 CE X 0 1 1 1 T X X 0 1 1 C X X X Outputs Q 0 No Chg No Chg Toggle Toggle
FTCP
X7833 GND
FTDCE Implementation CoolRunner-II
663
FTDCE
Usage
VHDL Inference Code

architecture Behavioral of ftdce is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event) then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (T) Q <= !Q; end
664
FTDCLE
FTDCLE
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
FTDCLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D L T CE C
FTDCLE
CLR
X9752
FTDCLE is a dual edge triggered toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High and CLR is Low, clock enable (CE) is overridden and the data on data input (D) is loaded into the flip-flop during the Low-to-High and High-to-Low clock (C) transitions. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 0 0 0 0 L X 1 1 1 1 0 0 0 0 CE X X X X X 0 1 1 1 T X X X X X X 0 1 1 D X 1 1 0 0 X X X X C X X X
Outputs Q 0 1 1 0 0 No Chg No Chg Toggle Toggle
665
FTDCLE
VCC
CE L AND3 AND3B2 OR2 GRD AND4B2 T AND3B2 OR4
FDDC
D AND2 C C CLR CLR Q
X9753
FTDCLE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftdcle is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event) then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D;
666
FTDCLE
else if (CE) if (T) Q <= !Q; end
667
FTDCLE
668
FTDCLEX
FTDCLEX
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
FTCLEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D L T CE C
FTDCLEX
CLR
X9754
FTDCLEX is a dual edge triggered toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High, CLR is Low, and CE is High, the data on data input (D) is loaded into the flipflop during the Low-to-High and High-to-Low clock (C) transitions. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied.
Inputs CLR 1 0 0 0 0 0 0 0 0 L X 1 1 1 1 0 0 0 0 CE X 1 1 1 1 0 1 1 1 T X X X X X X 0 1 1 D X 1 1 0 0 X X X X C X X X Outputs Q 0 1 1 0 0 No Chg No Chg Toggle Toggle
Usage
669
FTDCLEX
VHDL Inference Code

architecture Behavioral of ftdclex is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event) then if (CE='1') then if (L='1') then Q <= D; elsif (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
670
FTDCP
FTDCP
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset
FTDCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Primitive Primitive Primitive
PRE
FTDCP
Q
FTDCP is a toggle flip-flop with toggle enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the toggle enable input (T) is High and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-High and High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 PRE X 1 0 0 0 T X X 0 1 1 C X X X Outputs Q 0 1 No Chg Toggle Toggle
CLR
X9777
671
FTDCP
FTDCP
GND
X9778
FTDCP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftdcp is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event) then if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

always @(posedge C or negedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (T) Q <= !Q; end
672
FTDRSE
FTDRSE
Dual Edge Triggered Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
FTDRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
T CE C
FTDRSE
FTDRSE is a dual edge triggered toggle flip-flop with toggle and clock enable and synchronous reset and set. When the synchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When the synchronous set input (S) is High and R is Low, clock enable input (CE) is overridden and output Q is set High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High and R and S are Low, output Q toggles, or changes state, during the Low-to-High and High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
X9755
Inputs R 1 1 0 0 0 0 0 0 S X X 1 1 0 0 0 0 CE X X X X 0 1 1 1 T X X X X X 0 1 1 C X X
Outputs Q 0 0 1 1 No Chg No Chg Toggle Toggle
673
FTDRSE
VCC
CE AND2 T AND2B1
AND3B1 S OR4
FDD
AND3B1 R C AND2B1 C
X9756
FTDRSE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftdrse is begin process (C) begin if (C'event) then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE)
674
FTDRSE
if (T) Q <= !Q; end
675
FTDRSE
676
FTDRSLE
FTDRSLE
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
FTDRSLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D L T CE C
FTDRSLE
X9757
FTDRSLE is a dual edge triggered toggle/loadable flip-flop with toggle and clock enable and synchronous reset and set. The synchronous reset input (R), when High, overrides all other inputs and resets the data output (Q) Low. (Reset has precedence over Set.) When R is Low and synchronous set input (S) is High, the clock enable input (CE) is overridden and output Q is set High. When R and S are Low and load enable input (L) is High, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High and High-to-Low clock transitions. When R, S, and L are Low and CE is High, output Q toggles, or changes state, during the Low-toHigh and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 0 0 0 0 0 0 S 0 0 1 1 0 0 0 0 0 0 0 0 L X X X X 1 1 1 1 0 0 0 0 CE X X X X X X X X 0 1 1 1 T X X X X X X X X X 0 1 1 D X X X X 1 1 0 0 X X X X C X X
Outputs Q 0 0 1 1 1 1 0 0 No Chg No Chg Toggle Toggle
677
FTDRSLE
VCC
CE AND2 L D OR2 AND3B2 C GND T AND4B2 S AND2B1 OR5 Q
FDD
Q
AND4B2 D R C
X9758
AND2
FTDRSLE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftdrsle is begin process (C) begin if (C'event) then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;
678
FTDRSLE

always @(posedge C or negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
679
FTDRSLE
680
FTP
FTP
Toggle Flip-Flop with Toggle Enable and Asynchronous Preset
FTP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
T C
FTP
FTP is a toggle flip-flop with toggle enable and asynchronous preset. When the asynchronous preset (PRE) input is High, all other inputs are ignored and output Q is set High. When toggle-enable input (T) is High and PRE is Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_VIRTEX, STARTUP_SPARTAN3, or the STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 T X 0 1 C X X Outputs Q 1 No Chg Toggle
X3762
PRE TQ XOR2 C
FDP
PRE Q
T C
RLOC=R0C0 X6371
FTP Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
681
FTP
PRE TQ XOR2 C D
FDP
PRE Q Q
T C
RLOC=X0Y0
X9325
FTP Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

PRE
FTCP
PRE T Q Q
T C
C CLR
GND
X7680
FTP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftp is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (T) Q <= !Q; end
682
FTP

-- Component Declaration for FTP should be placed -- after architecture statement but before begin keyword component FTP port (Q : out STD_ULOGIC; C : in STD_ULOGIC; PRE : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTP -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for FTP should be placed -- in architecture after the begin keyword FTP_INSTANCE_NAME : port map (Q => C => PRE => T => FTP user_Q, user_C, user_PRE, user_T);

FTP FTP_instance_name (.Q (user_Q), .C (user_C), .PRE (user_PRE), .T (user_T));

BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET, XBLKNM
683
FTP
684
FTPE
FTPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Preset
FTPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
T CE C
FTPE
FTPE is a toggle flip-flop with toggle and clock enable and asynchronous preset. When the asynchronous preset (PRE) input is High, all other inputs are ignored and output Q is set High. When the toggle enable input (T) is High, clock enable (CE) is High, and PRE is Low, output Q toggles, or changes state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 CE X 0 1 1 T X X 0 1 C X X X Outputs Q 1 No Chg No Chg Toggle
X3765
685
FTPE
PRE TQ XOR2 CE C
FDPE
D PRE Q Q
CE C RLOC=R0C0 X8694
FTPE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FDPE
TQ XOR2 PRE D CE C RLOC=X0Y0 X9326 Q Q
PRE
T CE C
FTPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

PRE T CE C AND2 C CLR Q T
FTCP
PRE Q Q
GND
X7683
FTPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of ftpe is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;
686
FTPE

always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (CE) if (T) Q <= !Q; end
687
FTPE
688
FTPLE
FTPLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Preset
FTPLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D L T CE C
FTPLE
FTPLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous preset. When the asynchronous preset input (PRE) is High, all other inputs are ignored and output Q is set High. When the load enable input (L) is High and PRE is Low, the clock enable (CE) is overridden and the data (D) is loaded into the flip-flop during the Low-to-High clock transition. When L and PRE are Low and toggle-enable input (T) and CE are High, output Q toggles, or changes state, during the Low-toHigh clock transition. When CE is Low, clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 0 0 L X 1 1 0 0 0 CE X X X 0 1 1 T X X X X 0 1 D X 1 0 X X X C X X X Outputs Q 1 1 0 No Chg No Chg Toggle
X3770
689
FTPLE
TQ T XOR2 D L PRE D0 D1 S0 M2_1 O MD
FDPE
D OR2 CE C RLOC=R0C0 X6372 PRE Q Q
CE C
FTPLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
T XOR2 D L
TQ
M2_1
D0 D1 S0 O MD
PRE D OR2
FDPE
PRE Q Q
CE C
FTPLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC
CE AND2 L OR2 GND AND4B2 T AND3B2
FDP
AND3B2 PRE Q
D C
D AND2 PRE C
OR4
X7846
FTPLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
690
FTPLE
Usage
VHDL Inference Code

architecture Behavioral of ftple is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
691
FTPLE
692
FTRSE
FTRSE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
FTRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
T CE C
FTRSE
FTRSE is a toggle flip-flop with toggle and clock enable and synchronous reset and set. When the synchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When the synchronous set input (S) is High and R is Low, clock enable input (CE) is overridden and output Q is set High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High and R and S are Low, output Q toggles, or changes state, during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 S X 1 0 0 0 CE X X 0 1 1 T X X X 0 1 C X X Outputs Q 0 1 No Chg No Chg Toggle
X3768
693
FTRSE
TQ T XOR2 S OR2 D CE C R RLOC=R0C0 X7658 OR2 CE_S CE C R Q Q D_S
FDRE
FTRSE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
T S XOR2
TQ D_S OR2
FDRE
D Q Q CE_S
CE C R OR2
CE C R
RLOC=X0Y0 X9328
FTRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
VCC
CE AND2 T AND2B1
AND3B1 S OR4
FD
AND3B1 R C AND2B1 C
X7847
FTRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
694
FTRSE
VHDL Inference Code

architecture Behavioral of ftrse is begin process (C) begin if (C'event and C='1') then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE) if (T) Q <= !Q; end
695
FTRSE
696
FTRSLE
FTRSLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
FTRSLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
D L T CE C
FTRSLE
X3773
FTRSLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous reset and set. The synchronous reset input (R), when High, overrides all other inputs and resets the data output (Q) Low. (Reset has precedence over Set.) When R is Low and synchronous set input (S) is High, the clock enable input (CE) is overridden and output Q is set High. When R and S are Low and load enable input (L) is High, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-toHigh clock transition. When R, S, and L are Low, CE is High and T is High, output Q toggles, or changes state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 0 0 S 0 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 T X X X X X 0 1 D X X 1 0 X X X C X X Outputs Q 0 1 1 0 No Chg No Chg Toggle
697
FTRSLE
TQ T XOR2 D L S OR2 CE_S_L CE OR3 C D0 D1 S0 MD_S M2_1 O MD
FDRE
Q D CE C Q
R RLOC=R0C0 X7641
FTRSLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
T XOR2 D L S
TQ
M2_1
D0 D1 S0 O MD
MD_S OR2
FDRE
CE_S_L CE OR3 C R RLOC=X0Y0 X9329 D CE C R Q Q
FTRSLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC
CE AND2 L D OR2 AND3B2 C GND T AND4B2 S AND2B1 OR5 Q
FD
Q
AND4B2 D R C AND2
X7848
FTRSLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
698
FTRSLE
Usage
VHDL Inference Code

architecture Behavioral of ftrsle is begin process (C) begin if (C'event and C='1') then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
699
FTRSLE
700
FTSRE
FTSRE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset
FTSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S
T CE C
FTSRE
X3767
FTSRE is a toggle flip-flop with toggle and clock enable and synchronous set and reset. The synchronous set input, when High, overrides all other inputs and sets data output (Q) High. (Set has precedence over Reset.) When synchronous reset input (R) is High and S is Low, clock enable input (CE) is overridden and output Q is reset Low. When toggle enable input (T) and CE are High and S and R are Low, output Q toggles, or changes state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FTSRE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 0 R X 1 0 0 0 CE X X 0 1 1 T X X X 0 1 C X X Outputs Q 1 0 No Chg No Chg Toggle
701
FTSRE
TQ T XOR2 R S AND2B1 D_R
FDSE
S D Q Q
CE C OR2
CE_R CE C RLOC=R0C0
X7643
FTSRE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
T R S XOR2
TQ D_R AND2B1
FDSE
D S Q Q
CE C OR2
CE_R
FTSRE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC
CE AND2
R AND3B2
AND4B2
FD
D AND3B2 S C
X7849
OR4
FTSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
702
FTSRE
VHDL Inference Code

architecture Behavioral of ftsre is begin process (C) begin if (C'event and C='1') then if (S='1') then Q <= '1'; elsif (R='1') then Q <= '0'; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C) begin if (S) Q <= 1; else if (R) Q <= 0; else if (CE) if (T) Q <= !Q; end
703
FTSRE
704
FTSRLE
FTSRLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset
FTSRLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S FTSRLE
D L T CE C
X3772
FTSRLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous set and reset. The synchronous set input (S), when High, overrides all other inputs and sets data output (Q) High. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, clock enable input (CE) is overridden and output Q is reset Low. When load enable input (L) is High and S and R are Low, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enable input (T) and CE are High and S, R, and L are Low, output Q toggles, or changes state, during the Low-to- High clock transition. When CE is Low, clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously preset when a High-level pulse is applied on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously cleared, output Low, when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FTSRLE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 0 0 0 R X 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 T X X X X X 0 1 D X X 1 0 X X X C X X Outputs Q 1 0 1 0 No Chg No Chg Toggle
705
FTSRLE
T
XOR2
TQ
M2_1
D0 D1 S0 O MD
D L R
MD_S AND2B1
FDSE
D CE C Q
CE_R_L
CE
OR3
RLOC=R0C0
X7642
FTSRLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
T XOR2 D L R S
TQ
M2_1
D0 D1 S0 O MD
MD_S AND2B1
FDSE
D S Q Q
CE_R_L CE C OR3
CE C RLOC=R0C0 X9331
FTSRLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC
CE AND2
R AND4B3 T L OR2 GND
AND5B3
FD
D AND4B3 D C Q
X7850
AND3B1 S C
OR5
FTSRLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
706
FTSRLE
Usage
VHDL Inference Code

architecture Behavioral of ftsrle is begin process (C) begin if (C'event and C='1') then if (S='1') then Q <= '1'; elsif (R='1') then Q <= '0'; elsif (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

always @(posedge C) begin if (S) Q <= 1; else if (R) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end
707
FTSRLE
708
GND
GND
Ground-Connection Signal Tag
GND Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive
The GND signal tag, or parameter, forces a net or input function to a Low logic level. A net tied to GND cannot have any other source.
X3858
When the logic-trimming software or fitter encounters a net or input function tied to GND, it removes any logic that is disabled by the GND signal. The GND signal is only implemented when the disabled logic cannot be removed.
Usage
VHDL Inference Code:

gnd_signal <= '0';
Verilog Inference Code:

assign gnd_signal = 0;

-- Component Declaration for GND should be placed -- after architecture statement but before begin keyword component GND port (G : out STD_ULOGIC); end component; -- Component Attribute specification for GND -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here
-- Component Instantiation for GND should be placed -- in architecture after the begin keyword
709
GND
GND_INSTANCE_NAME : GND port map (G => user_G);

GND GND_instance_name (.G (user_G));

None
710
GT_AURORA_n
GT_AURORA_n
Gigabit Transceiver for High-Speed I/O
GT_AURORA_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*
*Supported for Virtex-II Pro but not for Virtex-II or Virtex-II Pro X.
This Xilinx protocol gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributesand their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
711
GT_AURORA_n
GT_AURORA_1
BREFCLK BREFCLK2 CHBONDI(3:0) CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(0:0) TXCHARDISPMODE(0:0) TXCHARDISPVAL(0:0) TXCHARISK(0:0) TXDATA(7:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9888
CHBONDDONE CHBONDO(3:0) CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(0:0) RXCHARISK(0:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(7:0) RXDISPERR(0:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(0:0) RXREALIGN RXRECCLK RXRUNDISP(0:0) TXBUFERR TXKERR(0:0) TXN TXP TXRUNDISP(0:0)
712
GT_AURORA_n
GT_AURORA_2
X9889
713
GT_AURORA_n
GT_AURORA_4
X9890
Usage
This design element is instantiated rather than inferred in the design code.
VHDL Instantiation Templates

GT_AURORA_1 VHDL Code
-- Component Attribute specification for GT_AURORA_1 -- should be placed after architecture declaration but -- before the begin keyword
714
GT_AURORA_n
component GT_AURORA_1 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00111110111"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111111"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000101"; boolean := TRUE; bit_vector := "0011111010"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 1; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 1;
715
GT_AURORA_n
TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
: integer := 500; : integer := 0);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);
716
GT_AURORA_n
end component; -- Component Attribute specification for GT_AURORA_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_AURORA_1 should be placed -- in architecture after the begin keyword GT_AURORA_1_INSTANCE_NAME : GT_AURORA_1 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value, CRC_END_OF_PKT => string_value, CRC_FORMAT => string_value, CRC_START_OF_PKT => string_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, DEC_VALID_COMMA_ONLY => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value, PCOMMA_10B_VALUE => bit_value, PCOMMA_DETECT => boolean_value, REF_CLK_V_SEL => integer_value, RX_BUFFER_USE => boolean_value, RX_CRC_USE => boolean_value,
717
GT_AURORA_n
RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B
=> => => => => => => => => => => => =>
integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B,
718
GT_AURORA_n
TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => =>
user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_AURORA_2 -- should be placed after architecture declaration but -- before the begin keyword component GT_AURORA_2 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00111110111"; bit_vector := "00111110111"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "1111111111"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000101";
719
GT_AURORA_n
MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN
: : : : : : : : : : : : : : : : : : :
boolean := bit_vector boolean := integer := boolean := boolean := integer := boolean := integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=
TRUE; := "0011111010"; TRUE; 0; TRUE; FALSE; 2; TRUE; 1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 2; 500; 0);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
720
GT_AURORA_n
RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(15 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_AURORA_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_AURORA_2 should be placed -- in architecture after the begin keyword GT_AURORA_2_INSTANCE_NAME : GT_AURORA_2 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value,
721
GT_AURORA_n
CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI,
722
GT_AURORA_n
CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_AURORA_4 -- should be placed after architecture declaration but -- before the begin keyword component GT_AURORA_4 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2
: : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00111110111"; bit_vector := "00111110111";
723
GT_AURORA_n
CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
bit_vector := "00111110111"; bit_vector := "00111110111"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 4; boolean := TRUE; bit_vector := "1111111111"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000101"; boolean := TRUE; bit_vector := "0011111010"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 4; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 4; integer := 500; integer := 0);
: : : : : : : : : : : : : : : : : : :
out out out out out out out out out out out out out out out out out out out
std_ulogic; std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(2 downto 0); std_ulogic; std_ulogic; std_logic_vector(31 downto 0); std_logic_vector(3 downto 0); std_logic_vector(1 downto 0); std_logic_vector(3 downto 0); std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(3 downto 0);
724
GT_AURORA_n
TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(31 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);
-- Component Attribute specification for GT_AURORA_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_AURORA_4 should be placed -- in architecture after the begin keyword GT_AURORA_4_INSTANCE_NAME : GT_AURORA_4 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value,
725
GT_AURORA_n
CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT,
726
GT_AURORA_n
RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);
Verilog Instantiation Templates

GT_AURORA_1 Verilog Code
GT_AURORA_1 GT_AURORA_1_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC),
727
GT_AURORA_n
.RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000;
728
GT_AURORA_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111111; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000101; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 1; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 1; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_AURORA_2 GT_AURORA_2_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT),
729
GT_AURORA_n
.RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000;
730
GT_AURORA_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111111; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000101; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_AURORA_4 GT_AURORA_4_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET),
731
GT_AURORA_n
.RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000;
732
GT_AURORA_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 4; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111111; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000101; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 4; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 4; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

None
733
GT_AURORA_n
734
GT_CUSTOM
GT_CUSTOM
GT_CUSTOM Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Primitive* No No No
This gigabit transceiver is fully customizable. You can set attributes for the primitives. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributesand their default attribute values. The following figure lists the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
735
GT_CUSTOM
GT_CUSTOM
X9891
736
GT_CUSTOM
Usage

GT_CUSTOM VHDL Code
-- Component Attribute specification for GT_CUSTOM -- should be placed after architecture declaration but -- before the begin keyword component GT_CUSTOM -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0;
737
GT_CUSTOM
RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK
: : : : : : : : : : : : : : :
boolean := boolean := integer := boolean := integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=
TRUE; FALSE; 2; TRUE; 1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 2; 500; 0);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
738
GT_CUSTOM
RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : :
in in in in in in in in in in in in
std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_CUSTOM -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_CUSTOM should be placed -- in architecture after the begin keyword GT_CUSTOM_INSTANCE_NAME : GT_CUSTOM -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value,
739
GT_CUSTOM
CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN
=> => => => => => => => => => => => => => => => => => => => => => => => => =>
string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN,
740
GT_CUSTOM
ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => =>
user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_CUSTOM Verilog Code
GT_CUSTOM GT_CUSTOM_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN),
741
GT_CUSTOM
.ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7";
742
GT_CUSTOM
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

None
743
GT_CUSTOM
744
GT_ETHERNET_n
GT_ETHERNET_n
GT_ETHERNET_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*
This Ethernet gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributesand their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
745
GT_ETHERNET_n
GT_ETHERNET_1
BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(0:0) TXCHARDISPMODE(0:0) TXCHARDISPVAL(0:0) TXCHARISK(0:0) TXDATA(7:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9892
CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(0:0) RXCHARISK(0:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(7:0) RXDISPERR(0:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(0:0) RXREALIGN RXRECCLK RXRUNDISP(0:0) TXBUFERR TXKERR(0:0) TXN TXP TXRUNDISP(0:0)
746
GT_ETHERNET_n
GT_ETHERNET_2
X9893
747
GT_ETHERNET_n
GT_ETHERNET_4
BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(3:0) TXCHARDISPMODE(3:0) TXCHARDISPVAL(3:0) TXCHARISK(3:0) TXDATA(31:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(3:0) RXCHARISK(3:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(31:0) RXDISPERR(3:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(3:0) RXREALIGN RXRECCLK RXRUNDISP(3:0) TXBUFERR TXKERR(3:0) TXN TXP TXRUNDISP(3:0)
X9894
Usage
748
GT_ETHERNET_n

GT_ETHERNET_1 VHDL Code
-- Component Attribute specification for GT_ETHERNET_1 -- should be placed after architecture declaration but -- before the begin keyword component GT_ETHERNET_1 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00110111100"; bit_vector := "00001010000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "ETHERNET"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 1; boolean := TRUE;
749
GT_ETHERNET_n
RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT
: : : : : : : : : : :
integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=
1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 1; 500; 0);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic;
750
GT_ETHERNET_n
TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : :
in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_ETHERNET_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_ETHERNET_1 should be placed -- in architecture after the begin keyword GT_ETHERNET_1_INSTANCE_NAME : -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT GT_ETHERNET_1
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value,
751
GT_ETHERNET_n
PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2
=> => => => => => => => => => => => => => => => => =>
bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2,
752
GT_ETHERNET_n
TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => =>
user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_ETHERNET_2 -- should be placed after architecture declaration but -- before the begin keyword component GT_ETHERNET_2 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00110111100"; bit_vector := "00001010000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "ETHERNET"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE;
753
GT_ETHERNET_n
MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET
: : : : : : : : : : : : : : : : : : : :
bit_vector boolean := bit_vector boolean := integer := boolean := boolean := integer := boolean := integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=
:= "1100000000"; TRUE; := "0011111000"; TRUE; 0; TRUE; FALSE; 2; TRUE; 1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 2; 500; 0);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
754
GT_ETHERNET_n
RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : :
in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(15 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_ETHERNET_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_ETHERNET_2 should be placed -- in architecture after the begin keyword GT_ETHERNET_2_INSTANCE_NAME : -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE GT_ETHERNET_2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value,
755
GT_ETHERNET_n
COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN
=> => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN,
756
GT_ETHERNET_n
REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => =>
user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_ETHERNET_4 -- should be placed after architecture declaration but -- before the begin keyword component GT_ETHERNET_4 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE
: : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00110111100"; bit_vector := "00001010000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE;
757
GT_ETHERNET_n
CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN
: : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 2; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "ETHERNET"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 4; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 4; integer := 500; integer := 0);
: : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
758
GT_ETHERNET_n
LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in
std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_ETHERNET_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_ETHERNET_4 should be placed -- in architecture after the begin keyword GT_ETHERNET_4_INSTANCE_NAME : -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 GT_ETHERNET_4
=> => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value,
759
GT_ETHERNET_n
CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => =>
user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP,
760
GT_ETHERNET_n
TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_ETHERNET_1 Verilog Code
GT_ETHERNET_1 GT_ETHERNET_1_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK),
761
GT_ETHERNET_n
.BREFCLK2 (user_BREFCLK2), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 1; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 0; user_instance_name.CHAN_BOND_ONE_SHOT = "TRUE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 7; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00110111100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00001010000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE";
762
GT_ETHERNET_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "ETHERNET"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 1; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 1; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_ETHERNET_2 GT_ETHERNET_2_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN),
763
GT_ETHERNET_n
.LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 1; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 0; user_instance_name.CHAN_BOND_ONE_SHOT = "TRUE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 7; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00110111100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00001010000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "ETHERNET"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE";
764
GT_ETHERNET_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_ETHERNET_4 GT_ETHERNET_4_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL),
765
GT_ETHERNET_n
.RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 1; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 0; user_instance_name.CHAN_BOND_ONE_SHOT = "TRUE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 7; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00110111100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00001010000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "ETHERNET"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000;
766
GT_ETHERNET_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 4; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 4; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

None
767
GT_ETHERNET_n
768
GT_FIBRE_CHAN_n
GT_FIBRE_CHAN_n
GT_FIBRERE_CHAN_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Primitive* No No No
This Fibre Channel gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
769
GT_FIBRE_CHAN_n
GT_FIBRE_CHAN_1
X9895
770
GT_FIBRE_CHAN_n
GT_FIBRE_CHAN_2
X9896
771
GT_FIBRE_CHAN_n
GT_FIBRE_CHAN_4
X9897
772
GT_FIBRE_CHAN_n
Usage

GT_FIBRE_CHAN_1 VHDL Code
-- Component Attribute specification for GT_FIBRE_CHAN_1 -- should be placed after architecture declaration but -- before the begin keyword component GT_FIBRE_CHAN_1 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 2; bit_vector := "00110111100"; bit_vector := "00010010101"; bit_vector := "00010110101"; bit_vector := "00010110101"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 4; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "FIBRE_CHAN"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0;
773
GT_FIBRE_CHAN_n
RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL
: : : : : : : : : : : : : : :
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0);
774
GT_FIBRE_CHAN_n
TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : :
in in in in in in in in
std_logic_vector(0 downto 0); std_logic_vector(7 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_FIBRE_CHAN_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_FIBRE_CHAN_1 should be placed -- in architecture after the begin keyword GT_FIBRE_CHAN_1_INSTANCE_NAME -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT : GT_FIBRE_CHAN_1
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value,
775
GT_FIBRE_CHAN_n
DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP
=> => => => => => => => => => => => => => => => => => => => => =>
boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP,
776
GT_FIBRE_CHAN_n
RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => =>
user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_FIBRE_CHAN_2 -- should be placed after architecture declaration but -- before the begin keyword component GT_FIBRE_CHAN_2 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 2; bit_vector := "00110111100"; bit_vector := "00010010101"; bit_vector := "00010110101"; bit_vector := "00010110101"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 4; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "FIBRE_CHAN";
777
GT_FIBRE_CHAN_n
CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL
: : : : : : : : : : : : : : : : : : : : : : : :
string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 2; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 2; integer := 500; integer := 0);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
778
GT_FIBRE_CHAN_n
RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(15 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_FIBRE_CHAN_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_FIBRE_CHAN_2 should be placed -- in architecture after the begin keyword GT_FIBRE_CHAN_2_INSTANCE_NAME -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 : GT_FIBRE_CHAN_2
=> => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value,
779
GT_FIBRE_CHAN_n
CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => =>
user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN,
780
GT_FIBRE_CHAN_n
ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => =>
user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_FIBRE_CHAN_4 -- should be placed after architecture declaration but -- before the begin keyword component GT_FIBRE_CHAN_4 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1
: : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 2; bit_vector := "00110111100"; bit_vector := "00010010101"; bit_vector := "00010110101"; bit_vector := "00010110101"; bit_vector := "00000000000";
781
GT_FIBRE_CHAN_n
CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 4; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "FIBRE_CHAN"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 4; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 4; integer := 500; integer := 0);
: : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X';
782
GT_FIBRE_CHAN_n
CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_FIBRE_CHAN_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_FIBRE_CHAN_4 should be placed -- in architecture after the begin keyword GT_FIBRE_CHAN_4_INSTANCE_NAME -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG : GT_FIBRE_CHAN_4
=> => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value,
783
GT_FIBRE_CHAN_n
CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => =>
user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP,
784
GT_FIBRE_CHAN_n
TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_FIBRE_CHAN_1 Verilog Code
GT_FIBRE_CHAN_1 GT_FIBRE_CHAN_1_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN),
785
GT_FIBRE_CHAN_n
.TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 1; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 0; user_instance_name.CHAN_BOND_ONE_SHOT = "TRUE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 7; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 2; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00110111100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00010010101; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00010110101; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00010110101; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000;
786
GT_FIBRE_CHAN_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 4; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "FIBRE_CHAN"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 1; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 1; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_FIBRE_CHAN_2 GT_FIBRE_CHAN_2_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2),
787
GT_FIBRE_CHAN_n
.CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 1; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 0; user_instance_name.CHAN_BOND_ONE_SHOT = "TRUE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 7; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 2; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00110111100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00010010101; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00010110101; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00010110101; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 4; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000;
788
GT_FIBRE_CHAN_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "FIBRE_CHAN"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_FIBRE_CHAN_4 GT_FIBRE_CHAN_4_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK),
789
GT_FIBRE_CHAN_n
.POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 1; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 0; user_instance_name.CHAN_BOND_ONE_SHOT = "TRUE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 7; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 2; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00110111100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00010010101; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00010110101; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00010110101; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 4; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "FIBRE_CHAN"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE";
790
GT_FIBRE_CHAN_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 4; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 4; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

None
791
GT_FIBRE_CHAN_n
792
GT_INFINIBAND_n
GT_INFINIBAND_n
GT_INFINIBAND_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Primitive* No No No
This Infiniband gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
793
GT_INFINIBAND_n
GT_INFINIBAND_1
BREFCLK BREFCLK2 CHBONDI(3:0) CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(0:0) TXCHARDISPMODE(0:0) TXCHARDISPVAL(0:0) TXCHARISK(0:0) TXDATA(7:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 CHBONDDONE CHBONDO(3:0) CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(0:0) RXCHARISK(0:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(7:0) RXDISPERR(0:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(0:0) RXREALIGN RXRECCLK RXRUNDISP(0:0) TXBUFERR TXKERR(0:0) TXN TXP TXRUNDISP(0:0)
X9898
794
GT_INFINIBAND_n
GT_INFINIBAND_2
BREFCLK BREFCLK2 CHBONDI(3:0) CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(1:0) TXCHARDISPMODE(1:0) TXCHARDISPVAL(1:0) TXCHARISK(1:0) TXDATA(15:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 CHBONDDONE CHBONDO(3:0) CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(1:0) RXCHARISK(1:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(15:0) RXDISPERR(1:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(1:0) RXREALIGN RXRECCLK RXRUNDISP(1:0) TXBUFERR TXKERR(1:0) TXN TXP TXRUNDISP(1:0)
X9899
795
GT_INFINIBAND_n
GT_INFINIBAND_4
X9900
796
GT_INFINIBAND_n
Usage

GT_INFINIBAND_1 VHDL Code
-- Component Attribute specification for GT_INFINIBAND_1 -- should be placed after architecture declaration but -- before the begin keyword component GT_INFINIBAND_1 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY LANE_ID MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00110111100"; bit_vector := LANE_ID; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "00110111100"; bit_vector := LANE_ID; bit_vector := "00001000101"; bit_vector := "00001000101"; boolean := TRUE; integer := 4; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "INFINIBAND"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE;
797
GT_INFINIBAND_n
REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET
: : : : : : : : : : : : : : : :
integer := boolean := boolean := integer := boolean := integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=
0; TRUE; FALSE; 1; TRUE; 1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 1; 500; 0);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
798
GT_INFINIBAND_n
RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : :
in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(7 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
downto downto downto downto downto
0); 0); 0); 0); 0);
-- Component Attribute specification for GT_INFINIBAND_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_INFINIBAND_1 should be placed -- in architecture after the begin keyword GT_INFINIBAND_1_INSTANCE_NAME -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE : GT_INFINIBAND_1
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value,
799
GT_INFINIBAND_n
COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY LANE_ID MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN
=> => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN,
800
GT_INFINIBAND_n
ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => =>
user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_INFINIBAND_2 -- should be placed after architecture declaration but -- before the begin keyword component GT_INFINIBAND_2 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4
: : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00110111100"; bit_vector := LANE_ID; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "00110111100"; bit_vector := LANE_ID; bit_vector := "00001000101"; bit_vector := "00001000101"; boolean := TRUE; integer := 4; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000";
801
GT_INFINIBAND_n
CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY LANE_ID MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "INFINIBAND"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 2; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 2; integer := 500; integer := 0);
: : : : : : : : : : : : : : : : : : : :
out out out out out out out out out out out out out out out out out out out out
std_ulogic; std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_logic_vector(2 downto 0); std_ulogic; std_ulogic; std_logic_vector(15 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_logic_vector(1 downto 0); std_ulogic;
802
GT_INFINIBAND_n
TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(15 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);
-- Component Attribute specification for GT_INFINIBAND_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_INFINIBAND_2 should be placed -- in architecture after the begin keyword GT_INFINIBAND_2_INSTANCE_NAME -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 : GT_INFINIBAND_2
=> => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value,
803
GT_INFINIBAND_n
CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY LANE_ID MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT,
804
GT_INFINIBAND_n
RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT_INFINIBAND_4 -- should be placed after architecture declaration but -- before the begin keyword component GT_INFINIBAND_4 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET
: : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8;
805
GT_INFINIBAND_n
CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY LANE_ID MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; bit_vector := "00110111100"; bit_vector := LANE_ID; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "00110111100"; bit_vector := LANE_ID; bit_vector := "00001000101"; bit_vector := "00001000101"; boolean := TRUE; integer := 4; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "INFINIBAND"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 4; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 4; integer := 500; integer := 0);
: out std_ulogic;
806
GT_INFINIBAND_n
CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(31 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);
-- Component Attribute specification for GT_INFINIBAND_4 -- should be placed after architecture declaration but -- before the begin keyword
807
GT_INFINIBAND_n
-- Enter constraints here -- Component Instantiation for GT_INFINIBAND_4 should be placed -- in architecture after the begin keyword GT_INFINIBAND_4_INSTANCE_NAME -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY LANE_ID MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM : GT_INFINIBAND_4
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value,
808
GT_INFINIBAND_n
SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR
=> => => => => => => =>
boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR,
809
GT_INFINIBAND_n
TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => =>
user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_INFINIBAND_1 Verilog Code
GT_INFINIBAND_1 GT_INFINIBAND_1_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK),
810
GT_INFINIBAND_n
.TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = LANE_ID; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = LANE_ID; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_USE = "TRUE"; user_instance_name.CHAN_BOND_SEQ_LEN = 4; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "INFINIBAND"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 1; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE";
811
GT_INFINIBAND_n
defparam defparam defparam defparam defparam defparam defparam
user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 1; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_INFINIBAND_2 GT_INFINIBAND_2_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA),
812
GT_INFINIBAND_n
.TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = LANE_ID; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = LANE_ID; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_USE = "TRUE"; user_instance_name.CHAN_BOND_SEQ_LEN = 4; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "INFINIBAND"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50;
813
GT_INFINIBAND_n
defparam defparam defparam defparam defparam defparam
user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_INFINIBAND_4 GT_INFINIBAND_4_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR),
814
GT_INFINIBAND_n
.TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = LANE_ID; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = LANE_ID; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_USE = "TRUE"; user_instance_name.CHAN_BOND_SEQ_LEN = 4; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "INFINIBAND"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 4; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE";
815
GT_INFINIBAND_n
defparam defparam defparam defparam defparam
user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 4; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

None
816
GT_XAUI_n
GT_XAUI_n
GT_XAUI_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No
This XAUI gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
817
GT_XAUI_n
GT_XAUI_1
X9902
818
GT_XAUI_n
GT_XAUI_2
X9903
819
GT_XAUI_n
GT_XAUI_4
X9904
820
GT_XAUI_n
Usage

GT_XAUI_1 VHDL Code
-- Component Attribute specification for GT_XAUI_1 -- should be placed after architecture declaration but -- before the begin keyword component GT_XAUI_1 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0;
821
GT_XAUI_n
RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK
: : : : : : : : : : : : : : :
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
822
GT_XAUI_n
RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : :
std_ulogic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(7 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
downto downto downto downto downto
0); 0); 0); 0); 0);
-- Component Attribute specification for GT_XAUI_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_XAUI_1 should be placed -- in architecture after the begin keyword GT_XAUI_1_INSTANCE_NAME : GT_XAUI_1 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value,
823
GT_XAUI_n
CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN
=> => => => => => => => => => => => => => => => => => => => => => => => => =>
string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN,
824
GT_XAUI_n
ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => =>
user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);
GT_XAUI_2 VHDL Code

-- Component Attribute specification for GT_XAUI_2 -- should be placed after architecture declaration but -- before the begin keyword component GT_XAUI_2 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2
: : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000";
825
GT_XAUI_n
CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK
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bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 2; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 2; integer := 500; integer := 0);
: : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic := 'X';
826
GT_XAUI_n
BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic := 'X'; std_logic_vector(3 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(15 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT_XAUI_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_XAUI_2 should be placed -- in architecture after the begin keyword GT_XAUI_2_INSTANCE_NAME : GT_XAUI_2 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value,
827
GT_XAUI_n
CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)
=> => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR,
828
GT_XAUI_n
RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);
GT_XAUI_4 VHDL Code

-- Component Attribute specification for GT_XAUI_4 -- should be placed after architecture declaration but -- before the begin keyword component GT_XAUI_4 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3
: : : : : : : :
boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000";
829
GT_XAUI_n
CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 4; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 4; integer := 500; integer := 0);
: : : : : :
out out out out out out
std_ulogic; std_logic_vector(3 std_ulogic; std_logic_vector(1 std_logic_vector(3 std_logic_vector(3
downto 0); downto 0); downto 0); downto 0);
830
GT_XAUI_n
RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(31 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);
-- Component Attribute specification for GT_XAUI_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_XAUI_4 should be placed -- in architecture after the begin keyword
831
GT_XAUI_n
GT_XAUI_4_INSTANCE_NAME : GT_XAUI_4 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value, CRC_END_OF_PKT => string_value, CRC_FORMAT => string_value, CRC_START_OF_PKT => string_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, DEC_VALID_COMMA_ONLY => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value, PCOMMA_10B_VALUE => bit_value, PCOMMA_DETECT => boolean_value, REF_CLK_V_SEL => integer_value, RX_BUFFER_USE => boolean_value, RX_CRC_USE => boolean_value, RX_DATA_WIDTH => integer_value, RX_DECODE_USE => boolean_value, RX_LOS_INVALID_INCR => integer_value, RX_LOS_THRESHOLD => integer_value, RX_LOSS_OF_SYNC_FSM => boolean_value, SERDES_10B => boolean_value, TERMINATION_IMP => integer_value, TX_BUFFER_USE => boolean_value, TX_CRC_FORCE_VALUE => bit_value, TX_CRC_USE => boolean_value, TX_DATA_WIDTH => integer_value,
832
GT_XAUI_n
TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
=> integer_value, => integer_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);
833
GT_XAUI_n

GT_XAUI_1 Verilog Code
GT_XAUI_1 GT_XAUI_1_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK),
834
GT_XAUI_n
.TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 1; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 1; user_instance_name.TX_DIFF_CTRL = 500;
835
GT_XAUI_n
defparam user_instance_name.TX_PREEMPHASIS = 0;

GT_XAUI_2 GT_XAUI_2_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2));
836
GT_XAUI_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;
837
GT_XAUI_n

GT_XAUI_4 GT_XAUI_4_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE";
838
GT_XAUI_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 4; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 4; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;
839
GT_XAUI_n

None
840
GT10_AURORA_n
GT10_AURORA_n
10-Gigabit Transceiver for High-Speed I/O
GT10_AURORA_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No
*Supported for Virtex-II Pro X but not for VirtexII or Virtex-II Pro.
This Xilinx protocol 10-gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2, or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
841
GT10_AURORA_n
GT10_AURORA_1
BREFCLKNIN BREFCLKPIN CHBONDI(4:0) ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) PMAINIT PMAREGADDR(5:0) PMAREGDATAIN(7:0) PMAREGRW PMAREGSTROBE PMARXLOCKSEL(1:0) POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH(1:0) RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH(1:0) RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(0:0) TXCHARDISPMODE(0:0) TXCHARDISPVAL(0:0) TXCHARISK(0:0) TXDATA(7:0) TXDATAWIDTH(1:0) TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH(1:0) TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
X10045
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(0:0)
RXCHARISK(0:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(7:0)
RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(0:0)
RXREALIGN
RXRECCLK
RXRUNDISP(0:0)
TXBUFERR
TXKERR(0:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(0:0)
842
GT10_AURORA_n
GT10_AURORA_2
X10046
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(1:0)
RXCHARISK(1:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(15:0)
RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(1:0)
RXREALIGN
RXRECCLK
RXRUNDISP(0:0)
TXBUFERR
TXKERR(1:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(1:0)
843
GT10_AURORA_n
GT10_AURORA_4
X10047
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
844
GT10_AURORA_n
Usage

GT10_AURORA_1 VHDL Code
-- Component Attribute specification for GT10_AURORA_1 -- should be placed after architecture declaration but -- before the begin keyword component GT10_AURORA_1 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 1; integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "0000"; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001000101"; bit_vector := "00001000101"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111";
845
GT10_AURORA_n
PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH
: : : : : :
string := "25_10"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0);
846
GT10_AURORA_n
RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(7 std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
downto downto downto downto downto downto
0); 0); 0); 0); 0); 0);
downto 0);
-- Component Attribute specification for GT10_AURORA_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_AURORA_1 should be placed -- in architecture after the begin keyword GT10_AURORA_1_INSTANCE_NAME : GT10_AURORA_1 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CLK_COR_8B10B_DE => boolean_value, CLK_COR_MAX_LAT => integer_value, CLK_COR_MIN_LAT => integer_value, CLK_COR_SEQ_1_1 => bit_value,
847
GT10_AURORA_n
CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC
=> => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC,
848
GT10_AURORA_n
ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
GT10_AURORA_2 Code
-- Component Attribute specification for GT10_AURORA_2 -- should be placed after architecture declaration but -- before the begin keyword component GT10_AURORA_2 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT
: integer := 1; : integer := 16;
849
GT10_AURORA_n
CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
string := "OFF"; boolean := FALSE; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "0000"; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001000101"; bit_vector := "00001000101"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111"; string := "25_20"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : :
out out out out out out out out out
std_ulogic; std_ulogic; std_ulogic; std_logic_vector(4 std_ulogic; std_logic_vector(1 std_logic_vector(1 std_logic_vector(1 std_logic_vector(2
downto 0); downto downto downto downto 0); 0); 0); 0);
850
GT10_AURORA_n
RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(15 downto 0); in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0);
851
GT10_AURORA_n
TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : :
in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_AURORA_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_AURORA_2 should be placed -- in architecture after the begin keyword GT10_AURORA_2_INSTANCE_NAME : GT10_AURORA_2 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CLK_COR_8B10B_DE => boolean_value, CLK_COR_MAX_LAT => integer_value, CLK_COR_MIN_LAT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_1_MASK => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_MASK => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_DROP => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, DEC_VALID_COMMA_ONLY => boolean_value, MCOMMA_10B_VALUE => bit_value,
852
GT10_AURORA_n
MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE
=> => => => => => => => => =>
boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE,
853
GT10_AURORA_n
RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
GT10_AURORA_2 VHDL Code

-- Component Attribute specification for GT10_AURORA_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_AURORA_4 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2
: : : : : : : : : : : : : : : : : : : : :
integer := 1; integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "0000"; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001000101"; bit_vector := "00001000101"; bit_vector := "0000"; boolean := FALSE; integer := 4; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00100011100";
854
GT10_AURORA_n
CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN
: : : : : : : : : : : : : : : : : : : : : : : : : : :
bit_vector := "00100011100"; bit_vector := "00100011100"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 4; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111"; string := "25_40"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic;
855
GT10_AURORA_n
ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_logic_vector(5 downto 0); std_logic_vector(7 downto 0); std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_AURORA_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_AURORA_4 should be placed -- in architecture after the begin keyword GT10_AURORA_4_INSTANCE_NAME : GT10_AURORA_4 -- synopsys translate_off
856
GT10_AURORA_n
generic map ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
integer_value, integer_value, string_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS,
857
GT10_AURORA_n
RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE,
858
GT10_AURORA_n
TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => =>
user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);

GT10_AURORA_1 Verilog Code
GT10_AURORA_1 GT10_AURORA_1_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL),
859
GT10_AURORA_n
.RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000;
860
GT10_AURORA_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "25_10"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

GT10_AURORA_2 GT10_AURORA_2_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT),
861
GT10_AURORA_n
.PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2;
862
GT10_AURORA_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "25_20"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

GT10_AURORA_4 GT10_AURORA_4_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK),
863
GT10_AURORA_n
.TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2));
864
GT10_AURORAX_n
GT10_AURORAX_n
GT10_AURORAX_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 No No Primitive* No No
This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter n represents number of bytes of the data path. Valid values are 4 or 8. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
865
GT10_AURORAX_n
GT10_AURORAX_4
X10048
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
866
GT10_AURORAX_n
GT10_AURORAX_8
X10049
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(7:0)
RXCHARISK(7:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(63:0)
RXDISPERR(7:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(7:0)
RXREALIGN
RXRECCLK
RXRUNDISP(7:0)
TXBUFERR
TXKERR(7:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(7:0)
867
GT10_AURORAX_n
Usage

GT10_AURORAX_4 VHDL Code
-- Component Attribute specification for GT10_AURORAX_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_AURORAX_4 -- synopsys translate_off generic ( CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; integer := 8; boolean := FALSE; integer := 36; integer := 28; bit_vector := "10000011110"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; boolean := FALSE; integer := 8; boolean := TRUE; bit_vector := "11111111"; string := "0_32"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; integer := 64; integer := 16; boolean := TRUE);
868
GT10_AURORAX_n
-- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
869
GT10_AURORAX_n
TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : :
std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_AURORAX_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_AURORAX_4 should be placed -- in architecture after the begin keyword GT10_AURORAX_4_INSTANCE_NAME : GT10_AURORAX_4 -- synopsys translate_off generic map ( CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_64B66B_SV => boolean_value, CLK_COR_MAX_LAT => integer_value, CLK_COR_MIN_LAT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_1_MASK => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value,
870
GT10_AURORAX_n
CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL
=> => => => => => => => => => => => => =>
bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, integer_value, integer_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL,
871
GT10_AURORAX_n
RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
GT10_AURORAX_8 Code
-- Component Attribute specification for GT10_AURORAX_8 -- should be placed after architecture declaration but -- before the begin keyword component GT10_AURORAX_8 -- synopsys translate_off generic ( CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV
: : : : : : : : : : : : : : : :
integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; integer := 8; boolean := FALSE;
872
GT10_AURORAX_n
CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK
: : : : : : : : : : : : : : : : : : : : : : : : :
integer := 36; integer := 28; bit_vector := "10000011110"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; boolean := FALSE; integer := 8; boolean := TRUE; bit_vector := "11111111"; string := "0_64"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; integer := 64; integer := 16; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(63 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(7 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_ulogic; out std_logic_vector(7 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0);
873
GT10_AURORAX_n
PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_logic_vector(5 downto 0); std_logic_vector(7 downto 0); std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic_vector(63 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_AURORAX_8 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_AURORAX_8 should be placed -- in architecture after the begin keyword GT10_AURORAX_8_INSTANCE_NAME : GT10_AURORAX_8 -- synopsys translate_off generic map ( CHAN_BOND_LIMIT => integer_value,
874
GT10_AURORAX_n
CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
string_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, integer_value, integer_value, boolean_value)
=> => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN,
875
GT10_AURORAX_n
RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
876
GT10_AURORAX_n

GT10_AURORAX_4 Verilog Code
GT10_AURORAX_4 GT10_AURORAX_4_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP),
877
GT10_AURORAX_n
.RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 8; user_instance_name.CHAN_BOND_64B66B_SV = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b10000011110; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "TRUE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 8; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "0_32"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1;
878
GT10_AURORAX_n
user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SH_CNT_MAX = 64; user_instance_name.SH_INVALID_CNT_MAX = 16; user_instance_name.TX_BUFFER_USE = "TRUE";
GT10_AURORAX_8 Verilog Code

GT10_AURORAX_8 GT10_AURORAX_8_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF),
879
GT10_AURORAX_n
.RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 8; user_instance_name.CHAN_BOND_64B66B_SV = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b10000011110; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "TRUE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 8; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111;
880
GT10_AURORAX_n
defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.PMA_SPEED = "0_64"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SH_CNT_MAX = 64; user_instance_name.SH_INVALID_CNT_MAX = 16; user_instance_name.TX_BUFFER_USE = "TRUE";

None
881
GT10_AURORAX_n
882
GT10_CUSTOM
GT10_CUSTOM
GT10_CUSTOM Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No
This 10-gigabit transceiver is fully customizable. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figure lists the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
883
GT10_CUSTOM
GT10_CUSTOM
X10050
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(7:0)
RXCHARISK(7:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(63:0)
RXDISPERR(7:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(7:0)
RXREALIGN
RXRECCLK
RXRUNDISP(7:0)
TXBUFERR
TXKERR(7:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(7:0)
884
GT10_CUSTOM
Usage

GT10_CUSTOM VHDL Code
-- Component Attribute specification for GT10_CUSTOM -- should be placed after architecture declaration but -- before the begin keyword component GT10_CUSTOM -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 1; integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; integer := 1; boolean := FALSE; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE;
885
GT10_CUSTOM
PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE
: : : : : : : : :
bit_vector := "11111111"; string := "0_32"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; integer := 64; integer := 16; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(63 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(7 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_ulogic; out std_logic_vector(7 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic;
886
GT10_CUSTOM
RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic_vector(63 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_CUSTOM -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_CUSTOM should be placed -- in architecture after the begin keyword GT10_CUSTOM_INSTANCE_NAME : GT10_CUSTOM -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_64B66B_SV => boolean_value,
887
GT10_CUSTOM
CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, integer_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, integer_value, integer_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK,
888
GT10_CUSTOM
TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
889
GT10_CUSTOM

GT10_CUSTOM Verilog Code
GT10_CUSTOM GT10_CUSTOM_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP),
890
GT10_CUSTOM
.RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_64B66B_SV = "FALSE"; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE";
891
GT10_CUSTOM
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "0_32"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SH_CNT_MAX = 64; user_instance_name.SH_INVALID_CNT_MAX = 16; user_instance_name.TX_BUFFER_USE = "TRUE";
892
GT10_INFINIBAND_n
GT10_INFINIBAND_n
GT10_INFINIBAND_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No
This Infiniband 10-gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figures lists the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
893
GT10_INFINIBAND_n
GT10_INFINIBAND_1
X10051
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(0:0)
RXCHARISK(0:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(7:0)
RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(0:0)
RXREALIGN
RXRECCLK
RXRUNDISP(0:0)
TXBUFERR
TXKERR(0:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(0:0)
894
GT10_INFINIBAND_n
GT10_INFINIBAND_2
X10052
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(1:0)
RXCHARISK(1:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(15:0)
RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(1:0)
RXREALIGN
RXRECCLK
RXRUNDISP(1:0)
TXBUFERR
TXKERR(1:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(1:0)
895
GT10_INFINIBAND_n
GT10_INFINIBAND_4
X10053
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
896
GT10_XAUI_n
GT10_XAUI_n
GT10_XAUI_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No No
This XAUI 10-gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.
897
GT10_XAUI_n
GT10_XAUI_1
X10062
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(0:0)
RXCHARISK(0:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(7:0)
RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(0:0)
RXREALIGN
RXRECCLK
RXRUNDISP(0:0)
TXBUFERR
TXKERR(0:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(0:0)
898
GT10_XAUI_n
GT10_XAUI_2
X10063
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(1:0)
RXCHARISK(1:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(15:0)
RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(1:0)
RXREALIGN
RXRECCLK
RXRUNDISP(1:0)
TXBUFERR
TXKERR(1:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(1:0)
899
GT10_XAUI_n
GT10_XAUI_4
X10064
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
900
GT10_XAUI_n
Usage

GT10_XAUI_1 VHDL Code
-- Component Attribute specification for GT10_XAUI_1 -- should be placed after architecture declaration but -- before the begin keyword component GT10_XAUI_1 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 2; integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111";
901
GT10_XAUI_n
PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH
: : : : : :
string := "25_10"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0);
902
GT10_XAUI_n
RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(7 std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
0); 0); 0); 0); 0); 0);
downto 0);
-- Component Attribute specification for GT10_XAUI_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_XAUI_1 should be placed -- in architecture after the begin keyword GT10_XAUI_1_INSTANCE_NAME : GT10_XAUI_1 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CLK_COR_8B10B_DE => boolean_value, CLK_COR_MAX_LAT => integer_value, CLK_COR_MIN_LAT => integer_value, CLK_COR_SEQ_1_1 => bit_value,
903
GT10_XAUI_n
CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC
=> => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC,
904
GT10_XAUI_n
ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
GT10_XAUI_2 Code
-- Component Attribute specification for GT10_XAUI_2 -- should be placed after architecture declaration but -- before the begin keyword component GT10_XAUI_2 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE
: integer := 2; : integer := 16; : string := "OFF";
905
GT10_XAUI_n
CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111"; string := "25_20"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : :
out out out out out out out out out out
std_ulogic; std_ulogic; std_ulogic; std_logic_vector(4 std_ulogic; std_logic_vector(1 std_logic_vector(1 std_logic_vector(1 std_logic_vector(2 std_ulogic;
906
GT10_XAUI_n
RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(15 downto 0); in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic;
907
GT10_XAUI_n
TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : :
in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_XAUI_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_XAUI_2 should be placed -- in architecture after the begin keyword GT10_XAUI_2_INSTANCE_NAME : GT10_XAUI_2 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CLK_COR_8B10B_DE => boolean_value, CLK_COR_MAX_LAT => integer_value, CLK_COR_MIN_LAT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_1_MASK => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_MASK => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_DROP => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, DEC_VALID_COMMA_ONLY => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value,
908
GT10_XAUI_n
PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE
=> => => => => => => => =>
bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE,
909
GT10_XAUI_n
RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
-- Component Attribute specification for GT10_XAUI_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_XAUI_4 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK
: : : : : : : : : : : : : : : : : : : : : : : :
integer := 2; integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000";
910
GT10_XAUI_n
CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT
: : : : : : : : : : : : : : : : : : : : : : : :
bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111"; string := "25_40"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic;
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GT10_XAUI_n
PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in
std_logic_vector(5 downto 0); std_logic_vector(7 downto 0); std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_XAUI_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_XAUI_4 should be placed -- in architecture after the begin keyword GT10_XAUI_4_INSTANCE_NAME : GT10_XAUI_4 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, CHAN_BOND_LIMIT => integer_value,
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GT10_XAUI_n
CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
string_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT,
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GT10_XAUI_n
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH,
914
GT10_XAUI_n
TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 End Here
=> => => => =>
user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);

GT10_XAUI_1 Verilog Code
GT10_XAUI_1 GT10_XAUI_1_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE),
915
GT10_XAUI_n
.RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 2; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000;
916
GT10_XAUI_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "25_10"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

GT10_XAUI_2 GT10_XAUI_2_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN),
917
GT10_XAUI_n
.PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 2; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36;
918
GT10_XAUI_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "25_20"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

GT10_XAUI_4 GT10_XAUI_4_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP),
919
GT10_XAUI_n
.BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 2; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000;
920
GT10_XAUI_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "25_40"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

None
921
GT10_XAUI_n
922
GT10_10GE_n
GT10_10GE_n
GT10_10GE_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No No
*Supported for Virtex-II Pro X but not for Virtex-II or Virtex-II Pro.
This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter n represents number of bytes of the data path. Valid values are 4 or 8. You can also set attributes for the primitives. See the RocketIO X Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO X Transceiver User Guide.
923
GT10_10GE_n
GT10_10GE_4
X10041
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
924
GT10_10GE_n
GT10_10GE_8
X10042
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(7:0)
RXCHARISK(7:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(63:0)
RXDISPERR(7:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(7:0)
RXREALIGN
RXRECCLK
RXRUNDISP(7:0)
TXBUFERR
TXKERR(7:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(7:0)
925
GT10_10GE_n
Usage

GT10_10GE_4 VHDL Code
-- Component Attribute specification for GT10_10GE_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_10GE_4 -- synopsys translate_off generic ( CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; integer := 8; boolean := FALSE; integer := 36; integer := 28; bit_vector := "10000011110"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; boolean := FALSE; integer := 8; boolean := TRUE; bit_vector := "11111111"; string := "6_32"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; integer := 64; integer := 16; boolean := TRUE);
926
GT10_10GE_n
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
927
GT10_10GE_n
: : : : : : : : : : : : : : : :
-- Component Attribute specification for GT10_10GE_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_10GE_4 should be placed -- in architecture after the begin keyword GT10_10GE_4_INSTANCE_NAME : GT10_10GE_4 -- synopsys translate_off generic map ( CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_64B66B_SV => boolean_value, CLK_COR_MAX_LAT => integer_value, CLK_COR_MIN_LAT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_1_MASK => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value,
928
GT10_10GE_n
=> => => => => => => => => => => => => =>
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
929
GT10_10GE_n
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
GT10_10GE_8 Code
-- Component Attribute specification for GT10_10GE_8 -- should be placed after architecture declaration but -- before the begin keyword component GT10_10GE_8 -- synopsys translate_off generic ( CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT
: : : : : : : : : : : : : : : : :
integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; integer := 8; boolean := FALSE; integer := 36;
930
GT10_10GE_n
CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT
: : : : : : : : : : : : : : : : : : : : : : : :
integer := 28; bit_vector := "10000011110"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; boolean := FALSE; integer := 8; boolean := TRUE; bit_vector := "11111111"; string := "6_64"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; integer := 64; integer := 16; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
931
GT10_10GE_n
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
-- Component Attribute specification for GT10_10GE_8 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_10GE_8 should be placed -- in architecture after the begin keyword GT10_10GE_8_INSTANCE_NAME : GT10_10GE_8 -- synopsys translate_off generic map ( CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value,
932
GT10_10GE_n
CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, integer_value, integer_value, boolean_value)
=> => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK,
933
GT10_10GE_n
RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 End Here
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
934
GT10_10GE_n

GT10_10GE_4 Verilog Code
GT10_10GE_4 GT10_10GE_4_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP),
935
GT10_10GE_n
.RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "TRUE"; user_instance_name.CHAN_BOND_SEQ_LEN = 8; user_instance_name.CHAN_BOND_64B66B_SV = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b10000011110; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "TRUE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 8; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "6_32"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1;
936
GT10_10GE_n
user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SH_CNT_MAX = 64; user_instance_name.SH_INVALID_CNT_MAX = 16; user_instance_name.TX_BUFFER_USE = "TRUE";
GT10_10GE_8 Verilog Code

GT10_10GE_8 GT10_10GE_8_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF),
937
GT10_10GE_n
.RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "TRUE"; user_instance_name.CHAN_BOND_SEQ_LEN = 8; user_instance_name.CHAN_BOND_64B66B_SV = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b10000011110; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "TRUE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 8; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111;
938
GT10_10GE_n
user_instance_name.PMA_SPEED = "6_64"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SH_CNT_MAX = 64; user_instance_name.SH_INVALID_CNT_MAX = 16; user_instance_name.TX_BUFFER_USE = "TRUE";
939
GT10_10GE_n
940
GT10_10GFC_n
GT10_10GFC_n
GT10_10GFC_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No No
This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter n represents number of bytes of the data path. Valid values are 4 or 8. You can also set attributes for the primitives. See the RocketIO X Transceiver User Guide for a description of these attributes and their default attribute values. For a description of the input and output ports for all values of n, see the RocketIO X Transceiver User Guide.
941
GT10_10GFC_n
GT10_10GFC_4
X10043
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
942
GT10_10GFC_n
GT10_10GFC_8
X10044
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(7:0)
RXCHARISK(7:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(63:0)
RXDISPERR(7:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(7:0)
RXREALIGN
RXRECCLK
RXRUNDISP(7:0)
TXBUFERR
TXKERR(7:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(7:0)
943
GT10_10GFC_n
Usage

GT10_10GFC_4 VHDL Code
-- Component Attribute specification for GT10_10GFC_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_10GFC_4 -- synopsys translate_off generic ( CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; integer := 8; boolean := FALSE; integer := 36; integer := 28; bit_vector := "10000011110"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; boolean := FALSE; integer := 8; boolean := TRUE; bit_vector := "11111111"; string := "0_32"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; integer := 64; integer := 16; boolean := TRUE);
944
GT10_10GFC_n
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
945
GT10_10GFC_n
: : : : : : : : : : : : : : : :
-- Component Attribute specification for GT10_10GFC_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_10GFC_4 should be placed -- in architecture after the begin keyword GT10_10GFC_4_INSTANCE_NAME : GT10_10GFC_4 -- synopsys translate_off generic map ( CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_1_MASK => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_MASK => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_64B66B_SV => boolean_value, CLK_COR_MAX_LAT => integer_value, CLK_COR_MIN_LAT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_1_MASK => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value,
946
GT10_10GFC_n
=> => => => => => => => => => => => => =>
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
947
GT10_10GFC_n
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
GT10_10GFC_8 VHDL Code

-- Component Attribute specification for GT10_10GE_8 -- should be placed after architecture declaration but -- before the begin keyword component GT10_10GE_8 -- synopsys translate_off generic ( CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT
: : : : : : : : : : : : : : : : :
integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; integer := 8; boolean := FALSE; integer := 36;
948
GT10_10GFC_n
CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT
: : : : : : : : : : : : : : : : : : : : : : : :
integer := 28; bit_vector := "10000011110"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := TRUE; boolean := FALSE; integer := 8; boolean := TRUE; bit_vector := "11111111"; string := "6_64"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; integer := 64; integer := 16; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
949
GT10_10GFC_n
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
-- Component Attribute specification for GT10_10GE_8 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_10GE_8 should be placed -- in architecture after the begin keyword GT10_10GE_8_INSTANCE_NAME : GT10_10GE_8 -- synopsys translate_off generic map ( CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value,
950
GT10_10GFC_n
CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_64B66B_SV CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SH_CNT_MAX SH_INVALID_CNT_MAX TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, integer_value, integer_value, boolean_value)
=> => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK,
951
GT10_10GFC_n
RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
952
GT10_10GFC_n

None
953
GT10_10GFC_n
954
GT10_OC48_n
GT10_OC48_n
GT10_OC48_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No No
This Xilinx protocol 10-gigabit transceiver supports 1, 2 and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2, or 4. You can also set attributes for the primitives. See the RocketIO X Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO X Transceiver User Guide.
955
GT10_OC48_n
GT10_OC48_1
X10056
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(0:0)
RXCHARISK(0:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(7:0)
RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(0:0)
RXREALIGN
RXRECCLK
RXRUNDISP(0:0)
TXBUFERR
TXKERR(0:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(0:0)
956
GT10_OC48_n
GT10_OC48_2
X10057
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(1:0)
RXCHARISK(1:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(15:0)
RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(1:0)
RXREALIGN
RXRECCLK
RXRUNDISP(1:0)
TXBUFERR
TXKERR(1:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(1:0)
957
GT10_OC48_n
GT10_OC48_4
X10058
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
958
GT10_OC48_n
Usage

GT10_OC48_1 VHDL Code
-- Component Attribute specification for GT10_OC48_1 -- should be placed after architecture declaration but -- before the begin keyword component GT10_OC48_1 -- synopsys translate_off generic ( ALIGN_COMMA_WORD COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN
: : : : : : : : : : : : : : :
integer := 1; bit_vector := "0011111111"; boolean := TRUE; boolean := TRUE; bit_vector := "0010101010"; boolean := TRUE; bit_vector := "0010101010"; boolean := TRUE; bit_vector := "11111111"; string := "31_8"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 out std_ulogic; out std_logic_vector(1 out std_logic_vector(0 out std_logic_vector(0 out std_logic_vector(2 out std_ulogic; out std_logic_vector(7 out std_logic_vector(0 out std_logic_vector(1 out std_logic_vector(0 out std_ulogic; out std_ulogic; out std_logic_vector(0 out std_ulogic; out std_logic_vector(0 out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(0 in std_ulogic;
downto 0); downto downto downto downto downto downto downto downto 0); 0); 0); 0); 0); 0); 0); 0);
downto 0); downto 0);
downto 0);
959
GT10_OC48_n
BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_logic_vector(4 std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_logic_vector(5 std_logic_vector(7 std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(7 std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
downto 0);
downto 0); downto 0); downto 0);
downto 0);
downto 0);
downto 0);
0); 0); 0); 0); 0); 0);
downto 0);
-- Component Attribute specification for GT10_OC48_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_OC48_1 should be placed
960
GT10_OC48_n
-- in architecture after the begin keyword GT10_OC48_1_INSTANCE_NAME : GT10_OC48_1 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, COMMA_10B_MASK => bit_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value, PCOMMA_10B_VALUE => bit_value, PCOMMA_DETECT => boolean_value, PMA_PWR_CNTRL => bit_value, PMA_SPEED => string_value, RX_BUFFER_USE => boolean_value, RX_LOS_INVALID_INCR => integer_value, RX_LOS_THRESHOLD => integer_value, RX_LOSS_OF_SYNC_FSM => boolean_value, TX_BUFFER_USE => boolean_value) -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE,
961
GT10_OC48_n
PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT10_OC48_2 -- should be placed after architecture declaration but -- before the begin keyword component GT10_OC48_2 -- synopsys translate_off generic ( ALIGN_COMMA_WORD COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE
: : : : : : : : : : :
integer := 1; bit_vector := "0011111111"; boolean := TRUE; boolean := TRUE; bit_vector := "0010101010"; boolean := TRUE; bit_vector := "0010101010"; boolean := TRUE; bit_vector := "11111111"; string := "31_16"; boolean := TRUE;
962
GT10_OC48_n
RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP
: : : :
integer integer boolean boolean
:= := := :=
1; 4; TRUE; TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic;
963
GT10_OC48_n
RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(15 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_OC48_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_OC48_2 should be placed -- in architecture after the begin keyword GT10_OC48_2_INSTANCE_NAME : GT10_OC48_2 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, COMMA_10B_MASK => bit_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value, PCOMMA_10B_VALUE => bit_value, PCOMMA_DETECT => boolean_value, PMA_PWR_CNTRL => bit_value, PMA_SPEED => string_value, RX_BUFFER_USE => boolean_value, RX_LOS_INVALID_INCR => integer_value, RX_LOS_THRESHOLD => integer_value, RX_LOSS_OF_SYNC_FSM => boolean_value, TX_BUFFER_USE => boolean_value) -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO
=> => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO,
964
GT10_OC48_n
PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH,
965
GT10_OC48_n
TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => =>
user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);

-- Component Attribute specification for GT10_OC48_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_OC48_4 -- synopsys translate_off generic ( ALIGN_COMMA_WORD COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN
: : : : : : : : : : : : : : :
: : : : : : : : : : : : : : : : : : : :
out out out out out out out out out out out out out out out out out out out out
std_ulogic; std_ulogic; std_ulogic; std_logic_vector(4 downto 0); std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(2 downto 0); std_ulogic; std_logic_vector(31 downto 0); std_logic_vector(3 downto 0); std_logic_vector(1 downto 0); std_logic_vector(3 downto 0); std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(3 downto 0); std_ulogic;
966
GT10_OC48_n
TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(31 downto 0); in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);
-- Component Attribute specification for GT10_OC48_4 -- should be placed after architecture declaration but -- before the begin keyword
967
GT10_OC48_n
-- Enter constraints here -- Component Instantiation for GT10_OC48_4 should be placed -- in architecture after the begin keyword GT10_OC48_4_INSTANCE_NAME : GT10_OC48_4 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, COMMA_10B_MASK => bit_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value, PCOMMA_10B_VALUE => bit_value, PCOMMA_DETECT => boolean_value, PMA_PWR_CNTRL => bit_value, PMA_SPEED => string_value, RX_BUFFER_USE => boolean_value, RX_LOS_INVALID_INCR => integer_value, RX_LOS_THRESHOLD => integer_value, RX_LOSS_OF_SYNC_FSM => boolean_value, TX_BUFFER_USE => boolean_value) -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT,
968
GT10_OC48_n
PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);

GT10_OC48_1 Verilog Code
GT10_OC48_1 GT10_OC48_1_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET),
969
GT10_OC48_n
.RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH),
970
GT10_OC48_n
.TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.COMMA_10B_MASK = 10'b0011111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "31_8"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

GT10_OC48_2 GT10_OC48_2_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR),
971
GT10_OC48_n
.PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.COMMA_10B_MASK = 10'b0011111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "31_16"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";
972
GT10_OC48_n
GT10_OC48_4 Code
GT10_OC48_4 GT10_OC48_4_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE),
973
GT10_OC48_n
.RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.COMMA_10B_MASK = 10'b0011111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "31_32"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

None
974
GT10_OC192_n
GT10_OC192_n
GT10_OC192_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No No
This Xilinx protocol 10-gigabit transceiver supports 4 and 8-byte data paths. The letter n represents number of bytes of the data path. Valid values are 4 or 8. You can also set attributes for the primitives. See the RocketIO X Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO X Transceiver User Guide.
975
GT10_OC192_n
GT10_OC192_4
BREFCLKNIN BREFCLKPIN CHBONDI(4:0) ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) PMAINIT PMAREGADDR(5:0) PMAREGDATAIN(7:0) PMAREGRW PMAREGSTROBE PMARXLOCKSEL(1:0) POWERDOWN REFCLKBSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH(1:0) RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH(1:0) RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(3:0) TXCHARDISPMODE(3:0) TXCHARDISPVAL(3:0) TXCHARISK(3:0) TXDATA(31:0) TXDATAWIDTH(1:0) TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH(1:0) TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
X10054
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
976
GT10_OC192_n
GT10_OC192_8
BREFCLKNIN BREFCLKPIN CHBONDI(4:0) ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) PMAINIT PMAREGADDR(5:0) PMAREGDATAIN(7:0) PMAREGRW PMAREGSTROBE PMARXLOCKSEL(1:0) POWERDOWN REFCLKBSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH(1:0) RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH(1:0) RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(7:0) TXCHARDISPMODE(7:0) TXCHARDISPVAL(7:0) TXCHARISK(7:0) TXDATA(63:0) TXDATAWIDTH(1:0) TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH(1:0) TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
X10055
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(7:0)
RXCHARISK(7:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(63:0)
RXDISPERR(7:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(7:0)
RXREALIGN
RXRECCLK
RXRUNDISP(7:0)
TXBUFERR
TXKERR(7:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(7:0)
977
GT10_OC192_n
Usage

-- Component Attribute specification for GT10_OC192_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_OC192_4 -- synopsys translate_off generic ( ALIGN_COMMA_WORD COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN
: : : : : : : : : : : : : : :
: : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic;
978
GT10_OC192_n
BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLKBSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_logic_vector(4 downto 0); std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_logic_vector(5 downto 0); std_logic_vector(7 downto 0); std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_OC192_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_OC192_4 should be placed -- in architecture after the begin keyword GT10_OC192_4_INSTANCE_NAME : GT10_OC192_4
979
GT10_OC192_n
-- synopsys translate_off generic map ( ALIGN_COMMA_WORD COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLKBSEL
=> => => => => => => => => => => => => => =>
integer_value, bit_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLKBSEL,
980
GT10_OC192_n
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

-- Component Attribute specification for GT10_OC192_8 -- should be placed after architecture declaration but -- before the begin keyword component GT10_OC192_8 -- synopsys translate_off generic ( ALIGN_COMMA_WORD COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on
: : : : : : : : : : : : : : :
981
GT10_OC192_n
port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLKBSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(63 downto 0); out std_logic_vector(7 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(7 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_ulogic; out std_logic_vector(7 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(7 downto 0); in std_logic_vector(7 downto 0); in std_logic_vector(7 downto 0); in std_logic_vector(7 downto 0);
982
GT10_OC192_n
TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : :
std_logic_vector(63 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_OC192_8 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_OC192_8 should be placed -- in architecture after the begin keyword GT10_OC192_8_INSTANCE_NAME : GT10_OC192_8 -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => integer_value, COMMA_10B_MASK => bit_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value, PCOMMA_10B_VALUE => bit_value, PCOMMA_DETECT => boolean_value, PMA_PWR_CNTRL => bit_value, PMA_SPEED => string_value, RX_BUFFER_USE => boolean_value, RX_LOS_INVALID_INCR => integer_value, RX_LOS_THRESHOLD => integer_value, RX_LOSS_OF_SYNC_FSM => boolean_value, TX_BUFFER_USE => boolean_value) -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC
=> => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC,
983
GT10_OC192_n
RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLKBSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLKBSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
984
GT10_OC192_n

GT10_OC192_4 GT10_OC192_4_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLKBSEL (user_REFCLKBSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE),
985
GT10_OC192_n
.RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.COMMA_10B_MASK = 10'b0011111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "15_32"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

GT10_OC192_8 GT10_OC192_8_name( .BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN),
986
GT10_OC192_n
.TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLKBSEL (user_REFCLKBSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 1; user_instance_name.COMMA_10B_MASK = 10'b0011111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b0010101010; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0010101010;
987
GT10_OC192_n
user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "15_64"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

None
988
GT10_PCI_EXPRESS_n
GT10_PCI_EXPRESS_n
GT10_PCI_EXPRESS_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No No
This Xilinx protocol 10-gigabit transceiver supports 1, 2 and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2, or 4. You can also set attributes for the primitives. See the RocketIO X Transceiver User Guide for a description of these attributes and their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO X Transceiver User Guide.
989
GT10_PCI_EXPRESS_n
GT10_PCI_EXPRESS_1
X10059
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(0:0)
RXCHARISK(0:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(7:0)
RXDISPERR(0:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(0:0)
RXREALIGN
RXRECCLK
RXRUNDISP(0:0)
TXBUFERR
TXKERR(0:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(0:0)
990
GT10_PCI_EXPRESS_n
GT10_PCI_EXPRESS_2
X10060
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(1:0)
RXCHARISK(1:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(15:0)
RXDISPERR(1:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(1:0)
RXREALIGN
RXRECCLK
RXRUNDISP(1:0)
TXBUFERR
TXKERR(1:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(1:0)
991
GT10_PCI_EXPRESS_n
GT10_PCI_EXPRESS_4
X10061
CHBONDDONE
CHBONDO(4:0)
PMARXLOCK
RXBUFSTATUS(1:0)
RXCHARISCOMMA(3:0)
RXCHARISK(3:0)
RXCLKCORCNT(2:0)
RXCOMMADET
RXDATA(31:0)
RXDISPERR(3:0)
RXLOSSOFSYNC(1:0)
RXNOTINTABLE(3:0)
RXREALIGN
RXRECCLK
RXRUNDISP(3:0)
TXBUFERR
TXKERR(3:0)
TXN
TXOUTCLK
TXP
TXRUNDISP(3:0)
992
GT10_PCI_EXPRESS_n
Usage
This design element is instantiated rather than inferred in the design code. VHDL Start

GT10_PCI_EXPRESS_1 Code
-- Component Attribute specification for GT10_PCI_EXPRESS_1 -- should be placed after architecture declaration but -- before the begin keyword component GT10_PCI_EXPRESS_1 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 2; integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "0000"; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001000101"; bit_vector := "00001000101"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE;
993
GT10_PCI_EXPRESS_n
PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF
: : : : : : :
bit_vector := "11111111"; string := "28_10"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;
994
GT10_PCI_EXPRESS_n
RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in
std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic_vector(7 std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
downto 0);
0); 0); 0); 0); 0); 0);
downto 0);
-- Component Attribute specification for GT10_PCI_EXPRESS_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_PCI_EXPRESS_1 should be placed -- in architecture after the begin keyword GT10_PCI_EXPRESS_1_INSTANCE_NAME -- synopsys translate_off generic map ( ALIGN_COMMA_WORD => CHAN_BOND_LIMIT => CHAN_BOND_MODE => CHAN_BOND_ONE_SHOT => CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_LEN => CLK_COR_8B10B_DE => CLK_COR_MAX_LAT => CLK_COR_MIN_LAT => : GT10_PCI_EXPRESS_1
integer_value, integer_value, string_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, integer_value, integer_value,
995
GT10_PCI_EXPRESS_n
CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI,
996
GT10_PCI_EXPRESS_n
ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
-- Component Attribute specification for GT10_PCI_EXPRESS_2 -- should be placed after architecture declaration but -- before the begin keyword component GT10_PCI_EXPRESS_2 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT
: integer := 2; : integer := 16;
997
GT10_PCI_EXPRESS_n
CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
string := "OFF"; boolean := FALSE; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "0000"; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001000101"; bit_vector := "00001000101"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111"; string := "28_20"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : :
out out out out out out out out out
std_ulogic; std_ulogic; std_ulogic; std_logic_vector(4 std_ulogic; std_logic_vector(1 std_logic_vector(1 std_logic_vector(1 std_logic_vector(2
998
GT10_PCI_EXPRESS_n
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(15 downto 0); in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0);
999
GT10_PCI_EXPRESS_n
TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP
: : : : :
in in in in in
std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT, user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP,
1000
GT10_PCI_EXPRESS_n
RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => => => => => => => => => => => => => => => => => =>
user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH, user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);
-- Component Attribute specification for GT10_PCI_EXPRESS_4 -- should be placed after architecture declaration but -- before the begin keyword component GT10_PCI_EXPRESS_4 -- synopsys translate_off generic ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2
: : : : : : : : : : : : : : : : : : : : : : : : : :
integer := 2; integer := 16; string := "OFF"; boolean := FALSE; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001001010"; bit_vector := "00001001010"; bit_vector := "0000"; bit_vector := "00110111100"; bit_vector := "00000000000"; bit_vector := "00001000101"; bit_vector := "00001000101"; bit_vector := "0000"; boolean := FALSE; integer := 2; boolean := FALSE; integer := 36; integer := 28; bit_vector := "00100011100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; bit_vector := "00000000000"; bit_vector := "00000000000";
1001
GT10_PCI_EXPRESS_n
CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT RXCOMMADET RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXOUTCLK TXP TXRUNDISP BREFCLKNIN BREFCLKPIN CHBONDI ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK PMAINIT PMAREGADDR PMAREGDATAIN
: : : : : : : : : : : : : : : : : : : : : :
bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "0000"; boolean := FALSE; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "0001111111"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1010000011"; boolean := TRUE; bit_vector := "0101111100"; boolean := TRUE; bit_vector := "11111111"; string := "28_40"; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := TRUE);
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(4 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(2 downto 0); out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_logic_vector(4 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_logic_vector(5 downto 0); in std_logic_vector(7 downto 0);
1002
GT10_PCI_EXPRESS_n
PMAREGRW PMAREGSTROBE PMARXLOCKSEL POWERDOWN REFCLK REFCLK2 REFCLKBSEL REFCLKSEL RXBLOCKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH RXDEC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH RXN RXP RXPOLARITY RXRESET RXSLIDE RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXDATAWIDTH TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINHIBIT TXINTDATAWIDTH TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2 end component;
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in
std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);
-- Component Attribute specification for GT10_PCI_EXPRESS_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT10_PCI_EXPRESS_4 should be placed -- in architecture after the begin keyword
GT10_PCI_EXPRESS_4_INSTANCE_NAME : GT10_PCI_EXPRESS_4
-- synopsys translate_off generic map ( ALIGN_COMMA_WORD CHAN_BOND_LIMIT
=> integer_value, => integer_value,
1003
GT10_PCI_EXPRESS_n
CHAN_BOND_MODE CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_MASK CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_MASK CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CLK_COR_8B10B_DE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_MASK CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_MASK CLK_COR_SEQ_2_USE CLK_COR_SEQ_DROP CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT PMA_PWR_CNTRL PMA_SPEED RX_BUFFER_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM TX_BUFFER_USE -- synopsys translate_on port map ( BREFCLKNOUT BREFCLKPOUT CHBONDDONE CHBONDO PMARXLOCK RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCLKCORCNT
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
string_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, bit_value, string_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value)
=> => => => => => => => =>
user_BREFCLKNOUT, user_BREFCLKPOUT, user_CHBONDDONE, user_CHBONDO, user_PMARXLOCK, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCLKCORCNT,
1004
GT10_PCI_EXPRESS_n
=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
user_RXCOMMADET, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXOUTCLK, user_TXP, user_TXRUNDISP, user_BREFCLKNIN, user_BREFCLKPIN, user_CHBONDI, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_PMAINIT, user_PMAREGADDR, user_PMAREGDATAIN, user_PMAREGRW, user_PMAREGSTROBE, user_PMARXLOCKSEL, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKBSEL, user_REFCLKSEL, user_RXBLOCKSYNC64B66BUSE, user_RXCOMMADETUSE, user_RXDATAWIDTH, user_RXDEC64B66BUSE, user_RXDEC8B10BUSE, user_RXDESCRAM64B66BUSE, user_RXIGNOREBTF, user_RXINTDATAWIDTH, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXSLIDE, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXDATAWIDTH, user_TXENC64B66BUSE, user_TXENC8B10BUSE, user_TXGEARBOX64B66BUSE, user_TXINHIBIT, user_TXINTDATAWIDTH,
1005
GT10_PCI_EXPRESS_n
TXPOLARITY TXRESET TXSCRAM64B66BUSE TXUSRCLK TXUSRCLK2
=> => => => =>
user_TXPOLARITY, user_TXRESET, user_TXSCRAM64B66BUSE, user_TXUSRCLK, user_TXUSRCLK2);

GT10_PCI_EXPRESS_1 GT10_PCI_EXPRESS_1_name(
.BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH),
1006
GT10_PCI_EXPRESS_n
.RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 2; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000;
1007
GT10_PCI_EXPRESS_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "28_10"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";
.BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN),
1008
GT10_PCI_EXPRESS_n
.PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 2; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36;
1009
GT10_PCI_EXPRESS_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "28_20"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";
.BREFCLKNOUT (user_BREFCLKNOUT), .BREFCLKPOUT (user_BREFCLKPOUT), .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .PMARXLOCK (user_PMARXLOCK), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXOUTCLK (user_TXOUTCLK), .TXP (user_TXP),
1010
GT10_PCI_EXPRESS_n
.TXRUNDISP (user_TXRUNDISP), .BREFCLKNIN (user_BREFCLKNIN), .BREFCLKPIN (user_BREFCLKPIN), .CHBONDI (user_CHBONDI), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .PMAINIT (user_PMAINIT), .PMAREGADDR (user_PMAREGADDR), .PMAREGDATAIN (user_PMAREGDATAIN), .PMAREGRW (user_PMAREGRW), .PMAREGSTROBE (user_PMAREGSTROBE), .PMARXLOCKSEL (user_PMARXLOCKSEL), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKBSEL (user_REFCLKBSEL), .REFCLKSEL (user_REFCLKSEL), .RXBLOCKSYNC64B66BUSE (user_RXBLOCKSYNC64B66BUSE), .RXCOMMADETUSE (user_RXCOMMADETUSE), .RXDATAWIDTH (user_RXDATAWIDTH), .RXDEC64B66BUSE (user_RXDEC64B66BUSE), .RXDEC8B10BUSE (user_RXDEC8B10BUSE), .RXDESCRAM64B66BUSE (user_RXDESCRAM64B66BUSE), .RXIGNOREBTF (user_RXIGNOREBTF), .RXINTDATAWIDTH (user_RXINTDATAWIDTH), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXSLIDE (user_RXSLIDE), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXDATAWIDTH (user_TXDATAWIDTH), .TXENC64B66BUSE (user_TXENC64B66BUSE), .TXENC8B10BUSE (user_TXENC8B10BUSE), .TXGEARBOX64B66BUSE (user_TXGEARBOX64B66BUSE), .TXINHIBIT (user_TXINHIBIT), .TXINTDATAWIDTH (user_TXINTDATAWIDTH), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXSCRAM64B66BUSE (user_TXSCRAM64B66BUSE), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_WORD = 2; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000;
1011
GT10_PCI_EXPRESS_n
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00001001010; user_instance_name.CHAN_BOND_SEQ_1_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00110111100; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00001000101; user_instance_name.CHAN_BOND_SEQ_2_MASK = 4'b0000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 2; user_instance_name.CLK_COR_8B10B_DE = "FALSE"; user_instance_name.CLK_COR_MAX_LAT = 36; user_instance_name.CLK_COR_MIN_LAT = 28; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00100011100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_MASK = 4'b0000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_DROP = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b0001111111; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1010000011; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0101111100; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.PMA_PWR_CNTRL = 8'b11111111; user_instance_name.PMA_SPEED = "28_40"; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.TX_BUFFER_USE = "TRUE";

None
1012
IBUF, 4, 8, 16
IBUF, 4, 8, 16
Single- and Multiple-Input Buffers
IBUF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II IBUF4 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II IBUF8, IBUF16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro Macro Macro Macro Macro No Macro Macro Macro Macro Primitive Primitive Primitive Primitive Primitive Primitive
IBUF
I O X9442
IBUF, IBUF4, IBUF8, and IBUF16 are single- and multiple-input buffers. An IBUF isolates the internal circuit from the signals coming into a chip. IBUFs are contained in input/output blocks (IOBs). IBUF inputs (I) are connected to an IPAD or an IOPAD. IBUF outputs (O) are connected to the internal circuit. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, see IBUF_selectIO for information on IBUF variants with selectable I/O interfaces.
IBUF4
I0 I1 I2 I3 O0 O1 O2 O3 X9443
1013
IBUF, 4, 8, 16
O[7:0]
IBUF8
IO I1 IBUF IBUF IBUF IBUF IBUF IBUF IBUF IBUF
O0 O1 O2 O3 O4 O5 O6 O7
X3803
I2 I3 I4
IBUF16
I5 I6
X3815
I7 I[7:0]
X7652
IBUF8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-II E, Virtex, Virtex-E
O[7:0]
I0 IBUF I1 IBUF I2 IBUF I3 IBUF I4 IBUF I5 IBUF I6 IBUF I7 IBUF I[7:0]
O0 O1 O2 O3 O4 O5 O6 O7
X9839
IBUF8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
IBUFs are typically inferred for all top level input ports, but they can also be instantiated if necessary.

-- Component Declaration for IBUF should be placed -- after architecture statement but before begin keyword component IBUF port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for IBUF -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here -- Component Instantiation for IBUF should be placed
1014
IBUF, 4, 8, 16
-- in architecture after the begin keyword IBUF_INSTANCE_NAME : IBUF port map (O => user_O, I => user_I);

IBUF instance_name (.O (user_O), .I (user_I));

BUFG (CPLDs) IOSTANDARD IOBDELAY
1015
IBUF, 4, 8, 16
1016
IBUF_selectIO
IBUF_selectIO
Single Input Buffer with Selectable I/O Interface
Architectures Supported IBUF_selectIO Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I O X9444
For Spartan-II, Spartan-IIE, Virtex, and Virtex-E, IBUF and its selectIO variants (listed in the "Components" column in the following table) are single input buffers whose I/O interface corresponds to a specific I/O standard. The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. For example, IBUF_SSTL3_II is a single input buffer that uses the SSTL3_II I/O-signaling standard. You can attach an IOSTANDARD attribute to an IBUF instance instead of using an IBUF_selectIO component. Check marks () in the "Spartan-II, Virtex" and "SpartanIIE, Virtex-E" columns indicate the components and IOSTANDARD attribute values available for those architectures. An IBUF isolates the internal circuit from the signals coming into a chip. For SpartanII, Spartan-IIE, Virtex, and Virtex-E, the dedicated GCLKIOB pad is input only. IBUF inputs (I) are connected to an IPAD or IOPAD. IBUF outputs (O) are connected to the internal circuit. The hardware implementation of the I/O standards requires that you follow a set of usage rules for the SelectIO buffers. See SelectIO Usage Rules below for information on using these components and IOSTANDARD attributes. Spartan-II, Spartan-IIE, Virtex, and Virtex-E IBUF_selectIO Components and IOSTANDARD Attributes
Component Spartan-II, Virtex Spartan-IIE, Virtex-E IOSTANDARD (Attribute Value) (defaults to LVTTL) AGP CTT GTL GTLP HSTL_I HSTL_III HSTL_IV LVCMOS2 VREF No 1.32 1.50 0.80 1.00 0.75 0.90 0.90 No Input VCCO 3.3 No No No No No 1.5 No 2.5
IBUF IBUF_AGP IBUF_CTT IBUF_GTL IBUF_GTLP IBUF_HSTL_I IBUF_HSTL_III IBUF_HSTL_IV IBUF_LVCMOS2
1017
IBUF_selectIO
Spartan-II, Spartan-IIE, Virtex, and Virtex-E IBUF_selectIO Components and IOSTANDARD Attributes
Component IBUF_LVCMOS18 IBUF_LVDS IBUF_LVPECL IBUF_PCI33_3 IBUF_PCI33_5 IBUF_PCI66_3 IBUF_PCIX66_3 IBUF_SSTL2_I IBUF_SSTL2_II IBUF_SSTL3_I IBUF_SSTL3_II Spartan-II, Virtex Spartan-IIE, Virtex-E IOSTANDARD (Attribute Value) LVCMOS18 LVDS LVPECL PCI33_3 PCI33_5 PCI66_3 PCIX66_3 SSTL2_I SSTL2_II SSTL3_I SSTL3_II VREF No No No No No No No 1.25 1.25 1.50 1.50 Input VCCO 1.8 No No 3.3 No 3.3 3.3 No No No No
The Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X library includes some IBUF_selectIO components for compatibility with older, existing designs and other architectures. For new Spartan-3 , Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs, however, the recommended method for using IBUF SelectIO buffers is to attach an IOSTANDARD attribute to an IBUF component. For example, attach IOSTANDARD=GTLP to an IBUF instead of using the IBUF_GTLP component for new Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs. The IOSTANDARD attributes that can be attached to an IBUF component are listed in the "IOSTANDARD (Attribute Value)" column in the following table. See SelectIO Usage Rules for information on using these IOSTANDARD attributes. Attach an IOSTANDARD attribute to an IBUF and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the input for the I/O standard asociated with that value. Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IBUF_selectIO IOSTANDARD Attributes
Architectures IOSTANDARD Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Attribute Values
Termination
Type Input
VREF Input*
Input VCCO
AGP GTL GTL_DCI GTLP GTLP_DCI HSTL_I HSTL_I_18 HSTL_I_DCI HSTL_I_DCI_18 HSTL_II
None None Single None Single None None Split Split None
1.32 0.80 0.80 1.00 1.00 0..75 0.9 0.75 0.9 0.75
No No 1.2 No 1.5 No No 1.5 1.8 No
1018
IBUF_selectIO
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IBUF_selectIO IOSTANDARD Attributes

Termination
Type Input
VREF Input*
Input VCCO
HSTL_II_18 HSTL_II_DCI HSTL_II_DCI_18 HSTL_III HSTL_III_18 HSTL_III_DCI HSTL_III_DCI_18 HSTL_IV HSTL_IV_18 HSTL_IV_DCI HSTL_IV_DCI_18 LVCMOS12 LVCMOS15 LVCMOS18 LVCMOS25 LVCMOS33 LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25 LVDCI_DV2_33 LVTTL (default) PCI33_3 PCI66_3 PCIX SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II_DCI SSTL2_I SSTL2_I_DCI SSTL2_II SSTL2_II_DCI SSTL3_I SSTL3_I_DCI
None Split Split None None Single Single None None Single Single None None None None None None None None None None None None None None None None None None Split None Split None Split None Split None Split
0.9 0.75 0.9 0.90 1.10 0.90 1.10 0.90 1.10 0.90 1.10 No No No No No No No No No No No No No No No No No 0.9 0.9 0.9 0.9 1.25 1.25 1.25 1.25 1.50 1.50
No 1.5 1.8 No No 1.5 1.8 No No 1.5 1.8 1.2 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 No 1.8 No 1.8 No 2.5 No 2.5 No 3.3
1019
IBUF_selectIO
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IBUF_selectIO IOSTANDARD Attributes

Termination
Type Input
VREF Input*
Input VCCO
SSTL3_II SSTL3_II_DCI
None Split
1.50 1.50
No 3.3
* VREF requirement when this IOSTANDARD is an input.
SelectIO Usage Rules

The Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X architectures include a versatile SelectIO interface to multiple voltage and drive standards. To select an I/O standard, you must choose the appropriate component from the library or add an IOSTANDARD attribute to the appropriate buffer component. For example, for an input buffer that uses the GTL standard, you would choose the IBUF_GTL component or choose the IBUF component and attach the IOSTANDARD=GTL attribute to it. See the following sections for information on the various input/output buffer components and attributes available to implement the desired standard: IBUF_selectIO IBUFG, IBUFG_selectIO IOBUF, IOBUF_selectIO OBUF_selectIO OBUFT_selectIO
The hardware implementation of the various I/O standards requires that certain usage rules be followed. Each I/O standard has voltage source requirements for input reference (VREF), output drive (VCCO), or both. In addition, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X have terminate type requirements. Each Spartan-II, Spartan-IIE, Virtex, Virtex-E, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X device has eight banks (two on each edge). Each bank has voltage sources shared by all I/O in the bank. Therefore, in a particular bank, the voltage source (for either input or output) must be of the same type. For Spartan-II, Spartan-IIE, Virtex, and Virtex-E, see Virtex, Virtex-E, Spartan-II, and Spartan-IIE Banking Rules below. Virtex-E follows the same banking rules as Virtex with a few additions. See Additional Banking Rules for Virtex-E and Spartan-IIE below for the additional Virtex-E rules. Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X have their own set of banking rules. See Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X Banking Rules below for Virtex-II, Virtex-II Pro, and Virtex-II Pro X rules.
Virtex, Virtex-E, Spartan-II, and Spartan-IIE Banking Rules

The hardware implementation of the various I/O standards requires that certain usage rules be followed. As shown in the following table, each I/O standard has voltage source requirements for input reference (VREF), output drive (VCCO), or
1020
IBUF_selectIO
both. Each Spartan-II, Spartan-IIE, Virtex, and Virtex-E device has eight banks (two on each edge). Each bank has voltage sources shared by all I/O in the bank. Therefore, in a particular bank, the voltage source (for either input or output) must be of the same type. The Input Banking (VREF) Rules section and the Output Banking (VCCO) Rules section below summarize the SelectIO component usage rules based on the hardware implementation. I/O Standards Supported in Virtex, Virtex-E, Spartan-II, and Spartan-IIE
I/O Standard AGP CTT LVTTL LVCMOS2 PCI33_3 PCI33_5 Application Graphics Memory General Purpose General Purpose PCI PCI Description Advanced graphics port Center tap terminated Low voltage transistor-transistor logic Low voltage complementary metaloxide semiconductor Peripheral component interface (33MHz 3.3V) Peripheral component interface (33MHZ 5.0V) PCI33_5 is not supported for Virtex-E or Spartan-IIE. PCI66_3 GTL GTL+ (GTLP) HSTL_I HSTL_III HSTL_IV SSTL2_I SSTL2_II SSTL3_I SSTL3_II PCI Backplane Backplane Hitachi SRAM Hitachi SRAM Hitachi SRAM Synchronous DRAM Synchronous DRAM Synchronous DRAM Synchronous DRAM Peripheral component interface (66MHz 3.3V) Gunning transceiver logic interface (to processors or backplane driver) Gunning transceiver logic interface Plus High Speed transceiver logic High Speed transceiver logic High Speed transceiver logic Stub-series terminated logic interface for SDRAM Stub-series terminated logic interface for SDRAM Stub-series terminated logic interface for SDRAM Stub-series terminated logic interface for SDRAM 3.3 No No 1.5 1.5 1.5 2.5 2.5 3.3 3.3 3.3* No No No No No No No No No No 0.80 1.00 0.75 0.90 0.90 1.25 1.25 1.50 1.50 Output VCCO 3.3 3.3 3.3 2.5 3.3 3.3 Input VCCO No No 3.3* 2.5* 3.3* No VREF 1.32 1.50 No No No No
*Only LVTTL, LVCMOS, and PCI need Input VCCO in Virtex-E and Spartan-IIE parts.
Input Banking (VREF) Rules

The low-voltage I/O standards that have a differential amplifier input require a voltage reference input (VREF). The VREF voltage source is provided as an external signal to the chip. Any input buffer component that does not require a VREF source (LVTTL, LVCMOS2, PCI) can be placed in any bank.
1021
IBUF_selectIO
All input buffer components that require a VREF source (GTL*, HSTL*, SSTL*, CTT, AGP) must be of the same I/O standard in a particular bank. For example, IBUF_SSTL2_I and IBUFG_SSTL2_I are compatible since they are the same I/O standard (SSTL2_I). If the bank contains any input buffer component that requires a VREF source, the following conditions apply.

One or more VREF sources must be connected to the bank via an IOB. The number of VREF sources is dependent on the device and package. The locations of the VREF sources are fixed for each device/package. All VREF sources must be used in that bank.
If the bank contains no input buffer component that requires a VREF source, the IOBs for VREF sources can be used for general I/O. Output buffer components of any type can be placed in the bank.
Output Banking (VCCO) Rules Because Virtex, Virtex-E, Spartan-II, and Spartan-IIE have multiple low-voltage standards, some control is required over the distribution of VCCO, the drive source voltage for output pins. To provide for maximum flexibility, the output pins are banked. In comparison to the VREF sources described above, the VCCO voltage sources are dedicated pins on the device and do not consume valuable IOBs. Any output buffer component that does not require a VCCO source (GTL, GTL+) can be placed in any bank. To be placed in a particular bank, all output buffer components that require VCCO must have the same supply voltage (VCCO). For example, OBUF_SSTL3_I and OBUF_PCI33_3 are compatible in the same output bank since VCCO=3.3 for both. Input buffer components of any type can be placed in the bank. The configuration pins on a Virtex, Virtex-E, Spartan-II, and Spartan-IIE device are on the right side of the chip. When configuring the device through a serial ProM, the user is required to use a VCCO of 3.3V in the two banks on the right hand side of the chip. If the user is not configuring the device through a serial ProM, the VCCO requirement is dependent upon the configuration source.
Banking Rules for OBUFT_selectIO with KEEPER If a KEEPER symbol is attached to an OBUFT_selectIO component (3-state output buffer) for an I/O standard that requires a VREF (for example, OBUFT_GTL, OBUFT_SSTL3_I), then the OBUFT_selectIO component follows the same rules as an IOBUF_selectIO component for the same standard. It must follow both the input banking and output banking rules. The KEEPER element requires that the VREF be properly driven.
Additional Banking Rules for Virtex-E and Spartan-IIE

The Virtex-E and Spartan-IIE architectures requires the same banking rules as described in the Virtex, Virtex-E, Spartan-II, and Spartan-IIE Banking Rules section.
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IBUF_selectIO
Additional I/O standards are supported as indicated in the following table. Additional I/O Standards Supported in Virtex-E and Spartan-IIE
I/O Standard Single Ended: LVCMOS18 General Purpose Low voltage complementary metaloxide semiconductor Low voltage differential signal 1.8 1.8 No Application Description Output VCCO Input VCCO VREF
Differential Signaling: LVDS Point-to-point or multi-drop backplanes, high noise immunity 2.5 2.5 No
LVPECL
High performance clocking, Low voltage positive emitter couple backplanes, differential logic 100MHz+ clocking, optical transceiver, high speed networking and mixed-signal interfacing
2.5
2.5
No
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X Banking Rules

The hardware implementation of the various I/O standards requires that certain usage rules be followed. Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices have eight banks (two on each edge), numbered from 0 through 7. Each bank has voltage sources shared by all I/O in the bank. The following table describes each I/O standard.
Descriptions of I/O Standards Supported In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X I/O Standard Single-Ended: AGPc GTL GTL_DCI GTL+ (GTLP) GTLP_DCI HSTL_I HSTL_I_18 HSTL_I__DCI HSTL_I__DCI_18 HSTL_II HSTL_II_18 HSTL_II__DCI HSTL_II__DCI_18 HSTL_III Graphics Memory Memory Memory Memory Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Advanced graphics port Gunning transceiver logic interface (to processors or backplace driver) Gunning transceiver logic interface with on-chip Digital Controlled Impedance Gunning transceiver logic interface Plus Gunning transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic High Speed transceiver logic High Speed transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic High Speed transceiver logic High Speed transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic Application Description
1023
IBUF_selectIO
Descriptions of I/O Standards Supported In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X I/O Standard HSTL_III_18 HSTL_III__DCI HSTL_III__DCI_18 HSTL_IVb HSTL_IV_18b HSTL_IV__DCIb HSTL_IV__DCI_18b LVCMOS12ad LVCMOS15a LVCMOS18a LVCMOS25a LVCMOS33ab LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33b LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25 LVDCI_DV2_33b LVTTLab PCI33_3b PCI66_3b PCIXb SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II_DCIb SSTL2_I Application Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM Hitachi SRAM General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose PCI PCI PCI High Speed transceiver logic High Speed transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic High Speed transceiver logic High Speed transceiver logic interface with on-chip Digital Controlled Impedance High Speed transceiver logic interface with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor Low voltage complementary metal-oxide semiconductor Low voltage complementary metal-oxide semiconductor Low voltage complementary metal-oxide semiconductor Low voltage complementary metal-oxide semiconductor Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage complementary metal-oxide semiconductor with on-chip Digital Controlled Impedance Low voltage transistor-transistor logic Peripheral component interface (33MHz 3.3V) Peripheral component interface (66MHz 3.3V) Peripheral component interface Description
Synchronous DRAM Stub-series terminated logic interface for SDRAM Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital Controlled Impedance Synchronous DRAM Stub-series terminated logic interface for SDRAM Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital Controlled Impedance Synchronous DRAM Stub-series terminated logic interface for SDRAM
1024
IBUF_selectIO
Descriptions of I/O Standards Supported In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X I/O Standard SSTL2_I_DCI SSTL2_II SSTL2_II_DCI SSTL3_Ib SSTL3_I_DCIb SSTL3_IIb SSTL3_II_DCIb Application Description
Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital Controlled Impedance Synchronous DRAM Stub-series terminated logic interface for SDRAM Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital Controlled Impedance Synchronous DRAM Stub-series terminated logic interface for SDRAM Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital Controlled Impedance Synchronous DRAM Stub-series terminated logic interface for SDRAM Synchronous DRAM Stub-series terminated logic interface for SDRAM with on-chip Digital Controlled Impedance
Notes: a LVTTL, LVCMOS15, LVCMOS18, and LVCMOS25 also require DRIVE and SLEW (FAST or Slow) attributes. b Not supported for Spartan-3 c Supported for Virtex-II only d Supported for Spartan-3 only
The following rules apply for using the various IO standards with Spartan-3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X: In any particular Spartan-3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X I/O bank, the voltage sources (both input and output) must be compatible. That is, they must have either the same voltage or an undefined (No) voltage. VREF, VCCO input, and VCCO output must be compatible within an I/O bank. In addition, to VREF and VCCO compatibility, the terminate type I/O standards must be compatible within the bank. For terminate type compatibility, the following rules apply:

Only one I/O buffer with terminate type of SINGLE can be in a particular bank. Only one I/O buffer with terminate type of SPLIT can be in a particular bank. Multiple I/O buffers with NONE and DRIVER terminate types can be in a particular bank. SPLIT and SINGLE can co-exist in the same bank. NONE and DRIVER types can co-exist with SPLIT and SINGLE types.
The bottom edge of a Spartan-3, Virtex-II Pro, or Virtex-II Pro X device is set for 3.3V. Therefore, on the bottom edge of the device, VCCO output and VCCO input must be 3.3V or No. To place an I/O buffer that requires a VREF in a bank, the reserved VREF sites in that bank must be empty. To place an I/O buffer that has a terminate type of SINGLE, SPLIT, or DRIVER in a bank, the reserved VREF sites in that bank must be empty. For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, differential signaling standards apply to IBUFDS, IBUFGDS, IBUFGDS_DIFF_OUT, OBUFDS, and OBUFTDS only (not IBUF or OBUF).
1025
IBUF_selectIO
The following table summarizes the values that you need to check for compatibility for each combination of I/O buffer programming (input, output, or bidirectional buffer). For example, the table shows that if you configure an output buffer as LVCMOS25, which has an output voltage of 2.5V, and an input buffer as LVCMOS15, which as an input voltage of 1.5V, the Out/In Voltage is checked. Because they have different voltages, this combination would not be allowed in a particular I/O bank.
IOB Programming Combinations Input Input Input Output Output Output Bidirectional Bidirectional Bidirectional Input Output Bidirectional Input Output Bidirectional Input Output Bidirectional
VREF Check Check
Output VCCO
Input VCCO Check
Out/In Voltage
Check Check Check Check Check Check Check Check Check Check Check Check Check Check Check Check
Usage
The recommended usage for IBUF_selectIO is to allow the IBUFs be inferred and apply the IOSTANDARD constraint to the input in either the UCF or in the HDL code. IBUF_selectIO can also be instantiated if necessary.

-- Component Declaration for IBUF_selectIO should be placed -- after architecture statement but before begin keyword component IBUF_selectIO port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for IBUF_selectIO -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IBUF_selectIO should be placed -- in architecture after the begin keyword IBUF_selectIO_INSTANCE_NAME : IBUF_selectIO port map (O => user_O, I => user_I);

IBUF_selectIO instance_name (.O (user_O), .I (user_I));
1026
IBUF_selectIO

IOBDELAY, IOSTANDARD
1027
IBUF_selectIO
1028
IBUFDS
IBUFDS
Differential Signaling Input Buffer with Selectable I/O Interface
IBUFDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I IB
X9255
IBUFDS is an input buffer that supports low-voltage, differential signaling. In IBUFDS, a design level interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).
Inputs I 0 0 1 1 IB 0 1 0 1
Outputs O -* 0 1 -*
* The dash (-) means No Change. The IOSTANDARD attribute values listed in the following table can be applied to an IBUFDS component to provide selectIO interface capability. A separate SelectIO component is not provided. Attach an IOSTANDARD attribute to an IBUFDS and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the inputs for the I/O standard associated with that value.
Architectures IOSTANDARD BLVDS_25 LDT_25 LDT_25_DT LVDS_25 (default) LVDS_25_DCI LVDS_33 Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X None Split None No No No No 2.5 No Termination Type Input None None Attribute Values VREF Input * No No Input VCCO No No
1029
IBUFDS
Architectures IOSTANDARD LVDSEXT_25 LVDSEXT_25_DCI LVDSEXT_33 LVDS_25_DT LVDXEST_25_DT LVPECL_25 LVPECL_33 ULVDS_25 ULVDS_25_DT
Attribute Values Termination Type Input None Split None None None None No No No No No No VREF Input * No No No Input VCCO No 2.5 No
Spartan-3
Virtex-II
Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, this design element is supported for instantiation but not for inference.

-- Component Declaration for IBUFDS should be placed -- after architecture statement but before begin keyword component IBUFDS port (O : out STD_ULOGIC; I : in STD_ULOGIC; IB : in STD_ULOGIC); end component; -- Component Attribute specification for IBUFDS -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IBUFDS should be placed -- in architecture after the begin keyword IBUFDS_INSTANCE_NAME : IBUFDS port map (O => user_O, I => user_I, IB => user_IB);

IBUFDS instance_name (.O (user_O), .I (user_I), .IB (user_IB));
1030
IBUFDS

IOSTANDARD IOBDELAY
1031
IBUFDS
1032
IBUFG, IBUFG_selectIO
Dedicated Input Buffer with Selectable I/O Interface
IBUFG, IBUFG_selectIO Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I O X9444
For Virtex, Virtex-E, Spartan-II, and Spartan-IIE, IBUFG and its selectIO variants (listed in the "Components" column in the table below) are dedicated input buffers for connecting to the clock buffer BUFG or CLKDLL. The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. For example, IBUFG_SSTL3_II is a single input buffer that uses the SSTL3_II I/O-signaling standard. You can attach an IOSTANDARD attribute to an IBUFG instance instead of using an IBUFG_selectIO component. Check marks () in the "Spartan-II, Virtex" and "Spartan-IIE, Virtex-E" columns indicate the components and IOSTANDARD attribute values available for those architectures. The Xilinx implementation software converts each BUFG to an appropriate type of global buffer for the target PLD device. The IBUFG input can only be driven by the global clock pins. The IBUFG output can drive CLKIN of a DLL/DCM, BUFG, or user logic. IBUFG can be routed to user logic and does not have to be routed to a DLL. The IBUFG can only be driven by an IPAD. The hardware implementation of the I/O standards requires that you follow a set of usage rules for the SelectIO buffers. See the SelectIO Usage Rules section included in the IBUF_selectIO section for information on using these components and the IOSTANDARD attributes. Spartan-II, Spartan-IIE, Virtex, and Virtex-E IBUFG_selectIO Components and IOSTANDARD Attributes
Component Spartan-II, Virtex Spartan-IIE, Virtex-E IOSTANDARD (Attribute Value) (defaults to LVTTL) AGP CTT GTL GTLP HSTL_I HSTL_III HSTL_IV VREF No 1.32 1.50 0.80 1.00 0.75 0.90 0.90 Input VCCO 3.3 No No No No No 1.5 No
IBUFG IBUFG_AGP IBUFG_CTT IBUFG_GTL IBUFG_GTLP IBUFG_HSTL_I IBUFG_HSTL_III IBUFG_HSTL_IV
1033
Spartan-II, Spartan-IIE, Virtex, and Virtex-E IBUFG_selectIO Components and IOSTANDARD Attributes
Component IBUFG_LVCMOS2 IBUFG_LVCMOS18 IBUFG_LVDS IBUFG_LVPECL IBUFG_PCI33_3 IBUFG_PCI33_5 IBUFG_PCI66_3 IBUFG_PCIX66_3 IBUFG_SSTL2_I IBUFG_SSTL2_II IBUFG_SSTL3_I IBUFG_SSTL3_II
Not
Spartan-II, Virtex
Spartan-IIE, Virtex-E
IOSTANDARD (Attribute Value) LVCMOS2 LVCMOS18 LVDS LVPECL PCI33_3 PCI33_5 PCI66_3 PCIX66_3 SSTL2_I SSTL2_II SSTL3_I SSTL3_II
VREF No No No No No No No No 1.25 1.25 1.50 1.50
Input VCCO 2.5 1.8 No No 3.3 No 3.3 3.3 No No No No
supported for Virtex-E.
The Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X library includes some IBUFG_selectIO components for compatibility with older, existing designs and other architectures. For new Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs, however, the recommended method for using IBUFG SelectIO buffers is to attach an IOSTANDARD attribute to an IBUFG component. For example, attach IOSTANDARD=GTLP to an IBUFG instead of using the IBUFG_GTLP component for new Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs. The IOSTANDARD attributes that can be attached to an IBUFG component are listed in the "IOSTANDARD (Attribute Value)" column in the following tableSpartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IBUFG_selectIO IOSTANDARD Attributes table. See the SelectIO Usage Rules section for information on using these IOSTANDARD attributes. Attach an IOSTANDARD attribute to an IBUFG and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the input for the I/O standard asociated with that value. Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IBUFG_selectIO IOSTANDARD Attributes
Architectures IOSTANDARD Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Termination Type Input Attribute Values VREF Input * Input VCCO
AGP GTL GTL_DCI GTLP GTLP_DCI HSTL_I HSTL_I_18
None None Single None Single None None
1.32 0.80 0.80 1.00 1.00 0.75 0.9
No No 1.2 No 1.5 No No
1034
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IBUFG_selectIO IOSTANDARD Attributes

HSTL_I_DCI HSTL_I_DCI_18 HSTL_II_18 HSTL_II_DCI_18 HSTL_III HSTL_III_18 HSTL_III_DCI HSTL_III_DCI_18 HSTL_IV HSTL_IV_18 HSTL_IV_DCI HSTL_IV_DCI_18 LVCMOS18 LVCMOS25 LVCMOS33 LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25 LVDCI_DV2_33 LVTTL (default) PCI33_3 PCI66_3 PCIX SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II_DCI SSTL2_I SSTL2_I_DCI SSTL2_II SSTL2_II_DCI SSTL3_I SSTL3_I_DCI
Split Split None Split None None Single Single None None Single Single None None None None None None None None None None None None None None None None Split None Split None Split None Split None Split
0.75 0.9 0.9 0.9 0.90 1.10 0.90 1.10 0.90 1.1 0.90 1.10 No No No No No No No No No No No No No No No 0.9 0.9 0.9 0.9 1.25 1.25 1.25 1.25 1.50 1.50
1.5 1.8 No 1.8 No No 1.5 1.8 No No 1.5 1.8 1.8 2.5 3.3 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 No 1.8 No 1.8 No 2.5 No 2.5 No 3.3
1035
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IBUFG_selectIO IOSTANDARD Attributes

SSTL3_II SSTL3_II_DCI
None Split
1.50 1.50
No 3.3
Usage
This design element is supported for schematic and instantiation. Synthesis tools usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the synthesis tool usually instantiates BUFGPs for the clocks that are most utilized. The BUFGP contains both a BUFG and an IBUFG.

-- Component Declaration for IBUFG should be placed -- after architecture statement but before begin keyword component IBUFG port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for IBUFG -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IBUFG should be placed -- in architecture after the begin keyword IBUFG_INSTANCE_NAME : IBUFG port map (O => user_O, I => user_I);

IBUFG instance_name (.O (user_O), .I (user_I));

IOSTANDARD IOBDELAY
1036
IBUFGDS
IBUFGDS
Dedicated Differential Signaling Input Buffer with Selectable I/O Interface
IBUFGDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
I IB
X9255
IBUFGDS is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or DCM. In IBUFGDS, a design level interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).
Inputs I 0 0 1 1 IB 0 1 0 1 Outputs O -* 0 1 -*
* The dash (-) means No Change. The IOSTANDARD attribute values listed in the following table can be applied to an IBUFGDS component to provide SelectIO interface capability. See the Xilinx Constraints Guide for information about using these attributes. A separate SelectIO component is not provided. Attach an IOSTANDARD attribute to an IBUFGDS and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the inputs for the I/O standard associated with that value.
Architectures IOSTANDARD BLVDS_25 LDT_25 LDT_25_DT LVDS_25 (default) LVDS_25_DCI Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X None Split No No No 2.5 Termination Type Input None None Attribute Values VREF Input * No No Input VCCO No No
1037
IBUFGDS
Architectures IOSTANDARD LVDS_25_DT LVDS_33 LVDSEXT_25 LVDSEXT_25_DCI LVDSEXT_33 LVDXEST_25_DT LVPECL_25 LVPECL_33 ULVDS_25 ULVDS_25_DT
Attribute Values Virtex-II Pro, Virtex-II Pro X Termination Type Input VREF Input * Input VCCO
Spartan-3
Virtex-II
None None None None None Split None
No No 2.5 No No No No
Usage
For HDL, this design element is supported for instantiation but not for inference.

-- Component Declaration for IBUFGDS should be placed -- after architecture statement but before begin keyword component IBUFGDS port (O : out STD_ULOGIC; I : in STD_ULOGIC; IB : in STD_ULOGIC); end component; -- Component Attribute specification for IBUFGDS -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IBUFGDS should be placed -- in architecture after the begin keyword IBUFGDS_INSTANCE_NAME : IBUFGDS port map (O => user_O, I => user_I, IB => user_IB);

IBUFGDS instance_name (.O (user_O), .I (user_I), .IB (user_IB));
1038
IBUFGDS

IOSTANDARD IOBDELAY
1039
IBUFGDS
1040
IBUFGDS_DIFF_OUT
IBUFGDS_DIFF_OUT
Differential I/O Input Buffer with Differential Outputs
IBUFGDS_DIFF_OUT Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
IBUFGDS_DIFF_OUT is a differential I/O input buffer with differential outputs. The differential output pair (O & OB) maintains the relation of its differential input pair. Thus, IBUFGDS_DIFF_OUT can be used to maintain the duty cycle of a clock input (even at high frequencies). In order to support this behavior, the outputs of IBUFGDS_DIFF_OUT need to drive a set of matched resources. Our recommended method for achieving this is to use the IBUFGDS_DIFF_OUT primitive driving two BUFGs which, by construction, will use two legs of the global clock network as the matched routing network. An example application is available at XAPP622 on the Xilinx support website at http://www.xilinx.com/xapp/xapp622.pdf.
Usage
IBUFGDS_DIFF_OUT is instantiated rather than inferred.

component IBUFGDS_DIFF_OUT
port (O : out OB : out I : in IB : in end component; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC);

module IBUFGDS_DIFF_OUT (O, OB, I, IB); output O, OB; input I, IB; endmodule Architectures IOSTANDARD BLVDS_25 LDT_25 LDT_25_DT Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Termination Type Input None None Attribute Values VREF Input * No No Input VCCO No No
1041
IBUFGDS_DIFF_OUT
Architectures IOSTANDARD LVDS_25 (default) LVDS_25_DCI LVDS_25_DT LVDS_33 LVDSEXT_25 LVDSEXT_25_DCI LVDSEXT_33 LVDXEST_25_DT LVPECL_25 LVPECL_33 ULVDS_25 ULVDS_25_DT
Attribute Values Virtex-II Pro, Virtex-II Pro X Termination Type Input None Split None None None None No No No No No No None Split None VREF Input * No No No No No No Input VCCO No 2.5 No No 2.5 No
Spartan-3
Virtex-II

Location constraint : Same as IBUFGDS
1042
ICAP_VIRTEX2
ICAP_VIRTEX2
User Interface to Virtex-II, Virtex-II Pro, and Virtex-II Pro X Internal Configuration Access Port
ICAP_VIRTEX, ICAP_VIRTEX2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
ICAP_VIRTEX2 I [7:0] WRITE CE CLK O [7:0] BUSY
No No No No No No
ICAP_VIRTEX2 provides user access to the Virtex-II, Virtex-II Pro, and Virtex-II Pro X internal configuration access port (ICAP).
Usage
X9256

-- Component Declaration for ICAP_VIRTEX2 should be placed -- after architecture statement but before begin keyword component ICAP_VIRTEX2 port (BUSY : out STD_ULOGIC; O : out STD_LOGIC_VECTOR (7 downto 0); CE : in STD_ULOGIC; CLK : in STD_ULOGIC; I : in STD_LOGIC_VECTOR (7 downto 0); WRITE : in STD_ULOGIC); end component; -- Component Attribute specification for ICAP_VIRTEX2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for ICAP_VIRTEX2 should be placed -- in architecture after the begin keyword ICAP_VIRTEX2_INSTANCE_NAME : ICAP_VIRTEX2 port map (BUSY => user_BUSY, O => user_O, CE => user_CE, CLK => user_CLK,
1043
ICAP_VIRTEX2
I => user_I, WRITE => user_WRITE);

ICAP_VIRTEX2 instance_name (.BUSY (user_BUSY), .O (user_O), .CE (user_CE), .CLK (user_CLK), .I (user_I), .WRITE (user_WRITE));

None
1044
IFD, 4, 8, 16
IFD, 4, 8, 16
Single- and Multiple-Input D Flip-Flops
IFD, IFD4, IFD8, IFD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
IFD
X3776
The IFD D-type flip-flop is contained in an input/output block (IOB), except for XC9500/XV/XL, CoolRunner XPLA3. The input (D) of the flip-flop is connected to an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, which synchronizes data entering the chip. The data on input D is loaded into the flip-flop during the Low-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. The flip-flops are asynchronously cleared with Low outputs when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
D0 D1 D2 D3 C
IFD4
Q0 Q1 Q2 Q3
X3799
D[7:0]
IFD8
Q[7:0]
X3811
D[15:0]
IFD16
Q[15:0]
X3833
1045
IFD, 4, 8, 16
Inputs D 0 1 C Outputs Q 0 1
VCC
FDCE
D IBUF C D_IN D CE C CLR Q Q
IOB=TRUE
GND
X9768
IFD Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC
FDCE
D C
LVTTL
D_IN
IBUF
D CE C CLR
IOB=TRUE GND X9333
IFD Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FDCP
IBUF D IBUF C C CLR Q D_IN D PRE Q Q
GND
X7852
IFD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1046
IFD, 4, 8, 16
Q[7:0]
IFD
D0 D C Q Q0
Q0 IFD
D1
Q1 D C Q
Q1 IFD
D2
D C
Q2
Q2 IFD
D3
D C
Q3
Q3 IFD
D4
Q4 D C Q
Q4 IFD
D5 D C Q
Q5
Q5 IFD
D6
Q6 D C Q
Q6 IFD
D7
Q7 D C Q
D[7:0] C
Q7
X6389
IFD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFD, you would infer an FD and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1047
IFD, 4, 8, 16
1048
IFD_1
IFD_1
Input D Flip-Flop with Inverted Clock
IFD_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
IFD_1
X3777
The IFD_1 D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input also provides data input for the flip-flop, which synchronizes data entering the chip. The D input data is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. The flip-flop is asynchronously cleared with Low output when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs D 0 1
VCC
Outputs C Q 0 1
FDCE
D IBUF C INV CB D_IN D CE C CLR Q Q
IOB=TRUE
GND
X9770
IFD_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1049
IFD_1
VCC
FDCE
D C INV
LVTTL
D_IN CB
IBUF
D CE C CLR
IOB=TRUE GND X9334
IFD_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFD_1, you would infer an FD_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1050
IFDDRCPE
IFDDRCPE
Dual Data Rate Input D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
IFDDRCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE D CE C0 C1 CLR X9398 IFDDRCPE Q0 Q1
IFDDRCPE is a dual data rate (DDR) input D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR). It consists of one input buffer and two identical flip-flops (FDCPE). When the asynchronous PRE is High and CLR is Low, both the Q0 and Q1 outputs are set High. When CLR is High, both outputs are reset Low. When PRE and CLR are Low and CE is High, data on the D input is loaded into the Q0 output on the Low-to High C0 clock transition, and into the Q1 output on the Low-to-High C1 clock transition. The flip-flops are asynchronously cleared with Low outputs when power is applied. The INIT attribute does not apply to IFDDRCPE components.
Inputs C0 X X X X X C1 X X X X X CE X X X 0 1 1 D X X X X D D CLR 1 0 1 0 0 0 PRE 0 1 1 0 0 0 Q0 0 1 0
Outputs Q1 0 1 0 No Chg No Chg D
No Chg D No Chg
1051
IFDDRCPE
PRE D CE C0 CLR
LVTTL
FDCPE
D CE C CLR INIT = 0 PRE Q Q0
IBUF
FDCPE
D CE C1 C CLR INIT = 0
X9785
PRE
Q1
IFDDRCPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDDRCPE, you would infer an FDDRCPE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.

-- Component Declaration for IFDDRCPE should be placed -- after architecture statement but before begin keyword component IFDDRCPE -- synthesis translate_on port (Q0 : out STD_ULOGIC; Q1 : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for IFDDRCPE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IFDDRCPE should be placed -- in architecture after the begin keyword IFDDRCPE_INSTANCE_NAME : IFDDRCPE port map (Q0 => user_Q0, Q1 => user_Q1, C0 => user_C0,
1052
IFDDRCPE
C1 => user_C1 CE => user_CE, CLR => user_CLR, D => user_D0, PRE => user_PRE);

IFDDRCPE IFDDRCPE_instance_name (.Q0 (user_Q0), .Q1 (user_Q1), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .CLR (user_CLR), .D (user_D), .PRE (user_PRE));

LOC, RLOC, and INIT
1053
IFDDRCPE
1054
IFDDRRSE
IFDDRRSE
Dual Data Rate Input D Flip-Flop with Synchronous Reset and Set and Clock Enable
IFDDRRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S D CE C0 C1 R X9401 IFDDRRSE Q0 Q1
IFDDRRSE is a dual data rate (DDR) input D flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE). It consists of one input buffer and two identical flip-flops (FDRSE). For the C0 input and Q0 output, reset (R) has precedence. The R input, when High, resets the Q0 output Low during the Low-to-High C0 clock transition. When S is High and R is Low, the Q0 output is set High during the Low-to-High C0 clock transition. For the C1 input and Q1 output, set (S) has precedence. The R input, when High, resets the Q1 output Low during the Low-to-High C1 clock transition. When S is High and R is Low, the Q0 output is set to High during the Low-to-High C1 clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The INIT attribute does not apply to IFDDRRSE components.
Inputs C0 X X X X X C1 X X X X X CE X X X X X X 0 1 1 D X X X X X X X D D R 1 0 1 1 0 1 0 0 0 S 0 1 1 0 1 1 0 0 0 Q0 0 1 0
Outputs Q1 No Chg No Chg No Chg 0 1 0 No Chg No Chg D
No Chg No Chg No Chg No Chg D No Chg
1055
IFDDRRSE
S D CE C0 R
LVTTL
FDRSE
D CE C R INIT = 0 S Q Q0
IBUF
FDRSE
D CE C1 C R INIT = 0
X9786
Q1
IFDDRRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDDRRSE, you would infer an FDDRRSE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.

-- Component Declaration for IFDDRRSE should be placed -- after architecture statement but before begin keyword component IFDDRRSE port (Q0 : out STD_ULOGIC; Q1 : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for IFDDRRSE -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for IFDDRRSE should be placed -- in architecture after the begin keyword IFDDRRSE_INSTANCE_NAME : IFDDRRSE port map (Q0 => user_Q0, Q1 => user_Q1, C0 => user_C0, C1 => user_C1, CE => user_CE,
1056
IFDDRRSE
D => user_D, R => user_R, S => user_S);

IFDDRRSE IFDDRRSE_instance_name (.Q0 (user_Q0), .Q1 (user_Q1), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .D (user_D), .R (user_R), .S (user_S));

LOC RLOC INIT
1057
IFDDRRSE
1058
IFDI
IFDI
Input D Flip-Flop (Asynchronous Preset)
IFDI Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
IFDI
X4617
The IFDI D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes data entering the chip. The data on input D is loaded into the flip-flop during the Low-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. The flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs D 0 1
VCC
Outputs C Q 0 1
D C IBUF
D_IN
D CE C
PRE
FDPE IOB=TRUE GND X8740
IFDI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1059
IFDI
VCC
FDPE
D C
LVTTL
D_IN
IBUF
PRE
CE C IOB=TRUE GND X9335
IFDI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDI, you would infer an FDP and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1060
IFDI_1
IFDI_1
Input D Flip-Flop with Inverted Clock (Asynchronous Preset)
IFDI_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
IFDI_1
X4386
The IFDI_1 D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes data entering the chip. The data on input D is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. The flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs D 0 1
VCC
Outputs C Q 0 1
D IBUF C INV CB
D_IN
D CE C
PRE
IFDI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1061
IFDI_1
VCC
FDPE
D C INV IOB=TRUE GND X9336
LVTTL
D_IN
IBUF CB
PRE
CE C
IFDI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDI_1, you would infer an FDP_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1062
IFDX, 4, 8, 16
IFDX, 4, 8, 16
Single- and Multiple-Input D Flip-Flops with Clock Enable
IFDX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II IFDX4, IFDX8, IFDX16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No Macro Macro Macro No No No
D CE C
IFDX
X6009
The IFDX D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, which synchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during the Low-toHigh clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. When CE is Low, flip-flop outputs do not change. The flip-flops are asynchronously cleared with Low outputs when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs Outputs C X Qn Dn No Chg
D0 D1 D2 D3 CE C
IFDX4
Q0 Q1 Q2 Q3
X6010
D[7:0] CE C
IFDX8
Q[7:0]
CE 1
X6011
Dn Dn X
1063
IFDX, 4, 8, 16
D[15:0] CE C
IFDX16
Q[15:0]
FDCE D
X6012
D_IN IBUF
CE C
D CE C
Q CLR
IOB=TRUE GND
X8742
IFDX Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1064
IFDX, 4, 8, 16
Q[7:0] IFDX D0
D CE C Q
Q0
Q0 IFDX D1
D CE C Q
Q1
Q1 IFDX D2
D CE C Q
Q2
Q2 IFDX D3
D CE C Q
Q3
Q3 IFDX D4
D CE C Q
Q4
Q4 IFDX D5
D CE C Q
Q5
Q5 IFDX D6
D CE C Q
Q6
Q6 IFDX D7
D CE C Q
Q7
D[7:0] CE C
Q7
X7635
IFDX8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1065
IFDX, 4, 8, 16
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDX, you would infer an FDCE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.

-- Component Declaration for IFDX should be placed -- after architecture statement but before begin keyword component IFDX port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for IFDX -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for IFDX should be placed -- in architecture after the begin keyword IFDX_INSTANCE_NAME : IFDX port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D);

IFDX IFDX_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D));

IOB
1066
IFDX_1
IFDX_1
Input D Flip-Flop with Inverted Clock and Clock Enable
IFDX_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D CE C
IFDX_1
X6014
The IFDX_1 D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input also provides data input for the flip-flop, which synchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. When the CE pin is Low, the output (Q) does not change. The flip-flop is asynchronously cleared with Low output, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For more information on IFDX_1, see ILDX, 4, 8, 16.
Inputs CE 1 0 D D X C X Outputs Q D No Chg
FDCE D CE C IBUF CB INV D_IN D CE C CLR Q Q
IOB=TRUE GND
X8743
IFDX_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1067
IFDX_1
FDCE
D CE C INV
LVTTL
D_IN
IBUF CB
D CE C CLR
IOB=TRUE GND X9337
IFDX_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDX_1, you would infer an FDCE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1068
IFDXI
IFDXI
Input D Flip-Flop with Clock Enable (Asynchronous Preset)
IFDXI Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D CE C
IFDXI
X6016
The IFDXI D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during the Low-to-High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. When the CE pin is Low, the output (Q) does not change. The flip-flop is asynchronously preset with High output, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, see ILDXI.
D CE C IBUF
D_IN
D CE C
PRE
IFDXI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1069
IFDXI
FDPE
D CE C
LVTTL
D_IN
IBUF
PRE
CE C IOB=TRUE GND X9338
IFDXI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDXI, you would infer an FDPE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1070
IFDXI_1
IFDXI_1
Input D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
IFDXI_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D CE C
IFDXI_1
X6018
The IFDXI_1 D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin. When the CE pin is Low, the output (Q) does not change. The flip-flop is asynchronously preset with High output when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, see ILDXI.
D CE C IBUF
D_IN CB INV
D CE C
PRE
IFDXI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1071
IFDXI_1
FDPE
D CE C INV IOB=TRUE GND X9339
LVTTL
D_IN CB
IBUF
PRE
CE C
IFDXI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an IFDXI_1, you would infer an FDPE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1072
ILD, 4, 8, 16
ILD, 4, 8, 16
Transparent Input Data Latches
ILD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II ILD4, ILD8, ILD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No Macro Macro Macro No No No
D G
ILD
X3774
ILD, ILD4, ILD8, and ILD16 are single or multiple transparent data latches, which can be used to hold transient data entering a chip. The ILD latch is contained in an input/output block (IOB), except for XC9500/XV/XL. The latch input (D) is connected to an IPAD or an IOPAD (without using an IBUF). When the gate input (G) is High, data on the inputs (D) appears on the outputs (Q). Data on the D inputs during the High-to-Low G transition is stored in the latch. The latch is asynchronously cleared with Low output when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs Outputs D 1 0 X D Q 1 0 No Chg D
D0 D1 D2 D3 G
ILD4
Q0 Q1 Q2 Q3
X3798
D[7:0]
ILD8
Q[7:0]
G 1 1 0
X3810
1073
ILD, 4, 8, 16
D[15:0]
ILD16
Q[15:0]
X3832
VCC
LDCE
D IBUF G D_IN D GE G CLR Q Q
IOB=TRUE
GND
X9767
ILD Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
VCC
LDCE
D G
LVTTL
D_IN
IBUF
D GE G CLR
IOB=TRUE GND X9340
ILD Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

G D IBUF D_IN AND2 D C CLR Q AND2B1
FDCP
PRE Q
GND
X8123
ILD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1074
ILD, 4, 8, 16
Q[7:0] ILD D0
D G Q
Q0
Q0 ILD D1
D G Q
Q1
Q1 ILD D2
D G Q
Q2
Q2 ILD D3
D G Q
Q3
Q3 ILD D4
D G Q
Q4
Q4 ILD D5
D G Q
Q5
Q5 ILD D6
D G Q
Q6
Q6 ILD D7
D G Q
Q7
D[7:0] G
Q7
X7853
ILD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILD, you would infer an LD and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1075
ILD, 4, 8, 16

-- Component Declaration for ILD should be placed -- after architecture statement but before begin keyword component ILD port (Q : out STD_ULOGIC; D : in STD_ULOGIC; DG : in STD_ULOGIC); end component; -- Component Attribute specification for ILD -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for ILD should be placed -- in architecture after the begin keyword ILD_INSTANCE_NAME port map (Q D G : ILD => user_Q, => user_D, => user_G);

ILD ILD_instance_name (.Q (user_Q), .D (user_D), .G (user_G));

INIT
1076
ILD_1
ILD_1
Transparent Input Data Latch with Inverted Gate
ILD_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D G
ILD_1
ILD_1 is a transparent data latch, which can be used to hold transient data entering a chip. When the gate input (G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High G transition is stored in the latch. The latch is asynchronously cleared with Low output when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs G 0 0 1 D 1 0 X D Outputs Q 1 0 D D
X4387
VCC
LDCE
D IBUF G INV GB D_IN D GE G CLR Q Q
IOB=TRUE
GND
X9769
ILD_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1077
ILD_1
VCC
LDCE
D G INV
LVTTL
D_IN GB
IBUF
D GE G CLR
IOB=TRUE GND X9341
ILD_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILD_1, you would infer an LD_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.

-- Component Declaration for ILD_1 should be placed -- after architecture statement but before begin keyword component ILD_1 port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC); end component; -- Component Attribute specification for ILD_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for ILD_1 should be placed -- in architecture after the begin keyword ILD_1_INSTANCE_NAME : ILD_1 port map (Q => user_Q, D => user_D, G => user_G);

ILD_1 ILD_1_instance_name (.Q (user_Q), .D (user_D), .G (user_G));

INIT
1078
ILDI
ILDI
Transparent Input Data Latch (Asynchronous Preset)
ILDI Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D G
ILDI
ILDI is a transparent data latch, which can hold transient data entering a chip. When the gate input (G) is High, data on the input (D) appears on the output (Q). Data on the D input during the High-to-Low G transition is stored in the latch. The latch is asynchronously preset, output High, when power is applied.
X4388
ILDIs and IFDIs

The ILDI is actually the input flip-flop master latch. It is possible to access two different outputs from the input flip-flop: one that responds to the level of the clock signal and another that responds to an edge of the clock signal. When using both outputs from the same input flip-flop, a transparent High latch (ILDI) corresponds to a falling edge-triggered flip-flop (IFDI_1). Similarly, a transparent Low latch (ILDI_1) corresponds to a rising edge-triggered flip-flop (IFDI).
1079
ILDI
VCC
D G IBUF
D_IN
D GE G
PRE
LDPE IOB=TRUE GND X8746
ILDI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC
D G
LVTTL
D_IN
IBUF
PRE
GE G
LDPE
IOB=TRUE GND X9342
ILDI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILDI, you would infer an LDP and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1080
ILDI_1
ILDI_1
Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
ILDI_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro* Macro Macro Macro No No No
* Macros cannot be implemented for Spartan-IIE.
D G
ILDI_1
ILDI_1 is a transparent data latch, which can hold transient data entering a chip. When the gate input (G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High G transition is stored in the latch. The latch is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For information on ILDI_1, see ILDI.
X4618
1081
ILDI_1
VCC
D G IBUF INV
D_IN GB
D GE G
PRE
LDPE IOB=TRUE GND X8747
ILDI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC
D G
LVTTL
D_IN GB
IBUF
PRE
GE G
INV
LDPE
IOB=TRUE GND X9343
ILDI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILDI_1, you would infer an LDP_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1082
ILDX, 4, 8, 16
ILDX, 4, 8, 16
Transparent Input Data Latches
ILDX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II ILDX4, ILDX8, ILDX16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
D GE G X6020
ILDX
ILDX, ILDX4, ILDX8, and ILDX16 are single or multiple transparent data latches, which can be used to hold transient data entering a chip. The latch input (D) is connected to an IPAD or an IOPAD (without using an IBUF). The latch is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
D0 D1 D2 D3 GE G
ILDX4
Q0 Q1 Q2 Q3
X6021
ILDXs and IFDXs

D[7:0] GE G X6022
ILDX8
Q[7:0]
The ILDX is actually the input flip-flop master latch. Two different outputs can be accessed from the input flip-flop: one that responds to the level of the clock signal and another that responds to an edge of the clock signal. When using both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a falling edge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a rising edge-triggered flip-flop (IFDX).
D[15:0] GE G
ILDX16
Q[15:0]
X6023
1083
ILDX, 4, 8, 16
Inputs GE 0 1 1 1 1 G X 0 1 1 D X X 1 0 D
Outputs Q No Chg No Chg 1 0 D
LDCE D GE G IBUF D_IN D GE G Q CLR Q
IOB=TRUE GND
X8748
ILDX Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

LDCE
D GE G
LVTTL
D_IN
IBUF
D GE G CLR
IOB=TRUE GND X9344
ILDX Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1084
ILDX, 4, 8, 16
Q[7:0]
ILDX
D0 D GE G Q0 Q
Q0 ILDX
D1
D GE G
Q1 Q
Q1 ILDX
D2
D GE G
Q2 Q
Q2 ILDX
D3
D GE G
Q3
Q3 ILDX
D4
D GE G
Q4
Q4 ILDX
D5
D GE G
Q5
Q5 ILDX
D6
D GE G
Q6
Q6 ILDX
D7
D GE G
Q7
D[7:0] GE G
Q7
X6405
ILDX8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILDX, you would infer an LDCE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1085
ILDX, 4, 8, 16
1086
ILDX_1
ILDX_1
Transparent Input Data Latch with Inverted Gate
ILDX_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D GE G
ILDX_1
ILDX_1 is a transparent data latch, which can be used to hold transient data entering a chip. When the gate input (G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High G transition is stored in the latch. The latch is asynchronously cleared with Low output, when power is applied.
X6025
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For more information on ILDX_1, see ILDX, 4, 8, 16.
Inputs GE 0 1 1 1 1 G X 1 0 0 D X X 1 0 D Outputs Q No Chg No Chg 1 0 D
LDCE D GE G IBUF GB INV D_IN D GE G Q CLR Q
IOB=TRUE GND
X8749
ILDX_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1087
ILDX_1
LDCE
D GE G INV
LVTTL
D_IN GB
IBUF
D GE G CLR
IOB=TRUE GND X9345
ILDX_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILDX_1, you would infer an LDCE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1088
ILDXI
ILDXI
Transparent Input Data Latch (Asynchronous Preset)
ILDXI Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D GE G
ILDXI
ILDXI is a transparent data latch, which can hold transient data entering a chip. When the gate input (G) is High, data on the input (D) appears on the output (Q). Data on the D input during the High-to-Low G transition is stored in the latch. The latch is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
X6026
ILDXIs and IFDXIs

The ILDXI is actually the input flip-flop master latch. Two different outputs can be accessed from the input flip-flop: one that responds to the level of the clock signal and another that responds to an edge of the clock signal. When using both outputs from the same input flip-flop, a transparent High latch (ILDXI) corresponds to a falling edge-triggered flip-flop (IFDXI_1). Similarly, a transparent Low latch (ILDXI_1) corresponds to a rising edge-triggered flip-flop (IFDXI). See the following figure for legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations.
ILDXI
IPAD D IO_ENABLE GE G Q IO_ENABLE IPAD D GE G Q
ILDXI_1
IFDXI_1
D CE CLOCK C CLOCK Q
IFDXI
D CE C Q
X6027
Legal Combinations of IFDXI and ILDXI for a Single IOB
1089
ILDXI
Inputs GE 0 1 1 1 1 G X 0 1 1 D X X 1 0 D
Outputs Q No Chg No Chg 1 0 D
D GE G IBUF
D_IN
PRE D Q GE G LDPE IOB=TRUE
GND
X8750
ILDXI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
D GE G
LVTTL
D_IN
IBUF
PRE
GE G
LDPE
IOB=TRUE GND X9346
ILDXI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILDXI, you would infer an LDPE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1090
ILDXI_1
ILDXI_1
Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
ILDXI_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D GE G
ILDXI_1
ILDXI_1 is a transparent data latch, which can hold transient data entering a chip. The latch is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, see ILDXI.
Inputs GE 0 1 1 1 1 G X 1 0 0 D X X 1 0 D Outputs Q No Chg No Chg 1 0 D
X6028
D GE G IBUF
D_IN GB INV
PRE D Q GE G LDPE IOB=TRUE
GND
X8751
ILDXI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1091
ILDXI_1
D GE G
LVTTL
D_IN GB
IBUF
PRE
GE G
INV
LDPE
IOB=TRUE GND X9347
ILDXI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an ILDXI_1, you would infer an LDPE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr i to pack all input registers into the IOBs.
1092
INV, 4, 8, 16
INV, 4, 8, 16
Single and Multiple Inverters
INV Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II INV4, INV8, INV16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Primitive Primitive
O X9422
INV, INV4, INV8, and INV16 are single and multiple inverters that identify signal inversions in a schematic.
O[7:0]
I0 I1 I2 I3
O0 O1 O2 O3 X9423
IO I1 I2 I3 I4 I5 INV INV INV INV INV INV INV INV
O0 O1 O2 O3 O4 O5 O6 O7
I [7:0] INV8
O [7:0]
I6 I7 I[7:0]
X9853
X7653 I [15:0] INV16

X9854
O [15:0]
INV8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
1093
INV, 4, 8, 16
VHDL Inference Code

architecture Behavioral of inv is
begin
process (i) begin o <= not i; end process; end Behavioral

always @(i) begin o = !i; end

-- Component Declaration for INV should be placed -- after architecture statement but before begin keyword component INV port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for INV -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for INV should be placed -- in architecture after the begin keyword INV_INSTANCE_NAME : INV port map (O => user_O, I => user_I);

INV instance_name (.O (user_O), .I (user_I));

None
1094
IOBUF, IOBUF_selectIO
Bi-Directional Buffer with Selectable I/O Interface
IOBUF, IOBUF_selectIO Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
T I O
X8406
IO
For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, IOBUF and its selectIO variants (listed in the "Component" column in the table below) are bi-directional buffers whose I/O interface corresponds to a specific I/O standard.The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. The S, F, and 2, 4, 6, 8, 12, 16, 24 extensions specify the slew rate (SLOW or FAST) and the drive power (2, 4, 6, 8, 12, 16, 24 mA) for the LVTTL standard variants. For example, IOBUF_F_2 is a bi-directional buffer that uses the LVTTL I/Osignaling standard with a FAST slew and 2mA of drive power. You can attach an IOSTANDARD attribute to an IOBUF instance instead of using an IOBUF_selectIO component. Check marks () in the "Spartan-II, Virtex" and "Spartan-IIE, Virtex-E" columns indicate the components and IOSTANDARD attribute values available for each architecture. IOBUF components that use the LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 signaling standards have selectable drive and slew rates using the DRIVE and FAST or SLOW constraints. The defaults are DRIVE=12 mA and SLOW slew. IOBUFs are composites of IBUF and OBUFT elements. The O output is X (unknown) when IO (input/output) is Z. IOBUFs can be implemented as interconnections of their component elements. The hardware implementation of the I/O standards requires that you follow a set of usage rules for the SelectIO buffers. See the SelectIO Usage Rules under the IBUF_selectIO section for information on using these components and IOSTANDARD attributes.
Inputs T 1 0 0 I X 1 0
Bidirectional
IO Z 1 0
Outputs O X 1 0
1095
Spartan-II, Spartan-IIE, Virtex, and Virtex-E IOBUF_selectIO Components and IOSTANDARD Attributes
Component IOBUF IOBUF_S_2 IOBUF_S_4 IOBUF_S_6 IOBUF_S_8 IOBUF_S_12 IOBUF_S_16 IOBUF_S_24 IOBUF_F_2 IOBUF_F_4 IOBUF_F_6 IOBUF_F_8 IOBUF_F_12 IOBUF_F_16 IOBUF_F_24 IOBUF_AGP IOBUF_CTT IOBUF_GTL IOBUF_GTLP IOBUF_HSTL_I IOBUF_HSTL_III IOBUF_HSTL_IV IOBUF_LVCMOS2 IOBUF_LVCMOS18 IOBUF_LVDS IOBUF_LVPECL IOBUF_PCI33_3 IOBUF_PCI33_5 IOBUF_PCI66_3 IOBUF_ PCIX66_3 IOBUF_SSTL2_I IOBUF_SSTL2_II IOBUF_SSTL3_I IOBUF_SSTL3_II
a Not b
Spartan-II, Virtex
IOSTANDARD (Attribute Value) defaults to LVTTL b LVTTL b LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL AGP CTT GTL GTLP HSTL_I HSTL_III HSTL_IV LVCMOS2 LVCMOS18 LVDS LVPECL PCI33_3 PCI33_5 PCI66_3 PCIX66_3 SSTL2_I SSTL2_II SSTL3_I SSTL3_II
b b b b
VREF No No No No No No No No No No No No No No No 1.32 1.50 0.80 0.80 0.75 0.90 0.90 No No No No No No No No 1.25 1.25 1.50 1.50
Output VCCO 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 No No 1.5 1.5 1.5 2.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 2.5 2.5 3.3 3.3
Input VCCO 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 No No No No No 1.5 No 2.5 1.8 No No 3.3 No 3.3 3.3 No No No No
LVTTL b
b b b
LVTTL b
b b b
LVTTL b
b
supported for Virtex-E. The LVCMOS18 attribute also requires a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE attribute descriptions in the Xilinx Constraints Guide for valid values for each architecture.
1096
The Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X library includes some IOBUF_selectIO components for compatibility with older, existing designs and other architectures. For new Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs, however, the recommended method for using IOBUF SelectIO buffers is to attach an IOSTANDARD attribute to an IOBUF component. For example, attach IOSTANDARD=GTLP to an IOBUF instead of using the IOBUF_GTLP component for new Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs. The IOSTANDARD attributes that can be attached to an IOBUF component are listed in the "IOSTANDARD (Attribute Value)" column in the following tableSpartan-II, Spartan-IIE, Virtex, and Virtex-E IOBUF_selectIO Components and IOSTANDARD Attributes table. See SelectIO Usage Rules for information on using these IOSTANDARD attributes. For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the IOSTANDARD attribute values listed in the following table can be applied to an IOBUF component to provide SelectIO interface capability for the inputs. The O output uses the LVTTL standard. Attach an IOSTANDARD attribute to an IOBUF and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the input for the I/O standard associated with that value. The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE attribute descriptions in the Xilinx Constraints Guide for valid values for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X. Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X IOBUF_selectIO Components and IOSTANDARD Attributes
Architectures
IOSTANDARD AGP GTL GTL_DCI GTLP GTLP_DCI HSTL_I HSTL_I_18 HSTL_II_18 HSTL_II_DCI_18 HSTL_III HSTL_III_18 HSTL_IV HSTL_IV_18 HSTL_IV_DCI HSTL_IV_DCI_18 LVCMOS12a LVCMOS15a LVCMOS18a LVCMOS25a LVCMOS33a Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Drive No No No No No No No No No No No No No No No 2, 4, 6 2, 4, 6, 8, 12 2, 4, 6, 8, 12, 16 2, 4, 6, 8, 12, 16, 24 2, 4, 6, 8, 12, 16, 24 Slew No No No No No No No No No No No No No No No
Attribute Values
Terminate Type Output None None Single None Single None None None Split None None None None Single Single Termination Type Input None None Single None Single None None None Split None None None None Single Single None None None None None VREF Input * 1.32 0.80 0.80 1.00 1.00 0.75 0.9 0.9 0.9 0.9 1.10 0.90 1.10 0.90 1.1 No No No No No Output VCCO 3.3 No 1.2 No 1.5 1.5 1.8 1.8 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.2 1.5 1.8 2.5 3.3 Input VCCO No No 1.2 No 1.5 No No No 1.8 No No No No 1.5 1.8 1.2 1.5 1.8 2.5 3.3
Fast/Slow None Fast/Slow None Fast/Slow None Fast/Slow None Fast/Slow None
1097
Architectures
IOSTANDARD LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25 LVDCI_DV2_33 LVTTL (default)a Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Drive No No No No No No No No 2, 4, 6, 8, 12, 16, 24 No No No No No No No No No No No No Slew No No No No No No No No
Attribute Values
Terminate Type Output Driver Driver Driver Driver Driver Driver Driver Driver Termination Type Input None None None None None None None None None None None None None None Split Split Split None None None None VREF Input * No No No No No No No No No No No No 0.9 0.9 0.9 1.25 1.5 1.25 1.25 1.50 1.50 Output VCCO 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 1.8 1.8 1.8 2.5 3.3 2.5 2.5 3.3 3.3 Input VCCO 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 No No 1.8 2.5 3.3 No No No No
Fast/Slow None No No No No No No No No No No No No None None None None None Split Split Split None None None None
PCI33_3 PCI66_3 PCIX SSTL18_I SSTL18_II SSTL18_II_DCI SSTL2_II_DCI SSTL3_II_DCI SSTL2_I SSTL2_II SSTL3_I SSTL3_II
Usage
For HDL, these design elements are instantiated rather than inferred.
VHDL Instantiation Template for IOBUF

-- Component Declaration for IOBUF should be placed -- after architecture statement but before begin keyword component IOBUF port (O : out STD_ULOGIC; IO : inout STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for IOBUF -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IOBUF should be placed -- in architecture after the begin keyword
1098
IOBUF_INSTANCE_NAME : IOBUF port map (O => user_O, IO => user_IO, I => user_I, T => user_T);
Verilog Instantiation Template for IOBUF

IOBUF instance_name (.O (user_O), .IO (user_IO), .I (user_I), .T (user_T));
VHDL Instantiation Template for IOBUF_selectIO

-- Component Declaration for IOBUF_selectIO should be placed -- after architecture statement but before begin keyword component IOBUF_selectIO port (O : out STD_ULOGIC; IO : inout STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for IOBUF_selectIO -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IOBUF_selectIO should be -- placed in architecture after the begin keyword IOBUF_selectIO_INSTANCE_NAME : IOBUF_selectIO port map (O => user_O, IO => user_IO, I => user_I, T => user_T);
Verilog Instantiation Template for IOBUF_selectIO

IOBUF_selectIO instance_name (.O (user_O), .IO (user_IO), .I (user_I), .T (user_T));

IOSTANDARD, DRIVE, and SLEW
1099
1100
IOBUFDS
IOBUFDS
3-State Differential Signaling I/O Buffer with Active Low Output Enable
IOBUFDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
T I O IO IOB
IOBUFDS is a single 3-state, differential signaling input/output buffer with active Low output enable.
Inputs
X9827
Bidirectional
T 1 0 0 IO Z 0 1 IOB Z 1 0
Outputs O -* 0 1
I X 0 1
* The dash (-) means No Change. BLVDS_25 is supported for IOSTANDARD. Attach an IOSTANDARD attribute to an IOBUFDS and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the outputs for the I/O standard associated with that value.
Architectures IOSTANDARD BLVDS_25 Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Termination Type Input None Attribute Values VREF Input * No Output VCCO 2.5 Input VCCO No
Usage
1101
IOBUFDS

-- Component Declaration for IOBUFDS should be placed -- after architecture statement but before begin keyword component IOBUFDS port (O : out STD_ULOGIC; IO : inout STD_ULOGIC; IOB : inout STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for IOBUFDS -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for IOBUFDS should be -- placed in architecture after the begin keyword IOBUFDS_INSTANCE_NAME : IOBUFDS port map (O => user_O, IO => user_IO, IOB => user_IOB, I => user_I, T => user_T);

IOBUFDS instance_name (.O (user_O), .IO (user_IO), .IOB (user_IOB), .I (user_I), .T (user_T));

IOSTANDARD IOBDELAY
1102
IOPAD, 4, 8, 16
IOPAD, 4, 8, 16
Single- and Multiple-Input/Output Pads
IOPAD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II IOPAD4, IOPAD8, IOPAD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
IO
X9783
IOPAD4 IO0 IO1 IO2 IO3 X3838
IOPAD, IOPAD4, IOPAD8, and IOPAD16 are single and multiple input/output pads. The IOPAD is a connection point from a device pin, used as a bidirectional signal, to a PLD device. The IOPAD is connected internally to an input/output block (IOB), which is configured by the software as a bidirectional block. Bidirectional blocks can consist of any combination of a 3-state output buffer (such as OBUFT or OFDE) and any available input buffer (such as IBUF or IFD). See the appropriate CAE tool interface user guide for details on assigning pin location and identification. Note: The LOC attribute cannot be used on IOPAD multiples.
IOPAD8 IO[7:0] X3841
IOPAD16 IO[15:0]
X3845
1103
IOPAD, 4, 8, 16
IO [7:0 ]
IOPAD
IO 0
IOPAD
IO 1
IOPAD
IO 2
IOPAD
IO 3
IOPAD
IO 4
IOPAD
IO 5
IOPAD
IO 6
IOPAD
IO 7
X 7854
IOPAD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, it is not necessary to use these elements in the design. They will be added automatically.

IOBDELAY PULLDOWN
1104
IPAD, 4, 8, 16
IPAD, 4, 8, 16
Single- and Multiple-Input Pads
IPAD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II IPAD4, IPAD8, IPAD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
IPAD I
X9787
IPAD4 I0 I1 I2 I3 X3837
IPAD, IPAD4, IPAD8, and IPAD16 are single and multiple input pads. The IPAD is a connection point from a device pin used for an input signal to the PLD device. It is connected internally to an input/output block (IOB), which is configured by the software as an IBUF, IFD, or ILD. See the appropriate CAE tool interface user guide for details on assigning pin location and identification. For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, pads must be used to drive IBUF and IBUFG inputs. An IPAD can be inferred by NGDBUILD if one is missing on an IBUF or IBUFG input. Note: The LOC attribute cannot be used on IPAD multiples.
IPAD8 I[7:0]
X3840
IPAD16 I[15:0]
X3844
1105
IPAD, 4, 8, 16
I[7:0]
IPAD IPAD IPAD IPAD IPAD IPAD IPAD IPAD
I0 I1 I2 I3 I4 I5 I6 I7 X7655
IPAD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage

IOBDELAY, PULLDOWN
1106
JTAGPPC
JTAGPPC
JTAG Primitive for the Power PC
JTAGPPC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Primitive* No No No
* Not supported for Virtex-II. Supported for Virtex-II Pro and Virtex-II Pro X only.
The JTAGPPC block allows connection from the JTAG logic in the PPC405 core to the JTAG logic of Virtex-II Pro and Virtex-II Pro X devices. The connections are made through programmable routing and so the connection only exists after configuration. Following is an example instantiation of the JTAGPPC block in Verilog:
JTAGPPC IJTAGPPC(.TDOTSPPC(TDO_TS_PPC), .TDOPPC(TDO_PPC),.TMS(TMS_PPC), .TDIPPC(TDI_PPC), .TCK(TCK_PPC)); PPC405 IPPC405 ( ... .JTGC405TCK (TCK_PPC), .JTGC405TDI (TDI_PPC), .JTGC405TMS (TMS_PPC), .C405JTGTDO (TDO_PPC), .C405JTGTDOEN (TDO_TS_PPC), ... )
When the block is instantiated in this fashion, the instruction registers of the PPC405 and the Virtex-II Pro and Virtex-II Pro X devices are linked in series. The following table lists the input and output pins for JTAGPPC.
Inputs TDOPPC TDOTSPPC Outputs TCK TDIPPC TMS
Usage
1107
JTAGPPC

-- Component Declaration for JTAGPPC should be placed -- after architecture statement but before begin keyword component JTAGPPC port (TCK : out STD_ULOGIC; TDIPPC : out STD_ULOGIC; TMS : out STD_ULOGIC; TDOPPC : in STD_ULOGIC; TDOTSPPC : in STD_ULOGIC); end component; -- Component Attribute specification for JTAGPPC -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for JTAGPPC should be placed -- in architecture after the begin keyword JTAGPPC_INSTANCE_NAME : JTAGPPC port map (TCK => user_TCK, TDIPPC => user_TDIPPC, TMS => user_TMS, TDOPPC => user_TDOPPC, TDOTSPPC => user_TDOTSPPC);

JTAGPPC JTAGPPC_instance_name (.TCK (user_TCK), .TDIPPC (user_TDIPPC), .TMS (user_TMS), .TDOPPC (user_TDOPPC), .TDOTSPPC (user_TDOTSPPC));

None
1108
KEEPER
KEEPER
KEEPER Symbol
KEEPER Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II * Primitive for XC9500XL/XV. Primitive Primitive Primitive No* No Primitive
O
X8718
KEEPER is a weak keeper element used to retain the value of the net connected to its bidirectional O pin. For example, if a logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the net driver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the net. For additional information on using a KEEPER element with SelectIO components, see the SelectIO Usage Rules in the "IBUF_selectIO" section
Usage

-- Component Declaration for KEEPER should be placed -- after architecture statement but before begin keyword component KEEPER port (O : inout STD_ULOGIC); end component; -- Component Attribute specification for KEEPER -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for KEEPER should be placed -- in architecture after the begin keyword KEEPER_INSTANCE_NAME : KEEPER port map (O => user_O);
1109
KEEPER

KEEPER KEEPER_instance_name (.O (user_O));
1110
LD
LD
Transparent Data Latch
LD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Primitive Primitive
D G
LD
LD is a transparent data latch. The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is High. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains Low. The latch is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs G 1 1 0 D 0 1 X D Outputs Q 0 1 No Chg D
X3740
1111
LD
G D AND2 D C
FDCP
PRE Q
CLR
AND2B1
GND
X7855
LD Implementation XC9500/XV/XL
Usage
VHDL Inference Code

architecture Behavioral of ld is begin process (G,D) begin if (G = '1') then Q <= D; end if; end process; end Behavioral;

always @ (D or G) begin if (G) Q <= D; end

-- Component Declaration for LD should be placed -- after architecture statement but before begin keyword component LD -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC); end component; -- Component Attribute specification for LD -- should be placed after architecture declaration but -- before the begin keyword
1112
LD
attribute INIT : string; attribute INIT of LD_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LD should be placed -- in architecture after the begin keyword LD_INSTANCE_NAME : LD -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D, G => user_G);

LD LD_instance_name (.Q (user_Q), .D (user_D), .G (user_G)); defparam LD_instance_name.INIT = bit_value;

INIT
1113
LD
1114
LD4, 8, 16
LD4, 8, 16
Multiple Transparent Data Latches
LD4, LD8, LD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D0 D1 D2 D3 G
LD4
Q0 Q1 Q2 Q3
LD4, LD8, and LD16 have, respectively, 4, 8, and 16 transparent data latches with a common gate enable (G). The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is High. The data on the D input during the High-toLow gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains Low. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active.
X4611 D[7:0]
LD8
Q[7:0]
X4612
D[15:0]
LD16
Q[15:0]
GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. See LD for information on single transparent data latches.
X4613
Inputs G 1 1 0 D 0 1 X D
Outputs Q 0 1 No Chg D
1115
LD4, 8, 16
Q[7:0]
LD D0 D G Q0 LD D1 D G Q1 LD D2 D G Q2 LD D3 D G D[7:0] Q3 Q Q3 D7 D G Q Q2 D6 D G Q Q1 D5 D G Q Q0 D4 D G
LD Q Q4
Q4 LD Q Q5
Q5 LD Q Q6
Q6 LD Q Q7
Q7
X9470
LD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of ld4 is begin process (G,D) begin if (G = '1') then Q <= D; end if; end process; end Behavioral;

always @ (D or G) begin if (G) Q <= D; end
1116
LD_1
LD_1
Transparent Data Latch with Inverted Gate
LD_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D G
LD_1
LD_1 is a transparent data latch with an inverted gate. The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High. The latch is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs G 0 0 1 D 0 1 X D Outputs Q 0 1 No Chg D
X3741
Usage
VHDL Inference Code

architecture Behavioral of ld_1 is begin process (G, D) begin
1117
LD_1
if (G='0') then Q <= D; end if; end process; end Behavioral

always @(D or G) begin if (!G) Q <= D; end

-- Component Declaration for LD_1 should be placed -- after architecture statement but before begin keyword component LD_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC); end component; -- Component Attribute specification for LD_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LD_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LD_1 should be placed -- in architecture after the begin keyword LD_1_INSTANCE_NAME : LD_1 -- synthesis translate_off generic map( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D, G => user_G);

LD_1 LD_1_instance_name (.Q (user_Q), .D (user_D), .G (user_G)); defparam LD_1_instance_name.INIT = bit_value;
1118
LD_1

INIT
1119
LD_1
1120
LDC
LDC
Transparent Data Latch with Asynchronous Clear
LDC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Primitive Primitive
D G
LDC
CLR X4070
LDC is a transparent data latch with asynchronous clear. When the asynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D) input while the gate enable (G) input is High and CLR is Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains low. The latch is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 G X 1 1 0 D X 0 1 X D Outputs Q 0 0 1 No Chg D
Usage
VHDL Inference Code

architecture Behavioral of ldc is begin
1121
LDC
process (CLR, D, G) begin if (CLR='1') then Q <= '0'; elsif (G='1') then Q <= D; end if; end process; end Behavioral;

always @ (G or D or CLR) begin if (CLR) Q <= 0; else if (G) Q <= D; end

-- Component Declaration for LDC should be placed -- after architecture statement but before begin keyword component LDC -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC); end component; -- Component Attribute specification for LDC -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDC_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDC should be placed -- in architecture after the begin keyword LDC_INSTANCE_NAME : LDC -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR, D => user_D, G => user_G);
1122
LDC

LDC LDC_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G)); defparam LDC_instance_name.INIT = bit_value;

INIT
1123
LDC
1124
LDC_1
LDC_1
Transparent Data Latch with Asynchronous Clear and Inverted Gate
LDC_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D G
LDC_1
CLR X3752
LDC_1 is a transparent data latch with asynchronous clear and inverted gate. When the asynchronous clear input (CLR) is High, it overrides the other inputs (D and G) and resets the data (Q) output Low. Q reflects the data (D) input while the gate enable (G) input and CLR are Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High. The latch is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 G X 0 0 1 D X 0 1 X D Outputs Q 0 0 1 No Chg D
Usage
1125
LDC_1
VHDL Inference Code

architecture Behavioral of ldc_1 is begin process (CLR, D, G) begin if (CLR='1') then Q <= '0'; elsif (G='0') then Q <= D; end if; end process; end Behavioral;

always @ (G or D or CLR) begin if (CLR) Q <= 0; else if (!G) Q <= D; end

-- Component Declaration for LDC_1 should be placed -- after architecture statement but before begin keyword component LDC_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC); end component; -- Component Attribute specification for LDC_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDC_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDC_1 should be placed -- in architecture after the begin keyword LDC_1_INSTANCE_NAME : LDC_1 -- synthesis translate_off generic map( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR,
1126
LDC_1
D => user_D, G => user_G);

LDC_1 LDC_1_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G)); defparam LDC_1_instance_name.INIT = bit_value;

INIT
1127
LDC_1
1128
LDCE
LDCE
Transparent Data Latch with Asynchronous Clear and Gate Enable
LDCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D GE G
LDCE
CLR X4979
LDCE is a transparent data latch with asynchronous clear and gate enable. When the asynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D) input while the gate (G) input and gate enable (GE) are High and CLR is Low. If GE is Low, data on D cannot be latched. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G or GE remains low. The latch is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 GE X 0 1 1 1 1 G X X 1 1 0 D X X 0 1 X D Outputs Q 0 No Chg 0 1 No Chg D
Usage
1129
LDCE
VHDL Inference Code

architecture Behavioral of ldce is begin process (CLR, D, G, GE) begin if (CLR='1') then Q <= '0'; elsif (GE = '1') then if (G='1') then Q <= D; end if; end if; end process; end Behavioral;

always @(CLR or D or G or GE) begin if (CLR) Q <= 0; else if (G && GE) Q <= D; end

-- Component Declaration for LDCE should be placed -- after architecture statement but before begin keyword component LDCE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC); end component; -- Component Attribute specification for LDCE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDCE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDCE should be placed -- in architecture after the begin keyword LDCE_INSTANCE_NAME : LDCE
1130
LDCE
-- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR, D => user_D, G => user_G, GE => user_GE);

LDCE LDCE_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G), .GE (user_GE)); defparam LDCE_instance_name.INIT = bit_value;

INIT
1131
LDCE
1132
LDCE_1
LDCE_1
Transparent Data Latch with Asynchronous Clear, Gate Enable, and Inverted Gate
LDCE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D GE G
LDCE_1
CLR X4930
LDCE_1 is a transparent data latch with asynchronous clear, gate enable, and inverted gate. When the asynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D) input while the gate (G) input and CLR are Low and gate enable (GE) is High. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High or GE remains Low. The latch is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 GE X 0 1 1 1 1 G X X 0 0 1 D X X 0 1 X D Outputs Q 0 No Chg 0 1 No Chg D
Usage
1133
LDCE_1
VHDL Inference Code

architecture Behavioral of ldce_1 is begin process (CLR, D, G, GE) begin if (CLR='1') then Q <= '0'; elsif (GE = '1') then if (G='0') then Q <= D; end if; end if; end process; end Behavioral;

always @(CLR or D or G or GE) begin if (CLR) Q <= 0; else if (!G && GE) Q <= D; end

-- Component Declaration for LDCE_1 should be placed -- after architecture statement but before begin keyword component LDCE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC); end component; -- Component Attribute specification for LDCE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDCE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDCE_1 should be placed -- in architecture after the begin keyword LDCE_1_INSTANCE_NAME : LDCE_1
1134
LDCE_1
-- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR, D => user_D, G => user_G, GE => user_GE);

LDCE_1 LDCE_1_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G), .GE (user_GE)); defparam LDCE_1_instance_name.INIT = bit_value;

INIT
1135
LDCE_1
1136
LD4CE, LD8CE, LD16CE

Transparent Data Latches with Asynchronous Clear and Gate Enable
LD4CE, LD8CE, LD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D0 D1 D2 D3 GE G
LD4CE
Q0 Q1 Q2 Q3
LD4CE, LD8CE, and LD16CE have, respectively, 4, 8, and 16 transparent data latches with asynchronous clear and gate enable. When the asynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) outputs Low. Q reflects the data (D) inputs while the gate (G) and gate enable (GE) are High, and CLR is Low. If GE is Low, data on D cannot be latched. The data on the D input during the High-toLow gate transition is stored in the latch. The data on the Q output remains unchanged as long as G or GE remains Low. The latch is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
CLR X6947
D[7:0] GE G
LD8CE
Q[7:0]
CLR X6948
Inputs
D[15:0] GE G
Outputs G X X 1 1 0 Dn X X 1 0 X Dn Qn 0 No Chg 1 0 No Chg Dn
LD16CE
CLR
Q[15:0]
GE X 0 1 1 1 1
1 0 0 0
X6949
CLR
0 0
Dn = referenced input, for example, D0, D1, D2 Qn = referenced output, for example, Q0, Q1, Q2
1137
LDCE D0 D Q GE G CLR Q0 LDCE D1 D Q GE G CLR Q1 LDCE D2 D Q GE G CLR Q2 LDCE D3 GE G CLR D Q GE G CLR Q3 X6538 Q3 Q2 Q1 Q0
LD4CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X
Q[7:0] LDCE D0 D GE G CLR Q0 LDCE D1 D GE G CLR Q1 LDCE D2 D GE G CLR Q2 LDCE D3 D GE G D[7:0] GE G CLR X6385 CLR Q3 Q Q3 D7 LDCE D GE G CLR Q7 Q Q7 Q Q2 D6 LDCE D GE G CLR Q6 Q Q6 Q Q1 D5 D GE G CLR Q5 LDCE Q Q5 Q Q0 D4 D GE G CLR Q4 LDCE Q Q4
LD8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X
1138
Usage
For HDL, these design elements are supported for inference only.
VHDL Inference Code

architecture Behavioral of ld4ce is begin process (CLR, D, G, GE) begin if (CLR='1') then Q <= "0000"; elsif (GE = '1') then if (G='1') then Q <= D; end if; end if; end process; end Behavioral;

always @(CLR or D or G or GE) begin if (CLR) Q <= 0; else if (G && GE) Q <= D; end
1139
1140
LDCP
LDCP
Transparent Data Latch with Asynchronous Clear and Preset
LDCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
Primitive Primitive Primitive Macro Primitive Primitive
LDCP
Q
LDCP is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs. When CLR is High, it overrides the other inputs and resets the data (Q) output Low. When PRE is High and CLR is low, it presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input is High and CLR and PRE are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains Low. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 PRE X 1 0 0 0 0 G X X 1 1 0 D X X 1 0 X D Outputs Q 0 1 1 0 No Chg D
CLR X8369
Usage
1141
LDCP
VHDL Inference Code

architecture Behavioral of ldcp is begin process (CLR, D, G, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (G='1') then Q <= D; end if; end process; end Behavioral;

always @ (CLR or PRE or D or G) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (G) Q <= D; end

-- Component Declaration for LDCP should be placed -- after architecture statement but before begin keyword component LDCP -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDCP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDCP_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDCP should be placed -- in architecture after the begin keyword
1142
LDCP
LDCP_INSTANCE_NAME : LDCP -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR, D => user_D, G => user_G, PRE => user_PRE);

LDCP LDCP_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G), .PRE (user_PRE)); defparam LDCP_instance_name.INIT = bit_value;

INIT
1143
LDCP
1144
LDCP_1
LDCP_1
Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate
LDCP_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
LDCP_1
Q
CLR X8370
LDCP_1 is a transparent data latch with data (D), asynchronous clear (CLR), preset (PRE) inputs, and inverted gate (G). When CLR is High, it overrides the other inputs and resets the data (Q) output Low. When PRE is High and CLR is Low, it presets the data (Q) output High. Q reflects the data (D) input while gate (G) input, CLR, and PRE are Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 PRE X 1 0 0 0 0 G X X 0 0 1 D X X 1 0 X D Outputs Q 0 1 1 0 No Chg D
Usage
1145
LDCP_1
VHDL Inference Code

architecture Behavioral of ldcp_1 is begin process (CLR, D, G, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (G='0') then Q <= D; end if; end process; end Behavioral;

always @ (CLR or PRE or D or G) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (!G) Q <= D; end

-- Component Declaration for LDCP_1 should be placed -- after architecture statement but before begin keyword component LDCP_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDCP_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDCP_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDCP_1 should be placed -- in architecture after the begin keyword
1146
LDCP_1
LDCP_1_INSTANCE_NAME : LDCP_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR, D => user_D, G => user_G, PRE => user_PRE);

LDCP_1 LDCP_1_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G), .PRE (user_PRE)); defparam LDCP_1_instance_name.INIT = bit_value;

INIT
1147
LDCP_1
1148
LDCPE
LDCPE
Transparent Data Latch with Asynchronous Clear and Preset and Gate Enable
LDCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D GE G
LDCPE
Q
CLR X8371
LDCPE is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), and gate enable (GE). When CLR is High, it overrides the other inputs and resets the data (Q) output Low. When PRE is High and CLR is Low, it presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input and gate enable (GE) are High and CLR and PRE are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G or GE remains Low. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 GE X X 0 1 1 1 1 G X X X 1 1 0 D X X X 0 1 X D Outputs Q 0 1 No Chg 0 1 No Chg D
1149
LDCPE
Usage
VHDL Inference Code

architecture Behavioral of ldcpe is begin process (CLR, D, G, GE, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (GE = '1') then if (G='1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (CLR or PRE or D or G or GE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (G && GE) Q <= D; end

-- Component Declaration for LDCPE should be placed -- after architecture statement but before begin keyword component LDCPE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDCPE
1150
LDCPE
-- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDCPE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDCPE should be placed -- in architecture after the begin keyword LDCPE_INSTANCE_NAME : LDCPE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR, D => user_D, G => user_G, GE => user_GE, PRE => user_PRE);

LDCPE LDCPE_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G), .GE (user_D), .PRE (user_PRE)); defparam LDCPE_instance_name.INIT = bit_value;

INIT
1151
LDCPE
1152
LDCPE_1
LDCPE_1
Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable, and Inverted Gate
LDCPE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D GE G
LDCPE_1
Q
CLR X8372
LDCPE_1 is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset (PRE), gate enable (GE), and inverted gate (G). When CLR is High, it overrides the other inputs and resets the data (Q) output Low. When PRE is High and CLR is Low, it presets the data (Q) output High. Q reflects the data (D) input while gate enable (GE) is High and gate (G), CLR, and PRE are Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G is High or GE is Low. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 GE X X 0 1 1 1 1 G X X X 0 0 1 D X X X 0 1 X D Outputs Q 0 1 No Chg 0 1 No Chg D
1153
LDCPE_1
Usage
VHDL Inference Code

architecture Behavioral of ldcpe_1 is begin process (CLR, D, G, GE, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (GE = '1') then if (G='0') then Q <= D; end if; end if; end process; end Behavioral;

always @ (CLR or PRE or D or G or GE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (!G && GE) Q <= D; end

-- Component Declaration for LDCPE_1 should be placed -- after architecture statement but before begin keyword component LDCPE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDCPE_1
1154
LDCPE_1
-- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDCPE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDCPE_1 should be placed -- in architecture after the begin keyword LDCPE_1_INSTANCE_NAME : LDCPE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, CLR => user_CLR, D => user_D, G => user_G, GE => user_GE, PRE => user_PRE);

LDCPE_1 LDCPE_1_instance_name (.Q (user_Q), .CLR (user_CLR), .D (user_D), .G (user_G), .GE (user_D), .PRE (user_PRE)); defparam LDCPE_1_instance_name.INIT = bit_value;

INIT
1155
LDCPE_1
1156
LDE
LDE
Transparent Data Latch with Gate Enable
LDE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D GE G
LDE
Q
LDE is a transparent data latch with data (D) and gate enable (GE) inputs. Output Q reflects the data (D) while the gate (G) input and gate enable (GE) are High. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G or GE remains Low. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs GE 0 1 1 1 1 G X 1 1 0 D X 0 1 X D Outputs Q No Chg 0 1 No Chg D
X8373
Usage
1157
LDE
VHDL Inference Code

architecture Behavioral of lde is begin process (D, G, GE) begin if (GE = '1' and G = '1') then Q <= D; end if; end process; end Behavioral;

always @(D or G or GE) begin if (G && GE) Q <= D; end

-- Component Declaration for LDE should be placed -- after architecture statement but before begin keyword component LDE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC); end component; -- Component Attribute specification for LDE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDE should be placed -- in architecture after the begin keyword LDE_INSTANCE_NAME : LDE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D, G => user_G,
1158
LDE
GE => user_GE);

LDE LDE_instance_name (.Q (user_Q), .D (user_D), .G (user_G), .GE (user_GE)); defparam LDE_instance_name.INIT = bit_value;

INIT
1159
LDE
1160
LDE_1
LDE_1
Transparent Data Latch with Gate Enable and Inverted Gate
LDE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D GE G
LDE_1
Q
X8374
LDE_1 is a transparent data latch with data (D), gate enable (GE), and inverted gate (G). Output Q reflects the data (D) while the gate (G) input is Low and gate enable (GE) is High. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G is High or GE is Low. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs GE 0 1 1 1 1 G X 0 0 1 D X 0 1 X D Outputs Q No Chg 0 1 No Chg D
Usage
1161
LDE_1
VHDL Inference Code

architecture Behavioral of lde_1 is begin process (D, G, GE) begin if (GE = '1' and G = '0') then Q <= D; end if; end process; end Behavioral;

always @ (D or G or GE) begin if (!G && GE) Q <= D; end

-- Component Declaration for LDE_1 should be placed -- after architecture statement but before begin keyword component LDE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC); end component; -- Component Attribute specification for LDE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDE_1 should be placed -- in architecture after the begin keyword LDE_1_INSTANCE_NAME : LDE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D, G => user_G,
1162
LDE_1
GE => user_GE);

LDE_1 LDE_1_instance_name (.Q (user_Q), .D (user_D), .G (user_G), .GE (user_GE)); defparam LDE_1_instance_name.INIT = bit_value;

INIT
1163
LDE_1
1164
LDG
LDG
Transparent Datagate Latch
LDG Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Primitive
D G
LDG
X9813
LDG is a transparent DataGate latch used for gating input signals to decrease power dissipation. The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High. The D input(s) of the LDG must be connected to a device input pad(s) and must have no other fan-outs (must not branch). The CPLD fitter maps the G input to the device's DataGate Enable control pin (DGE). There must be no more than one DataGate Enable signal in the design. The DataGate Enable signal may be driven either by a device input pin or any on-chip logic source. The DataGate Enable signal may be reused by other ordinary logic in the design. The latch is asynchronously cleared, output Low, when power is applied, or when global reset is active. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. See LDG4, 8, 16 for information on multiple transparent datagate latches for the CoolRunner-II series.
Inputs G 0 0 1 D 0 1 X D
Outputs Q 0 1 No Chg D
Usage
For HDL, this design element can be instantiated.

component LDG
1165
LDG
port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC); end component; ... begin ... INSTANCE_NAME : LDG port map (Q => user_Q, D => user_D, G => user_G);

LDG instance_name (.Q (user_Q), .D (user_D), .G (user_G));
1166
LDG4, 8, 16
LDG4, 8, 16
Multiple Transparent Datagate Latches
LDG4, LDG8, LDG16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
D0 D1 D2 D3 G
LDG4
Q0 Q1 Q2 Q3
LDG4, LDG8, and LDG16 have, respectively, 4, 8, and 16 transparent DataGate latches with a common gate enable (G). These latches are used to gate input signals in order to decrease power dissipation during periods when activity on the input pins is not of interest to the CPLD. The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High. The D input(s) of the LDG must be connected to a device input pad(s) and must have no other fan-outs (must not branch). The CPLD fitter maps the G input to the device's DataGate Enable control pin (DGE). There must be no more than one DataGate Enable signal in the design. The DataGate Enable signal may be driven either by a device input pin or any on-chip logic source. The DataGate Enable signal may be reused by other ordinary logic in the design. The latch is asynchronously cleared, output Low, when power is applied. See LDG for information on single transparent data latches.
X9810
X9809
D[7:0]
LDG8
Q[7:0]
Inputs G 0
D[15:0] LDG16 Q[15:0]
Outputs D 0 1 X D Q 0 1 No Chg D
0 1
X9811
1167
LDG4, 8, 16
Q[7:0]
LDG D0 D G Q0 LDG D1 D G Q1 LDG D2 D G Q2 LDG D3 D G D[7:0] Q3 Q Q3 D7 D G Q Q2 D6 D G Q Q1 D5 D G Q Q0 D4 D G
LDG Q Q4
Q4 LDG Q Q5
Q5 LDG Q Q6
Q6 LDG Q Q7
Q7
X9812
LDG8 Implementation
1168
LDP
LDP
Transparent Data Latch with Asynchronous Preset
LDP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
LDP
Q
LDP is a transparent data latch with asynchronous preset (PRE). When the PRE input is High, it overrides the other inputs and presets the data (Q) output High. Q reflects the data (D) input while gate (G) input is High and PRE is Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains Low. The latch is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 0 G X 1 1 0 D X 0 1 X D Outputs Q 1 0 1 No Chg D
X8375
Usage
1169
LDP
VHDL Inference Code

architecture Behavioral of ldp is begin process (PRE, G) begin if (PRE='1') then Q <= "1"; elsif (G='1') then Q <= D; end if; end process; end Behavioral;

always @ (PRE or D or G) begin if (PRE) Q <= 1; else if (G) Q <= D; end

-- Component Declaration for LDP should be placed -- after architecture statement but before begin keyword component LDP -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDP_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDP should be placed -- in architecture after the begin keyword LDP_INSTANCE_NAME : LDP -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D,
1170
LDP
G => user_G, PRE => user_PRE);

LDP LDP_instance_name (.Q (user_Q), .D (user_D), .G (user_G), .PRE (user_PRE)); defparam LDP_instance_name.INIT = bit_value;

INIT
1171
LDP
1172
LDP_1
LDP_1
Transparent Data Latch with Asynchronous Preset and Inverted Gate
LDP_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
LDP_1
Q
LDP_1 is a transparent data latch with asynchronous preset (PRE) and inverted gate (G). When the PRE input is High, it overrides the other inputs and presets the data (Q) output High. Q reflects the data (D) input while gate (G) input and PRE are Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High. The latch is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 0 G X 0 0 1 D X 0 1 X D Outputs Q 1 0 1 No Chg D
X8376
Usage
1173
LDP_1
VHDL Inference Code

architecture Behavioral of ldp_1is begin process (PRE, G) begin if (PRE='1') then Q <= "1111"; elsif (G='0') then Q <= D; end if; end process; end Behavioral;

always @ (PRE or D or G) begin if (PRE) Q <= 1; else if (!G) Q <= D; end

-- Component Declaration for LDP_1 should be placed -- after architecture statement but before begin keyword component LDP_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDP_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDP_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDP_1 should be placed -- in architecture after the begin keyword LDP_1_INSTANCE_NAME : LDP_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D,
1174
LDP_1
G => user_G, PRE => user_PRE);

LDP_1 LDP_1_instance_name (.Q (user_Q), .D (user_D), .G (user_G), .PRE (user_PRE)); defparam LDP_1_instance_name.INIT = bit_value;

INIT
1175
LDP_1
1176
LDPE
LDPE
Transparent Data Latch with Asynchronous Preset and Gate Enable
LDPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D GE G
LDPE
X6954
LDPE is a transparent data latch with asynchronous preset and gate enable. When the asynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input and gate enable (GE) are High. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G or GE remains Low. The latch is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 0 0 GE X 0 1 1 1 1 G X X 1 1 0 D X X 0 1 X D Outputs Q 1 No Chg 0 1 No Chg D
Usage
1177
LDPE
VHDL Inference Code

architecture Behavioral of ldpe is begin process (D, G, GE, PRE) begin if (PRE='1') then Q <= '1'; elsif (GE = '1') then if (G='1') then Q <= D; end if; end if; end process; end Behavioral;

always @ (PRE or D or G or GE) begin if (PRE) Q <= 1; else if (G && GE) Q <= D; end

-- Component Declaration for LDPE should be placed -- after architecture statement but before begin keyword component LDPE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDPE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDPE_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDPE should be placed -- in architecture after the begin keyword LDPE_INSTANCE_NAME : LDPE
1178
LDPE
-- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D, G => user_G, GE => user_GE, PRE => user_PRE);

LDPE LDPE_instance_name (.Q (user_Q), .D (user_D), .G (user_G), .GE (user_GE), .PRE (user_PRE)); defparam LDPE_instance_name.INIT = bit_value;

INIT
1179
LDPE
1180
LDPE_1
LDPE_1
Transparent Data Latch with Asynchronous Preset, Gate Enable, and Inverted Gate
LDPE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE
D GE G
LDPE_1
LDPE_1 is a transparent data latch with asynchronous preset, gate enable, and inverted gate. When the asynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflects the data (D) input while the gate (G) and PRE are Low and gate enable (GE) is High. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High or GE remains Low. The latch is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 0 0 GE X 0 1 1 1 1 G X X 0 0 1 D X X 0 1 X D Outputs Q 1 No Chg 0 1 No Chg D
X7573
Usage
1181
LDPE_1
VHDL Inference Code

architecture Behavioral of ldpe_1 is begin process (D, G, GE, PRE) begin if (PRE='1') then Q <= '1'; elsif (GE = '1') then if (G='0') then Q <= D; end if; end if; end process; end Behavioral;

always @ (PRE or D or G or GE) begin if (PRE) Q <= 1; else if (!G && GE) Q <= D; end

-- Component Declaration for LDPE_1 should be placed -- after architecture statement but before begin keyword component LDPE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; D : in STD_ULOGIC; G : in STD_ULOGIC; GE : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for LDPE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LDPE_1_instance_name : label is "0"; -- values can be (0 or 1)
-- Component Instantiation for LDPE_1 should be placed -- in architecture after the begin keyword LDPE_1_INSTANCE_NAME : LDPE_1
1182
LDPE_1
-- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, D => user_D, G => user_G, GE => user_GE, PRE => user_PRE);

LDPE_1 LDPE_1_instance_name (.Q (user_Q), .D (user_D), .G (user_G), .GE (user_GE), .PRE (user_PRE)); defparam LDPE_1_instance_name.INIT = bit_value;

INIT
1183
LDPE_1
1184
LUT1, 2, 3, 4
LUT1, 2, 3, 4
1-, 2-, 3-, 4-Bit Look-Up-Table with General Output
LUT1, LUT2, LUT3, LUT4 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
LUT1
O I0
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and 4-bit look-up-tables (LUTs) with general output (O). A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs, must be attached to the LUT to specify its function. LUT1 provides a look-up-table version of a buffer or inverter. LUTs are the basic Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II, Spartan-IIE, and Spartan-3 building blocks. Two LUTs are available in each CLB slice; four LUTs are available in each CLB. The variants, LUT1_D, LUT2_D, LUT3_D, LUT4_D and LUT1_L, LUT2_L, LUT3_L, LUT4_L provide additional types of outputs that can be used by different timing models for more accurate pre-layout timing estimation. LUT3 Function Table
O
X9852
I1
LUT2
O
I0
X8379
I2 I1 I0
LUT3
Inputs I2 0 I1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1
Outputs O INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7]
X8382
I3 I2
LUT4
O
0 0 0 1
X8385
I1 I0
1 1 1
INIT = binary equivalent of the hexadecimal number assigned to the INIT attribute
1185
LUT1, 2, 3, 4
Usage
LUTs are generally inferred with the logic portions of the HDL code. Xilinx suggests that you instantiate LUTs only if you have a need to implicitly specify the logic mapping, or if you need to manually place or relationally place the logic.
VHDL Instantiation Template for LUT1

-- Component Declaration for LUT1 should be placed -- after architecture statement but before begin keyword component LUT1 -- synthesis translate_off generic ( INIT : bit_vector := X"2"); -- synthesis translate_on port (O : out STD_ULOGIC; IO : in STD_ULOGIC); end component; -- Component Attribute specification for LUT1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT1_instance_name : label is "2"; -- values can be 0, 1, 2,or 3
-- Component Instantiation for LUT1 should be placed -- in architecture after the begin keyword LUT1_INSTANCE_NAME : LUT1 -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (O => user_O, IO => user_IO);
Verilog Instantiation Template For LUT1

LUT1 LUT1_instance_name (.O (user_O), .IO (user_IO)); defparam LUT1_instance_name.INIT = hex_value;

-- Component Declaration for LUT2 should be placed -- after architecture statement but before begin keyword component LUT2 -- synthesis translate_off generic ( INIT : bit_vector := X"4"); -- synthesis translate_on
1186
LUT1, 2, 3, 4
port (O : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT2 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT2_instance_name : label is "4"; -- values can be 0, 1, 2,3, or 4
-- Component Instantiation for LUT2 should be placed -- in architecture after the begin keyword LUT2_INSTANCE_NAME : LUT2 -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (O => user_O, I0 => user_I0, I1 => user_I1);

LUT2 LUT2_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1)); defparam LUT2_instance_name.INIT = hex_value;

-- Component Declaration for LUT3 should be placed -- after architecture statement but before begin keyword component LUT3 -- synthesis translate_off generic ( INIT : bit_vector := X"8"); -- synthesis translate_on port (O : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT3 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT3_instance_name : label is "8"; -- values can be 0, 1, 2, 3, 4, 5, 6, 7, 8
1187
LUT1, 2, 3, 4
-- Component Instantiation for LUT3 should be placed -- in architecture after the begin keyword -LUT3_INSTANCE_NAME : LUT3 -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2);

LUT3 LUT3_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2)); defparam LUT4_instance_name.INIT = hex_value;

-- Component Declaration for LUT4 should be placed -- after architecture statement but before begin keyword component LUT4 -- synthesis translate_off generic ( INIT : bit_vector := X"16"); -- synthesis translate_on port (O : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT4 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT4_instance_name : label is "16"; -- values can be 0 through 16
-- Component Instantiation for LUT4 should be placed -- in architecture after the begin keyword
LUT4_INSTANCE_NAME : LUT4 -- synthesis translate_off generic map ( INIT => hex_value)
1188
LUT1, 2, 3, 4
-- synthesis translate_on port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3);

LUT4 LUT4_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3)); defparam LUT4_instance_name.INIT = hex_value;

BEL INIT LOC U_SET
1189
LUT1, 2, 3, 4
1190
LUT1_D, LUT2_D, LUT3_D, LUT4_D

1-, 2-, 3-, 4-Bit Look-Up-Table with Dual Output
LUT1_D, LUT2_D, LUT3_D, LUT4_D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
LUT1_D
LO
I0
LUT1_D, LUT2_D, LUT3_D, and LUT4_D are, respectively, 1-, 2-, 3-, and 4-bit lookup-tables (LUTs) with two functionally identical outputs, O and LO. The O output is a general interconnect. The LO output is used to connect to another output within the same CLB slice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs, must be attached to the LUT to specify its function. LUT1_D provides a look-up-table version of a buffer or inverter. See also LUT1, 2, 3, 4 and LUT1_L, LUT2_L, LUT3_L, LUT4_L. LUT3_D Function Table
X8377
I1
LUT2_D
LO
I0
X8380
I2 I1 I0
LUT3_D
LO
Inputs I2 0 0 0 I1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1 O INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7]
Outputs LO INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7]
X8383
I3 I2 I1 I0
LUT4_D
LO O
0 1 1 1 1
X8386
Usage
1191
VHDL Instantiation Template for LUT1_D

-- Component Declaration for LUT1_D should be placed -- after architecture statement but before begin keyword component LUT1_D -- synthesis translate_off generic ( INIT : bit_vector := X"2"); -- synthesis translate_on port (LO : out STD_ULOGIC; O : out STD_ULOGIC; I0 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT1_D -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT1_D_instance_name : label is "2"; -- values can be 0, 1, 2,or 3
-- Component Instantiation for LUT1_D should be placed -- in architecture after the begin keyword LUT1_D_INSTANCE_NAME : LUT1_D -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (LO => user_LO, O => user_O, IO => user_IO);
Verilog Instantiation Template For LUT1_D

LUT1_D LUT1_D_instance_name (.LO (user_LO), .O (user_O), .IO (user_IO)); defparam LUT1_D_instance_name.INIT = hex_value;

-- Component Declaration for LUT2_D should be placed -- after architecture statement but before begin keyword component LUT2_D -- synthesis translate_off generic ( INIT : bit_vector := X"4"); -- synthesis translate_on port (LO : out STD_ULOGIC; O : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC);
1192
end component; -- Component Attribute specification for LUT2_D -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT2_D_instance_name : label is "4"; -- Component Instantiation for LUT2_D should be placed -- in architecture after the begin keyword LUT2_D_INSTANCE_NAME : LUT2_D -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (LO => user_LO, O => user_O, I0 => user_I0, I1 => user_I1);

LUT2_D LUT2_D_instance_name (.LO (user_O), .O (user_O), .I0 (user_I0), .I1 (user_I1)); defparam LUT2_D_instance_name.INIT = hex_value;

-- Component Declaration for LUT3_D should be placed -- after architecture statement but before begin keyword component LUT3_D -- synthesis translate_off generic ( INIT : bit_vector := X"8"); -- synthesis translate_on port (LO : out STD_ULOGIC; O : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT3_D -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT3_D_instance_name : label is "8";
-- Component Instantiation for LUT3_D should be placed
1193
-- in architecture after the begin keyword LUT3_D_INSTANCE_NAME : LUT3_D -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (LO => user_LO, O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2);

LUT3_D LUT3_D_instance_name (.LO (user_LO), .O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2)); defparam LUT3_D_instance_name.INIT = hex_value;

-- Component Declaration for LUT4_D should be placed -- after architecture statement but before begin keyword component LUT4_D -- synthesis translate_off generic ( INIT : bit_vector := X"16"); -- synthesis translate_on port (LO : out STD_ULOGIC; O : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT4_D -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT4_D_instance_name : label is "16"; -- values can be 0 through 16
-- Component Instantiation for LUT4_D should be placed -- in architecture after the begin keyword LUT4_D_INSTANCE_NAME : LUT4_D -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on
1194
port map (LO => user_LO, O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3);

LUT4_D LUT4_D_instance_name (.LO (user_LO), .O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3)); defparam LUT4_D_instance_name.INIT = hex_value;

INIT LOC RLOC BEL U_SET
1195
1196
LUT1_L, LUT2_L, LUT3_L, LUT4_L

1-, 2-, 3-, 4-Bit Look-Up-Table with Local Output
LUT1_L, LUT2_L, LUT3_L, LUT4_L Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
I3 I2
LUT4_L
LO
I1 I0
LUT1_L, LUT2_L, LUT3_L, and LUT4_L are, respectively, 1-, 2-, 3-, and 4- bit look-uptables (LUTs) with a local output (LO) that is used to connect to another output within the same CLB slice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs, must be attached to the LUT to specify its function. LUT1_L provides a look-up-table version of a buffer or inverter.
LUT1_L
LO
See also LUT1, 2, 3, 4 and LUT1_D, LUT2_D, LUT3_D, LUT4_D. LUT3_L Function Table
I0
X8378
Inputs
I1
Outputs I0 0 1 0 1 0 1 0 1 LO INIT[0] INIT[1] INIT[2] INIT[3] INIT[4] INIT[5] INIT[6] INIT[7]
LUT2_L
LO
I2 0 0
I1 0 0 1 1 0 0 1 1
I0
X8381
0 0 1 1 1 1
I2 I1 I0
LUT3_L
LO
X8384
Usage
1197
VHDL Instantiation Template for LUT1_L

-- Component Declaration for LUT1_L should be placed -- after architecture statement but before begin keyword component LUT1_L -- synthesis translate_off generic ( INIT : bit_vector := X"2"); -- synthesis translate_on port (LO : out STD_ULOGIC; IO : inSTD_ULOGIC); end component; -- Component Attribute specification for LUT1_L -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT1_L_instance_name : label is "2"; -- values can be 0, 1, 2,or 3
-- Component Instantiation for LUT1_L should be placed -- in architecture after the begin keyword LUT1_L_INSTANCE_NAME : LUT1_L -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (LO => user_LO, IO => user_IO);
Verilog Instantiation Template For LUT1_L

LUT1_L LUT1_L_instance_name (.LO (user_LO), .IO (user_IO)); defparam LUT1_L_instance_name.INIT = hex_value;

-- Component Declaration for LUT2_L should be placed -- after architecture statement but before begin keyword component LUT2_L -- synthesis translate_off generic ( INIT : bit_vector := X"4"); -- synthesis translate_on port (LO : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT2_L -- should be placed after architecture declaration but
1198
-- before the begin keyword attribute INIT : string; attribute INIT of LUT2_L_instance_name : label is "4";
-- Component Instantiation for LUT2_L should be placed -- in architecture after the begin keyword LUT2_L_INSTANCE_NAME : LUT2_L -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (LO => user_LO, I0 => user_I0, I1 => user_I1);

LUT2_L LUT2_L_instance_name (.LO (user_O), .I0 (user_I0), .I1 (user_I1)); defparam LUT2_L_instance_name.INIT = hex_value;

-- Component Declaration for LUT3_L should be placed -- after architecture statement but before begin keyword component LUT3_L -- synthesis translate_off generic ( INIT : bit_vector := X"8"); -- synthesis translate_on port (LO : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT3_L -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT3_L_instance_name : label is "8";
-- Component Instantiation for LUT3_L should be placed -- in architecture after the begin keyword -LUT3_L_INSTANCE_NAME : LUT3_L -- synthesis translate_off generic map (
1199
INIT => hex_value) -- synthesis translate_on port map (LO => user_LO, I0 => user_I0, I1 => user_I1, I2 => user_I2);

LUT3_L LUT3_L_instance_name (.LO .I0 .I1 .I2 (user_LO), (user_I0), (user_I1), (user_I2));
defparam LUT3_L_instance_name.INIT = hex_value;

-- Component Declaration for LUT4_L should be placed -- after architecture statement but before begin keyword -component LUT4_L -- synthesis translate_off generic ( INIT : bit_vector := X"16"); -- synthesis translate_on port (LO : out STD_ULOGIC; IO : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component; -- Component Attribute specification for LUT4_L -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of LUT4_L_instance_name : label is "16"; -- values can be 0 through 16
-- Component Instantiation for LUT4_L should be placed -- in architecture after the begin keyword -LUT4_L_INSTANCE_NAME : LUT4_L -- synthesis translate_off generic map ( INIT => hex_value) -- synthesis translate_on port map (LO => user_LO, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3);
1200

LUT4_L LUT4_L_instance_name (.LO .I0 .I1 .I2 .I3 (user_LO), (user_I0), (user_I1), (user_I2), (user_I3));
defparam LUT4_L_instance_name.INIT = hex_value;

INIT LOC RLOC BEL U_SET
1201
1202
M2_1
M2_1
2-to-1 Multiplexer
M2_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D0 D1 S0 X4026
The M2_1 multiplexer chooses one data bit from two sources (D1 or D0) under the control of the select input (S0). The output (O) reflects the state of the selected data input. When Low, S0 selects D0 and when High, S0 selects D1.
Inputs S0 1 1 0 0
D0 M0 AND2B1
Outputs D0 X X 1 0 O 1 0 1 0
D1 1 0 X X
S0
O OR2
D1 AND2
M1
X7661
M2_1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-3, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
1203
M2_1
VHDL Inference Code

architecture Behavioral of m2_1 is begin process (D0,D1,S0) begin case S0 is when '0' => O <= D0; when '1' => O <= D1; when others => NULL; end case; end process; end Behavioral;

always @(D0 or D1 or S0) begin case (S0) 0 : O <= D0; 1 : O <= D1; endcase end
1204
M2_1B1
M2_1B1
2-to-1 Multiplexer with D0 Inverted
M2_1B1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
D0 D1 S0 X4027
The M2_1B1 multiplexer chooses one data bit from two sources (D1 or D0) under the control of select input (S0). When S0 is Low, the output (O) reflects the inverted value of D0. When S0 is High, O reflects the state of D1.
Inputs S0 1 1 0 0
D0 M0 AND2B2
Outputs D0 X X 1 0 O 1 0 0 1
D1 1 0 X X
S0
O OR2
D1 AND2
M1
X7662
M2_1B1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-3, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
1205
M2_1B1
VHDL Inference Code

architecture Behavioral of m2_1b1 is begin process (D0,D1,S0) begin case S0 is when '0' => O <= not D0; when '1' => O <= D1; when others => NULL; end case; end process; end Behavioral;

always @(D0 or D1 or S0) begin case (S0) 0 : O <= !D0; 1 : O <= D1; endcase end
1206
M2_1B2
M2_1B2
2-to-1 Multiplexer with D0 and D1 Inverted
M2_1B2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
D0 D1 S0 X4028
The M2_1B2 multiplexer chooses one data bit from two sources (D1 or D0) under the control of select input (S0). When S0 is Low, the output (O) reflects the inverted value of D0. When S0 is High, O reflects the inverted value of D1.
Inputs S0 1 1 0 0
D0
Outputs D0 X X 1 0 O 0 1 0 1
D1 1 0 X X
M0 AND2B2
S0
O OR2
D1 AND2B1
M1
X7663
M2_1B2 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
1207
M2_1B2
VHDL Inference Code

architecture Behavioral of m2_1b2 is begin process (D0,D1,S0) begin case S0 is when '0' => O <= not D0; when '1' => O <= not D1; when others => NULL; end case; end process; end Behavioral;

always @(D0 or D1 or S0) begin case (S0) 0 : O <= !D0; 1 : O <= !D1; endcase end
1208
M2_1E
M2_1E
2-to-1 Multiplexer with Enable
M2_1E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
D0 D1 S0 E X4029
M2_1E is a 2-to-1 multiplexer with enable. When the enable input (E) is High, the M2_1E chooses one data bit from two sources (D1 or D0) under the control of select input (S0). When Low, S0 selects D0 and when High, S0 selects D1. When E is Low, the output is Low.
Inputs E 0 1 1 1 1
D0 E S0 AND3B1 O OR2 M1 D1 AND3 X7858
Outputs D1 X X X 1 0 D0 X 1 0 X X O 0 1 0 1 0
S0 X 0 0 1 1
M0
M2_1E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
1209
M2_1E
VHDL Inference Code

architecture Behavioral of m2_1e is begin process (D0,D1,E,S0) begin if (E='0') then O <= '0'; else case S0 is when '0' => O <= D0; when '1' => O <= D1; when others => NULL; end case; end if; end process; end Behavioral;

begin if (!E) O <= 0; else begin case (S0) 0 : O <= D0; 1 : O <= D1; endcase end end
1210
M4_1E
M4_1E
D0 D1 D2 D3 S0 S1 E X4030
M4_1E is an 4-to-1 multiplexer with enable. When the enable input (E) is High, the M4_1E multiplexer chooses one data bit from four sources (D3, D2, D1, or D0) under the control of the select inputs (S1 S0). The output (O) reflects the state of the selected input as shown in the truth table. When E is Low, the output is Low.
Inputs E 0 1 1 1 1 S1 X 0 0 1 1
M2_1E
D0 D1 D0 D1 S0 E D2 D3 S0 E S1 X7859 D0 D1 S0 E O
Outputs D1 X X D1 X X D2 X X X D2 X D3 X X X X D3 O 0 D0 D1 D2 D3
S0 X 0 1 0 1
D0 X D0 X X X
M2_1
M01 M01 M23 D0 D1 S0 O 0 O
M2_1E
O
M23
M4_1E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1211
M4_1E
M2_1E
D0 D1 D0 D1 S0 E D2 D3 S0 E S1 D0 D1 S0 E O
MUXF5
M01 M01 M23
M2_1E
O
I0 I1 S
O 0
M23 X9348
M4_1E Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, VirtexII Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of m4_1e is begin process (D,E,S) begin if (E='0') then O <= '0'; else case S is when when when when when end case; end if; end process;
"00" => O "01" => O "10" => O "11" => O others =>
<= D(0); <= D(1); <= D(2); <= D(3); NULL;
end Behavioral;

always @(D or E or S) begin if (!E) O <= 0; else begin case (S) 0 1 2 3 endcase end end : : : : O O O O <= <= <= <= D[0]; D[1]; D[2]; D[3];
1212
M8_1E
M8_1E
D0 D1 D2 D3 D4 D5 D6 D7 S0 S1 S2 E X4031 O
M8_1E is an 8-to-1 multiplexer with enable. When the enable input (E) is High, the M8_1E multiplexer chooses one data bit from eight sources (D7 D0) under the control of the select inputs (S2 S0). The output (O) reflects the state of the selected input as shown in the truth table. When E is Low, the output is Low.
Inputs E 0 1 1 1 1 1 1 1 1 S2 X 0 0 0 0 1 1 1 1 S1 X 0 0 1 1 0 0 1 1 S0 X 0 1 0 1 0 1 0 1 D7 D0 X D0 D1 D2 D3 D4 D5 D6 D7
Outputs O 0 D0 D1 D2 D3 D4 D5 D6 D7
Dn represents signal on the Dn input; all other data inputs are dont-cares (X).
1213
M8_1E
M2_1
D0 D1 D0 D1 S0 O
M01 M2_1
M01 M23 D0 D1 S0 O
M03
M2_1
D2 D3 D0 D1 S0 O
M23 M2_1E
M03 M47 D0 D1 S0 E O O
M2_1
D4 D5 D0 D1 S0
M45 M2_1
M45 M67 D0 D1 S0 O O
M47
M2_1
D6 D7 S0 S1 S2 E D0 D1 S0
M67
X7640
M8_1E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

M2_1E
D0 D1 D0 D1 S0 E D2 D3 D0 D1 S0 E D0 D1 S0 E D0 D1 S0 E O
MUXF5_L
M01 M01 M23 I0 I1 S LO M03
M2_1E
O
MUXF6
M23 M03 M47 I0 I1 S O O O
M2_1E
D4 D5 O
MUXF5_L
M45 M45 M67 I0 I1 S LO M47
M2_1E
D6 D7 S0 O
M67
S1 S2 E X8716
M8_1E Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of m8_1e is begin process (D,E,S)
1214
M8_1E
begin if (E='0') then O <= '0'; else case S is when when when when when when when when when end case; end if; end process; end Behavioral;
"000" => O <= D(0); "001" => O <= D(1); "010" => O <= D(2); "011" => O <= D(3); "100" => O <= D(4); "101" => O <= D(5); "110" => O <= D(6); "111" => O <= D(7); others => NULL;

always @(D or E or S) begin if (!E) O <= 0; else begin case (S) 0 1 2 3 4 5 6 7 endcase end end : : : : : : : : O O O O O O O O <= <= <= <= <= <= <= <= D[0]; D[1]; D[2]; D[3]; D[4]; D[5]; D[6]; D[7];
1215
M8_1E
1216
M16_1E
M16_1E
M16_1E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 S0 S1 S2 S3 E X4032 O
M16_1E is a 16-to-1 multiplexer with enable. When the enable input (E) is High, the M16_1E multiplexer chooses one data bit from 16 sources (D15 D0) under the control of the select inputs (S3 S0). The output (O) reflects the state of the selected input as shown in the truth table. When E is Low, the output is Low.
Inputs E 0 1 1 1 1 . . . 1 1 1 1 S3 X 0 0 0 0 . . . 1 1 1 1 S2 X 0 0 0 0 . . . 1 1 1 1 S1 X 0 0 1 1 . . . 0 0 1 1 S0 X 0 1 0 1 . . . 0 1 0 1 D15 D0 X D0 D1 D2 D3 . . . D12 D13 D14 D15
Outputs O 0 D0 D1 D2 D3 . . . D12 D13 D14 D15
Dn represents signal on the Dn input; all other data inputs are don't-cares (X).
Usage
1217
M16_1E
VHDL Inference Code

architecture Behavioral of m16_1e is begin process (D,E,S) begin if (E='0') then O <= '0'; else case S is when when when when when when when when when when when when when when when when when end case; end if; end process; end Behavioral;
"0000" "0001" "0010" "0011" "0100" "0101" "0110" "0111" "1000" "1001" "1010" "1011" "1100" "1101" "1110" "1111" others
=> => => => => => => => => => => => => => => => =>
O <= D(0); O <= D(1); O <= D(2); O <= D(3); O <= D(4); O <= D(5); O <= D(6); O <= D(7); O <= D(8); O <= D(9); O <= D(10); O <= D(11); O <= D(12); O <= D(13); O <= D(14); O <= D(15); NULL;

always @(D or E or S) begin if (!E) O <= 0; else begin case (S) 0 : O <= D[0]; 1 : O <= D[1]; 2 : O <= D[2]; 3 : O <= D[3]; 4 : O <= D[4]; 5 : O <= D[5]; 6 : O <= D[6]; 7 : O <= D[7]; 8 : O <= D[8]; 9 : O <= D[9]; 10 : O <= D[10]; 11 : O <= D[11]; 12 : O <= D[12]; 13 : O <= D[13];
1218
M16_1E
14 : O <= D[14]; 15 : O <= D[15]; endcase end end
1219
M16_1E
1220
MULT_AND
MULT_AND
Fast Multiplier AND
MULT_AND Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
I1 I0 LO X8405
MULT_AND is an AND component used exclusively for building fast and smaller multipliers. The I1 and I0 inputs must be connected to the I1 and I0 inputs of the associated LUT. The LO output must be connected to the DI input of the associated MUXCY, MUXCY_D, or MUXCY_L.
Inputs I1 0 0 1 1 I0 0 1 0 1
Output LO 0 0 0 1
LO S LUT4 B1 A1 B0 A0 I3 I2 I1 IO
MUXCY_L
0 1 DI CI
LI CI
O XORCY
SUM1
I1 I0
LO
MULT_AND CO X8733
Example Multiplier Using MULT_AND
Usage
1221
MULT_AND

-- Component Declaration for MULT_AND should be placed -- after architecture statement but before begin keyword component MULT_AND port (LO : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC); end component; -- Component Attribute specification for MULT_AND -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MULT_AND should be placed -- in architecture after the begin keyword MULT_AND_INSTANCE_NAME : MULT_AND port map (LO => user_LO, I0 => user_I0, I1 => user_I1);

MULT_AND MULT_AND_instance_name (.LO (user_LO), .I0 (user_I0), .I1 (user_I1));

U_SET MULT_STYLE
1222
MULT18X18
MULT18X18
18 x 18 Signed Multiplier
MULT18, MULT18X Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
MULT18x18 A [17:0] P [35:0] B [17:0]
MULT18X18 is a combinational signed 18-bit by 18-bit multiplier. The value represented in the 18-bit input A is multiplied by the value represented in the 18-bit input B. Output P is the 36-bit product of A and B. A, B, and P are two's complement.
Inputs A A B B Output P A*B
X9258
XST, Synplify, Exemplar and Synopsys all have the ability to infer the MULT18X18.
Usage
For HDL, this design element can only be instantiated.

-- Component Declaration for MULT18X18 should be placed -- after architecture statement but before begin keyword component MULT18X18 port (P : out STD_LOGIC_VECTOR (35 downto 0); A : in STD_LOGIC_VECTOR (17 downto 0); B : in STD_LOGIC_VECTOR (17 downto 0)); end component; -- Component Attribute specification for MULT18X18 -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MULT18X18 should be placed -- in architecture after the begin keyword MULT18X18_INSTANCE_NAME : MULT18X18
1223
MULT18X18
port map (P => user_P, A => user_A, B => user_B);

MULT18X18 MULT18X18_instance_name (.P (user_P), .A (user_A), .B (user_B));

MULT_STYLE
1224
MULT18X18S
MULT18X18S
18 x 18 Signed Multiplier -- Registered Version
MULT18X, MULT18S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
A [17:0] B [17:0] C CE R
MULT18X18S
P [35:0]
MULT18X18S is the registered version of the 18 x 18 signed multiplier with output P and inputs A, B, C, CE, and R. The registers are initialized to 0 after the GSR pulse. The value represented in the 18-bit input A is multiplied by the value represented in the 18-bit input B. Output P is the 36-bit product of A and B. A, B, and P are two's complement.
Inputs C X CE X 1 0 Am X Am X Output
X9733
Bn
X Bn X
R
1 0 0
P 0 A*B No Chg
Usage

-- Component Declaration for MULT18X18S should be placed -- after architecture statement but before begin keyword component MULT18X18S port (P : out STD_LOGIC_VECTOR (35 downto 0); A : in STD_LOGIC_VECTOR (17 downto 0); B : in STD_LOGIC_VECTOR (17 downto 0); C : in STD_ULOGIC; CE : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for MULT18X18S -- should be placed after architecture declaration but -- before the begin keyword
1225
MULT18X18S
-- Attributes should be placed here -- Component Instantiation for MULT18X18S should be placed -- in architecture after the begin keyword
MULT18X18S_INSTANCE_NAME : MULT18X18S port map (P => user_P, A => user_A, B => user_B, CE => user_CE, C => user_C, R => user_R);

MULT18X18S MULT18X18S_instance_name (.P (user_P), .A (user_A), .B (user_B), .C (user_C), .CE (user_CE), .R (user_R));

HU_SET MULT_STYLE
1226
MUXCY
MUXCY
2-to-1 Multiplexer for Carry Logic with General Output
MUXCY Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
O S
MUXCY
MUXCY is used to implement a 1-bit high-speed carry propagate function. One such function can be implemented per logic cell (LC), for a total of: 2-bits per CLB for Virtex, Virtex-E, Spartan-II, and Spartan-IIE 4-bits per configurable logic block (CLB) for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X
DI CI
X8728
The direct input (DI) of an LC is connected to the DI input of the MUXCY. The carry in (CI) input of an LC is connected to the CI input of the MUXCY. The select input (S) of the MUXCY is driven by the output of the lookup table (LUT) and configured as a MUX function. The carry out (O) of the MUXCY reflects the state of the selected input and implements the carry out function of each LC. When Low, S selects DI; when High, S selects CI. The variants, MUXCY_D and MUXCY_L provide additional types of outputs that can be used by different timing models for more accurate pre-layout timing estimation.
Inputs S 0 0 1 1 DI 1 0 X X CI X X 1 0
Outputs O 1 0 1 0
Usage
1227
MUXCY

-- Component Declaration for MUXCY should be placed -- after architecture statement but before begin keyword component MUXCY port (O : out STD_ULOGIC; CI : in STD_ULOGIC; DI : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXCY -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXCY should be placed -- in architecture after the begin keyword MUXCY_INSTANCE_NAME : MUXCY port map (O => user_O, CI => user_CI, DI => user_DI, S => user_S);

MUXCY MUXCY_instance_name (.O (user_O), .CI (user_CI), .DI (user_DI), .S (user_S));

U_SET
1228
MUXCY_D
MUXCY_D
2-to-1 Multiplexer for Carry Logic with Dual Output
MUXCY_D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
LO O S
MUXCY_D
DI CI
X8729
MUXCY_D is used to implement a 1-bit high-speed carry propagate function. One such function can be implemented per logic cell (LC), for a total of 4-bits per configurable logic block (CLB). The direct input (DI) of an LC is connected to the DI input of the MUXCY_D. The carry in (CI) input of an LC is connected to the CI input of the MUXCY_D. The select input (S) of the MUX is driven by the output of the lookup table (LUT) and configured as an XOR function. The carry out (O and LO) of the MUXCY_D reflects the state of the selected input and implements the carry out function of each LC. When Low, S selects DI; when High, S selects CI. Outputs O and LO are functionally identical. The O output is a general interconnect. See also MUXCY and MUXCY_L
Inputs S 0 0 1 1 DI 1 0 X X CI X X 1 0 O 1 0 1 0
Outputs LO 1 0 1 0
Usage
1229
MUXCY_D

-- Component Declaration for MUXCY_D should be placed -- after architecture statement but before begin keyword component MUXCY_D port (LO : out STD_ULOGIC; O : out STD_ULOGIC; CI : in STD_ULOGIC; DI : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXCY_D -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXCY_D should be placed -- in architecture after the begin keyword MUXCY_D_INSTANCE_NAME port map (LO => O => CI => DI => S => : MUXCY_D user_O, user_O, user_CI, user_DI, user_S);

MUXCY_D MUXCY_D_instance_name (.LO (user_LO), .O (user_O), .CI (user_CI), .DI (user_DI), .S (user_S));

U_SET
1230
MUXCY_L
MUXCY_L
2-to-1 Multiplexer for Carry Logic with Local Output
MUXCY_L Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
LO S
MUXCY_L
DI CI
X8730
MUXCY_L is used to implement a 1-bit high-speed carry propagate function. One such function can be implemented per logic cell (LC), for a total of 4-bits per configurable logic block (CLB). The direct input (DI) of an LC is connected to the DI input of the MUXCY_L. The carry in (CI) input of an LC is connected to the CI input of the MUXCY_L. The select input (S) of the MUXCY_L is driven by the output of the lookup table (LUT) and configured as an XOR function. The carry out (LO) of the MUXCY_L reflects the state of the selected input and implements the carry out function of each LC. When Low, S selects DI; when High, S selects CI. See also MUXCY and MUXCY_D
Inputs S 0 0 1 1 DI 1 0 X X CI X X 1 0
Outputs LO 1 0 1 0
Usage
1231
MUXCY_L

-- Component Declaration for MUXCY_L should be placed -- after architecture statement but before begin keyword component MUXCY_L port (LO : out STD_ULOGIC; CI : in STD_ULOGIC; DI : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXCY_L -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXCY_L should be placed -- in architecture after the begin keyword MUXCY_L_INSTANCE_NAME : MUXCY_L port map (LO => user_O, CI => user_CI, DI => user_DI, S => user_S);

MUXCY_L MUXCY_L_instance_name (.LO (user_LO), .CI (user_CI), .DI (user_DI), .S (user_S));

U_SET
1232
MUXF5
MUXF5
2-to-1 Lookup Table Multiplexer with General Output
MUXF5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I0 I1 S
X8431
MUXF5 provides a multiplexer function in a CLB slice for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables. The local outputs (LO) from the two lookup tables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. The variants, MUXF5_D and MUXF5_L, provide additional types of outputs that can be used by different timing models for more accurate pre-layout timing estimation.
Inputs S 0 0 1 1 I0 1 0 X X I1 X X 1 0
Outputs O 1 0 1 0
Usage

-- Component Declaration for MUXF5 should be placed -- after architecture statement but before begin keyword component MUXF5 port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXF5
1233
MUXF5
-- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF5 should be placed -- in architecture after the begin keyword MUXF5_INSTANCE_NAME : MUXF5 port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

MUXF5 MUXF5_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .S (user_S));
1234
MUXF5_D
MUXF5_D
2-to-1 Lookup Table Multiplexer with Dual Output
MUXF5_D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
I0 I1 S
LO O
X8432
MUXF5_D provides a multiplexer function in a CLB slice for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables. The local outputs (LO) from the two lookup tables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output is used to connect to other inputs within the same CLB slice. See also MUXF5 and MUXF5_L
Inputs S 0 0 1 1 I0 1 0 X X I1 X X 1 0 O 1 0 1 0
Outputs LO 1 0 1 0
Usage

-- Component Declaration for MUXF5_D should be placed -- after architecture statement but before begin keyword component MUXF5_D port (LO : out STD_ULOGIC; O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component;
1235
MUXF5_D
-- Component Attribute specification for MUXF5_D -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF5_D should be placed -- in architecture after the begin keyword MUXF5_D_INSTANCE_NAME port map (LO => O => I0 => I1 => S => : MUXF5_D user_LO, user_O, user_I0, user_I1, user_S);

MUXF5_D MUXF5_D_instance_name (.LO (user_LO), .O (user_O), .I0 (user_I0), .I1 (user_I1), .S (user_S));
1236
MUXF5_L
MUXF5_L
2-to-1 Lookup Table Multiplexer with Local Output
MUXF5_L Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I0 I1 S
X8433
LO
MUXF5_L provides a multiplexer function in a CLB slice for creating a function-of-5 lookup table or a 4-to-1 multiplexer in combination with the associated lookup tables. The local outputs (LO) from the two lookup tables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. The LO output is used to connect to other inputs within the same CLB slice. See also MUXF5 and MUXF5_D.
Inputs S 0 0 1 1 I0 1 0 X X I1 X X 1 0
Output LO 1 0 1 0
Usage

-- Component Declaration for MUXF5_L should be placed -- after architecture statement but before begin keyword component MUXF5_L port (LO : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXF5_L
1237
MUXF5_L
-- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF5_L should be placed -- in architecture after the begin keyword MUXF5_L_INSTANCE_NAME port map (LO => I0 => I1 => S => : MUXF5_L user_LO, user_I0, user_I1, user_S);

MUXF5_L MUXF5_L_instance_name (.LO (user_LO), .I0 (user_I0), .I1 (user_I1), .S (user_S));
1238
MUXF6
MUXF6
MUXF6 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
I0 I1 S
X8434
MUXF6 provides a multiplexer function in a full Virtex, Virtex-E, Spartan-II, or Spartan-IIE CLB, or one half of a Spartan-3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X CLB (two slices) for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. The variants, MUXF6_D and MUXF6_L, provide additional types of outputs that can be used by different timing models for more accurate pre-layout timing estimation.
Inputs S 0 0 1 1 I0 1 0 X X I1 X X 1 0
Outputs O 1 0 1 0
Usage

-- Component Declaration for MUXF6 should be placed -- after architecture statement but before begin keyword component MUXF6 port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC);
1239
MUXF6
end component; -- Component Attribute specification for MUXF6 -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF6 should be placed -- in architecture after the begin keyword MUXF6_INSTANCE_NAME : MUXF6 port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

1240
MUXF6_D
MUXF6_D
MUXF6_D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I0 I1 S
X8435
LO O
MUXF6_D provides a multiplexer function in a full Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II, Spartan-IIE, or Spartan-3 CLB, or one half of a Spartan3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X CLB (two slices) for creating a function-of6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output is used to connect to other inputs within the same CLB slice. See also MUXF6 and MUXF6_L
Inputs S 0 0 1 1 I0 1 0 X X I1 X X 1 0 O 1 0 1 0
Outputs LO 1 0 1 0
Usage

-- Component Declaration for MUXF6_D should be placed -- after architecture statement but before begin keyword component MUXF6_D port (LO : out STD_ULOGIC; O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC;
1241
MUXF6_D
S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXF6_D -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF6_D should be placed -- in architecture after the begin keyword MUXF6_D_INSTANCE_NAME : MUXF6_D port map (LO => user_LO, O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

1242
MUXF6_L
MUXF6_L
MUXF6_L Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
I0 I1 S
LO
X8436
MUXF6_L provides a multiplexer function in a full Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II, Spartan-II E, or Spartan-3 CLB, or one half of a Spartan-3, Virtex-II, Virtex-II Pro, or Virtex-II Pro X CLB (two slices) for creating a function-of-6 lookup table or an 8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. The local outputs (LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. The LO output is used to connect to other inputs within the same CLB slice. See also MUXF6 and MUXF6_D.
Inputs S 0 0 1 1 I0 1 0 X X I1 X X 1 0
Output LO 1 0 1 0
Usage

-- Component Declaration for MUXF6_L should be placed -- after architecture statement but before begin keyword component MUXF6_L port (LO : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component;
1243
MUXF6_L
-- Component Attribute specification for MUXF6_L -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF6_L should be placed -- in architecture after the begin keyword MUXF6_L_INSTANCE_NAME : MUXF6_L port map (LO => user_LO, I0 => user_I0, I1 => user_I1, S => user_S);

1244
MUXF7
MUXF7
MUXF7 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I0 I1 S
X8431
MUXF7 provides a multiplexer function in a full Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X CLB for creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables. Local outputs (LO) of MUXF6 are connected to the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. The variants, MUXF7_D and MUXF7_L, provide additional types of outputs that can be used by different timing models for more accurate pre-layout timing estimation.
Inputs S 0 1 X X I0 I0 X 0 1 I1 X I1 0 1
Outputs O I0 I1 0 1
Usage

-- Component Declaration for MUXF7 should be placed -- after architecture statement but before begin keyword component MUXF7 port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXF7
1245
MUXF7
-- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF7 should be placed -- in architecture after the begin keyword MUXF7_INSTANCE_NAME : MUXF7 port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

1246
MUXF7_D
MUXF7_D
MUXF7_D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
I0 I1 S
LO O
X8432
MUXF7_D provides a multiplexer function in one full Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X CLB for creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables. Local outputs (LO) of MUXF6 are connected to the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output is used to connect to other inputs within the same CLB slice. See also MUXF7 and MUXF7_L.
Inputs S 0 1 X X I0 I0 X 0 1 I1 X I1 0 1 O I0 I1 0 1
Outputs LO I0 I1 0 1
Usage

-- Component Declaration for MUXF7_D should be placed -- after architecture statement but before begin keyword component MUXF7_D port (LO : out STD_ULOGIC; O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component;
1247
MUXF7_D
-- Component Attribute specification for MUXF7_D -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF7_D should be placed -- in architecture after the begin keyword MUXF7_D_INSTANCE_NAME : MUXF7_D port map (LO => user_LO, O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

1248
MUXF7_L
MUXF7_L
MUXF7_L Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I0 I1 S
X8433
LO
MUXF7_L provides a multiplexer function in a full Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X CLB for creating a function-of-7 lookup table or a 16-to-1 multiplexer in combination with the associated lookup tables. Local outputs (LO) of MUXF6 are connected to the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1. The LO output is used to connect to other inputs within the same CLB slice. See also MUXF7 and MUXF7_D.
Output LO I0 I1 0 1
Usage

-- Component Declaration for MUXF7_L should be placed -- after architecture statement but before begin keyword component MUXF7_L port (LO : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXF7_L
1249
MUXF7_L
-- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for MUXF7_L should be placed -- in architecture after the begin keyword MUXF7_L_INSTANCE_NAME : MUXF7_L port map (LO => user_LO, I0 => user_I0, I1 => user_I1, S => user_S);

1250
MUXF8
MUXF8
MUXF8 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
I0 I1 S
X8434
MUXF8 provides a multiplexer function in two full Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X CLBs for creating a function-of-8 lookup table or a 32-to-1 multiplexer in combination with the associated lookup tables, MUXF5s, MUXF6s, and MUXF7s. Local outputs (LO) of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1.
Outputs O I0 I1 0 1
Usage

-- Component Declaration for MUXF8 should be placed -- after architecture statement but before begin keyword component MUXF8 port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for MUXF8 -- should be placed after architecture declaration but -- before the begin keyword
1251
MUXF8
-- Attributes should be placed here -- Component Instantiation for MUXF8 should be placed -- in architecture after the begin keyword MUXF8_INSTANCE_NAME : MUXF8 port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

1252
NAND2-9
NAND2-9
2- to 9-Input NAND Gates with Inverted and Non-Inverted Inputs
NAND2, NAND3, NAND4, NAND5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive Primitive
NAND2B1, NAND2B2, NAND3B1, NAND3B2, NAND3B3, NAND4B1, NAND4B2, NAND4B3, NAND4B4, NAND5B1, NAND5B2, NAND5B3, NAND5B4, NAND5B5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II NAND6, NAND7, NAND8, NAND9 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro
1253
NAND2-9
I1 I0
I2 I1 I0
I3 I2 I1 I0
I4 I3 I2 I1 I0 NAND4 NAND5
I5 I4 I3 I2 I1 I0 NAND6 I6
NAND2
NAND3
I1 I0
I2 I1 I0
I3 I2 I1 I0
I4 I3 I2 I1 I0
I5 I4 I3 I2 I1 I0
NAND2B1
NAND3B1
NAND4B1
NAND5B1 I7 I6 I5 I4 I3 I2 I1 I0
NAND7
I1 I0
I2 I1 I0
I3 I2 I1 I0
I4 I3 I2 I1 I0
NAND2B2
NAND3B2
NAND4B2
NAND5B2 IA I7 I6 I5 I4 I3 I2 I1 I0
NAND8
I2 I1 I0
I3 I2 I1 I0
I4 I3 I2 I1 I0
NAND3B3
NAND4B3 I4 I3 I2 I1 I0 NAND4B4
NAND5B3
NAND9
I3 I2 I1 I0
NAND5B4
I4 I3 I2 I1 I0 NAND5B5 X9429
NAND Gate Representations NAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NAND gates of six to nine inputs are available with only noninverting inputs. To invert inputs, use external inverters. Since each input uses a CLB resource, replace gates with unused inputs with gates having the necessary number of inputs. See NAND12, 16 for information on additional NAND functions.
1254
NAND2-9
FMAP
I4 I3 S1 S0 I7 I6 I5 I4 AND4 I7 O NAND2 I3 I2 I1 I0 AND4 S0 I6 I5 I4 S1 I2 I1 RLOC=R0C0.S0 O O
FMAP
FMAP
NAND8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4 I3 S1 S0 I2 I1 RLOC=X0Y1 I7 I6 I5 I4 AND4 I7 I6 I5 O NAND2 I3 I2 I1 I0 AND4 S0 I3 I2 I1 I0 I4 I3 I2 I1 RLOC=X0Y0 X9349 O S0 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1 S1 O O
FMAP
FMAP
NAND8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
NAND2 through NAND5 are primitives that can be inferred or instantiated. NAND6 through NAND9 are macros which can be inferred.
1255
NAND2-9
VHDL Inference Code

architecture Behavioral of nand6 is begin process (I0, I1, I2, I3, I4, I5) begin O <= not (I0 and I1 and I2 and I3 and I4 and I5); end process; end Behavioral;

Following is a Verilog example of how to infer a NAND6 element:
always @(I0 or I1 or I2 or I3 or I4 or I5) begin O <= !(I0 && I1 && I2 && I3 && I4 && I5); end
VHDL Instantiation Template for NAND5

Following is the VHDL code for NAND5. To instantiate NAND2, remove I2, I3, and I4. To instantiate NAND3, remove I3 and I4, For NAND4, remove I4. NAND2B1, and NAND2B2 have the same code as NAND2. NAND3B1, 3B2, and 3B3 have the same code as NAND3 and so forth.
-- Component Declaration for NAND5 should be placed -- after architecture statement but before begin keyword component NAND5 port (O : out I0 : in I1 : in I2 : in I3 : in I4 : in end component; -----
STD_ULOGIC; STD_ULOGIC; STD_ULOGIC; STD_ULOGIC; STD_ULOGIC; STD_ULOGIC);
Component Attribute specification for NAND5 should be placed after architecture declaration but before the begin keyword Attributes should be placed here
-- Component Instantiation for NAND5 should be placed -- in architecture after the begin keyword NAND5_INSTANCE_NAME : NAND5 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4);
1256
NAND2-9
Verilog Instantiation Template for NAND5

NAND5 NAND5_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4));

None
1257
NAND2-9
1258
NAND12, 16
NAND12, 16
12- and 16-Input NAND Gates with Non-Inverted Inputs
NAND12, NAND16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 NAND12 X9430 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 NAND16 X9431
The NAND function is performed in the Configurable Logic Block (CLB) function generators for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X. The 12- and 16-input NAND functions are available only with non-inverting inputs. To invert some or all inputs, use external inverters. See NAND2-9 for more information on NAND functions.
FMAP
S2 S1 S0 I4 I3 I2 I1 RLOC=R0C0.S0 I11 I10 I9 I8 AND4 I7 I6 I5 I4 AND4 I3 I2 I1 I0 AND4 S0 O O
FMAP
S2 I11 I10 I9 I8 I4 I3 I2 I1 RLOC=R0C0.S0 O S2
S1 NAND3
FMAP
FMAP
1259
NAND12, 16
FMAP
I4 I11 I10 I9 I8 AND4 RLOC=X0Y1 S2 S2 S1 S0 I3 I2 I1 O O
FMAP
I7 I6 I5 I4 AND4 NAND3 RLOC=X0Y1 S1 O I11 I10 I9 I8 I4 I3 I2 I1 O S2
FMAP
I3 I2 I1 I0 AND4 S0 I7 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1
FMAP
1260
NAND12, 16
FMAP I15 I14 I13 I12 AND4 RLOC=R0C0.S1 C2 FMAP I11 I10 I9 I8 AND4 RLOC=R0C0.S1 C1 FMAP I7 I6 I5 I4 AND4 C0 RLOC=R1C0.S1 S1 LO MUXCY_L S 0 DI 1 CI I4 RLOC=R1C0.S1 I7 I6 I5 I4 I3 O I2 I1 S1 S2 LO MUXCY_L S 0 DI 1 CI RLOC=R0C0.S1 I11 I10 I9 I8 I4 I3 O I2 I1 S2 S3 VCC O MUXCY S 0 DI 1 CI I12 RLOC=R0C0.S1 I15 I14 I13 I4 I3 O I2 I1 S3
FMAP I3 I2 I1 I0 AND4 S0 LO MUXCY_L S 0 DI 1 CI RLOC=R1C0.S1 I3 I2 I1 I0 I4 I3 O I2 I1 RLOC=R1C0.S1 S0
CIN
X8709 GND
1261
NAND12, 16
FMAP
I15 I15 I14 S3 I13 VCC I12 AND4 C2 S DI O MUXCY 0 1 CI I12 RLOC=X0Y1 I13 I14 I4 I3 O I2 I1 RLOC=X0Y1 S3
FMAP
I11 I11 I10 S2 I9 I8 AND4 C1 S LO MUXCY_L 0 DI 1 CI I8 RLOC=X0Y1 I9 I10 I4 I3 O I2 I1 RLOC=X0Y1 S2
FMAP
I7 I7 I6 S1 I5 I4 AND4 C0 S LO MUXCY_L 0 DI 1 CI I4 RLOC=X0Y0 I5 I6 I4 I3 O I2 I1 RLOC=X0Y0 S1
FMAP
I3 I2 S0 I1 I0 AND4 RLOC=X0Y0 CIN S I3 LO MUXCY_L 0 DI 1 CI RLOC=X0Y0 I2 I1 I0 I4 I3 O I2 I1 S0
GND
X9351
Usage
For HDL, NAND12 and NAND16 are macros that are inferred. See NAND2-9 for more information about inferring NAND gates.

None
1262
NOR2-9
NOR2-9
2- to 9-Input NOR Gates with Inverted and Non-Inverted Inputs
NOR2, NOR3, NOR4, NOR5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive Primitive
NOR2B1, NOR2B2, NOR3B1, NOR3B2, NOR3B3, NOR4B1, NOR4B2, NOR4B3, NOR4B4, NOR5B1, NOR5B2, NOR5B3, NOR5B4, NOR5B5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II NOR6, NOR7 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II NOR8, NOR9 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro
1263
NOR2-9
I5 I3 I1 0 I0 I2 I1 I0 0 I1 I0 I2 0 I2 I1 I0 0 I2 I1 I0 NOR2 NOR3 I3 I2 I1 0 I0 I1 I0 0 I1 I0 I2 0 I2 I1 I0 NOR5B1 0 I6 I5 I4 I3 I3 I2 I1 0 I0 I1 I0 0 I1 I1 I0 I0 I2 0 I4 I3 I2 0 I2 I1 I0 NOR7 0 NOR4 I4 I3 NOR5 NOR6 I4 I3 I4 I3 0
NOR2B1
NOR3B1
NOR4B1
NOR2B2
NOR3B2
NOR4B2
NOR5B2 I7 I4 I3 I6 I5 0 I4 0 I3 I2 I1 I0
I3 I2 I1 I0 0 I2 0 I1 I0
I2 I1 I0
NOR3B3
NOR4B3
NOR5B3
NOR8
I4 I3 I2 I1 I0 0 I3 I2 I1 I0 NOR4B4 I4 I3 I2 I1 I0 NOR5B5 X9432 0 NOR5B4 0 IA I7 I6 I5 I4 I3 I2 I1 I0 NOR9 0
NOR Gate Representations NOR gates of up to five inputs are available in any combination of inverting and noninverting inputs. NOR gates of six to nine inputs are available with only noninverting inputs. To invert some or all inputs, use external inverters. Since each input uses a CLB resource, replace gates with unused inputs with gates having the necessary number of inputs. See NOR12, 16 for information on additional NOR functions.
1264
NOR2-9
FMAP
I4 I3 S1 S0 I7 I6 I5 I4 OR4 O NOR2 I3 I2 I1 I0 OR4 S0 S1 I2 I1 RLOC=R0C0.S0 O O
FMAP
FMAP
NOR8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4 I7 I6 I5 I4 OR4 RLOC=X0Y1 O S1 S1 S0 I3 I2 I1 O O
FMAP
NOR2 I3 I2 I1 I0 OR4 RLOC=X0Y0 S0 I7 I6 I5 I4 I4 I3 I2 I1 O S1
FMAP
NOR8 Implementation Spartan-3, Virtex-II, Virtex-II Pro , Virtex-II Pro X
Usage
NOR2 through NOR5 are primitives that can be inferred or instantiated. NOR6 through NOR9 are macros which can be inferred.
1265
NOR2-9
VHDL Inference Code

architecture Behavioral of nor6 is begin process (I0, I1, I2, I3, I4, I5) begin O <= not (I0 or I1 or I2 or I3 or I4 or I5); end process; end Behavioral;
Verilog Inference Code (NOR6)

always @(I0 or I1 or I2 or I3 or I4 or I5) begin O <= !(I0 || I1 || I2 || I3 || I4 || I5); end
VHDL Instantiation Template for NOR5

Following is the VHDL code for NOR5. To instantiate NOR2, remove I2, I3, and I4. To instantiate NOR3, remove I3 and I4, For NOR4, remove I4. NOR2B1, and NOR2B2 have the same code as NOR2. NOR3B1, 3B2, and 3B3 have the same code as NOR3 and so forth.
-- Component Declaration for NOR5 should be placed -- after architecture statement but before begin keyword component NOR5 port (O : out I0 : in I1 : in I2 : in I3 : in I4 : in end component;
-- Component Attribute specification for NOR5 -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for NOR5 should be placed -- in architecture after the begin keyword NOR5_INSTANCE_NAME : NOR5 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4);
1266
NOR2-9
Verilog Instantiation Template for NOR5

NOR5 NOR5_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4));

None
1267
NOR2-9
1268
NOR2-9
1269
NOR2-9
1270
NOR12, 16
NOR12, 16
12- and 16-Input NOR Gates with Non-Inverted Inputs
NOR12, NOR16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 NOR12 X9433
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 NOR16 X9434
The 12- and 16-input NOR functions are available only with non-inverting inputs. To invert some or all inputs, use external inverters. See NOR2-9 for more information on NOR functions.
1271
NOR12, 16
FMAP I15 I14 I13 I12 NOR4 RLOC=R0C0.S1 C2 FMAP I11 I10 I9 I8 NOR4 C1 FMAP I7 I6 I5 I4 NOR4 C0 RLOC=R1C0.S1 S1 LO MUXCY_L S 0 DI 1 CI I4 RLOC=R1C0.S1 I7 I6 I5 I4 I3 O I2 I1 S1 S2 LO MUXCY_L S 0 DI 1 CI RLOC=R0C0.S1 I11 I10 I9 I8 I4 I3 O I2 I1 RLOC=R0C0.S1 S2 S3 S 0 DI 1 CI I12 O MUXCY RLOC=R0C0.S1 I15 I14 I13 I4 I3 O I2 I1 S3
FMAP I3 I2 I1 I0 NOR4 RLOC=R1C0.S1 DI S0 LO MUXCY_L S 0 1 CI RLOC=R1C0.S1 I3 I2 I1 I0 I4 I3 O I2 I1 S0
CIN GND VCC
X8707
NOR16 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1272
NOR12, 16
FMAP
I15 I14 S3 I13 I12 NOR4 C2 RLOC=X0Y1 S O MUXCY 0 1 DI CI RLOC=X0Y1 I15 I14 I13 I12 I4 I3 O I2 I1 S3
FMAP
I11 I10 S2 I9 I8 NOR4 C1 RLOC=X0Y1 S LO MUXCY_L 0 1 DI CI RLOC=X0Y1 I11 I10 I9 I8 I4 I3 O I2 I1 S2
FMAP
I7 I6 S1 I5 I4 NOR4 C0 RLOC=X0Y0 S LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I7 I6 I5 I4 I4 I3 O I2 I1 S1
FMAP
I3 I2 S0 I1 I0 NOR4 RLOC=X0Y0 CIN GND VCC X9353 S LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I3 I2 I1 I0 I4 I3 O I2 I1 S0
NOR16 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, NOR12 and NOR16 are macros that can be inferred. See NOR2-9 for more information about inferring NOR gates.
1273
NOR12, 16
1274
OBUF, 4, 8, 16
OBUF, 4, 8, 16
Single- and Multiple-Output Buffers
OBUF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II OBUF4, OBUF8, OBUF16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Primitive Primitive
OBUF
I O X9445
OBUF, OBUF4, OBUF8, and OBUF16 are single and multiple output buffers. An OBUF isolates the internal circuit and provides drive current for signals leaving a chip. OBUFs exist in input/output blocks (IOB). The output (O) of an OBUF is connected to an OPAD or an IOPAD. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, if a high impedance (Z) signal from an on-chip 3-state buffer (like BUFE) is applied to the input of an OBUF, it is propagated to the CPLD device output pin. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, see OBUF_selectIO for information on OBUF variants with selectable I/O interfaces. The I/O interface standard used by OBUF, 4, 8, and 16 is LVTTL. Also, Virtex, Virtex-E, Spartan-II, and Spartan-IIE OBUF, 4, 8, and 16 have selectable drive and slew rates using the DRIVE and SLOW or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
O [7:0]
X9850
OBUF4
I0 I1 I2 I3 O0 O1 O2 O3 X9446
OBUF8 I [7:0]
OBUF16 I [15:0] O [15:0]

X9851
1275
OBUF, 4, 8, 16
O[7:0] IO I1 I2 I3 I4 I5 I6 I7 I[7:0] OBUF OBUF OBUF OBUF OBUF OBUF OBUF OBUF X7654 O0 O1 O2 O3 O4 O5 O6 O7
OBUF8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E
O[7:0]
I0 OBUF I1 OBUF I2 OBUF I3 OBUF I4 OBUF I5 OBUF I6 OBUF I7 OBUF I[7:0]
O0 O1 O2 O3 O4 O5 O6 O7
X9840
OBUF8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
OBUFs are typically inferred for all top level input ports, but they can also be instantiated if necessary.

-- Component Declaration for OBUF should be placed -- after architecture statement but before begin keyword component OBUF port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for OBUF -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OBUF should be placed
1276
OBUF, 4, 8, 16
-- in architecture after the begin keyword OBUF_INSTANCE_NAME : OBUF port map (O => user_O, I => user_I);

OBUF_instance_name (.O (user_O), .I (user_I));

DRIVE IOSTANDARD IOBDELAY SLEW
1277
OBUF, 4, 8, 16
1278
OBUF_selectIO
OBUF_selectIO
Single Output Buffer with Selectable I/O Interface
OBUF_selectIO Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
O X9444
For Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II, and SpartanIIE, OBUF and its selectIO variants (listed in the "Components" column in the table below) are single output buffers whose I/O interface corresponds to a specific I/O standard. The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. The S, F, and 2, 4, 6, 8, 12, 16, 24 extensions specify the slew rate (SLOW or FAST) and the drive power (2, 4, 6, 8, 12, 16, 24 mA) for the LVTTL standard variants. For example, OBUF_F_12 is a single output buffer that uses the LVTTL I/O-signaling standard with a FAST slew and 12mA of drive power. You can attach an IOSTANDARD attribute to an OBUF instance instead of using an OBUF_selectIO component. Check marks () in the "Spartan-II, Virtex" and "Spartan-IIE, Virtex-E" columns indicate the components and IOSTANDARD attribute values available for those architectures. For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, an OBUF that uses the LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, or LVCMOS33 signaling standards has selectable drive and slew rates using the DRIVE and SLOW or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew. For Virtex, Virtex-E, Spartan-II, and Spartan-IIE, an OBUF that uses the LVTTL signaling standard has selectable drive and slew rates using the DRIVE and SLOW or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew. An OBUF isolates the internal circuit and provides drive current for signals leaving a chip. OBUFs exist in input/output blocks (IOB). The output (O) of an OBUF is connected to an OPAD or an IOPAD. The hardware implementation of the I/O standard requires that you follow a set of usage rules for the SelectIO buffer components. See the SelectIO Usage Rules under the IBUF_selectIO section for information on using these components.
1279
OBUF_selectIO
Spartan-II, Spartan-IIE, Virtex, and Virtex-E OBUF_selectIO Components and IOSTANDARD Attributes
Component OBUF OBUF_S_2 OBUF_S_4 OBUF_S_6 OBUF_S_8 OBUF_S_12 OBUF_S_16 OBUF_S_24 OBUF_F_2 OBUF_F_4 OBUF_F_6 OBUF_F_8 OBUF_F_12 OBUF_F_16 OBUF_F_24 OBUF_AGP OBUF_CTT OBUF_GTL OBUF_GTLP OBUF_HSTL_I OBUF_HSTL_III OBUF_HSTL_IV OBUF_LVCMOS2 OBUF_LVCMOS18 OBUF_LVDS OBUF_LVPECL OBUF_PCI33_3 OBUF_PCI33_5 OBUF_PCI66_3 OBUF_PCIx66_3 OBUF_SSTL2_I OBUF_SSTL2_II OBUF_SSTL3_I OBUF_SSTL3_II
Not b
Spartan-II, Virtex
IOSTANDARD (Attribute Value) (default is LVTTL) b LVTTL b LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL AGP CTT GTL GTLP HSTL_I HSTL_III HSTL_IV LVCMOS2 LVCMOS18 LVDS LVPECL PCI33_3 PCI33_5 PCI66_3 PCIx66_3 SSTL2_I SSTL2_II SSTL3_I SSTL3_II
b b b
Output VCCO 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 No No 1.5 1.5 1.5 2.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 2.5 2.5 3.3 3.3
LVTTL b
b b b
LVTTL b
b b b
LVTTL b
b
supported for Virtex-E. The LVTTL attribute also requires a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE attribute descriptions in the Xilinx Constraints Guide for valid values for each architecture.
1280
OBUF_selectIO
The Virtex-II, Virtex-II Pro, and Virtex-II Pro X library includes some OBUF_selectIO components for compatibility with older, existing designs and other architectures. For new Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs, however, the recommended method for using OBUF SelectIO buffers is to attach an IOSTANDARD attribute to an OBUF component. For example, attach IOSTANDARD=GTLP to an OBUF instead of using the OBUF_GTLP component for new Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs. The IOSTANDARD attributes that can be attached to an OBUF component are listed in the "IOSTANDARD (Attribute Value)" column. Attach an IOSTANDARD attribute to an OBUF and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the output for the I/O standard associated with that value. The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE attribute descriptions in the Xilinx Constraints Guide. Virtex-II, Virtex-II Pro, Virtex-II Pro X OBUF_selectIO IOSTANDARD Attributes
Architectures
IOSTANDARD AGP GTL GTL_DCI GTLP GTLP_DCI HSTL_I HSTL_I_18 HSTL_I_DCI HSTL_I_DCI_18 HSTL_II HSTL_II_18 HSTL_II_DCI HSTL_II_DCI_18 HSTL_III HSTL_III_18 HSTL_III_DCI HSTL_III_DCI_18 HSTL_IV HSTL_IV_18 HSTL_IV_DCI HSTL_IV_DCI_18 LVCMOS12a LVCMOS15a LVCMOS18a LVCMOS25
a
Attribute Values
Drive No No No No No No No No No No No No No No No No No No No No No 2, 4, 6, 8 Slew No No No No No No No No No No No No No No No No No No No No No Fast/Slow Fast/Slow Fast/Slow Fast/Slow Fast/Slow No No Termination Type Output None None Single None Single None None None None None None Split Split None None None None None None Single Single None None None None None Driver Driver VREF Input * 1.32 .8 .8 1.0 1.0 .75 .90 .75 .9 .75 .9 .75 .9 .9 1.1 .9 1.1 .9 1.1 .9 1.1 No No No No No No No Output VCCO 3.3 No 1.2 No 1.5 1.5 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.2 1.5 1.8 2.5 3.3 1.5 1.8
Spartan-3
Virtex-II
Virtex-II Pro, Virtex-II Pro X
2, 4, 6, 8, 12, 16 2, 4, 6, 8, 12, 16 2, 4, 6, 8, 12, 16, 24 2, 4, 6, 8, 12, 16, 24 No No
LVCMOS33a LVDCI_15 LVDCI_18
1281
OBUF_selectIO
Virtex-II, Virtex-II Pro, Virtex-II Pro X OBUF_selectIO IOSTANDARD Attributes

Architectures
IOSTANDARD LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25 LVDCI_DV2_33 LVTTLa PCI33_3 PCI66_3 PCIX SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II_DCI SSTL2_I SSTL2_I_DCI SSTL2_II SSTL2_II_DCI SSTL3_I SSTL3_I_DCI SSTL3_II SSTL3_II_DCI Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Drive No No No No No No 2, 4, 6, 8, 12, 16, 24 No No No No No No No No No No No No No No No
Attribute Values
Slew No No No No No No Fast/Slow No No No No No No No No No No No No No No No Termination Type Output Driver Driver Driver Driver Driver Driver None None None None None None None Split None None None Split None None None Split VREF Input * No No No No No No No No No No .9 .9 .9 .9 1.25 1.25 1.25 1.25 1.5 1.5 1.5 1.5 Output VCCO 2.5 3.3 1.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 1.8 1.8 1.8 1.8 2.5 2.5 2.5 2.5 3.3 3.3 3.3 3.3
Usage
The recommended usage for OBUF_selectIO is to allow the OBUFs be inferred and apply the IOSTANDARD constraint to the input in either the UCF or in the HDL code. OBUF_selectIO can also be instantiated if necessary..

-- Component Declaration for OBUF_selectIO should be placed -- after architecture statement but before begin keyword component OBUF_selectIO port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for OBUF_selectIO -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OBUF_selectIO should be placed
1282
OBUF_selectIO
-- in architecture after the begin keyword OBUF_selectIO_INSTANCE_NAME : OBUF_selectIO port map (O => user_O, I => user_I);

OBUF_selectIO instance_name (.O (user_O), .I (user_I));

DRIVE IOBDELAY SLEW IOSTANDARD
1283
OBUF_selectIO
1284
OBUFDS
OBUFDS
Differential Signaling Output Buffer with Selectable I/O Interface
OBUFDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
O OB
OBUFDS
X9259
OBUFDS is a single output buffer that supports low-voltage, differential signaling (1.8v CMOS). OBUFDS isolates the internal circuit and provides drive current for signals leaving the chip. Its output is represented as two distinct ports (O and OB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).
Inputs I 0 1 O 0 1 Outputs OB 1 0
The IOSTANDARD attribute values listed in the following table can be applied to an OBUFDS component to provide SelectIO interface capability. See the Xilinx Constraints Guide for information using these attributes.
Attach an IOSTANDARD attribute to an OBUFDS and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the output for the I/O standard associated with that value. Architectures IOSTANDARD BLVDS_25 LDT_25 LVDS_25 (default) LVDS_33 LVDSEXT_25 LVDSEXT_33 LVPECL_25 LVPECL_33 ULVDS_25 Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Termination Type Output None None None None None None None None None Attribute Values VREF Input * No No No No No No No No No Output VCCO 2.5 2.5 2.5 3.3 2.5 3.3 2.5 3.3 2.5
1285
OBUFDS
Architectures IOSTANDARD Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Termination Type Output
Attribute Values VREF Input * Output VCCO
Usage
For HDL, this design element should be instantiated rather than inferred.

-- Component Declaration for OBUFDS should be placed -- after architecture statement but before begin keyword component OBUFDS port (O : out STD_ULOGIC; OB : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for OBUFDS -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OBUFDS should be placed -- in architecture after the begin keyword OBUFDS_INSTANCE_NAME : OBUFDS port map (O => user_O, OB => user_OB, I => user_I);

OBUFDS instance_name (.O (user_O), .OB (user_OB), .I (user_I));

IOSTANDARD, IOBDELAY
1286
OBUFE, 4, 8, 16
OBUFE, 4, 8, 16
3-State Output Buffers with Active-High Output Enable
OBUFE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro Primitive Primitive Primitive
OBUFE4, OBUFE8, OBUFE16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro Macro Macro Macro
OBUFE
E I O X9447
OBUFE4
E I0 I1 I2 I3 O0 O1 O2 O3 X9448
OBUFE, OBUFE4, OBUFE8, and OBUFE16 are 3-state buffers with inputs I, I3 I0, I7 I0, and I15-I0, respectively; outputs O, O3 O0, O7 O0, and O15-O0, respectively; and active-High output enable (E). When E is High, data on the inputs of the buffers is transferred to the corresponding outputs. When E is Low, the output is High impedance (off or Z state). An OBUFE isolates the internal circuit and provides drive current for signals leaving a chip. An OBUFE output is connected to an OPAD or an IOPAD. An OBUFE input is connected to the internal circuit.
Inputs E 0 1 1 I X 1 0
T INV OBUFT X7860 T O
Outputs O Z 1 0
OBUFE8 E I [7:0] O [7:0]

X9848
E I
OBUFE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1287
OBUFE, 4, 8, 16
OBUFE16 E I [15:0] O [15:0]
LVTTL
SLOW 12
E
X9849
T INV
T O OBUFT X9355
OBUFE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

O[7:0] E IO E I1 E I2 E I3 E I4 E I5 E I6 E I7 I[7:0] E OBUFE X7649 OBUFE O7 OBUFE O6 OBUFE O5 OBUFE O4 OBUFE O3 OBUFE O2 OBUFE O1 O0
OBUFE8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage

-- Component Declaration for OBUFE should be placed -- after architecture statement but before begin keyword component OBUFE port (O : out STD_ULOGIC; E : in STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for OBUFE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OBUFE should be placed -- in architecture after the begin keyword OBUFE_INSTANCE_NAME : OBUFE
1288
OBUFE, 4, 8, 16
port map (O => user_O, E => user_E, I => user_I);

OBUFE_instance_name (.O (user_O), .E (user_E), .I (user_I));

IOBDELAY
1289
OBUFE, 4, 8, 16
1290
OBUFT, 4, 8, 16
OBUFT, 4, 8, 16
Single and Multiple 3-State Output Buffers with Active-Low Output Enable
OBUFT Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive
OBUFT4, OBUFT8, OBUFT16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
OBUFT
T I O X9449
OBUFT4
T I0 I1 I2 I3 O0 O1 O2 O3 X9450
OBUFT, OBUFT4, OBUFT8, and OBUFT16 are single and multiple 3-state output buffers with inputs I, I3 I0, I7 I0, I15 I0, outputs O, O3 O0, O7 O0, O15 O0, and active-Low output enables (T). When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, the output is high impedance (off or Z state). OBUFTs isolate the internal circuit and provide extra drive current for signals leaving a chip. An OBUFT output is connected to an OPAD or an IOPAD. For Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II, Spartan-IIE, and Spartan-3, see OBUFT_selectIO for information on OBUFT variants with selectable I/O interfaces. OBUFT, 4, 8, and 16 use the LVTTL standard. Also, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II, Spartan-IIE, and Spartan-3 OBUFT, 4, 8, and 16 have selectable drive and slew rates using the DRIVE and SLOW or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
Inputs
OBUFT16 T I[15:0] O[15:0]
Outputs I X 1 0 O Z 1 0
T 1 0 0
X3817
1291
OBUFT, 4, 8, 16
OBUFT8 T I O[7:0]
I1 IO
O[7:0] T O0 T OBUFT O1 T I2 T I3 T I4 T I5 T I6 T I7 I[7:0] T OBUFT OBUFT O7 OBUFT O6 OBUFT O5 OBUFT O4 OBUFT O3 OBUFT O2
X3805
X7651
OBUFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E
O[7:0] T I0 T I1 T I2 T I3 T I4 T I5 T I6 T I7 OBUFT I[7:0] T
X9838
O0 OBUFT O1 OBUFT O2 OBUFT O3 OBUFT O4 OBUFT O5 OBUFT O6 OBUFT O7
OBUFT8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, OBUFT is instantiated rather than inferred.
1292
OBUFT, 4, 8, 16

-- Component Declaration for OBUFT should be placed -- after architecture statement but before begin keyword component OBUFT port (O : out STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for OBUFT -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OBUFT should be placed -- in architecture after the begin keyword OBUFT_INSTANCE_NAME : OBUFT port map (O => user_O, I => user_I, T => user_T);

OBUFT instance_name (.O (user_O), .I (user_I), .T (user_T));

DRIVE IOSTANDARD IOBDELAY SLEW
1293
OBUFT, 4, 8, 16
1294
OBUFT_selectIO
OBUFT_selectIO
Single 3-State Output Buffer with Active-Low Output Enable and Selectable I/O Interface
OBUFT_selectIO Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
T I O X9451
For Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, Spartan-II, Spartan-IIE, and Spartan-3, OBUFT and its selectIO variants (listed in the "Component" column in the table below) are single 3-state output buffers with active-Low output Enable whose I/O interface corresponds to a specific I/O standard. The name extensions (LVCMOS2, PCI33_3, PCI33_5, etc.) specify the standard. The S, F, and 2, 4, 6, 8, 12, 16, 24 extensions specify the slew rate (SLOW or FAST) and the drive power (2, 4, 6, 8, 12, 16, 24 mA) for the LVTTL standard. For example, OBUFT_S_4 is a 3-state output buffer with active-Low output enable that uses the LVTTL I/O signaling standard with a SLOW slew and 4mA of drive power. You can attach an IOSTANDARD attribute to an OBUFT instance instead of using an OBUFT_selectIO component. Check marks () in the "Spartan-II, Virtex," and "Spartan-IIE, Virtex-E" columns indicate the components and IOSTANDARD attribute values available for each architecture. The hardware implementation of the I/O standards requires that you follow a set of usage rules for the SelectIO buffers. See SelectIO Usage Rules under the IBUF_selectIO section for information on using these components and IOSTANDARD attributes. Spartan-II, Spartan-IIE, Virtex, and Virtex-E OBUFT_selectIO Components and IOSTANDARD Attributes
Component Spartan-II, Virtex Spartan-IIE, Virtex-E IOSTANDARD (Attribute Value) defaults to LVTTL LVTTL
b
Output VCCO 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
OBUFT OBUFT_S_2 OBUFT_S_4 OBUFT_S_6 OBUFT_S_8 OBUFT_S_12 OBUFT_S_16 OBUFT_S_24 OBUFT_F_2
LVTTL b LVTTL b LVTTL LVTTL LVTTL LVTTL

b b b
LVTTL b
b
1295
OBUFT_selectIO
Spartan-II, Spartan-IIE, Virtex, and Virtex-E OBUFT_selectIO Components and IOSTANDARD Attributes
Component OBUFT_F_4 OBUFT_F_6 OBUFT_F_8 OBUFT_F_12 OBUFT_F_16 OBUFT_F_24 OBUFT_AGP OBUFT_CTT OBUFT_GTL OBUFT_GTLP OBUFT_HSTL_I OBUFT_HSTL_III OBUFT_HSTL_IV OBUFT_LVCMOS2 OBUFT_LVCMOS18 OBUFT_LVDS OBUFT_LVPECL OBUFT_PCI33_3 OBUFT_PCI33_5 OBUFT_PCI66_3 OBUFT_PCIX66_3 OBUFT_SSTL2_I OBUFT_SSTL2_II OBUFT_SSTL3_I OBUFT_SSTL3_II
Spartan-II, Virtex
IOSTANDARD (Attribute Value) LVTTL b LVTTL b LVTTL LVTTL LVTTL AGP CTT GTL GTLP HSTL_I HSTL_III HSTL_IV LVCMOS2 LVCMOS18 LVDS LVPECL PCI33_3 PCI33_5 PCI66_3 PCIX66_3 SSTL2_I SSTL2_II SSTL3_I SSTL3_II
b b b b
Output VCCO 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 No No 1.5 1.5 1.5 2.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3 2.5 2.5 3.3 3.3
LVTTL b
Not supported for Virtex-E. b The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE attribute descriptions in the Xilinx Constraints Guide for valid values for each architecture.
The Virtex-II, Virtex-II Pro, and Virtex-II Pro X library includes some OBUFT_selectIO components for compatibility with older, existing designs and other architectures. For new Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs, however, the recommended method for using OBUFT SelectIO buffers is to attach an IOSTANDARD attribute to an OBUFT component. For example, attach IOSTANDARD=GTLP to an OBUFT instead of using the OBUFT_GTLP component for new Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X designs. The IOSTANDARD attributes that can be attached to an OBUFT component are listed in the "IOSTANDARD (Attribute Value)" column in the following table. See SelectIO Usage Rules for information on using these IOSTANDARD attributes.
1296
OBUFT_selectIO
Attach an IOSTANDARD attribute to an OBUFT and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the output for the I/O standard associated with that value.
The LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 attributes also require a slew value (FAST or SLOW) and DRIVE value. See the FAST, SLOW, and DRIVE attribute descriptions in the Xilinx Constraints Guide.
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X OBUFT_selectIO IOSTANDARD Attributes

Architectures
IOSTANDARD AGP GTL GTL_DCI GTLP GTLP_DCI HSTL_I HSTL_I_18 HSTL_I_DCI HSTL_I_DCI_18 HSTL_II_18 HSTL_II_DCI_18 HSTL_III HSTL_III_18 HSTL_III_DCI HSTL_III_DCI_18 HSTL_IV HSTL_IV_18 HSTL_IV_DCI HSTL_IV_DCI_18 LVCMOS12a LVCMOS15a LVCMOS18a LVCMOS25a LVCMOS33a LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 LVDCI_DV2_15 LVDCI_DV2_18 LVDCI_DV2_25 LVDCI_DV2_33 LVTTLa PCI33_3 PCI66_3 PCIX Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Drive No No No No No No No No No No No No No No No No No No No 2, 4, 6 2, 4, 6, 8, 12 2, 4, 6, 8, 12, 16 2, 4, 6, 8, 12, 16, 24 2, 4, 6, 8, 12, 16, 24 No No No No No No No No 2, 4, 6, 8, 12, 16, 24 No No No
Attribute Values
Slew No No No No No No No No No No No No No No No No No No No Fast/Slow Fast/Slow Fast/Slow Fast/Slow Fast/Slow No No No No No No No No Fast/Slow No No No Termination Type Output None None Single None Single None None None None None Split None None None None None None Single Single None None None None None Driver Driver Driver Driver Driver Driver Driver Driver None None None None VREF Input * 1.32 .8 .8 1.0 1.0 .75 .90 .75 .9 .9 .9 .9 1.1 .9 1.1 .9 1.1 .9 1.1 No No No No No No No No No No No No No No No No No Output VCCO 3.3 No 1.2 No 1.5 1.5 1.8 1.5 1.8 1.8 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.5 1.8 1.2 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 1.5 1.8 2.5 3.3 3.3 3.3 3.3 3.3
1297
OBUFT_selectIO
Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X OBUFT_selectIO IOSTANDARD Attributes

Architectures
IOSTANDARD SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II_DCI SSTL2_I SSTL2_I_DCI SSTL2_II SSTL2_II_DCI SSTL3_I SSTL3_I_DCI SSTL3_II SSTL3_II_DCI Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Drive No No No No No No No No No No No No
Attribute Values
Slew No No No No No No No No No No No No Termination Type Output None None None Split None None None Split None None None Split VREF Input * .9 .9 .9 .9 1.25 1.25 1.25 1.25 1.5 1.5 1.5 1.5 Output VCCO 1.8 1.8 1.8 1.8 2.5 2.5 2.5 2.5 3.3 3.3 3.3 3.3
OBUFT and its variants have selectable drive and slew rates using the DRIVE and FAST or SLOW constraints. The defaults are DRIVE=12 mA and SLOW slew. When T is Low, data on the input of the buffer is transferred to the output. When T is High, the output is high impedance (off or Z state). OBUFTs isolate the internal circuit and provide extra drive current for signals leaving a chip. An OBUFT_selectIO output is connected to an OPAD or an IOPAD.
Usage

-- Component Declaration for OBUFT_selectIO should be placed -- after architecture statement but before begin keyword component OBUFT_selectIO port (O : out STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for OBUFT_selectIO -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here -- Component Instantiation for OBUFT_selectIO should be -- placed in architecture after the begin keyword OBUFT_selectIO_INSTANCE_NAME : OBUFT_selectIO port map (O => user_O, I => user_I,
1298
OBUFT_selectIO
T => user_T);

OBUFT_selectIO instance_name (.O (user_O), .I (user_I), .T (user_T));

DRIVE, IOBDELAY, SLEW, and IOSTANDARD
1299
OBUFT_selectIO
1300
OBUFTDS
OBUFTDS
3-State Differential Signaling Output Buffer with Active Low Output Enable and Selectable I/O Interface
OBUFTDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
T I O OB
OBUFTDS is a single 3-state, differential signaling output buffer with active Low enable and a Select I/O interface. When T is Low, data on the input of the buffer is transferred to the output (O) and inverted output (OB). When T is High, both outputs are high impedance (off or Z state).
OBUFTDS
X9260
Inputs I X 0 1 T 1 0 0 O Z 0 1
Outputs OB Z 1 0
The IOSTANDARD attribute values listed in the following table can be applied to an IBUFGDS component to provide selectIO interface capability. See the Xilinx Constraints Guide for information using these attributes. The hardware implementation of the I/O standards requires that you follow a set of usage rules for the SelectIO buffer components. See the SelectIO Usage Rules under the IBUF_selectIO section for information on using these IOSTANDARD attributes.
1301
OBUFTDS
Attach an IOSTANDARD attribute to an OBUFTDS and assign the value indicated in the "IOSTANDARD (Attribute Value)" column to program the outputs for the I/O standard associated with that value.
Architectures IOSTANDARD BLVDS_25 LDT_25 LVDS_25 (default) LVDS_33 LVPECL_25 LVPECL_33 LVDSEXT_25 LVDSEXT_33 ULVDS_25 Spartan-3 Virtex-II Virtex-II Pro, Virtex-II Pro X Termination Type Output None None None None None None None None None Attribute Values VREF Input * No No No No No No No No No Output VCCO 2.5 2.5 2.5 3.3 2.5 3.3 2.5 3.3 2.5
Usage

-- Component Declaration for OBUFTDS should be placed -- after architecture statement but before begin keyword component OBUFTDS port (O : out STD_ULOGIC; OB : out STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for OBUFTDS -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OBUFTDS should be -- placed in architecture after the begin keyword OBUFTDS_INSTANCE_NAME : OBUFTDS port map (O => user_O, OB => user_OB, I => user_I, T => user_T);

OBUFTDS instance_name (.O (user_O),
1302
OBUFTDS
.OB (user_OB), .I (user_I), .T (user_T));

IOSTANDARD, IOBDELAY
1303
OBUFTDS
1304
OFD, 4, 8, 16
OFD, 4, 8, 16
Single- and Multiple-Output D Flip-Flops
OFD, OFD4, OFD8, OFD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
OFD
OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops. The outputs (for example, Q3 Q0) are connected to OPADs or IOPADs. The data on the D inputs is loaded into the flip-flops during the Low-to-High clock (C) transition and appears on the Q outputs. The flip-flops are asynchronously cleared with Low outputs when power is applied, or when global reset is active. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
X3778
D0 D1 D2 D3 C
OFD4
Q0 Q1 Q2 Q3
X3800
D[7:0]
OFD8
Q[7:0]
Inputs D C
Outputs Q 0 1
C X3812
0 1
Q[15:0]
D[15:0]
OFD16
C
VCC
X3834
D C D CE C
FDCE
Q O_OUT OBUF Q
CLR
IOB=TRUE
GND
X9766
OFD Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1305
OFD, 4, 8, 16
VCC
FDCE
D C D CE C CLR Q Q_OUT
LVTTL SLOW 12
OBUF
IOB=TRUE GND X9361
OFD Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

FD
D D Q Q_OUT OBUF C C X6378 Q
OFD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1306
OFD, 4, 8, 16
Q[7:0] OFD D0
D C Q
Q0
Q0 OFD D1
D C Q
Q1
Q1 OFD D2
D C Q
Q2
Q2 OFD D3
D C Q
Q3
Q3 OFD D4
D C Q
Q4
Q4 OFD D5
D C Q
Q5
Q5 OFD D6
D C Q
Q6
Q6 OFD D7
D C Q
Q7
D[7:0] C
Q7
X7644
OFD8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1307
OFD, 4, 8, 16
Q[7:0] FD D0
D C Q
Q0 OBUF
Q0 FD D1
D C Q
Q1 OBUF
Q1 FD D2
D C Q
Q2 OBUF
Q2 FD D3
D C Q
Q3 OBUF
Q3 FD D4
D C Q
Q4 OBUF
Q4 FD D5
D C Q
Q5 OBUF
Q5 FD D6
D C Q
Q6 OBUF
Q6 FD D7
D C Q
Q7 OBUF
D[7:0] C
Q7
X7648
OFD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1308
OFD, 4, 8, 16
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFD, you would infer an FD and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1309
OFD, 4, 8, 16
1310
OFD_1
OFD_1
Output D Flip-Flop with Inverted Clock
OFD_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
OFD_1
OFD_1 is located in an input/output block (IOB). The output (Q) of the D flip-flop is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition and appears on the Q output. The flip-flop is asynchronously cleared, output Low, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs D D C Outputs Q D
X3779
VCC
FDCE
D D CE C INV CB C CLR Q Q_OUT OBUF O
IOB=TRUE GND
X9771
OFD_1 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X
1311
OFD_1
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFD_1, you would infer an FD_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1312
OFDDRCPE
OFDDRCPE
Dual Data Rate Output D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
OFDDRCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
PRE D0 D1 CE C0 C1 CLR X9387 OFDDRCPE Q
OFDDRCPE is a dual data rate (DDR) output D flip-flop with clock enable (CE) and asynchronous preset (PRE) and clear (CLR). It consists of one output buffer and one dual data rate flip-flop (FDDRCPE). When the asynchronous PRE is High and CLR is Low, the Q output is preset High. When CLR is High, Q is set Low. Data on the D0 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C1 clock transition. The INIT attribute does not apply to OFDDRCPE components. The flip-flops are asynchronously cleared with Low outputs when power is applied.
Inputs C0 X X X X X
PRE D0 D1 CE C0 C1 CLR
Outputs D1 X X X X X D1 CLR 1 0 1 0 0 0 PRE 0 1 1 0 0 0 Q 0 1 0 No Chg D0 D1
C1 X X X X X
CE X X X 0 1 1
FDDRCPE
D0 D1 CE C0 C1 CLR INIT = 0 PRE
D0 X X X X D0 X
LVTTL SLOW 12
Q_OUT OBUF
X9362
OFDDRCPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1313
OFDDRCPE
Usage
For HDL, the OFDDRCPE design element should be instantiated rather than inferred.

-- Component Declaration for OFDDRCPE should be placed -- after architecture statement but before begin keyword component OFDDRCPE port (Q : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for OFDDRCPE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OFDDRCPE should be placed -- in architecture after the begin keyword OFDDRCPE_INSTANCE_NAME : OFDDRCPE port map (Q => user_O, C0 => user_C0, C1 => user_C1, CE => user_CE, CLR => user_CLR, D0 => user_D0, D1 => user_D1, PRE => user_PRE);

OFDDRCPE instance_name (.Q (user_O), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .CLR (user_CLR), .D0 (user_D0), .D1 (user_D1), .PRE (user_I));
1314
OFDDRRSE
OFDDRRSE
Dual Data Rate Output D Flip-Flop with Synchronous Reset and Set and Clock Enable
OFDDRRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
S D0 D1 CE C0 C1 R X9386 OFDDRRSE Q
OFDDRRSE is a dual data rate (DDR) output D flip-flop with synchronous reset (R) and set (S) and clock enable (CE). It consists of one output buffer and one dual data rate flip-flop (FDDRRSE). On a Low-to-High clock transition (C0 or C1), a High R input resets the Q output Low; a Low R input with a High S input sets Q High. When both R and S are Low and clock enable is High, data on the D0 input is loaded into the flip-flop on a Low-toHigh C0 clock transition and data on the D1 input is loaded into the flip-flop on a Low-to-High C1 clock transition. The flip-flops are asynchronously cleared with Low outputs when power is applied, or when global reset is active. The INIT attribute does not apply to OFDDRRSE components.
Inputs C0 X X X X X C1 X X X X X CE X X X X X X 0 1 1 D0 X X X X X X X D0 X D1 X X X X X X X X D1 R 1 0 1 1 0 1 0 0 0 S 0 1 1 0 1 1 0 0 0
Outputs Q 0 1 0 0 1 0 No Chg D0 D1
1315
OFDDRRSE
S D0 D1 CE C0 C1 R
FDDRRSE
D0 D1 CE C0 C1 R INIT = 0 X9363 S
LVTTL SLOW 12
Q_OUT OBUF
OFDDRRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, the OFDDRRSE design element should be instantiated rather than inferred.

-- Component Declaration for OFDDRRSE should be placed -- after architecture statement but before begin keyword component OFDDRRSE port (Q : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for OFDDRRSE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OFDDRRSE should be placed -- in architecture after the begin keyword OFDDRRSE_INSTANCE_NAME : OFDDRRSE port map (Q => user_O, C0 => user_C0, C1 => user_C1, CE => user_CE, D0 => user_D0, D1 => user_D1, R => user_R, S => user_S);
1316
OFDDRRSE

OFDDRRSE instance_name (.Q (user_Q), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .D0 (user_D0), .D1 (user_D1), .R (user_R), .S (user_S));
1317
OFDDRRSE
1318
OFDDRTCPE
OFDDRTCPE
Dual Data Rate D Flip-Flop with Active-Low 3-State Output Buffer, Clock Enable, and Asynchronous Preset and Clear
OFDDRTCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
T PRE D0 OFDDRTCPE D1 CE C0 C1 CLR X9389 O
OFDDRTCPE is a dual data rate (DDR) D flip-flop with clock enable (CE) and asynchronous preset and clear whose output is enabled by a 3-state buffer. It consists of a dual data rate flip-flop (FDDRCPE) and a 3-state output buffer (OBUFT). The data output (O) of the flip-flop is connected to the input of the output buffer (OBUFT). The output of the OBUFT is connected to an OPAD or IOPAD. When the active-Low enable input (T) is Low, output is enabled and the data on the flip-flop's Q output appears on the OBUFT's O output. When the asynchronous PRE is High and CLR is Low, the O output is preset High. When CLR is High, O is set Low. Data on the D0 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C1 clock transition. When T is High, outputs are high impedance (Off). When CE is Low and T is Low, the outputs do not change. The flip-flops are asynchronously cleared with Low outputs when power is applied. The INIT attribute does not apply to OFDDRTCPE components.
Inputs C0 X X X X X X C1 X X X X X X CE X X X X 0 1 1 D0 X X X X X D0 X D1 X X X X X X D1 CLR X 1 0 1 0 0 0 PRE X 0 1 1 0 0 0 T 1 0 0 0 0 0 0
Outputs O Z 0 1 0 No Chg D0 D1
1319
OFDDRTCPE
T PRE D0 D1 CE C0 C1 CLR
FDDRCPE
D0 D1 CE C0 C1 CLR IOB=TRUE PRE Q Q_OUT
LVTTL SLOW 12
T O OBUFT
X9364
OFDDRTCPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, the OFDDRTCPE design element should be instantiated rather than inferred.

-- Component Declaration for OFDDRTCPE should be placed -- after architecture statement but before begin keyword component OFDDRTCPE port (O : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; PRE : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for OFDDRTCPE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OFDDRTCPE should be placed -- in architecture after the begin keyword OFDDRTCPE_INSTANCE_NAME : OFDDRTCPE port map (O => user_O, C0 => user_C0, C1 => user_C1, CE => user_CE, CLR => user_CLR, D0 => user_D0, D1 => user_D1, PRE => user_PRE, T => user_T);
1320
OFDDRTCPE

OFDDRTCPE instance_name (.O (user_O), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .CLR (user_CLR), .D0 (user_D0), .D1 (user_D1), .PRE (user_PRE), .T (user_T));
1321
OFDDRTCPE
1322
OFDDRTRSE
OFDDRTRSE
Dual Data Rate D Flip-Flop with Active-Low 3-State Output Buffer, Synchronous Reset and Set, and Clock Enable
OFDDRTRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
T S D0 OFDDRTRSE D1 CE C0 C1 R O
OFDDRTRSE is a dual data rate (DDR) D flip-flop with clock enable (CE) and synchronous reset and set whose output is enabled by a 3-state buffer. It consists of a dual data rate flip-flop (FDDRRSE) and a 3-state output buffer (OBUFT). The data output (O) of the flip-flop is connected to the input of the output buffer (OBUFT). The output of the OBUFT is connected to an OPAD or IOPAD. When the active-Low enable input (T) is Low, output is enabled and the data on the flip-flop's Q output appears on the OBUFT's O output. On a Low-to-High clock transition (C0 or C1), a High R input resets the Q output Low; a Low R input with a High S input sets O High. When both R and S are Low and clock enable is High, data on the D0 input is loaded into the flip-flop on a Low-to-High C0 clock transition and data on the D1 input is loaded into the flip-flop on a Low-to-High C1 clock transition. When T is High, outputs are high impedance (Off). When CE is Low and T is Low, the outputs do not change. The flip-flops are asynchronously cleared with Low outputs when power is applied. The INIT attribute does not apply to OFDDRTRSE components.
X9388
Inputs C0 X X X X X C1 X X X X X CE X X X X X X X 0 D0 X X X X X X X X D1 X X X X X X X X R X 1 0 1 1 0 1 0 S X 0 1 1 0 1 1 0 T 1 0 0 0 0 0 0 0
Outputs O Z 0 1 0 0 1 0 No Chg
1323
OFDDRTRSE
Inputs C0 X
T S D0 D1 CE C0 C1 R
Outputs D1 X D1 R 0 0 S 0 0 T 0 0 O D0 D1
C1 X
CE 1 1
D0 D0 X
FDDRRSE
D0 D1 CE C0 C1 R IOB=TRUE S Q
LVTTL SLOW 12
T Q_OUT OBUFT O
X9365
OFDDRTRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, the OFDDRTRSE design element should be instantiated rather than inferred.

-- Component Declaration for OFDDRTRSE should be placed -- after architecture statement but before begin keyword component OFDDRTRSE port (O : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for OFDDRTRSE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for OFDDRTRSE should be placed -- in architecture after the begin keyword OFDDRTRSE_INSTANCE_NAME : OFDDRTRSE port map (O => user_O, C0 => user_C0, C1 => user_C1, CE => user_CE, D0 => user_D0,
1324
OFDDRTRSE
D1 => user_D1, R => user_R, S => user_S, T => user_T);

OFDDRTRSE instance_name (.O (user_O), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .D0 (user_D0), .D1 (user_D1), .R (user_R), .S (user_S), .T (user_T));
1325
OFDDRTRSE
1326
OFDE, 4, 8, 16
OFDE, 4, 8, 16
D Flip-Flops with Active-High Enable Output Buffers
OFDE, OFDE4, OFDE8, OFDE16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
E
D C
OFDE
X3782
OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) are connected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. When the active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the O outputs. When E is Low, outputs are high impedance (Z state or Off). The flip-flops are asynchronously cleared with Low outputs when power is applied, or when global reset is active. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.
D0 D1 D2 D3 C
OFDE4
Q0 Q1 Q2 Q3
X3802
Q[7:0]
D[7:0]
OFDE8
Inputs E D X 1 0 C X
Outputs O Z 1 0
C X3814
0 1 1
D[15:0]
OFDE16
Q[15:0]
X3836
1327
OFDE, 4, 8, 16
VCC
E INV D
FDCE
D CE Q Q_OUT
T O OBUFT
C CLR
IOB=TRUE GND
X9775
OFDE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
E INV T O
OBUFT FD
D D Q
X8044
OFDE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1328
OFDE, 4, 8, 16
O[7:0] E D0
OFDE
D C Q O0 O0
E D1
OFDE
D C Q O1 O1
E D2
OFDE
D C Q O2 O2
E D3
OFDE
D C Q O3 O3
E D4
OFDE
D C Q O4 O4
E D5
OFDE
D C Q O5 O5
E D6
OFDE
D C Q O6 O6
E D[7:0] E C D7
OFDE
D C Q O7 X6379 O7
OFDE8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDE, you would infer an FDE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1329
OFDE, 4, 8, 16
1330
OFDE_1
OFDE_1
D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock
OFDE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
E
D C
OFDE_1
X3783
OFDE_1 and its output buffer are located in an input/output block (IOB). The data output of the flip-flop (Q) is connected to the input of an output buffer or OBUFE. The output of the OBUFE is connected to an OPAD or an IOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When the active-High enable input (E) is High, the data on the flip-flop output (Q) appears on the O output. When E is Low, the output is high impedance (Z state or Off). The flip-flop is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs E 0 1 1
VCC
Outputs C X O Z 1 0
D X 1 0
E INV D
FDCE
D CE CB Q Q_OUT
T O OBUFT
C INV
C CLR
IOB=TRUE GND
X9774
OFDE_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1331
OFDE_1
VCC E INV D C INV CB T

LVTTL SLOW 12
FDCE
D CE C CLR Q Q_OUT
T O OBUFT
IOB=TRUE GND X9370
OFDE_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDE_1, you would infer an FDE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1332
OFDI
OFDI
Output D Flip-Flop (Asynchronous Preset)
OFDI Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
OFDI
OFDI is contained in an input/output block (IOB). The output (Q) of the D flip-flop is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the Low-to-High clock (C) transition and appears at the output (Q). The flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
X4582
VCC
D C
D CE C
PRE
Q_OUT OBUF
OFDI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1333
OFDI
VCC
FDPE
D PRE Q Q_OUT
LVTTL SLOW 12
D C
CE C IOB=TRUE GND
OBUF
X9368
OFDI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDI, you would infer an FDP and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1334
OFDI
1335
OFDI
1336
OFDI_1
OFDI_1
Output D Flip-Flop with Inverted Clock (Asynchronous Preset)
OFDI_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
OFDI_1
OFDI_1 exists in an input/output block (IOB). The D flip-flop output (Q) is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition and appears on the Q output. The flip-flop is asynchronously preset, output High, when power is applied.
X4384
VCC
D C INV CB
D CE C
PRE
Q_OUT OBUF
OFDI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1337
OFDI_1
VCC
FDPE
D C INV D CB PRE Q Q_OUT
LVTTL SLOW 12
CE C IOB=TRUE GND
OBUF
X9369
OFDI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDI_1, you would infer an FDP_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1338
OFDT, 4, 8, 16
OFDT, 4, 8, 16
Single and Multiple D Flip-Flops with Active-Low 3-State Output Enable Buffers
OFDT, OFDT4, OFDT8, OFDT16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D C
OFDT
X3780
OFDT, OFDT4, OFDT8, and OFDT16 are single or multiple D flip-flops whose outputs are enabled by a 3-state buffers. The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of the OBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on the flip-flop outputs (Q) appears on the O outputs. When T is High, outputs are high impedance (Off). The flip-flops are asynchronously cleared with Low outputs, when power is applied, or when global reset is active.
D0 D1 D2 D3 C
OFDT4
Q0 Q1 Q2 Q3
Inputs Outputs C X O Z D
X3801
D[15:0]
OFDT16
Q[15:0]
T 1 0
D X D
X3835
D[7:0]
OFDT8
Q[7:0]
X3813
1339
OFDT, 4, 8, 16
VCC
FDCE
D D CE C C CLR Q O_OUT
T O OBUFT
IOB=TRUE GND
X9773
OFDT Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

VCC T
LVTTL SLOW 12
FDCE
D C D CE C CLR Q O_OUT
T O OBUFT
IOB=TRUE GND X9366
OFDT Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

T T O
OBUFT FD
D D Q
C O X8043
OFDT Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1340
OFDT, 4, 8, 16
T D0
OFDT
D C Q O0 O0
O[7:0]
T D1
OFDT
D C Q O1 O1
T D2
OFDT
D C Q O2 O2
T D3
OFDT
D C Q O3 O3
T D4
OFDT
D C Q O4 O4
T D5
OFDT
D C Q O5 O5
T D6
OFDT
D C Q O6 O6
T D[7:0] T C D7
OFDT
D C Q O7 O7
X6377
OFDT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDT, you would infer an FDCE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1341
OFDT, 4, 8, 16
1342
OFDT_1
OFDT_1
D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock
OFDT_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
T
D C
OFDT_1
X3781
OFDT_1 and its output buffer are located in an input/output block (IOB). The flipflop data output (Q) is connected to the input of an output buffer (OBUFT). The OBUFT output is connected to an OPAD or an IOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When the activeLow enable input (T) is Low, the data on the flip-flop output (Q) appears on the O output. When T is High, the output is high impedance (Off). The flip-flop is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs T 1 0 0
VCC
Outputs C X O Z 1 0
D X 1 0
FDCE
D D CE C INV CB C CLR Q Q_OUT
T O OBUFT
IOB=TRUE GND
X9772
OFDT_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1343
OFDT_1
VCC T
LVTTL SLOW 12
FDCE
D C INV CB D CE C CLR Q Q_OUT
T O OBUFT
IOB=TRUE GND X9367
OFDT_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDT_1, you would infer an FDCE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1344
OFDX, 4, 8, 16
OFDX, 4, 8, 16
Single- and Multiple-Output D Flip-Flops with Clock Enable
OFDX, OFDX4, OFDX8, OFDX16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D CE C
OFDX
OFDX, OFDX4, OFDX8, and OFDX16 are single and multiple output D flip-flops. The Q outputs are connected to OPADs or IOPADs. The data on the D inputs is loaded into the flip-flops during the Low-to-High clock (C) transition and appears on the Q outputs. When CE is Low, flip-flop outputs do not change. The flip-flops are asynchronously cleared with Low outputs, when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs Outputs C X Q Dn No Chg
X4988
D0 D1 D2 D3 CE C
OFDX4
Q0 Q1 Q2 Q3
X4989
CE
D[7:0] CE C X4990 FDCE D D[15:0] CE C Q[15:0] CE C D CE C CLR
D Dn X
OFDX8
Q[7:0]
1 0
Q_OUT OBUF
OFDX16
IOB=TRUE X4991 GND
X8754
OFDX Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1345
OFDX, 4, 8, 16
FDCE
D CE C D CE C CLR Q Q_OUT
LVTTL SLOW 12
OBUF
IOB=TRUE GND X9357
OFDX Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Q[7:0]
OFDX
D0 D CE C Q Q0 Q0
OFDX
D1 D CE C Q Q1 Q1
OFDX
D2 D CE C Q Q2 Q2
OFDX
D3 D CE C Q Q3
Q3
OFDX
D4 D CE C Q Q4
Q4
OFDX
D5 D CE C Q Q5
Q5
OFDX
D6 D CE C Q Q6
Q6
OFDX
D7 D CE C Q Q7
D[7:0] C CE
Q7
X6408
OFDX8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X
1346
OFDX, 4, 8, 16
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDX, you would infer an FDCE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1347
OFDX, 4, 8, 16
1348
OFDX_1
OFDX_1
Output D Flip-Flop with Inverted Clock and Clock Enable
OFDX_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D CE C
OFDX_1
OFDX_1 is located in an input/output block (IOB). The output (Q) of the D flip-flop is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition and appears on the Q output. When the CE pin is Low, the output (Q) does not change. The flip-flop is asynchronously cleared with Low output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
X4992
FDCE D CE C INV CB D CE C CLR Q Q_OUT OBUF Q
IOB=TRUE GND
X8755
OFDX_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1349
OFDX_1
FDCE
D CE C INV CB D CE C CLR Q Q_OUT
LVTTL SLOW 12
OBUF
IOB=TRUE GND X9358
OFDX_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDX_1, you would infer an FDCE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1350
OFDXI
OFDXI
Output D Flip-Flop with Clock Enable (Asynchronous Preset)
OFDXI Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D CE C
OFDXI
OFDXI is contained in an input/output block (IOB). The output (Q) of the D flip-flop is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the Low-to-High clock (C) transition and appears at the output (Q). When CE is Low, the output does not change. The flip-flop is asynchronously preset with High output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
X6000
D CE C
D CE C
PRE
Q_OUT OBUF
OFDXI Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1351
OFDXI
FDPE
D CE C D PRE Q Q_OUT
LVTTL SLOW 12
CE C IOB=TRUE GND
OBUF
X9359
OFDXI Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDXI, you would infer an FDPE and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1352
OFDXI_1
OFDXI_1
Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
OFDXI_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No
D CE C
OFDXI_1
OFDXI_1 is located in an input/output block (IOB). The D flip-flop output (Q) is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition and appears on the Q output. When CE is Low, the output (Q) does not change. The flip-flop is asynchronously preset with High output when power is applied, or when global reset is active. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
X6001
D CE C INV CB
D CE C
PRE
Q_OUT OBUF
OFDXI_1 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1353
OFDXI_1
FDPE
D CE C INV IOB=TRUE GND X9360 CB D PRE Q Q_OUT
LVTTL SLOW 12
CE C
OBUF
OFDXI_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
This component is inside of the IOB. It cannot be directly inferred. The most common design practice is to infer a regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. For instance, to get an OFDXI_1, you would infer an FDPE_1 and put the IOB = TRUE attribute on the component. Or, you could use the map option pr o to pack all output registers into the IOBs.
1354
OPAD, 4, 8, 16
OPAD, 4, 8, 16
Single- and Multiple-Output Pads
OPAD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II OPAD4, OPAD8, OPAD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Primitive Primitive
OPAD O
X9784
OPAD, OPAD4, OPAD8, and OPAD16 are single and multiple output pads. An OPAD connects a device pin to an output signal of a PLD. It is internally connected to an input/output block (IOB), which is configured by the software as an OBUF, an OBUFT, an OBUFE, an OFD, or an OFDT. See the appropriate CAE tool interface user guide for details on assigning pin location and identification.
O[7:0]
OPAD4 O0 O1 O2 O3 X3839
O0 OPAD O1 OPAD
OPAD8 O[7:0]
O2 OPAD O3 OPAD
X3842
O4 OPAD O5 OPAD
OPAD16 O[15:0]
O6 OPAD O7 OPAD
X3846 X7656
OPAD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1355
OPAD, 4, 8, 16
Usage

IOBDELAY, PULLDOWN
1356
OR2-9
OR2-9
2- to 9-Input OR Gates with Inverted and Non-Inverted Inputs
OR2, OR2B1, OR2B2, OR3, OR3B1, OR3B2, OR3B3, OR4, OR4B1, OR4B2, OR4B3, OR4B4 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive Primitive
OR5, OR5B1, OR5B2, OR5B3, OR5B4, OR5B5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II PRO XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II OR6, OR7, OR8, OR9 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II PRO XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro
1357
OR2-9
I5 I3 I1 0 I0 I2 I1 I0 0 I1 I0 I2 0 I2 I1 I0 OR4 OR5 I6 I3 I2 I1 0 I0 I1 I0 0 I1 I0 I2 0 I2 I1 I0 0 I4 I3 I5 I4 I3 I2 I1 I0 OR2B1 OR3B1 OR4B1 OR5B1 I7 I6 I3 I1 0 I0 I2 I1 I0 0 I1 I0 I2 0 I2 I1 I0 0 I3 I2 I1 I0 OR2B2 OR3B2 OR4B2 OR5B2 IA I7 I3 I2 I1 I0 0 I1 I0 I2 0 I4 I3 I2 I1 I0 0 I6 I5 I4 I3 I2 I1 I0 OR3B3 OR4B3 OR5B3 OR9 0 OR8 I4 I3 I5 I4 0 OR7 0 0 I4 I3 I3 I2 I1 I0 OR2 OR3 OR6 0 I4
I3 I2 I1 I0 0
I4 I3 I2 I1 I0 OR4B4 OR5B4 0
I4 I3 I2 I1 I0 OR5B5 0
X9435
OR Gate Representations
1358
OR2-9
The OR function is performed in the Configurable Logic Block (CLB) function generators for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X. OR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. OR functions of six to nine inputs are available with only non-inverting inputs. To invert some or all inputs, use external inverters. Since each input uses a CLB resource, replace functions with unused inputs with functions having the necessary number of inputs. See OR2-9 for information on additional OR functions for the Spartan-II, SpartanIIE, Virtex, and Virtex-E.
FMAP
I4 I3 S1 S2 I7 I6 I5 I4 OR4 O OR2 I3 I2 I1 I0 OR4 S0 S1 I2 I1 RLOC=R0C0.S0 O O
FMAP
FMAP
OR8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1359
OR2-9
FMAP
I7 I6 I5 I4 OR4 RLOC=X0Y1 O OR2 I3 I2 I1 I0 OR4 RLOC=X0Y0 S0 S1 S1 S0 I4 I3 I2 I1 O O
FMAP
I7 I6 I5 I4 I4 I3 I2 I1 O S1
FMAP
OR8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
OR2 through OR5 are primitives that can be inferred or instantiated. OR6 through OR9 are macros which can be inferred.
VHDL Inference Code

architecture Behavioral of or6 is begin process (I0, I1, I2, I3, I4, I5) begin O <= (I0 or I1 or I2 or I3 or I4 or I5); end process; end Behavioral;
Verilog Inference Code (OR6)

always @(I0 or I1 or I2 or I3 or I4 or I5) begin O <= (I0 || I1 || I2 || I3 || I4 || I5); end
VHDL Instantiation Template for OR5

Following is the VHDL code for OR5. To instantiate OR2, remove I2, I3, and I4. To instantiate OR3, remove I3 and I4, For OR4, remove I4. OR2B1, and OR2B2 have the same code as OR2. OR3B1, 3B2, and 3B3 have the same code as OR3 and so forth.
1360
OR2-9
-- Component Declaration for OR5 should be placed -- after architecture statement but before begin keyword component OR5 port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC; I4: in STD_ULOGIC); end component; -- Component Attribute specification for OR5 -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for OR5 should be placed -- in architecture after the begin keyword OR5_INSTANCE_NAME : OR5 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4);
Verilog Instantiation Template for OR5

OR5 OR5_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4));

None
1361
OR2-9
1362
OR12, 16
OR12, 16
12- and 16-Input OR Gates with Non-Inverted Inputs
OR12, OR16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II PRO CoolRunner XPLA3 CoolRunner-II
I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 OR12 X9436
Macro Macro Macro Macro No No
XC9500, XC9500XV, XC9500XL No
See OR2-9 for information on OR functions.
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 OR16
X9437
1363
OR12, 16
FMAP I15 I14 I13 I12 NOR4 RLOC=R0C0.S1 C2 FMAP I11 I10 I9 I8 NOR4 C1 FMAP I7 I6 I5 I4 NOR4 C0 RLOC=R1C0.S1 S1 LO MUXCY_L S 0 DI 1 CI I4 RLOC=R1C0.S1 I7 I6 I5 I4 I3 O I2 I1 S1 S2 LO MUXCY_L S 0 DI 1 CI RLOC=R0C0.S1 I11 I10 I9 I8 I4 I3 O I2 I1 RLOC=R0C0.S1 S2 S3 VCC S 0 DI 1 CI I12 O MUXCY RLOC=R0C0.S1 I15 I14 I13 I4 I3 O I2 I1 S3
FMAP I3 I2 I1 I0 NOR4 RLOC=R1C0.S1 DI S0 LO MUXCY_L S 0 1 CI RLOC=R1C0.S1 I3 I2 I1 I0 I4 I3 O I2 I1 S0
CIN
X8706 GND
OR16 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1364
OR12, 16
FMAP
I15 I15 I14 S3 I13 I12 NOR4 RLOC=X0Y1 C2 VCC S O MUXCY 0 DI 1 CI I12 RLOC=X0Y1 I13 I14 I4 I3 I2 I1 O S3
FMAP
I11 I11 I10 S2 I9 I8 NOR4 RLOC=X0Y1 C1 S LO MUXCY_L 0 1 DI CI RLOC=X0Y1 I9 I8 I10 I4 I3 I2 I1 O S2
FMAP
I7 I7 I6 S1 I5 I4 NOR4 RLOC=X0Y0 C0 S LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I5 I4 I6 I4 I3 I2 I1 O S1
FMAP
I3 I3 I2 S0 I1 I0 NOR4 RLOC=X0Y0 CIN S LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I1 I0 I2 I4 I3 I2 I1 O S0
GND
X9372
OR16 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
For HDL, OR12 and OR16 are macros that are inferred. See OR2-9 for information about inferring OR gates.
1365
OR12, 16
1366
ORCY
ORCY
OR with Carry Logic
ORCY Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I CI ORCY X9403
ORCY is a special OR with general O output used for generating faster and smaller arithmetic functions. Each Virtex-II, Virtex-II Pro, and Virtex-II Pro X slice contains a dedicated 2-input OR gate that ORs together carry out values for a series of horizontally adjacent carry chains. The OR gate gets one input external to the slice and the other input from the output of the high order carry mux. The OR gate's output drives the next slice's OR gate horizontally across the die. Only MUXCY outputs can drive the signal on the CI pin. Only ORCY outputs or logic zero can drive the I pin.
Usage
For HDL, the ORCY design element should be instantiated rather than inferred.

-- Component Declaration for ORCY should be placed -- after architecture statement but before begin keyword component ORCY port (O : out STD_ULOGIC; CI : in STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for ORCY -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for ORCY should be placed -- in architecture after the begin keyword ORCY_INSTANCE_NAME : ORCY
1367
ORCY
port map (O => user_O, CI => user_CI, I => user_I);

ORCY instance_name (.O (user_O), .CI (user_CI), .I (user_I));

None
1368
PPC405
PPC405
Primitive for the Power PC Core
PPC405 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No Primitive* No No No
* Not supported for Virtex-II. Supported for Virtex-II Pro and Virtex-II Pro X only.
The PowerPC 405 embedded core is a 32-bit RISC core integrating a PowerPC 405 CPU, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers, and a memory management unit (MMU). Integrated on-chip memory (OCM) controllers provide dedicated interfaces between Block SelectRAM memory and the processor core instruction and data paths for high-speed access. The PowerPC 405 core implements the PowerPC User Instruction Set. For complete information about the PowerPC 405, see the following documents: Virtex-II Pro Datasheet Virtex-II Pro Handbook The PowerPC 405 Core Processor Block Manual The PowerPC 405 User Guide
The following table lists the inputs and outputs of the primitive. For detailed information about the pinouts, see the DS083 Virtex-II Pro Data Sheet.
Inputs BRAMDSOCMCLK BRAMDSOCMRDDBUS [0:31] BRAMISOCMCLK BRAMISOCMRDDBUS [0:63] CPMC405CLOCK CPMC405CORECLKINACTIVE CPMC405CPUCLKEN CPMC405JTAGCLKEN CPMC405TIMERCLKEN CPMC405TIMERTICK
Outputs C405CPMCORESLEEPREQ C405CPMMSRCE C405CPMMSREE C405CPMTIMERIRQ C405CPMTIMERRESETREQ C405DBGMSRWE C405DBGSTOPACK C405DBGWBCOMPLETE C405DBGWBFULL C405DBGWBIAR[0:29]
1369
PPC405
Inputs DBGC405DEBUGHALT DBGC405EXTBUSHOLDACK DBGC405UNCONDDEBUGEVENT DCRC405ACK DCRC405DBUSIN [0:31] DSARCVALUE [0:7] DSCNTLVALUE [0:7] EICC405CRITINPUTIRQ EICC405EXTINPUTIRQ ISARCVALUE [0:7] ISCNTLVALUE [0:7] JTGC405BNDSCANTDO JTGC405TCK JTGC405TDI JTGC405TMS JTGC405TRSTNEG MCBCPUCLKEN MCBJTAGEN MCBTIMEREN MCPPCRST PLBC405DCUADDRACK PLBC405DCUBUSY PLBC405DCUERR PLBC405DCURDDACK PLBC405DCURDDBUS [0:63] PLBC405DCURDWDADDR [1:3] PLBC405DCUSSIZE1 PLBC405DCUWRDACK PLBC405ICUADDRACK PLBC405ICUBUSY PLBC405ICUERR PLBC405ICURDDACK PLBC405ICURDDBUS [0:63] PLBC405ICURDWDADDR [1:3] PLBC405ICUSSIZE1 PLBCLK RSTC405RESETCHIP RSTC405RESETCORE RSTC405RESETSYS TIEC405DETERMINISTICMULT TIEC405DISOPERANDFWD C405DCRABUS [0:9]
Outputs
C405DCRDBUSOUT [0:31] C405DCRREAD C405DCRWRITE C405JTGCAPTUREDR C405JTGEXTEST C405JTGPGMOUT C405JTGSHIFTDR C405JTGTDO C405JTGTDOEN C405JTGUPDATEDR C405PLBDCUABORT C405PLBDCUABUS [0:31] C405PLBDCUBE [0:7] C405PLBDCUCACHEABLE C405PLBDCUGUARDED C405PLBDCUPRIORITY [0:1] C405PLBDCUREQUEST C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUU0ATTR C405PLBDCUWRDBUS [0:63] C405PLBDCUWRITETHRU C405PLBICUABORT C405PLBICUABUS [0:29] C405PLBICUCACHEABLE C405PLBICUPRIORITY [0:1] C405PLBICUREQUEST C405PLBICUSIZE [2:3] C405PLBICUU0ATTR C405RSTCHIPRESETREQ C405RSTCORERESETREQ C405RSTSYSRESETREQ C405TRCCYCLE C405TRCEVENEXECUTIONSTATUS [0:1] C405TRCODDEXECUTIONSTATUS [0:1] C405TRCTRACESTATUS [0:3] C405TRCTRIGGEREVENTOUT C405TRCTRIGGEREVENTTYPE [0:10] C405XXXMACHINECHECK DSOCMBRAMABUS [8:29]
1370
PPC405
Inputs TIEC405MMUEN TIEDSOCMDCRADDR [0:7] TIEISOCMDCRADDR [0:7] TRCC405TRACEDISABLE TRCC405TRIGGEREVENTIN
Outputs DSOCMBRAMBYTEWRITE [0:3] DSOCMBRAMEN DSOCMBRAMWRDBUS [0:31] DSOCMBUSY ISOCMBRAMEN ISOCMBRAMEVENWRITEEN ISOCMBRAMODDWRITEEN ISOCMBRAMRDABUS [8:28] ISOCMBRAMWRABUS [8:28] ISOCMBRAMWRDBUS [0:31]
1371
PPC405
PPC405
BRAMDSOCMCLK BRAMDSOCMRDDBUS(0:31) BRAMISOCMCLK BRAMISOCMRDDBUS(0:63) CPMC405CLOCK CPMC405CORECLKINACTIVE CPMC405CPUCLKEN CPMC405JTAGCLKEN CPMC405TIMERCLKEN CPMC405TIMERTICK DBGC405DEBUGHALT DBGC405EXTBUSHOLDACK DBGC405UNCONDDEBUGEVENT DCRC405ACK DCRC405DBUSIN(0:31) DSARCVALUE(0:7) DSCNTLVALUE(0:7) EICC405CRITINPUTIRQ EICC405EXTINPUTIRQ ISARCVALUE(0:7) ISCNTLVALUE(0:7) JTGC405BNDSCANTDO JTGC405TCK JTGC405TDI JTGC405TMS JTGC405TRSTNEG MCBCPUCLKEN MCBJTAGEN MCBTIMEREN MCPPCRST PLBC405DCUADDRACK PLBC405DCUBUSY PLBC405DCUERR PLBC405DCURDDACK PLBC405DCURDDBUS(0:63) PLBC405DCURDWDADDR(1:3) PLBC405DCUSSIZE1 PLBC405DCUWRDACK PLBC405ICUADDRACK PLBC405ICUBUSY PLBC405ICUERR PLBC405ICURDDACK PLBC405ICURDDBUS(0:63) PLBC405ICURDWDADDR(1:3) PLBC405ICUSSIZE1 PLBCLK RSTC405RESETCHIP RSTC405RESETCORE RSTC405RESETSYS TIEC405DETERMINISTICMULT TIEC405DISOPERANDFWD TIEC405MMUEN TIEDSOCMDCRADDR(0:7) TIEISOCMDCRADDR(0:7) TRCC405TRACEDISABLE TRCC405TRIGGEREVENTIN C405CPMCORESLEEPREQ C405CPMMSRCE C405CPMMSREE C405CPMTIMERIRQ C405CPMTIMERRESETREQ C405DBGMSRWE C405DBGSTOPACK C405DBGWBCOMPLETE C405DBGWBFULL C405DBGWBIAR(0:29) C405DCRABUS(0:9) C405DCRDBUSOUT(0:31) C405DCRREAD C405DCRWRITE C405JTGCAPTUREDR C405JTGEXTEST C405JTGPGMOUT C405JTGSHIFTDR C405JTGTDO C405JTGTDOEN C405JTGUPDATEDR C405PLBDCUABORT C405PLBDCUABUS(0:31) C405PLBDCUBE(0:7) C405PLBDCUCACHEABLE C405PLBDCUGUARDED C405PLBDCUPRIORITY(0:1) C405PLBDCUREQUEST C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUU0ATTR C405PLBDCUWRDBUS(0:63) C405PLBDCUWRITETHRU C405PLBICUABORT C405PLBICUABUS(0:29) C405PLBICUACHEABLE C405PLBICUPRIORITY(0:1) C405PLBICUREQUEST C405PLBICUSIZE(2:3) C405PLBICUU0ATTR C405RSTCHIPRESETREQ C405RSTCORERESETREQ C405RSTSYSRESETREQ C405TRCCYCLE C405TRCEVENEXECUTIONSTATUS(0:1) C405TRCODDEXECUTIONSTATUS(0:1) C405TRCTRACESTATUS(0:3) C405TRCTRIGGEREVENTOUT C405TRCTRIGGEREVENTTYPE(0:10) C405XXXMACHINECHECK DSOCMBRAMABUS(8:29) DSOCMBRAMBYTEWRITE(0:3) DSOCMBRAMEN DSOCMBRAMWRDBUS(0:31) DSOCMBUSY ISOCMBRAMEN ISOCMBRAMEVENWRITEEN ISOCMBRAMODDWRITEEN ISOCMBRAMRDABUS(8:28) ISOCMBRAMWRABUS(8:28) ISOCMBRAMWRDBUS(0:31)
X9929
1372
PPC405
Usage
For HDL, the PPC405 design element is instantiated rather than inferred.

-- Component Declaration for PPC405 should be placed -- after architecture statement but before begin keyword
component PPC405
port (C405CPMCORESLEEPREQ C405CPMMSRCE C405CPMMSREE C405CPMTIMERIRQ
: out STD_ULOGIC;
: out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC;
C405CPMTIMERRESETREQ C405DBGMSRWE C405DBGSTOPACK C405DBGWBCOMPLETE C405DBGWBFULL C405DBGWBIAR C405DCRABUS C405DCRDBUSOUT C405DCRREAD C405DCRWRITE C405JTGCAPTUREDR C405JTGEXTEST C405JTGPGMOUT C405JTGSHIFTDR C405JTGTDO C405JTGTDOEN C405JTGUPDATEDR C405PLBDCUABORT C405PLBDCUABUS C405PLBDCUBE
: out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_LOGIC_VECTOR (29 downto 0); : out STD_LOGIC_VECTOR (9 downto 0); : out STD_LOGIC_VECTOR (31 downto 0); : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_LOGIC_VECTOR (31 downto 0); : out STD_LOGIC_VECTOR (7 downto 0); : out STD_ULOGIC; : out STD_ULOGIC; : out STD_LOGIC_VECTOR (1 downto 0);
C405PLBDCUCACHEABLE C405PLBDCUGUARDED C405PLBDCUPRIORITY
1373
PPC405
C405PLBDCUREQUEST C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUU0ATTR C405PLBDCUWRDBUS C405PLBDCUWRITETHRU C405PLBICUABORT C405PLBICUABUS
: out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_LOGIC_VECTOR (63 downto 0); : out STD_ULOGIC;
: out STD_ULOGIC; : out STD_LOGIC_VECTOR (29 downto 0); : out STD_ULOGIC; : out STD_LOGIC_VECTOR (1 downto 0); : out STD_ULOGIC; : out STD_LOGIC_VECTOR (3 downto 2); : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC;
C405PLBICUCACHEABLE C405PLBICUPRIORITY C405PLBICUREQUEST C405PLBICUSIZE C405PLBICUU0ATTR C405RSTCHIPRESETREQ C405RSTCORERESETREQ C405RSTSYSRESETREQ C405TRCCYCLE
C405TRCEVENEXECUTIONSTATUS: out STD_LOGIC_VECTOR (1 downto 0); C405TRCODDEXECUTIONSTATUS : out STD_LOGIC_VECTOR (1 downto 0); C405TRCTRACESTATUS : out STD_LOGIC_VECTOR (3 downto 0);
C405TRCTRIGGEREVENTOUT : out STD_ULOGIC; C405TRCTRIGGEREVENTTYPE : out STD_LOGIC_VECTOR (10 downto 0); C405XXXMACHINECHECK DSOCMBRAMABUS DSOCMBRAMBYTEWRITE DSOCMBRAMEN DSOCMBRAMWRDBUS DSOCMBUSY ISOCMBRAMEN : out STD_ULOGIC;
: out STD_LOGIC_VECTOR (29 downto 8); : out STD_LOGIC_VECTOR (3 downto 0);
: out STD_ULOGIC; : out STD_LOGIC_VECTOR (31 downto 0);
: out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC; : out STD_ULOGIC;
ISOCMBRAMEVENWRITEEN ISOCMBRAMODDWRITEEN ISOCMBRAMRDABUS ISOCMBRAMWRABUS ISOCMBRAMWRDBUS BRAMDSOCMCLK
: out STD_LOGIC_VECTOR (28 downto 8); : out STD_LOGIC_VECTOR (28 downto 8); : out STD_LOGIC_VECTOR (31 downto 0); : in STD_ULOGIC;
1374
PPC405
BRAMDSOCMRDDBUS BRAMISOCMCLK BRAMISOCMRDDBUS CPMC405CLOCK
: in STD_LOGIC_VECTOR (31 downto 0); : in STD_ULOGIC; : in STD_LOGIC_VECTOR (63 downto 0); : in STD_ULOGIC; : in STD_ULOGIC;
CPMC405CORECLKINACTIVE CPMC405CPUCLKEN CPMC405JTAGCLKEN CPMC405TIMERCLKEN CPMC405TIMERTICK DBGC405DEBUGHALT
: in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC;
DBGC405EXTBUSHOLDACK
DBGC405UNCONDDEBUGEVENT : in STD_ULOGIC; DCRC405ACK DCRC405DBUSIN DSARCVALUE DSCNTLVALUE : in STD_ULOGIC; : in STD_LOGIC_VECTOR (31 downto 0); : in STD_LOGIC_VECTOR (7 downto 0); : in STD_LOGIC_VECTOR (7 downto 0); : in STD_ULOGIC; : in STD_ULOGIC;
EICC405CRITINPUTIRQ EICC405EXTINPUTIRQ ISARCVALUE ISCNTLVALUE
: in STD_LOGIC_VECTOR (7 downto 0); : in STD_LOGIC_VECTOR (7 downto 0); : in STD_ULOGIC;
JTGC405BNDSCANTDO JTGC405TCK JTGC405TDI JTGC405TMS JTGC405TRSTNEG MCBCPUCLKEN MCBJTAGEN MCBTIMEREN MCPPCRST
: in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_LOGIC_VECTOR (63 downto 0);
PLBC405DCUADDRACK PLBC405DCUBUSY PLBC405DCUERR PLBC405DCURDDACK PLBC405DCURDDBUS
1375
PPC405
PLBC405DCURDWDADDR PLBC405DCUSSIZE1 PLBC405DCUWRDACK PLBC405ICUADDRACK PLBC405ICUBUSY PLBC405ICUERR PLBC405ICURDDACK PLBC405ICURDDBUS PLBC405ICURDWDADDR PLBC405ICUSSIZE1 PLBCLK
: in STD_LOGIC_VECTOR (3 downto 1);
: in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_LOGIC_VECTOR (63 downto 0); : in STD_LOGIC_VECTOR (3 downto 1);
: in STD_ULOGIC;
: in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC; : in STD_ULOGIC;
RSTC405RESETCHIP RSTC405RESETCORE RSTC405RESETSYS
TIEC405DETERMINISTICMULT : in STD_ULOGIC; TIEC405DISOPERANDFWD TIEC405MMUEN TIEDSOCMDCRADDR TIEISOCMDCRADDR TRCC405TRACEDISABLE : in STD_ULOGIC;
: in STD_ULOGIC; : in STD_LOGIC_VECTOR (7 downto 0); : in STD_LOGIC_VECTOR (7 downto 0); : in STD_ULOGIC; : in STD_ULOGIC);
TRCC405TRIGGEREVENTINE end component;
-- Component Attribute specification for PPC405 -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for PPC405 should be placed -- in architecture after the begin keyword
PPC405_INSTANCE_NAME : PPC405 port map (C405CPMCORESLEEPREQ => user_C405CPMCORESLEEPREQ,
1376
PPC405
C405CPMMSRCE C405CPMMSREE C405CPMTIMERIRQ
=> user_C405CPMMSRCE, => user_C405CPMMSREE, => user_C405CPMTIMERIRQ, => user_ C405CPMTIMERRESETREQ,
C405CPMTIMERRESETREQ C405DBGMSRWE C405DBGSTOPACK C405DBGWBCOMPLETE C405DBGWBFULL C405DBGWBIAR C405DCRABUS C405DCRDBUSOUT C405DCRREAD C405DCRWRITE C405JTGCAPTUREDR C405JTGEXTEST C405JTGPGMOUT C405JTGSHIFTDR C405JTGTDO
=> user_C405DBGMSRWE, => user_C405DBGSTOPACK, => user_C405DBGWBCOMPLETE, => user_C405DBGWBFULL, => user_C405DBGWBIAR, => user_C405DCRABUS, => user_C405DCRDBUSOUT, => user_C405DCRREAD, => user_C405DCRWRITE, => user_C405JTGCAPTUREDR, => user_C405JTGEXTEST, => user_C405JTGPGMOUT, => user_C405JTGSHIFTDR, => user_C405JTGTDO,
C405JTGTDOEN C405JTGUPDATEDR C405PLBDCUABORT C405PLBDCUABUS C405PLBDCUBE
=> user_C405JTGTDOEN, => user_C405JTGUPDATEDR, => user_C405PLBDCUABORT, => user_C405PLBDCUABUS, => user_C405PLBDCUBE, => user_C405PLBDCUCACHEABLE, => user_C405PLBDCUGUARDED, => user_C405PLBDCUPRIORITY, => user_C405PLBDCUREQUEST, => user_C405PLBDCURNW, => user_C405PLBDCUSIZE2, => user_C405PLBDCUU0ATTR, => user_C405PLBDCUWRDBUS, => user_C405PLBDCUWRITETHRU,
C405PLBDCUCACHEABLE C405PLBDCUGUARDED C405PLBDCUPRIORITY C405PLBDCUREQUEST C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUU0ATTR C405PLBDCUWRDBUS C405PLBDCUWRITETHRU C405PLBICUABORT C405PLBICUABUS
=> user_C405PLBICUABORT, => user_C405PLBICUABUS,
1377
PPC405
C405PLBICUCACHEABLE C405PLBICUPRIORITY C405PLBICUREQUEST C405PLBICUSIZE C405PLBICUU0ATTR C405RSTCHIPRESETREQ C405RSTCORERESETREQ C405RSTSYSRESETREQ C405TRCCYCLE
=> user_C405PLBICUCACHEABLE, => user_C405PLBICUPRIORITY, => user_C405PLBICUREQUEST,
=> user_C405PLBICUSIZE, => user_C405PLBICUU0ATTR, => user_C405RSTCHIPRESETREQ, => user_C405RSTCORERESETREQ, => user_C405RSTSYSRESETREQ, => user_C405TRCCYCLE,
C405TRCEVENEXECUTIONSTATUS => user_C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS => user_C405TRCODDEXECUTIONSTATUS, C405TRCTRACESTATUS => user_C405TRCTRACESTATUS, => user_C405TRCTRIGGEREVENTOUT, => user_C405TRCTRIGGEREVENTTYPE, => user_C405XXXMACHINECHECK, => user_DSOCMBRAMABUS, => user_DSOCMBRAMBYTEWRITE,
C405TRCTRIGGEREVENTOUT C405TRCTRIGGEREVENTTYPE C405XXXMACHINECHECK DSOCMBRAMABUS DSOCMBRAMBYTEWRITE DSOCMBRAMEN DSOCMBRAMWRDBUS DSOCMBUSY ISOCMBRAMEN
=> user_DSOCMBRAMEN, => user_DSOCMBRAMWRDBUS,
=> user_DSOCMBUSY, => user_ISOCMBRAMEN, => user_ISOCMBRAMEVENWRITEEN, => user_ISOCMBRAMODDWRITEEN, => user_ISOCMBRAMRDABUS, => user_ISOCMBRAMWRABUS, => user_ISOCMBRAMWRDBUS, => user_BRAMDSOCMCLK, => user_BRAMDSOCMRDDBUS, => user_BRAMISOCMCLK, => user_BRAMISOCMRDDBUS, => user_CPMC405CLOCK, => user_CPMC405CORECLKINACTIVE,
ISOCMBRAMEVENWRITEEN ISOCMBRAMODDWRITEEN ISOCMBRAMRDABUS ISOCMBRAMWRABUS ISOCMBRAMWRDBUS BRAMDSOCMCLK BRAMDSOCMRDDBUS BRAMISOCMCLK BRAMISOCMRDDBUS CPMC405CLOCK
CPMC405CORECLKINACTIVE CPMC405CPUCLKEN CPMC405JTAGCLKEN
=> user_CPMC405CPUCLKEN, => user_CPMC405JTAGCLKEN,
1378
PPC405
CPMC405TIMERCLKEN CPMC405TIMERTICK DBGC405DEBUGHALT
=> user_CPMC405TIMERCLKEN, => user_CPMC405TIMERTICK, => user_DBGC405DEBUGHALT,
DBGC405EXTBUSHOLDACK
=> user_DBGC405EXTBUSHOLDACK, =>
DBGC405UNCONDDEBUGEVENT user_DBGC405UNCONDDEBUGEVENT, DCRC405ACK DCRC405DBUSIN DSARCVALUE DSCNTLVALUE EICC405CRITINPUTIRQ EICC405EXTINPUTIRQ ISARCVALUE ISCNTLVALUE
=> user_DCRC405ACK, => user_DCRC405DBUSIN, => user_DSARCVALUE, => user_DSCNTLVALUE, => user_EICC405CRITINPUTIRQ, => user_EICC405EXTINPUTIRQ,
=> user_ISARCVALUE, => user_ISCNTLVALUE, => user_JTGC405BNDSCANTDO,
JTGC405BNDSCANTDO JTGC405TCK JTGC405TDI JTGC405TMS JTGC405TRSTNEG MCBCPUCLKEN MCBJTAGEN MCBTIMEREN MCPPCRST
=> user_JTGC405TCK, => user_JTGC405TDI, => user_JTGC405TMS, => user_JTGC405TRSTNEG, => user_MCBCPUCLKEN, => user_MCBJTAGEN, => user_MCBTIMEREN, => user_MCPPCRST, => user_PLBC405DCUADDRACK, => user_PLBC405DCUBUSY, => user_PLBC405DCUERR, => user_PLBC405DCURDDACK, => user_PLBC405DCURDDBUS, => user_PLBC405DCURDWDADDR,
PLBC405DCUADDRACK PLBC405DCUBUSY PLBC405DCUERR PLBC405DCURDDACK PLBC405DCURDDBUS PLBC405DCURDWDADDR PLBC405DCUSSIZE1 PLBC405DCUWRDACK PLBC405ICUADDRACK PLBC405ICUBUSY PLBC405ICUERR PLBC405ICURDDACK
=> user_PLBC405DCUSSIZE1, => user_PLBC405DCUWRDACK, => user_PLBC405ICUADDRACK, => user_PLBC405ICUBUSY, => user_PLBC405ICUERR, => user_PLBC405ICURDDACK,
1379
PPC405
PLBC405ICURDDBUS PLBC405ICURDWDADDR PLBC405ICUSSIZE1 PLBCLK
=> user_PLBC405ICURDDBUS, => user_PLBC405ICURDWDADDR,
=> user_PLBC405ICUSSIZE1, => user_PLBCLK, => user_RSTC405RESETCHIP, => user_RSTC405RESETCORE, => user_RSTC405RESETSYS,
RSTC405RESETCHIP RSTC405RESETCORE RSTC405RESETSYS
TIEC405DETERMINISTICMULT => user_TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD TIEC405MMUEN TIEDSOCMDCRADDR TIEISOCMDCRADDR TRCC405TRACEDISABLE TRCC405TRIGGEREVENTINE => user_TIEC405DISOPERANDFWD,
=> user_TIEC405MMUEN, => user_TIEDSOCMDCRADDR, => user_TIEISOCMDCRADDR, => user_TRCC405TRACEDISABLE, => user_TRCC405TRIGGEREVENTINE);

PPC405 instance_name (.C405CPMCORESLEEPREQ (user_C405CPMCORESLEEPREQ), .C405CPMMSRCE (user_C405CPMMSRCE), .C405CPMMSREE (user_C405CPMMSREE), .C405CPMTIMERIRQ (user_C405CPMTIMERIRQ), .C405CPMTIMERRESETREQ (user_ C405CPMTIMERRESETREQ), .C405DBGMSRWE (user_C405DBGMSRWE), .C405DBGSTOPACK (user_C405DBGSTOPACK), .C405DBGWBCOMPLETE (user_C405DBGWBCOMPLETE), .C405DBGWBFULL (user_C405DBGWBFULL), .C405DBGWBIAR (user_C405DBGWBIAR), .C405DCRABUS (user_C405DCRABUS), .C405DCRDBUSOUT (user_C405DCRDBUSOUT), .C405DCRREAD (user_C405DCRREAD), .C405DCRWRITE (user_C405DCRWRITE), .C405JTGCAPTUREDR (user_C405JTGCAPTUREDR), .C405JTGEXTEST (user_C405JTGEXTEST), .C405JTGPGMOUT (user_C405JTGPGMOUT), .C405JTGSHIFTDR (user_C405JTGSHIFTDR), .C405JTGTDO (user_C405JTGTDO),
1380
PPC405
.C405JTGTDOEN (user_C405JTGTDOEN), .C405JTGUPDATEDR (user_C405JTGUPDATEDR), .C405PLBDCUABORT (user_C405PLBDCUABORT), .C405PLBDCUABUS (user_C405PLBDCUABUS), .C405PLBDCUBE (user_C405PLBDCUBE), .C405PLBDCUCACHEABLE (user_C405PLBDCUCACHEABLE), .C405PLBDCUGUARDED (user_C405PLBDCUGUARDED), .C405PLBDCUPRIORITY (user_C405PLBDCUPRIORITY), .C405PLBDCUREQUEST (user_C405PLBDCUREQUEST), .C405PLBDCURNW (user_C405PLBDCURNW), .C405PLBDCUSIZE2 (user_C405PLBDCUSIZE2), .C405PLBDCUU0ATTR (user_C405PLBDCUU0ATTR), .C405PLBDCUWRDBUS (user_C405PLBDCUWRDBUS), .C405PLBDCUWRITETHRU (user_C405PLBDCUWRITETHRU), .C405PLBICUABORT (user_C405PLBICUABORT), .C405PLBICUABUS (user_C405PLBICUABUS), .C405PLBICUCACHEABLE (user_C405PLBICUCACHEABLE), .C405PLBICUPRIORITY (user_C405PLBICUPRIORITY), .C405PLBICUREQUEST (user_C405PLBICUREQUEST), .C405PLBICUSIZE (user_C405PLBICUSIZE), .C405PLBICUU0ATTR (user_C405PLBICUU0ATTR), .C405RSTCHIPRESETREQ (user_C405RSTCHIPRESETREQ), .C405RSTCORERESETREQ (user_C405RSTCORERESETREQ), .C405RSTSYSRESETREQ (user_C405RSTSYSRESETREQ), .C405TRCCYCLE (user_C405TRCCYCLE), .C405TRCEVENEXECUTIONSTATUS(user_C405TRCEVENEXECUTIO NSTATUS), .C405TRCODDEXECUTIONSTATUS (user_C405TRCODDEXECUTIONSTATUS), .C405TRCTRACESTATUS (user_C405TRCTRACESTATUS), .C405TRCTRIGGEREVENTOUT (user_C405TRCTRIGGEREVENTOUT), .C405TRCTRIGGEREVENTTYPE (user_C405TRCTRIGGEREVENTTYPE), .C405XXXMACHINECHECK (user_C405XXXMACHINECHECK), .DSOCMBRAMABUS (user_DSOCMBRAMABUS), .DSOCMBRAMBYTEWRITE (user_DSOCMBRAMBYTEWRITE),
1381
PPC405
.DSOCMBRAMEN (user_DSOCMBRAMEN), .DSOCMBRAMWRDBUS(user_DSOCMBRAMWRDBUS), .DSOCMBUSY (user_DSOCMBUSY), .ISOCMBRAMEN (user_ISOCMBRAMEN), .ISOCMBRAMEVENWRITEEN (user_ISOCMBRAMEVENWRITEEN), .ISOCMBRAMODDWRITEEN (user_ISOCMBRAMODDWRITEEN), .ISOCMBRAMRDABUS (user_ISOCMBRAMRDABUS), .ISOCMBRAMWRABUS (user_ISOCMBRAMWRABUS), .ISOCMBRAMWRDBUS (user_ISOCMBRAMWRDBUS), .BRAMDSOCMCLK (user_BRAMDSOCMCLK), .BRAMDSOCMRDDBUS (user_BRAMDSOCMRDDBUS), .BRAMISOCMCLK (user_BRAMISOCMCLK), .BRAMISOCMRDDBUS (user_BRAMISOCMRDDBUS), .CPMC405CLOCK (user_CPMC405CLOCK), .CPMC405CORECLKINACTIVE (user_CPMC405CORECLKINACTIVE), .CPMC405CPUCLKEN (user_CPMC405CPUCLKEN), .CPMC405JTAGCLKEN (user_CPMC405JTAGCLKEN), .CPMC405TIMERCLKEN (user_CPMC405TIMERCLKEN), .CPMC405TIMERTICK (user_CPMC405TIMERTICK), .DBGC405DEBUGHALT (user_DBGC405DEBUGHALT), .DBGC405EXTBUSHOLDACK (user_DBGC405EXTBUSHOLDACK), .DBGC405UNCONDDEBUGEVENT (user_DBGC405UNCONDDEBUGEVENT), .DCRC405ACK (user_DCRC405ACK), .DCRC405DBUSIN (user_DSARCVALUE), .DSCNTLVALUE (user_DSCNTLVALUE), .EICC405CRITINPUTIRQ (user_EICC405CRITINPUTIRQ), .EICC405EXTINPUTIRQ (user_EICC405EXTINPUTIRQ), .ISARCVALUE (user_ISARCVALUE), .ISCNTLVALUE (user_ISCNTLVALUE), .JTGC405BNDSCANTDO (user_JTGC405BNDSCANTDO), .JTGC405TCK (user_JTGC405TCK), .JTGC405TDI (user_JTGC405TDI), .JTGC405TMS (user_JTGC405TMS), .JTGC405TRSTNEG (user_JTGC405TRSTNEG), .MCBCPUCLKEN (user_MCBCPUCLKEN),
1382
PPC405
.MCBJTAGEN (user_MCBJTAGEN), .MCBTIMEREN (user_MCBTIMEREN), .MCPPCRST (user_MCPPCRST), .PLBC405DCUADDRACK (user_PLBC405DCUADDRACK), .PLBC405DCUBUSY (user_PLBC405DCUBUSY), .PLBC405DCUERR (user_PLBC405DCUERR), .PLBC405DCURDDACK (user_PLBC405DCURDDACK), .PLBC405DCURDDBUS (user_PLBC405DCURDDBUS), .PLBC405DCURDWDADDR (user_PLBC405DCURDWDADDR), .PLBC405DCUSSIZE1 (user_PLBC405DCUSSIZE1), .PLBC405DCUWRDACK (user_PLBC405DCUWRDACK), .PLBC405ICUADDRACK (user_PLBC405ICUADDRACK), .PLBC405ICUBUSY (user_PLBC405ICUBUSY), .PLBC405ICUERR (user_PLBC405ICUERR), .PLBC405ICURDDACK (user_PLBC405ICURDDACK), .PLBC405ICURDDBUS (user_PLBC405ICURDDBUS), .PLBC405ICURDWDADDR (user_PLBC405ICURDWDADDR), .PLBC405ICUSSIZE1 (user_PLBC405ICUSSIZE1), .PLBCLK (user_PLBCLK), .RSTC405RESETCHIP (user_RSTC405RESETCHIP), .RSTC405RESETCORE (user_RSTC405RESETCORE), .RSTC405RESETSYS (user_RSTC405RESETSYS), .TIEC405DETERMINISTICMULT (user_TIEC405DETERMINISTICMULT), .TIEC405DISOPERANDFWD (user_TIEC405DISOPERANDFWD), .TIEC405MMUEN (user_TIEC405MMUEN), .TIEDSOCMDCRADDR (user_TIEDSOCMDCRADDR), .TIEISOCMDCRADDR (user_TIEISOCMDCRADDR), .TRCC405TRACEDISABLE (user_TRCC405TRACEDISABLE), .TRCC405TRIGGEREVENTINE (user_TRCC405TRIGGEREVENTINE));
1383
PPC405
1384
PULLDOWN
PULLDOWN
Resistor to GND for Input Pads
PULLDOWN Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
PULLDOWN resistor elements are connected to input, output, or bidirectional pads to guarantee a logic Low level for nodes that might float.
X3860
Usage
For HDL, the PULLDOWN design element is instantiated rather than inferred.

-- Component Declaration for PULLDOWN should be placed -- after architecture statement but before begin keyword component PULLDOWN port (O : out STD_ULOGIC); end component; -- Component Attribute specification for PULLDOWN -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for PULLDOWN should be placed -- in architecture after the begin keyword PULLDOWN_INSTANCE_NAME : PULLDOWN port map (O => user_O);

PULLDOWN instance_name (.O (user_O));

None
1385
PULLDOWN
1386
PULLUP
PULLUP
Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
PULLUP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive No Primitive* Primitive
* Supported only on input-only pins for CoolRunner XPLA3.
The pull-up elements establish a High logic level for open-drain elements and macros (DECODE, WAND, WORAND) or 3-state nodes (TBUF) when all the drivers are off. The buffer outputs are connected together as a wired-AND to form the output (O). When all the inputs are High, the output is off. To establish an output High level, a PULLUP resistor(s) is tied to output (O). One PULLUP resistor uses the least power, two pull-up resistors achieve the fastest Low-to-High speed.
X3861
To indicate two PULLUP resistors, append a DOUBLE parameter to the pull-up symbol attached to the output (O) node. See the appropriate CAE tool interface user guide for details.
Usage
For HDL, the PULLUP design element is instantiated rather than inferred.

-- Component Declaration for PULLUP should be placed -- after architecture statement but before begin keyword component PULLUP port (O : out STD_ULOGIC); end component; -- Component Attribute specification for PULLUP -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for PULLUP should be placed -- in architecture after the begin keyword PULLUP_INSTANCE_NAME : PULLUP
1387
PULLUP
port map (O => user_O);

PULLUP instance_name (.O (user_O));

DOUBLE HBLKNM
1388
RAM16X1D
RAM16X1D
16-Deep by 1-Wide Static Dual Port Synchronous RAM
RAM16X1D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
WE D WCLK A0 A1 A2 A3 DPRA0 DPRA1 DPRA2 DPRA3
RAM16X1D
SPO DPO
RAM16X1D is a 16-word by 1-bit static dual port random access memory with synchronous write capability. The device has two separate address ports: the read address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports are completely asynchronous. The read address controls the location of the data driven out of the output pin (DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D) into the word selected by the 4-bit write address. For predictable performance, write address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an activeHigh WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D X X X D X SPO data_a data_a data_a D data_a Outputs DPO data_d data_d data_d data_d data_d
X4950
data_a = word addressed by bits A3-A0 data_d = word addressed by bits DPRA3-DPRA0
The SPO output reflects the data in the memory cell addressed by A3 A0. The DPO output reflects the data in the memory cell addressed by DPRA3 DPRA0. Note: The write process is not affected by the address on the read address port.
1389
RAM16X1D
Specifying Initial Contents of a RAM

You can use the INIT attribute to specify an initial value directly on the symbol if the RAM is 1 bit wide and 16, 32, 64, or 128 bits deep. The value must be a hexadecimal number, for example, INIT=ABAC. If the INIT attribute is not specified, the RAM is initialized with zero. For Virtex, Virtex-E, Spartan-II, and Spartan-IIE, lower INIT values get mapped to the G function generator and upper INIT values get mapped to the F function generator. See the "INIT" section of the Constraints Guide for more information on the INIT attribute. For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, wide RAMs (2, 4, and 8-bit wide single port synchronous RAMs with a WCLK) can also be initialized. These RAMs, however, require INIT_xx attributes. See Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM in the RAM16X2S section for more information on initializing Virtex-II wide RAM.
Usage
For HDL, this design element can be inferred or instantiated. The instantiation code is shown below. For information on how to infer RAM, see the XST User Guide.

-- Component Declaration for RAM16X1D should be placed -- after architecture statement but before begin keyword component RAM16X1D -- synthesis translate_off generic (INIT : bit_vector := X"16"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM16X1D -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM16X1D should be placed -- in architecture after the begin keyword
1390
RAM16X1D
RAM16X1D_INSTANCE_NAME : RAM16X1D -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (DPO => user_DPO, SPO => user_SPO, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, D => user_D, DPRA0 => user_DPRA0, DPRA1 => user_DPRA1, DPRA2 => user_DPRA2, DPRA3 => user_DPRA3, WCLK => user_WCLK, WE => user_WE);

RAM16X1D instance_name (.DPO (user_DPO), .SPO (user_SPO), .A0(user_A0), .A1(user_A1), .A2(user_A2), .A3(user_A3), .D (user_D), .DPRA0(user_DPRA0), .DPRA1(user_DPRA1), .DPRA2(user_DPRA2), .DPRA3(user_DPRA3), .WCLK(user_WCLK), .WE (user_WE)); defparam RAM16X1D_instance_name.INIT = hex_value;

BLKNM HBLKNM HU_SET INIT LOC RLOC U_SET XBLKNM
1391
RAM16X1D
1392
RAM16X1D_1
RAM16X1D_1
16-Deep by 1-Wide Static Dual Port Synchronous RAM with NegativeEdge Clock
RAM16X1D_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
WE RAM16X1D_1 SPO D DPO WCLK A0 A1 A2 A3 DPRA0 DPRA1 DPRA2 DPRA3
RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock. The device has two separate address ports: the read address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports are completely asynchronous. The read address controls the location of the data driven out of the output pin (DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any negative transition on WCLK loads the data on the data input (D) into the word selected by the 4-bit write address. For predictable performance, write address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an activeHigh WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. You can initialize RAM16X1D_1 during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
X8419
1393
RAM16X1D_1
Usage

-- Component Declaration for RAM16X1D_1 should be placed --- after architecture statement but before begin keyword component RAM16X1D_1 -- synthesis translate_off generic (INIT: bit_vector := X"16"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM16X1D_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM16X1D_1 should be placed -- in architecture after the begin keyword RAM16X1D_1_INSTANCE_NAME : RAM16X1D_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (DPO => user_DPO, SPO => user_SPO, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, D => user_D, DPRA0 => user_DPRA0, DPRA1 => user_DPRA1, DPRA2 => user_DPRA2, DPRA3 => user_DPRA3, WCLK => user_WCLK, WE => user_WE);
1394
RAM16X1D_1

RAM16X1D_1 instance_name (.DPO (user_DPO), .SPO (user_SPO), .A0(user_A0), .A1(user_A1), .A2(user_A2), .A3(user_A3), .D (user_D), .DPRA0(user_DPRA0), .DPRA1(user_DPRA1), .DPRA2(user_DPRA2), .DPRA3(user_DPRA3), .WCLK(user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

1395
RAM16X1D_1
1396
RAM16X1S
RAM16X1S
16-Deep by 1-Wide Static Synchronous RAM
RAM16X1S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
WE D WCLK A0 A1 A2 A3
RAM16X1S
X4942
RAM16X1S is a 16-word by 1-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D) into the word selected by the 4-bit address (A3 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins. You can initialize RAM16X1S during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
Inputs WE(mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D X X X D X
Outputs O Data Data Data D Data
Data = word addressed by bits A3 A0
Usage
1397
RAM16X1S

-- Component Declaration for RAM16X1S should be placed -- after architecture statement but before begin keyword component RAM16X1S -- synthesis translate_off generic (INIT: bit_vector := X"16"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM16X1S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM16X1S should be placed -- in architecture after the begin keyword RAM16X1S_INSTANCE_NAME : RAM16X1S -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, D => user_D, WCLK => user_WCLK, WE => user_WE);

RAM16X1S instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

BEL, BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM
1398
RAM16X1S_1
RAM16X1S_1
16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
RAM16X1S_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
WE RAM16X1S_1 D WCLK A0 A1 A2 A3
X9458
RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any negative transition on WCLK loads the data on the data input (D) into the word selected by the 4-bit address (A3 A0). For predictable performance, address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an active-Low WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins. You can initialize RAM16X1S_1 during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
Inputs WE(mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D X X X D X
Usage
1399
RAM16X1S_1

-- Component Declaration for RAM16X1S_1 should be placed -- after architecture statement but before begin keyword component RAM16X1S_1 -- synthesis translate_off generic (INIT : bit_vector := X"16"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM16X1S_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM16X1S_1 should be placed -- in architecture after the begin keyword RAM16X1S_1_INSTANCE_NAME : RAM16X1S_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, D => user_D, WCLK => user_WCLK, WE => user_WE);

RAM16X1S_1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

BEL
1400
RAM16X1S_1
1401
RAM16X1S_1
1402
RAM16X2D
RAM16X2D
RAM16X2D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro No No No
WE D0 D1 WCLK A0 A1 A2 A3 DPRA0 DPRA1 DPRA2 DPRA3
RAM16X2D
SPO0 SPO1 DPO0 DPO1
RAM16X2D is a 16-word by 2-bit static dual port random access memory with synchronous write capability. The device has two separate address ports: the read address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports are completely asynchronous. The read address controls the location of data driven out of the output pin (DPO1 DPO0), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D1 D0) into the word selected by the 4-bit write address. For predictable performance, write address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The initial contents of RAM16X2D cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
X4951
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D1-D0 X X X D1-D0 X
Outputs SPO1-SPO0 data_a data_a data_a D1-D0 data_a DPO1-DPO0 data_d data_d data_d data_d data_d
1403
RAM16X2D
User
For HDL, this design element is inferred. See the XST User Guide for details.
1404
RAM16X2S
RAM16X2S
RAM16X2S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Primitive Macro No No No
WE D0 D1 WCLK A0 A1 A2 A3
RAM16X2S O0
O1
RAM16X2S is a 16-word by 2-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D1 D0) into the word selected by the 4-bit address (A3 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pins (O1 O0) is the data that is stored in the RAM at the location defined by the values on the address pins. Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of RAM16X2S cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 and INIT_01 properties to specify the initial contents of RAM16X2S as described in Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM in this section. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1(read) 1(read) 1(write) 1 (read) WCLK X 0 1 D1-D0 X X X D1-D0 X Outputs O1-O0 Data Data Data D1-D0 Data
X4944
1405
RAM16X2S
Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM
You can use the INIT_xx properties to specify the initial contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X wide RAM. INIT_00 initializes the RAM cells corresponding to the O0 output, INIT_01 initializes the cells corresponding to the O1 output, etc. For example, a RAM16X2S instance is initialized by INIT_00 and INIT_01 containing 4 hex characters each. A RAM16X8S instance is initialized by eight properties INIT_00 through INIT_07 containing 4 hex characters each. A RAM64x2S instance is completely initialized by two properties INIT_00 and INIT_01 containing 16 hex characters each. See the INIT_xx section of the Constraints Guide for more information on the INIT_xx attribute.
Usage

-- Component Declaration for RAM16X2S should be placed -- after architecture statement but before begin keyword component RAM16X2S -- synthesis translate_off generic (INIT_00 : bit_vector := X"16"; INIT_01: bit_vector := X"16"); -- synthesis translate_on port (O0 : out STD_ULOGIC; O1 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM16X2S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM16X2S should be placed -- in architecture after the begin keyword RAM16X2S_INSTANCE_NAME : RAM16X2S -- synthesis translate_off generic map (INIT_00 => hex_value, INIT_01 => hex_value) -- synthesis translate_on port map (O0 => user_O0,
1406
RAM16X2S
O1 => user_O1, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, D0 => user_D0, D1 => user_D1, WCLK => user_WCLK, WE => user_WE);

RAM16X2S instance_name (.O0 (user_O0), .O1 (user_O1), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3) .D0 (user_D0), .D1 (user_D1), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT_00 = hex_value; defparam user_instance_name.INIT_01 = hex_value;

BEL INIT_xx BLKNM HBLKNM HU_SET INIT LOC RLOC U_SET XBLKNM
1407
RAM16X2S
1408
RAM16X4D
RAM16X4D
WE D0 D1 D2 D3 WCLK A0 A1 A2 A3 DPRA0 DPRA1 DPRA2 DPRA3
RAM16X4D
SPO0 SPO1 SPO2 SPO3 DPO0 DPO1 DPO2 DPO3
RAM16X4D is a 16-word by 4-bit static dual port random access memory with synchronous write capability. The device has two separate address ports: the read address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports are completely asynchronous. The read address controls the location of data driven out of the output pin (DPO3 DPO0), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D3 D0) into the word selected by the 4-bit write address. For predictable performance, write address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The initial contents of RAM16X4D cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D3-D0 X X X D3-D0 X Outputs SPO3-SPO0 data_a data_a data_a D3-D0 data_a DPO3-DPO0 data_d data_d data_d data_d data_d
X4952
1409
RAM16X4D
Usage
For HDL, this design element must be inferred. For information on how to infer RAM, see the XST User Guide.
1410
RAM16X4D
1411
RAM16X4D
1412
RAM16X4S
RAM16X4S
WE D0 D1 D2 D3 WCLK A0 A1 A2 A3
RAM16X4S
O0 O1 O2 O3
RAM16X4S is a 16-word by 4-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D3 D0) into the word selected by the 4-bit address (A3 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pins (O3 O0) is the data that is stored in the RAM at the location defined by the values on the address pins. Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of RAM16X4S cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use INIT_00 through INIT_03 to specify the initial contents of RAM16X4S as described in the Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAMsection in the RAM16X2S section. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D3 D0 X X X D3-D0 X Outputs O3 O0 Data Data Data D3-D0 Data
X4945
1413
RAM16X4S
Usage

-- Component Declaration for RAM16X4S should be placed -- after architecture statement but before begin keyword component RAM16X4S -- synthesis translate_off generic (INIT_00 : bit_vector INIT_01 : bit_vector INIT_02 : bit_vector INIT_03 : bit_vector -- synthesis translate_on port (O0 : out STD_ULOGIC; O1 : out STD_ULOGIC; O2 : out STD_ULOGIC; O3 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
:= := := :=
X"16"; X"16"; X"16"; X"16");
-- Component Attribute specification for RAM16X4S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM16X4S should be placed -- in architecture after the begin keyword RAM16X4S_INSTANCE_NAME : RAM16X4S -- synthesis translate_off generic map (INIT_00 => hex_value, INIT_01 => hex_value, INIT_02 => hex_value, INIT_03 => hex_value) -- synthesis translate_on port map (O0 => user_O0, O1 => user_O1, O2 => user_O2, O3 => user_O3, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3,
1414
RAM16X4S
D0 => user_D0, D1 => user_D1, D2 => user_D2, D3 => user_D3, WCLK => user_WCLK, WE => user_WE);

RAM16X4S instance_name (.O0 (user_O0), .O1 (user_O1), .O2 (user_O2), .O3 (user_O3), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .D0 (user_D0), .D1 (user_D1), .D2 (user_D2), .D3 (user_D3), .WCLK (user_WCLK), .WE (user_WE)); defparam defparam defparam defparam user_instance_name.INIT_00 user_instance_name.INIT_01 user_instance_name.INIT_02 user_instance_name.INIT_03 = = = = hex_value; hex_value; hex_value; hex_value;

1415
RAM16X4S
1416
RAM16X8D
RAM16X8D
D[7:0] WE WCLK A0 A1 A2 A3 DPRA0 DPRA1 DPRA2 DPRA3
RAM16X8D
SPO[7:0] DPO[7:0]
RAM16X8D is a 16-word by 8-bit static dual port random access memory with synchronous write capability. The device has two separate address ports: the read address (DPRA3 DPRA0) and the write address (A3 A0). These two address ports are completely asynchronous. The read address controls the location of data driven out of the output pin (DPO7 DPO0), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D7 D0) into the word selected by the 4-bit write address (A3 A0). For predictable performance, write address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The initial contents of RAM16X8D cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D7-D0 X X X D7-D0 X Outputs SP7-SPO0 data_a data_a data_a D7-D0 data_a DPO7-DPO0 data_d data_d data_d data_d data_d
X9781
The SPO output reflects the data in the memory cell addressed by A3 A0. The DPO output reflects the data in the memory cell addressed by DPRA3 DPRA0. The write process is not affected by the address on the read address port.
1417
RAM16X8D
Usage
For HDL, this design element must be inferred. For information on how to infer RAM, see the XST User Guide.
1418
RAM16X8D
1419
RAM16X8D
1420
RAM16X8S
RAM16X8S
RAM16X8S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro No No No
D[7:0] WE WCLK A0 A1 A2 A3
RAM16X8S
O[7:0]
X9782
RAM16X8S is a 16-word by 8-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on data inputs (D7 D0) into the word selected by the 4-bit address (A3 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pins (O7 O0) is the data that is stored in the RAM at the location defined by the values on the address pins. Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of RAM16X8S cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use INIT_00 through INIT_07 to specify the initial contents of RAM16X8S as described in the Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM section in the RAM16X2S section. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D7-D0 X X X D7-D0 X Outputs O7-O0 Data Data Data D7-D0 Data
1421
RAM16X8S
Usage
1422
RAM16X8S

-- Component Declaration for RAM16X8S should be placed -- after architecture statement but before begin keyword component RAM16X8S -- synthesis translate_off generic (INIT_00 : bit_vector INIT_01 : bit_vector INIT_02 : bit_vector INIT_03 : bit_vector INIT_04 : bit_vector INIT_05 : bit_vector INIT_06 : bit_vector INIT_07 : bit_vector -- synthesis translate_on port (O0 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
:= := := := := := := :=
X"16"; X"16"; X"16"; X"16"; X"16"; X"16"; X"16"; X"16");
-- Component Attribute specification for RAM16X8S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here -- Component Instantiation for RAM16X8S should be placed -- in architecture after the begin keyword RAM16X8S_INSTANCE_NAME : RAM16X8S -- synthesis translate_off generic map (INIT_00 => hex_value, INIT_01 => hex_value, INIT_02 => hex_value, INIT_03 => hex_value, INIT_04 => hex_value, INIT_05 => hex_value, INIT_06 => hex_value, INIT_07 => hex_value) -- synthesis translate_on port map (O0 => user_O0, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, D => user_D, WCLK => user_WCLK, WE => user_WE);
1423
RAM16X8S

RAM16X8S instance_name (.O0 (user_O0), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.INIT_00 user_instance_name.INIT_01 user_instance_name.INIT_02 user_instance_name.INIT_03 user_instance_name.INIT_04 user_instance_name.INIT_05 user_instance_name.INIT_06 user_instance_name.INIT_07 = = = = = = = = hex_value; hex_value; hex_value; hex_value; hex_value; hex_value; hex_value; hex_value;

1424
RAM32X1D
RAM32X1D
32-Deep by 1-Wide Static Dual Static Port Synchronous RAM
RAM32X1D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
WE D WCLK A0 A1 A2 A3 A4 DPRA0 DPRA1 DPRA2 DPRA3 DPRA4
RAM32x1D SPO DPO
RAM32X1D is a 32-word by 1-bit static dual port random access memory with synchronous write capability. The device has two separate address ports: the read address (DPRA4 DPRA0) and the write address (A4 A0). These two address ports are completely asynchronous. The read address controls the location of the data driven out of the output pin (DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D) into the word selected by the 5-bit write address. For predictable performance, write address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an activeHigh WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. You can initialize RAM32X1D during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
X9261
1425
RAM32X1D
Usage

-- Component Declaration for RAM32X1D should be placed -- after architecture statement but before begin keyword component RAM32X1D -- synthesis translate_off generic (INIT : bit_vector := X"32"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; DPRA4 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM32X1D -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM32X1D should be placed -- in architecture after the begin keyword RAM32X1D_INSTANCE_NAME : RAM32X1D -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (DPO => user_DPO, SPO => user_SPO, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, D => user_D, DPRA0 => user_DPRA0, DPRA1 => user_DPRA1, DPRA2 => user_DPRA2, DPRA3 => user_DPRA3, DPRA4 => user_DPRA4,
1426
RAM32X1D
WCLK => user_WCLK, WE => user_WE);

RAM32X1D instance_name (.DPO (user_DPO), .SPO (user_SPO), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3( user_A3), .A4 (user_A4), .D (user_D), .DPRA0 (user_DPRA0), .DPRA1 (user_DPRA1), .DPRA2 (user_DPRA2), .DPRA3 (user_DPRA3), .DPRA4 (user_DPRA4), .WCLK (user_WCLK), .WE (user_WE)); defparam RAM32X1D_instance_name.INIT = hex_value;

1427
RAM32X1D
1428
RAM32X1D_1
RAM32X1D_1
32-Deep by 1-Wide Static Dual Port Synchronous RAM with NegativeEdge Clock
RAM32X1D_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
WE RAM32x1D_1 SPO D WCLK A0 A1 A2 A3 A4 DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 X9262 DPO
RAM32X1D_1 is a 32-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock. The device has two separate address ports: the read address (DPRA4 DPRA0) and the write address (A4 A0). These two address ports are completely asynchronous. The read address controls the location of the data driven out of the output pin (DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any negative transition on WCLK loads the data on the data input (D) into the word selected by the 5-bit write address. For predictable performance, write address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an activeLow WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. You can initialize RAM32X1D_1 during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
1429
RAM32X1D_1
Usage

-- Component Declaration for RAM32X1D_1 should be placed -- after architecture statement but before begin keyword component RAM32X1D_1 -- synthesis translate_off generic (INIT : bit_vector := X"32"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; DPRA4 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM32X1D_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM32X1D_1 should be placed -- in architecture after the begin keyword RAM32X1D_1_INSTANCE_NAME : RAM32X1D_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (DPO => user_DPO, SPO => user_SPO, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, D => user_D, DPRA0 => user_DPRA0, DPRA1 => user_DPRA1, DPRA2 => user_DPRA2, DPRA3 => user_DPRA3, DPRA4 => user_DPRA4,
1430
RAM32X1D_1
WCLK => user_WCLK, WE => user_WE);

RAM32X1D_1 instance_name (.DPO (user_DPO), .SPO (user_SPO), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .D (user_D), .DPRA0 (user_DPRA0), .DPRA1 (user_DPRA1), .DPRA2 (user_DPRA2), .DPRA3 (user_DPRA3), .DPRA4 (user_DPRA4), .WCLK (user_WCLK), .WE (user_WE)); defparam RAM32X1D_1_instance_name.INIT = hex_value;

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM
1431
RAM32X1D_1
1432
RAM32X1S
RAM32X1S
RAM32X1S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
WE D WCLK A0 A1 A2 A3 A4
RAM32X1S
X4943
RAM32X1S is a 32-word by 1-bit static random access memory with synchronous write capability. When the write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D) into the word selected by the 5-bit address (A4 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins. You can initialize RAM32X1S during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D X X X D X Outputs O Data Data Data D Data
Usage
1433
RAM32X1S

-- Component Declaration for RAM32X1S should be placed -- after architecture statement but before begin keyword component RAM32X1S -- synthesis translate_off generic (INIT : bit_vector := X"32"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A4 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM32X1S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here -- Component Instantiation for RAM32X1S should be placed -- in architecture after the begin keyword RAM32X1S_INSTANCE_NAME : RAM32X1S -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, D => user_D, WCLK => user_WCLK, WE => user_WE);

RAM32X1S instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM
1434
RAM32X1S_1
RAM32X1S_1
RAM32X1S_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
WE RAM32X1S_1 D WCLK A0 A1 A2 A3 A4
X8417
RAM32X1S_1 is a 32-word by 1-bit static random access memory with synchronous write capability. When the write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any negative transition on WCLK loads the data on the data input (D) into the word selected by the 5-bit address (A4 A0). For predictable performance, address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an active-Low WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins. You can initialize RAM32X1S_1 during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D X X X D X
Usage
1435
RAM32X1S_1

-- Component Declaration for RAM32X1S_1 should be placed -- after architecture statement but before begin keyword component RAM32X1S_1 -- synthesis translate_off generic (INIT : bit_vector := X"32"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A4 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM32X1S_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM32X1S_1 should be placed -- in architecture after the begin keyword RAM32X1S_1_INSTANCE_NAME : RAM32X1S_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, D => user_D, WCLK => user_WCLK, WE => user_WE);
1436
RAM32X1S_1

RAM32X1S_1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

1437
RAM32X1S_1
1438
RAM32X2S
RAM32X2S
WE D0 D1 WCLK A0 A1 A2 A3 A4
RAM32X2S
O0 O1
RAM32X2S is a 32-word by 2-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D1 D0) into the word selected by the 5-bit address (A4 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pins (O1 O0) is the data that is stored in the RAM at the location defined by the values on the address pins. Except for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of RAM32X2S cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. For Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 and INIT_01 properties to specify the initial contents of RAM32X2S as described in Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM in the RAM16X2S section. Mode selection is shown in the following truth table.
X4947
1439
RAM32X2S
Usage
1440
RAM32X2S

-- Component Declaration for RAM32X2S should be placed -- after architecture statement but before begin keyword component RAM32X2S -- synthesis translate_off generic (INIT_00 : bit_vector := X"32"; INIT_01 : bit_vector := X"32"); -- synthesis translate_on port (O0 : out STD_ULOGIC; O1 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM32X2S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM32X2S should be placed -- in architecture after the begin keyword RAM32X2S_INSTANCE_NAME : RAM32X2S -- synthesis translate_off generic map (INIT_00 => hex_value, INIT_01 => hex_value) -- synthesis translate_on port map (O0 => user_O0, O1 => user_O1, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, D0 => user_D0, D1 => user_D1, WCLK => user_WCLK, WE => user_WE);
1441
RAM32X2S

RAM32X2S instance_name (.O0 (user_O0), .O1 (user_O1), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .D0 (user_D0), .D1 (user_D1), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT_00 = hex_value; defparam user_instance_name.INIT_01 = hex_value;

INIT_xx BLKNM HBLKNM HU_SET INIT LOC RLOC U_SET XBLKNM
1442
RAM32X4S
RAM32X4S
WE D0 D1 D2 D3 WCLK A0 A1 A2 A3 A4
RAM32X4S
O0 O1 O2 O3
RAM32X4S is a 32-word by 4-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data inputs (D3 D0) into the word selected by the 5-bit address (A4 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pins (O3 O0) is the data that is stored in the RAM at the location defined by the values on the address pins.
X4948
Except for Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of RAM32X4S cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 through INIT_03 properties to specify the initial contents of RAM32X4S as described in Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM in the RAM16X2S section. Mode selection is shown in the following truth table.
Inputs WE 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D3-D0 X X X D3-D0 X Outputs O3-O0 Data Data Data D3-D0 Data
1443
RAM32X4S
Usage
1444
RAM32X4S

-- Component Declaration for RAM32X4S should be placed -- after architecture statement but before begin keyword component RAM32X4S -- synthesis translate_off generic (INIT_00 : bit_vector INIT_01 : bit_vector INIT_02 : bit_vector INIT_03 : bit_vector -- synthesis translate_on port (O0 : out STD_ULOGIC; O1 : out STD_ULOGIC; O2 : out STD_ULOGIC; O3 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
:= := := :=
X"32"; X"32"; X"32"; X"32");
-- Component Instantiation for RAM32X4S should be placed -- in architecture after the begin keyword RAM32X4S_INSTANCE_NAME : RAM32X4S -- synthesis translate_off generic map (INIT_00 => hex_value, INIT_01 => hex_value, INIT_02 => hex_value, INIT_03 => hex_value) -- synthesis translate_on port map (O0 => user_O0, O1 => user_O1, O2 => user_O2, O3 => user_O3, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, D0 => user_D0, D1 => user_D1, D2 => user_D2,
1445
RAM32X4S
D3 => user_D3, WCLK => user_WCLK, WE => user_WE);

RAM32X4S instance_name (.O0 (user_O0), .O1 (user_O1), .O2 (user_O2), .O3 (user_O3), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .D0 (user_D0), .D1 (user_D1), .D2 (user_D2), .D3 (user_D3), .WCLK (user_WCLK), .WE (user_WE)); defparam defparam defparam defparam user_instance_name.INIT_00 user_instance_name.INIT_01 user_instance_name.INIT_02 user_instance_name.INIT_03 = = = = hex_value; hex_value; hex_value; hex_value;

INIT_xx BLKNM HBLKNM HU_SET INIT LOC RLOC U_SET XBLKNM
1446
RAM32X8S
RAM32X8S
D[7:0] WE WCLK A0 A1 A2 A3 A4
RAM32X8S
O[7:0]
RAM32X8S is a 32-word by 8-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data inputs (D7 D0) into the word selected by the 5-bit address (A4 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pins (O7 O0) is the data that is stored in the RAM at the location defined by the values on the address pins. Except for Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the initial contents of RAM32X8S cannot be specified directly. See Specifying Initial Contents of a RAM in the RAM16X1D section. For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, you can use the INIT_00 through INIT_07 properties to specify the initial contents of RAM32X8S as described in Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM in the RAM16X2S section. Mode selection is shown in the following truth table.
X9780
1447
RAM32X8S
O[7:0]
RAM32X1S
D0 WE O D WCLK A0 A1 A2 A3 A4 O0 O0 D4
RAM32X1S
O WE D WCLK A0 A1 A2 A3 A4 O4 O4
RAM32X1S
D1 O WE D WCLK A0 A1 A2 A3 A4 O1 O1 D5
RAM32X1S
WE O D WCLK A0 A1 A2 A3 A4 O5 O5
RAM32X1S
RAM32X1S
O WE D WCLK A0 A1 A2 A3 A4 O6 O6
RAM32X1S
RAM32X1S
O WE D WCLK A0 A1 A2 A3 A4 O7
O7
D[7:0] WE WCLK A0 A1 A2 A3 A4
X6417
RAM32X8S Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
Usage
1448
RAM32X8S

-- Component Declaration for RAM32X8S should be placed -- after architecture statement but before begin keyword component RAM32X8S -- synthesis translate_off generic (INIT_00 : bit_vector INIT_01 : bit_vector INIT_02 : bit_vector INIT_03 : bit_vector INIT_04 : bit_vector INIT_05 : bit_vector INIT_06 : bit_vector INIT_07 : bit_vector -- synthesis translate_on port (O0 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
:= := := := := := := :=
X"32"; X"32"; X"32"; X"32"; X"32"; X"32"; X"32"; X"32");
-- Component Instantiation for RAM32X8S should be placed -- in architecture after the begin keyword RAM32X8S_INSTANCE_NAME : RAM32X8S -- synthesis translate_off generic map (INIT_00 => hex_value, INIT_01 => hex_value, INIT_02 => hex_value, INIT_03 => hex_value, INIT_04 => hex_value, INIT_05 => hex_value, INIT_06 => hex_value, INIT_07 => hex_value) -- synthesis translate_on port map (O0 => user_O0, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, D => user_D, WCLK => user_WCLK, WE => user_WE);
1449
RAM32X8S

RAM32X8S instance_name (.O0 (user_O0), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.INIT_00 user_instance_name.INIT_01 user_instance_name.INIT_02 user_instance_name.INIT_03 user_instance_name.INIT_04 user_instance_name.INIT_05 user_instance_name.INIT_06 user_instance_name.INIT_07 = = = = = = = = hex_value; hex_value; hex_value; hex_value; hex_value; hex_value; hex_value; hex_value;

BLKNM HBLKNM HU_SET INIT INIT_xx LOC RLOC U_SET XBLKNM
1450
RAM32X8S
1451
RAM32X8S
1452
RAM64X1D
RAM64X1D
64-Deep by 1-Wide Dual Port Static Synchronous RAM
RAM64X1D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
WE D WCLK A0 A1 A2 A3 A4 A5 DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5
RAM64x1D SPO DPO
RAM64X1D is a 64-word by 1-bit static dual port random access memory with synchronous write capability. The device has two separate address ports: the read address (DPRA5 DPRA0) and the write address (A5 A0). These two address ports are completely asynchronous. The read address controls the location of the data driven out of the output pin (DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D) into the word selected by the 6-bit (A0 - A5) write address. For predictable performance, write address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. You can initialize RAM64X1D during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
X9263
1453
RAM64X1D
Usage

-- Component Declaration for RAM64X1D should be placed -- after architecture statement but before begin keyword component RAM64X1D -- synthesis translate_off generic (INIT : bit_vector -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; DPRA4 : in STD_ULOGIC; DPRA5 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
:= X"64");
-- Component Attribute specification for RAM64X1D -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM64X1D should be placed -- in architecture after the begin keyword RAM64X1D_INSTANCE_NAME : RAM64X1D -- synthesis translate_off generic map(INIT => hex_value) -- synthesis translate_on port map (DPO => user_DPO, SPO => user_SPO, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, D => user_D, DPRA0 => user_DPRA0, DPRA1 => user_DPRA1,
1454
RAM64X1D
DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
=> => => => => =>
user_DPRA2, user_DPRA3, user_DPRA4, user_DPRA5, user_WCLK, user_WE);

RAM64X1D instance_name (.DPO (user_DPO), .SPO (user_SPO), .A0(user_A0), .A1(user_A1), .A2(user_A2), .A3(user_A3), .A4(user_A4), .A5(user_A5), .D (user_D), .DPRA0(user_DPRA0), .DPRA1(user_DPRA1), .DPRA2(user_DPRA2), .DPRA3(user_DPRA3), .DPRA4(user_DPRA4), .DPRA5(user_DPRA5), .WCLK(user_WCLK), .WE (user_WE)); defparam RAM64X1D_instance_name.INIT = hex_value;

1455
RAM64X1D
1456
RAM64X1D_1
RAM64X1D_1
64-Deep by 1-Wide Dual Port Static Synchronous RAM with NegativeEdge Clock
RAM64X1D_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
WE RAM64x1D_1 SPO D WCLK A0 A1 A2 A3 A4 A5 DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 X9264 DPO
RAM64X1D_1 is a 64-word by 1-bit static dual port random access memory with synchronous write capability and a negative-edge clock. The device has two separate address ports: the read address (DPRA5 DPRA0) and the write address (A5 A0). These two address ports are completely asynchronous. The read address controls the location of the data driven out of the output pin (DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any negative transition on WCLK loads the data on the data input (D) into the word selected by the 6-bit (A0 - A5) write address. For predictable performance, write address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an active-Low WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block. You can initialize RAM64X1D_1 during configuration using the INIT attribute. See Specifying Initial Contents of a RAM in the RAM16X1D section. Mode selection is shown in the following truth table.
1457
RAM64X1D_1
Usage

-- Component Declaration for RAM64X1D_1 should be placed -- after architecture statement but before begin keyword component RAM64X1D_1 -- synthesis translate_off generic (INIT : bit_vector -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; DPRA4 : in STD_ULOGIC; DPRA5 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
:= X"64");
-- Component Attribute specification for RAM64X1D_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM64X1D_1 should be placed -- in architecture after the begin keyword RAM64X1D_1_INSTANCE_NAME : RAM64X1D_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (DPO => user_DPO, SPO => user_SPO, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, D => user_D, DPRA0 => user_DPRA0, DPRA1 => user_DPRA1,
1458
RAM64X1D_1
DPRA2 => user_DPRA2, DPRA3 => user_DPRA3, DPRA4 => user_DPRA4, DPRA5 => user_DPRA5, WCLK => user_WCLK, WE => user_WE);

RAM64X1D_1 instance_name (.DPO (user_DPO), .SPO (user_SPO), .A0(user_A0), .A1(user_A1), .A2(user_A2), .A3(user_A3), .A4(user_A4), .A5(user_A5), .D (user_D), .DPRA0(user_DPRA0), .DPRA1(user_DPRA1), .DPRA2(user_DPRA2), .DPRA3(user_DPRA3), .DPRA4(user_DPRA4), .DPRA5(user_DPRA5), .WCLK(user_WCLK), .WE (user_WE)); defparam RAM64X1D_1_instance_name.INIT = hex_value;

1459
RAM64X1D_1
1460
RAM64X1S
RAM64X1S
RAM64X1S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
WE D WCLK A0 A1 A2 A3 A4 A5
RAM64x1S O
X9265
Inputs WE (mode) 0 (read) 1 (read) 1 (read) 1 (write) 1 (read) WCLK X 0 1 D X X X D X
Usage
1461
RAM64X1S

-- Component Declaration for RAM64X1S should be placed -- after architecture statement but before begin keyword component RAM64X1S -- synthesis translate_off generic (INIT : bit_vector := X"64"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM64X1S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM64X1S should be placed -- in architecture after the begin keyword RAM64X1S_INSTANCE_NAME : RAM64X1S -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, D => user_D, WCLK => user_WCLK, WE => user_WE);
1462
RAM64X1S

RAM64X1S instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5(user_A5), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

1463
RAM64X1S
1464
RAM64X1S_1
RAM64X1S_1
RAM64X1S_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
WE RAM64x1S_1 O D WCLK A0 A1 A2 A3 A4 A5 X9266
Usage
1465
RAM64X1S_1

-- Component Declaration for RAM64X1S_1 should be placed -- after architecture statement but before begin keyword component RAM64X1S_1 -- synthesis translate_off generic (INIT : bit_vector := X"64"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM64X1S_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM64X1S_1 should be placed -- in architecture after the begin keyword RAM64X1S_1_INSTANCE_NAME : RAM64X1S_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, D => user_D, WCLK => user_WCLK, WE => user_WE);
1466
RAM64X1S_1

RAM64X1S_1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5(user_A5), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

1467
RAM64X1S_1
1468
RAM64X2S
RAM64X2S
RAM64X2S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
WE D0 D1 WCLK A0 A1 A2 A3 A4 A5
RAM64x2S O0 O1
RAM64X2S is a 64-word by 2-bit static random access memory with synchronous write capability. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input (D1 D0) into the word selected by the 6-bit address (A5 A0). For predictable performance, address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK can be active-High or activeLow. Any inverter placed on the WCLK input net is absorbed into the block. The signal output on the data output pins (O1 O0) is the data that is stored in the RAM at the location defined by the values on the address pins. You can use the INIT_00 and INIT_01 properties to specify the initial contents of RAM64X2S as described in Specifying Initial Contents of a Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X Wide RAM in the RAM16X2S section. Mode selection is shown in the following truth table.
X9410
Usage
1469
RAM64X2S

-- Component Declaration for RAM64X2S should be placed -- after architecture statement but before begin keyword component RAM64X2S -- synthesis translate_off generic (INIT_00 : bit_vector := X"64"; INIT_01 : bit_vector := X"64"); -- synthesis translate_on port (O0 : out STD_ULOGIC; O1 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM64X2S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM64X2S should be placed -- in architecture after the begin keyword RAM64X2S_INSTANCE_NAME : RAM64X2S -- synthesis translate_off generic map (INIT_00 => hex_value, INIT_01 => hex_value) -- synthesis translate_on port map (O0 => user_O0, O1 => user_O1, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, D0 => user_D0, D1 => user_D1, WCLK => user_WCLK, WE => user_WE);
1470
RAM64X2S

RAM64X2S instance_name (.O0 (user_O0), .O1 (user_O1), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5(user_A5), .D0 (user_D0), .D1 (user_D1), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT_00 = hex_value; defparam user_instance_name.INIT_01 = hex_value;

1471
RAM64X2S
1472
RAM128X1S
RAM128X1S
RAM128X1S Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
WE D WCLK A0 A1 A2 A3 A4 A5 A6
RAM128x1S O
X9267
Usage
1473
RAM128X1S

-- Component Declaration for RAM128X1S should be placed -- after architecture statement but before begin keyword component RAM128X1S -- synthesis translate_off generic (INIT : bit_vector := X"128"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; A6 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM128X1S -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM128X1S should be placed -- in architecture after the begin keyword RAM128X1S_INSTANCE_NAME : RAM128X1S -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, A6 => user_A6, D => user_D, WCLK => user_WCLK, WE => user_WE);
1474
RAM128X1S

RAM128X1S instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5 (user_A5), .A6 (user_A6), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

1475
RAM128X1S
1476
RAM128X1S_1
RAM128X1S_1
RAM128X1S_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
WE RAM128x1S_1 O D WCLK A0 A1 A2 A3 A4 A5 A6 X9268
Usage
1477
RAM128X1S_1

-- Component Declaration for RAM128X1S_1 should be placed -- after architecture statement but before begin keyword component RAM128X1S_1 -- synthesis translate_off generic (INIT : bit_vector := X"128"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; A6 : in STD_ULOGIC; D : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; -- Component Attribute specification for RAM128X1S_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for RAM128X1S_1 should be placed -- in architecture after the begin keyword RAM128X1S_1_INSTANCE_NAME : RAM128X1S_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, A6 => user_A6, D => user_D, WCLK => user_WCLK, WE => user_WE);
1478
RAM128X1S_1

RAM128X1S_1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5 (user_A5), .A6 (user_A6), .D (user_D), .WCLK (user_WCLK), .WE (user_WE)); defparam user_instance_name.INIT = hex_value;

1479
RAM128X1S_1
1480
RAMB4_Sn
RAMB4_Sn
4096-Bit Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 8, or 16 Bits
RAMB4_Sn Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive No Primitive No No No
WE EN RST CLK ADDR[11:0] DI[0]
RAMB4_S1
DO[0]
RAMB4_S1, RAMB4_S2, RAMB4_S4, RAMB4_S8, and RAMB4_S16 are dedicated random access memory blocks with synchronous write capability. They provide the capability for fast, discrete, large blocks of RAM in each Virtex, Virtex-E, Spartan-II, and Spartan-IIE device.The RAMB4_Sn cell configurations are listed in the following table.
X8416
WE EN RST CLK ADDR[10:0] DI[1:0]
RAMB4_S2 DO[1:0]
Component RAMB4_S1 RAMB4_S2 RAMB4_S4
Depth 4096 2048 1024 512 256
Width 1 2 4 8 16
Address Bus (11:0) (10:0) (9:0) (8:0) (7:0)
Data Bus (0:0) (1:0) (3:0) (7:0) (15:0)
X8415
RAMB4_S8 RAMB4_S16
WE EN RST CLK ADDR[9:0] DI[3:0]
RAMB4_S4 DO[3:0]
X8414
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the output (DO) retains the last state. When EN is High and reset (RST) is High, DO is cleared during the Low-to-High clock (CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI. When EN is High and WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition. When EN and WE are High, the data on the data input (DI) is loaded into the word selected by the write address (ADDR) during the Low-to-High clock transition and the data output (DO) reflects the selected (addressed) word. The above description assumes an active High EN, WE, RST, and CLK. However, the active level can be changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource. RAMB4_Sn's may be initialized during configuration. See Specifying Initial Contents of a Block RAM below. Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contents of the block RAM are not altered.
1481
RAMB4_Sn
Virtex, Virtex-E, Spartan-II, and Spartan-IIE simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. Mode selection is shown in the following truth table.
Inputs EN 0 1 1 1 1 RST X 1 1 0 0 WE X 0 1 0 1 CLK X ADDR X X addr addr addr DI X X data X data DO No Chg 0 0 RAM(addr) data
Outputs RAM Contents No Chg No Chg RAM(addr) =>data No Chg RAM(addr) =>data
addr=RAM address RAM(addr)=RAM contents at address ADDR data=RAM input data
Specifying Initial Contents of a Block RAM

You can use the INIT_xx attributes to specify an initial value during device configuration. The initialization of each RAMB4_Sn is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. See the INIT_xx section of the Constraints Guide for more information on these attributes. If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Usage
VHDL Instantiation Template for RAMB4_Sn

-- Component Declaration for RAMB4_Sn -- Should be placed after architecture statement but before begin keyword component RAMB4_Sn -- synthesis translate_off generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1482
RAMB4_Sn
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; ); -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0); ADDR : in STD_LOGIC_VECTOR (11 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; RST : in STD_ULOGIC; WE : in STD_ULOGIC);
end component;
-- Component Attribute Specification for RAMB4_Sn -- Should be placed after architecture declaration but before the begin keyword
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RAMB4_Sn
-- Put attributes, if necessary
-- Component Instantiation for RAMB4_Sn -- Should be placed in architecture after the begin keyword
RAMB4_Sn_INSTANCE_NAME : RAMB4_Sn -- synthesis translate_off generic map ( INIT_00 => hex_value, INIT_01 => hex_value, INIT_02 => hex_value, INIT_03 => hex_value, INIT_04 => hex_value, INIT_05 => hex_value, INIT_06 => hex_value, INIT_07 => hex_value, INIT_08 => hex_value, INIT_09 => hex_value, INIT_0A => hex_value, INIT_0B => hex_value, INIT_0C => hex_value, INIT_0D => hex_value, INIT_0E => hex_value, INIT_0F => hex_value) -- synopsys translate_on port map (DO => user_DO, ADDR => user_ADDR, CLK => user_CLK, DI => user_DI, EN => user_EN, RST => user_RST, WE => user_WE);
Verilog Instantiation Template for RAMB4_Sn

RAMB4_Sn user_instance_name (.DO (user_DO),
1484
RAMB4_Sn
.ADDR (user_ADDR), .CLK (user_CLK), .DI (user_DI), .EN (user_EN), .RST (user_RST), .WE (user_WE));
defparam user_instance_name.INIT_00 = 256_bit_hex_value; defparam user_instance_name.INIT_01 = 256_bit_hex_value; defparam user_instance_name.INIT_02 = 256_bit_hex_value; defparam user_instance_name.INIT_03 = 256_bit_hex_value; defparam user_instance_name.INIT_04 = 256_bit_hex_value; defparam user_instance_name.INIT_05 = 256_bit_hex_value; defparam user_instance_name.INIT_06 = 256_bit_hex_value; defparam user_instance_name.INIT_07 = 256_bit_hex_value; defparam user_instance_name.INIT_08 = 256_bit_hex_value; defparam user_instance_name.INIT_09 = 256_bit_hex_value; defparam user_instance_name.INIT_0A = 256_bit_hex_value; defparam user_instance_name.INIT_0B = 256_bit_hex_value; defparam user_instance_name.INIT_0C = 256_bit_hex_value; defparam user_instance_name.INIT_0D = 256_bit_hex_value; defparam user_instance_name.INIT_0E = 256_bit_hex_value; defparam user_instance_name.INIT_0F = 256_bit_hex_value;

INIT_xx
1485
RAMB4_Sn
1486
RAMB4_Sm_Sn
RAMB4_Sm_Sn
4096-Bit Dual-Port Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 8, or 16 Bits
RAMB4_Sm_Sn Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive No Primitive No No No
1487
RAMB4_Sm_Sn
WEA ENA RSTA CLKA ADDRA[11:0] DIA[0]
RAMB4_S1_S1
WEA ENA DOA[0] RSTA CLKA ADDRA[11:0] DIA[0]
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
WEA ENA DOA[0] RSTA
RAMB4_S1_S16
DOA[0] CLKA ADDRA[11:0] DIA[0]
WEB ENB RSTB CLKB ADDRB[11:0] DIB[0] X8359 DOB[0]
WEB ENB RSTB CLKB ADDRB[10:0] DIB[1:0] X8390 DOB[1:0]
WEA ENA RSTA CLKA ADDRA[10:0] DIA[1:0]
RAMB4_S2_S2
WEA ENA DOA[1:0] RSTA CLKA ADDRA[10:0] DIA[1:0]
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
RAMB4_S4_S4
DOA[3:0]
WEA ENA RSTA CLKA ADDRA[9:0] DIA[3:0]
RAMB4_S4_S8
RAMB4_S4_S16
RAMB4_S8_S8
WEA ENA DOA[7:0] RSTA
RAMB4_S8_S16
WEA ENA RSTA DOA[7:0]
RAMB4_S16_S16
DOA[15:0] CLKA ADDRA[7:0] DIA[15:0]
CLKA ADDRA[8:0] DIA[7:0]
WEB ENB RSTB DOB[15:0] CLKB ADDRB[7:0] DIB[15:0] X8400
X8727
RAMB4_Sm_Sn Representations
1488
RAMB4_Sm_Sn
The RAMB4_Sm_Sn components listed in the following table are 4096-bit dual-ported dedicated random access memory blocks with synchronous write capability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port is independently configured to a specific data width.
Component RAMB4_S1_S1 RAMB4_S1_S2 RAMB4_S1_S4 RAMB4_S1_S8 RAMB4_S1_S16 RAMB4_S2_S2 RAMB4_S2_S4 RAMB4_S2_S8 RAMB4_S2_S16 RAMB4_S4_S4 RAMB4_S4_S8 RAMB4_S4_S16 RAMB4_S8_S8 RAMB4_S8_S16 RAMB4_S16_S16
Port A Depth 4096 4096 4096 4096 4096 2048 2048 2048 2048 1024 1024 1024 512 512 256
Port A Width 1 1 1 1 1 2 2 2 2 4 4 4 8 8 16
Port A ADDR (11:0) (11:0) (11:0) (11:0) (11:0) (10:0) (10:0) (10:0) (10:0) (9:0) (9:0) (9:0) (8:0) (8:0) (7:0)
Port A DI (0:0) (0:0) (0:0) (0:0) (0:0) (1:0) (1:0) (1:0) (1:0) (3:0) (3:0) (3:0) (7:0) (7:0) (15:0)
Port B Depth 4096 2048 1024 512 256 2048 1024 512 256 1024 512 256 512 256 256
Port B Width 1 2 4 8 16 2 4 8 16 4 8 16 8 16 16
Port B ADDR (11:0) (10:0) (9:0) (8:0) (7:0) (10:0) (9:0) (8:0) (7:0) (9:0) (8:0) (7:0) (8:0) (7:0) (7:0)
Port B DI (0:0) (1:0) (3:0) (7:0) (15:0) (1:0) (3:0) (7:0) (15:0) (3:0) (7:0) (15:0) (7:0) (15:0) (15:0)
ADDR=address bus for the port DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clockto-out time referenced to the CLKA. All port B input pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out time referenced to the CLKB. The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and the output (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during the Low-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data at DIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during the Low-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loaded into the word selected by the write address (ADDRA) during the Low-to-High clock transition and the data output (DOA) reflects the selected (addressed) word. The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and the output (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during the Low-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data at DIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during the Low-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into the word selected by the write address (ADDRB) during the
1489
RAMB4_Sm_Sn
Low-to-High clock transition and the data output (DOB) reflects the selected (addressed) word. The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource. RAMB_Sm_Sn's may be initialized during configuration. See the following truth table. Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contents of the block RAM are not altered. Virtex, Virtex-E, Spartan-II, and Spartan-IIE simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. Mode selection is shown in the following truth table.
Inputs EN(A/B) 0 1 1 1 1 RST(A/B) X 1 1 0 0 WE(A/B) X 0 1 0 1 CLK(A/B) X ADDR(A/B) X X addr addr addr DI(A/B) X X data X data DO(A/B) No Chg 0 0 RAM(addr) data Outputs RAM Contents No Chg No Chg RAM(addr) =>data No Chg RAM(addr) =>data
addr=RAM address of port A/B RAM(addr)=RAM contents at address ADDRA/ADDRB data=RAM input data at pins DIA/DIB
Address Mapping
Each port accesses the same set of 4096 memory cells using an addressing scheme that is dependent on the width of the port. The physical RAM location that is addressed for a particular width is determined from the following formula.
Start=((ADDR port+1)*(Widthport)) -1 End=(ADDRport)*(Widthport)
The following table shows address mapping for each port width. Port Address Mapping
Port Width 1 2 4 8 16 4096 2048 1024 512 256 <----<----<----<----<----15 07 03 01 00 14 13 06 12 Port Addresses 11 05 02 10 09 04 08 07 03 01 00 06 05 02 04 03 01 00 02 01 00 00
1490
RAMB4_Sm_Sn
Port A and Port B Conflict Resolution

A RAMB4_Sm_Sn component is a true dual-ported RAM in that it allows simultaneous reads of the same memory cell. When one port is performing a write to a given memory cell, the other port should not address that memory cell (for a write or a read) within the clock-to-clock setup window. If both ports write to the same memory cell simultaneously, violating the clock-tosetup requirement, the data stored will be invalid. If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating the clock setup requirement, the write will be successful but the data read will be invalid.
Specifying Initial Contents of a Block RAM

You can use the INIT_0x attributes to specify an initial value during device configuration. The initialization of each RAMB4_Sm_Sn is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. See the INIT_xx section of the Constraints Guide for more information on these attributes. If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Usage
VHDL Instantiation Template for RAMB4_Sm_Sn

-- Component Declaration for RAMB4_Sm_Sn -- Should be placed after architecture statement but before begin keyword component RAMB4_Sm_Sn -- synthesis translate_off generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1491
RAMB4_Sm_Sn
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; ); -- synthesis translate_on port (DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (0 downto 0); ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (11 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (0 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC); end component; -- Component Attribute Specification for RAMB4_Sm_Sn -- Should be placed after architecture declaration but before the begin keyword -- Put attributes, if necessary
1492
RAMB4_Sm_Sn
-- Component Instantiation for RAMB4_Sm_Sn -- Should be placed in architecture after the begin keyword RAMB4_Sm_Sn_INSTANCE_NAME : RAMB4_Sm_Sn -- synthesis translate_off generic map ( INIT_00 => vector_value, INIT_01 => vector_value, INIT_02 => vector_value, INIT_03 => vector_value, INIT_04 => vector_value, INIT_05 => vector_value, INIT_06 => vector_value, INIT_07 => vector_value, INIT_08 => vector_value, INIT_09 => vector_value, INIT_0A => vector_value, INIT_0B => vector_value, INIT_0C => vector_value, INIT_0D => vector_value, INIT_0E => vector_value, INIT_0F => vector_value) -- synopsys translate_on port map (DOA => user_DOA, DOB => user_DOB, ADDRA => user_ADDRA, ADDRB => user_ADDRB, CLKA => user_CLKA, CLKB => user_CLKB, DIA => user_DIA, DIB => user_DIB, ENA => user_ENA, ENB => user_ENB, RSTA => user_RSTA, RSTB => user_RSTB, WEA => user_WEA,
1493
RAMB4_Sm_Sn
WEB => user_WEB);
Verilog Instantiation Template for RAMB16_S1, S2, and S4

RAMB4_Sm_Sn user_instance_name (.DOA (user_DOA), .DOB (user_DOB), .ADDRA (user_ADDRA), .ADDRB (user_ADDRB), .CLKA (user_CLKA), .CLKB (user_CLKB), .DIA (user_DIA), .DIB (user_DIB), .ENA (user_ENA), .ENB (user_ENB), .RSTA (user_RSTA), .RSTB (user_RSTB), .WEA (user_WEA), .WEB (user_WEB));
1494
RAMB4_Sm_Sn

INIT_xx
1495
RAMB4_Sm_Sn
1496
RAMB16_Sn
RAMB16_Sn
16384-Bit Data Memory and 2048-Bit Parity Memory, Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 9, 18, or 36 Bits
RAMB16_Sn Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
WE EN SSR CLK ADDR [13:0] DI [0:0]
RAMB16_S1
WE EN DO [0:0] SSR CLK ADDR [12:0] DI [1:0]
RAMB16_S2
WE EN DO [1:0] SSR CLK ADDR [11:0] DI [3:0]
RAMB16_S4
DO [3:0]
WE EN SSR CLK ADDR [10:0] DI [7:0] DIP [0:0]
RAMB16_S9 DOP [0:0] DO [7:0]
RAMB16_S18 DOP [1:0] DO [15:0]
RAMB16_S36 DOP [3:0] DO [31:0]
X9465
RAMB16_S1 through RAMB16_S36 Representations RAMB16_S1, RAMB16_S2, RAMB16_S4, RAMB16_S9, RAMB16_S18, and RAMB16_S36 are dedicated random access memory blocks with synchronous write capability. The block RAM port has 16384 bits of data memory. RAMB16_S9, RAMB16_S18, and RAMB16_S36 have an additional 2048 bits of parity memory. The RAMB16_Sn cell configurations are listed in the following table.
Component
Data Cells Depth Width 1 2
Parity Cells Depth Width -
Address Bus
Data Bus
Parity Bus
RAMB16_S1 RAMB16_S2
16384 8192
(13:0) (12:0)
(0:0) (1:0)
1497
RAMB16_Sn
Component
Data Cells Depth Width 4 8 16 32
Parity Cells Depth 2048 1024 512 Width 1 2 4
Address Bus
Data Bus
Parity Bus
RAMB16_S4 RAMB16_S9 RAMB16_S18 RAMB16_S36
4096 2048 1024 512
(11:0) (10:0) (9:0) (8:0)
(3:0) (7:0) (15:0) (31:0)
(0:0) (1:0) (3:0)
1498
RAMB16_Sn
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the outputs (DO and DOP) retain the last state. When EN is High and reset (SSR) is High, DO and DOP are set to SRVAL during the Low-to-High clock (CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI and DIP. When SSR is Low, EN is High, and WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition. The output value depends on the mode. By default WRITE_MODE=WRITE_FIRST, when EN and WE are High and SSR is Low, the data on the data inputs (DI and DIP) is loaded into the word selected by the write address (ADDR) during the Low-to-High clock transition. See Write Mode Selection for information on setting the WRITE_MODE. The above description assumes an active High EN, WE, SSR, and CLK. However, the active level can be changed by placing an inverter on the port. Any inverter placed on a RAMB16 port is absorbed into the block and does not use a CLB resource.
Inputs GS R EN SSR WE CLK ADD R DI DIP DO DOP
Outputs RAM Contents Data RAM Parity RAM No Chg No Chg No Chg RAM(addr) =>pdata No Chg RAM(addr) =>pdata
1 0 0 0 0 0
X 0 1 1 1 1
X X 1 1 0 0
X X 0 1 0 1
X X
X X X addr addr addr
X X X data X data
X X X
INIT No Chg SRVAL
INIT No Chg SRVAL SRVAL RAM(addr) Chga
No Chg No Chg No Chg RAM(addr) =>data No Chg
pdata SRVAL X RAM(addr) Chga
No RAM(addr) pdata No RAM (addr)b RAM(addr)b =>data datac pdatac
GSR=Global Set Reset signal INIT=Value specified by the INIT attribute for data memory. Default is all zeros. SRVAL=Value after assertion of SSR as specified by the SRVAL attribute. addr=RAM address RAM(addr)=RAM contents at address ADDR data=RAM input data pdata=RAM parity data
aWRITE_MODE=NO_CHANGE bWRITE_MODE=READ_FIRST cWRITE_MODE=WRITE_FIRST
1499
RAMB16_Sn
Initializing Memory Contents of a Single-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory contents of a RAMB16 during device configuration. The initialization of each RAMB16_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64 hex values for a total of 16384 bits. You can use the INITP_xx attributes to specify an initial value for the parity memory during device configuration or assertion. The initialization of the parity memory for ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00 through INITP_07) of 64 hex values for a total of 2048 bits. If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial strings are padded with zeros to the left. See the Constraints Guide for more information on these attributes.
Initializing the Output Register of a Single-Port RAMB16

In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, each bit in the output register can be initialized at power on to either a 0 or 1. In addition, the initial state specified for power on can be different than the state that results from assertion of a set/reset. Two types of properties control initialization of the output register for a single-port RAMB16: INIT and SRVAL. The INIT attribute specifies the output register value at power on. You can use the SRVAL attribute to define the state resulting from assertion of the SSR (set/reset) input. The INIT and SRVAL attributes specify the initialization value as a hexadecimal string. The value is dependent upon the port width. For example, for a RAMB16_S1 with port width equal to 1, the output register contains 1 bit. Therefore, the INIT or SRVAL value can only be specified as a 1 or 0. For RAMB16_S4 with port width equal to 4, the output register contains 4 bits. In this case, you can specify a hexadecimal value from 0 through F to initialize the 4 bits of the output register. For those ports that include parity bits, the parity portion of the output register is specified in the high order bit position of the INIT or SRVAL value. The INIT and SRVAL attributes default to zero if they are not set by the user. See the Constraints Guide for more information on these attributes.
Write Mode Selection

The WRITE_MODE attribute controls RAMB16 memory and output contents. By default, the WRITE_MODE is set to WRITE_FIRST. This means that input is read, written to memory, and then passed to output. You can set the WRITE_MODE to READ_FIRST to read the memory contents, pass the memory contents to the outputs, and then write the input to memory. Or, you can set the WRITE_MODE to NO_CHANGE to have the input written to memory without changing the output.
Usage
1500
RAMB16_Sn
VHDL Instantiation Template for RAMB16_S1, S2, and S4

-- Component Declaration for RAMB16_{S1 | S2 | S4} -- Should be placed after architecture statement but before begin keyword component RAMB16_{S1 | S2 | S4} -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : X"0000000000000000000000000000000000000000000000000000000000000000";
:= bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector := := := := := := := := := := := := := := := := := := := := := := := :=
1501
RAMB16_Sn
INIT_19 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : X"0000000000000000000000000000000000000000000000000000000000000000";
bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector
:= := := := := := := := := := := := := := := := := := := := := := := := := := := := :=
1502
RAMB16_Sn
INIT_36 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"); -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0) ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector
:= := := := := := := := := :=
-- Component Attribute Specification for RAMB16_{S1 | S2 | S4} -- Should be placed after architecture declaration but before the begin keyword -- Put attributes, if necessary
-- Component Instantiation for RAMB16_{S1 | S2 | S4} -- Should be placed in architecture after the begin keyword
1503
RAMB16_Sn
RAMB16_{S1 | S2 | S4}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value, INIT_01 => vector_value, INIT_02 => vector_value, INIT_03 => vector_value, INIT_04 => vector_value, INIT_05 => vector_value, INIT_06 => vector_value, INIT_07 => vector_value, INIT_08 => vector_value, INIT_09 => vector_value, INIT_0A => vector_value, INIT_0B => vector_value, INIT_0C => vector_value, INIT_0D => vector_value, INIT_0E => vector_value, INIT_0F => vector_value, INIT_10 => vector_value, INIT_11 => vector_value, INIT_12 => vector_value, INIT_13 => vector_value, INIT_14 => vector_value, INIT_15 => vector_value, INIT_16 => vector_value, INIT_17 => vector_value, INIT_18 => vector_value, INIT_19 => vector_value, INIT_1A => vector_value, INIT_1B => vector_value, INIT_1C => vector_value, INIT_1D => vector_value, INIT_1E => vector_value, INIT_1F => vector_value, INIT_20 => vector_value, INIT_21 => vector_value, INIT_22 => vector_value, INIT_23 => vector_value, INIT_24 => vector_value, INIT_25 => vector_value, INIT_26 => vector_value, INIT_27 => vector_value, INIT_28 => vector_value, INIT_29 => vector_value, INIT_2A => vector_value, INIT_2B => vector_value, INIT_2C => vector_value, INIT_2D => vector_value, INIT_2E => vector_value, INIT_2F => vector_value, INIT_30 => vector_value, INIT_31 => vector_value, INIT_32 => vector_value, INIT_33 => vector_value, INIT_34 => vector_value, INIT_35 => vector_value,
1504
RAMB16_Sn
INIT_36 => vector_value, INIT_37 => vector_value, INIT_38 => vector_value, INIT_39 => vector_value, INIT_3A => vector_value, INIT_3B => vector_value, INIT_3C => vector_value, INIT_3D => vector_value, INIT_3E => vector_value, INIT_3F => vector_value, SRVAL=> bit_value, WRITE_MODE => user_WRITE_MODE) -- synopsys translate_on port map (DO => user_DO, ADDR => user_ADDR, CLK => user_CLK, DI => user_DI, EN => user_EN, SSR => user_SSR, WE => user_WE);
Verilog Instantiation Template for RAMB16_S1, S2, and S4

RAMB16_{S1 | S2 | S4} user_instance_name (.DO(user_DO), .ADDR (user_ADDR), .CLK (user_CLK), .DI (user_DI), .EN (user_EN), .SSR (user_SSR), .WE (user_WE)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.INIT = bit_value; user_instance_name.INIT_00 = 256_bit_hex_value; user_instance_name.INIT_01 = 256_bit_hex_value; user_instance_name.INIT_02 = 256_bit_hex_value; user_instance_name.INIT_03 = 256_bit_hex_value; user_instance_name.INIT_04 = 256_bit_hex_value; user_instance_name.INIT_05 = 256_bit_hex_value; user_instance_name.INIT_06 = 256_bit_hex_value; user_instance_name.INIT_07 = 256_bit_hex_value; user_instance_name.INIT_08 = 256_bit_hex_value; user_instance_name.INIT_09 = 256_bit_hex_value; user_instance_name.INIT_0A = 256_bit_hex_value; user_instance_name.INIT_0B = 256_bit_hex_value; user_instance_name.INIT_0C = 256_bit_hex_value; user_instance_name.INIT_0D = 256_bit_hex_value; user_instance_name.INIT_0E = 256_bit_hex_value; user_instance_name.INIT_0F = 256_bit_hex_value; user_instance_name.INIT_10 = 256_bit_hex_value; user_instance_name.INIT_11 = 256_bit_hex_value; user_instance_name.INIT_12 = 256_bit_hex_value; user_instance_name.INIT_13 = 256_bit_hex_value; user_instance_name.INIT_14 = 256_bit_hex_value; user_instance_name.INIT_15 = 256_bit_hex_value; user_instance_name.INIT_16 = 256_bit_hex_value; user_instance_name.INIT_17 = 256_bit_hex_value; user_instance_name.INIT_18 = 256_bit_hex_value; user_instance_name.INIT_19 = 256_bit_hex_value;
1505
RAMB16_Sn
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.INIT_1A = 256_bit_hex_value; user_instance_name.INIT_1B = 256_bit_hex_value; user_instance_name.INIT_1C = 256_bit_hex_value; user_instance_name.INIT_1D = 256_bit_hex_value; user_instance_name.INIT_1E = 256_bit_hex_value; user_instance_name.INIT_1F = 256_bit_hex_value; user_instance_name.INIT_20 = 256_bit_hex_value; user_instance_name.INIT_21 = 256_bit_hex_value; user_instance_name.INIT_22 = 256_bit_hex_value; user_instance_name.INIT_23 = 256_bit_hex_value; user_instance_name.INIT_24 = 256_bit_hex_value; user_instance_name.INIT_25 = 256_bit_hex_value; user_instance_name.INIT_26 = 256_bit_hex_value; user_instance_name.INIT_27 = 256_bit_hex_value; user_instance_name.INIT_28 = 256_bit_hex_value; user_instance_name.INIT_29 = 256_bit_hex_value; user_instance_name.INIT_2A = 256_bit_hex_value; user_instance_name.INIT_2B = 256_bit_hex_value; user_instance_name.INIT_2C = 256_bit_hex_value; user_instance_name.INIT_2D = 256_bit_hex_value; user_instance_name.INIT_2E = 256_bit_hex_value; user_instance_name.INIT_2F = 256_bit_hex_value; user_instance_name.INIT_30 = 256_bit_hex_value; user_instance_name.INIT_31 = 256_bit_hex_value; user_instance_name.INIT_32 = 256_bit_hex_value; user_instance_name.INIT_33 = 256_bit_hex_value; user_instance_name.INIT_34 = 256_bit_hex_value; user_instance_name.INIT_35 = 256_bit_hex_value; user_instance_name.INIT_36 = 256_bit_hex_value; user_instance_name.INIT_37 = 256_bit_hex_value; user_instance_name.INIT_38 = 256_bit_hex_value; user_instance_name.INIT_39 = 256_bit_hex_value; user_instance_name.INIT_3A = 256_bit_hex_value; user_instance_name.INIT_3B = 256_bit_hex_value; user_instance_name.INIT_3C = 256_bit_hex_value; user_instance_name.INIT_3D = 256_bit_hex_value; user_instance_name.INIT_3E = 256_bit_hex_value; user_instance_name.INIT_3F = 256_bit_hex_value; user_instance_name.SRVAL = bit_value; user_instance_name.WRITE_MODE = write_mode;
1506
RAMB16_Sn
VHDL Instantiation Template for RAMB16_S9, S18 and S36

-- Component Declaration for RAMB16_{S9 | S18 | S36} -- Should be placed after architecture statement but before begin keyword component RAMB16_{S9 | S18 | S36} -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : X"0000000000000000000000000000000000000000000000000000000000000000";
:= bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector := := := := := := := := := := := := := := := := := := := := := := := :=
1507
RAMB16_Sn
INIT_19 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : X"0000000000000000000000000000000000000000000000000000000000000000";
bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector
:= := := := := := := := := := := := := := := := := := := := := := := := := := := := :=
1508
RAMB16_Sn
INIT_36 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_00 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"; ); -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0); DOP : out STD_LOGIC_VECTOR (1 downto 0); ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); DIP : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;
bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector bit_vector
:= := := := := := := := := := := := := := := := := :=
-- Component Attribute Specification for RAMB16_{S9 | S18 | S36} -- Should be placed after architecture declaration but before the begin keyword -- Put attributes, if necessary
1509
RAMB16_Sn
-- Component Instantiation for RAMB16_{S9 | S18 | S36} -- Should be placed in architecture after the begin keyword RAMB16_{S9 | S18 | S36}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value, INIT_01 => vector_value, INIT_02 => vector_value, INIT_03 => vector_value, INIT_04 => vector_value, INIT_05 => vector_value, INIT_06 => vector_value, INIT_07 => vector_value, INIT_08 => vector_value, INIT_09 => vector_value, INIT_0A => vector_value, INIT_0B => vector_value, INIT_0C => vector_value, INIT_0D => vector_value, INIT_0E => vector_value, INIT_0F => vector_value, INIT_10 => vector_value, INIT_11 => vector_value, INIT_12 => vector_value, INIT_13 => vector_value, INIT_14 => vector_value, INIT_15 => vector_value, INIT_16 => vector_value, INIT_17 => vector_value, INIT_18 => vector_value, INIT_19 => vector_value, INIT_1A => vector_value, INIT_1B => vector_value, INIT_1C => vector_value, INIT_1D => vector_value, INIT_1E => vector_value, INIT_1F => vector_value, INIT_20 => vector_value, INIT_21 => vector_value, INIT_22 => vector_value, INIT_23 => vector_value, INIT_24 => vector_value, INIT_25 => vector_value, INIT_26 => vector_value, INIT_27 => vector_value, INIT_28 => vector_value, INIT_29 => vector_value, INIT_2A => vector_value, INIT_2B => vector_value, INIT_2C => vector_value, INIT_2D => vector_value, INIT_2E => vector_value, INIT_2F => vector_value, INIT_30 => vector_value, INIT_31 => vector_value,
1510
RAMB16_Sn
INIT_32 => vector_value, INIT_33 => vector_value, INIT_34 => vector_value, INIT_35 => vector_value, INIT_36 => vector_value, INIT_37 => vector_value, INIT_38 => vector_value, INIT_39 => vector_value, INIT_3A => vector_value, INIT_3B => vector_value, INIT_3C => vector_value, INIT_3D => vector_value, INIT_3E => vector_value, INIT_3F => vector_value, INITP_00 => vector_value, INITP_01 => vector_value, INITP_02 => vector_value, INITP_03 => vector_value, INITP_04 => vector_value, INITP_05 => vector_value, INITP_06 => vector_value, INITP_07 => vector_value SRVAL => bit_value, WRITE_MODE => user_WRITE_MODE) -- synopsys translate_on port map (DO => user_DO, DOP => user_DOP, ADDR => user_ADDR, CLK => user_CLK, DI => user_DI, DIP => user_DIP, EN => user_EN, SSR => user_SSR, WE => user_WE);
1511
RAMB16_Sn
Verilog Instantiation Template for RAMB16_S18 and S36

RAMB16_{S9 | S18 | S36} user_instance_name (.DO(user_DO), .DOP (user_DOP), .ADDR (user_ADDR), .CLK (user_CLK), .DI (user_DI), .DIP (user_DIP), .EN (user_EN), .SSR (user_SSR), .WE (user_WE)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.INIT = bit_value; user_instance_name.INIT_00 = 256_bit_hex_value; user_instance_name.INIT_01 = 256_bit_hex_value; user_instance_name.INIT_02 = 256_bit_hex_value; user_instance_name.INIT_03 = 256_bit_hex_value; user_instance_name.INIT_04 = 256_bit_hex_value; user_instance_name.INIT_05 = 256_bit_hex_value; user_instance_name.INIT_06 = 256_bit_hex_value; user_instance_name.INIT_07 = 256_bit_hex_value; user_instance_name.INIT_08 = 256_bit_hex_value; user_instance_name.INIT_09 = 256_bit_hex_value; user_instance_name.INIT_0A = 256_bit_hex_value; user_instance_name.INIT_0B = 256_bit_hex_value; user_instance_name.INIT_0C = 256_bit_hex_value; user_instance_name.INIT_0D = 256_bit_hex_value; user_instance_name.INIT_0E = 256_bit_hex_value; user_instance_name.INIT_0F = 256_bit_hex_value; user_instance_name.INIT_10 = 256_bit_hex_value; user_instance_name.INIT_11 = 256_bit_hex_value; user_instance_name.INIT_12 = 256_bit_hex_value; user_instance_name.INIT_13 = 256_bit_hex_value; user_instance_name.INIT_14 = 256_bit_hex_value; user_instance_name.INIT_15 = 256_bit_hex_value; user_instance_name.INIT_16 = 256_bit_hex_value; user_instance_name.INIT_17 = 256_bit_hex_value; user_instance_name.INIT_18 = 256_bit_hex_value; user_instance_name.INIT_19 = 256_bit_hex_value; user_instance_name.INIT_1A = 256_bit_hex_value; user_instance_name.INIT_1B = 256_bit_hex_value; user_instance_name.INIT_1C = 256_bit_hex_value; user_instance_name.INIT_1D = 256_bit_hex_value; user_instance_name.INIT_1E = 256_bit_hex_value; user_instance_name.INIT_1F = 256_bit_hex_value; user_instance_name.INIT_20 = 256_bit_hex_value; user_instance_name.INIT_21 = 256_bit_hex_value; user_instance_name.INIT_22 = 256_bit_hex_value; user_instance_name.INIT_23 = 256_bit_hex_value; user_instance_name.INIT_24 = 256_bit_hex_value; user_instance_name.INIT_25 = 256_bit_hex_value; user_instance_name.INIT_26 = 256_bit_hex_value; user_instance_name.INIT_27 = 256_bit_hex_value; user_instance_name.INIT_28 = 256_bit_hex_value; user_instance_name.INIT_29 = 256_bit_hex_value; user_instance_name.INIT_2A = 256_bit_hex_value; user_instance_name.INIT_2B = 256_bit_hex_value; user_instance_name.INIT_2C = 256_bit_hex_value;
1512
RAMB16_Sn
defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam
user_instance_name.INIT_2D = 256_bit_hex_value; user_instance_name.INIT_2E = 256_bit_hex_value; user_instance_name.INIT_2F = 256_bit_hex_value; user_instance_name.INIT_30 = 256_bit_hex_value; user_instance_name.INIT_31 = 256_bit_hex_value; user_instance_name.INIT_32 = 256_bit_hex_value; user_instance_name.INIT_33 = 256_bit_hex_value; user_instance_name.INIT_34 = 256_bit_hex_value; user_instance_name.INIT_35 = 256_bit_hex_value; user_instance_name.INIT_36 = 256_bit_hex_value; user_instance_name.INIT_37 = 256_bit_hex_value; user_instance_name.INIT_38 = 256_bit_hex_value; user_instance_name.INIT_39 = 256_bit_hex_value; user_instance_name.INIT_3A = 256_bit_hex_value; user_instance_name.INIT_3B = 256_bit_hex_value; user_instance_name.INIT_3C = 256_bit_hex_value; user_instance_name.INIT_3D = 256_bit_hex_value; user_instance_name.INIT_3E = 256_bit_hex_value; user_instance_name.INIT_3F = 256_bit_hex_value; user_instance_name.INITP_00 = 256_bit_hex_value; user_instance_name.INITP_01 = 256_bit_hex_value; user_instance_name.INITP_02 = 256_bit_hex_value; user_instance_name.INITP_03 = 256_bit_hex_value; user_instance_name.INITP_04 = 256_bit_hex_value; user_instance_name.INITP_05 = 256_bit_hex_value; user_instance_name.INITP_06 = 256_bit_hex_value; user_instance_name.INITP_07 = 256_bit_hex_value; user_instance_name.SRVAL = bit_value; user_instance_name.WRITE_MODE = write_mode;

INIT INIT_xx SRVAL WRITE_MODE HU_SET INITP_xx SRVAL WRITE_MODE
1513
RAMB16_Sn
1514
RAMB16_Sm_Sn
RAMB16_Sm_Sn
16384-Bit Data Memory and 2048-Bit Parity Memory, Dual-Port Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 9, 18, or 36 Bits
RAMB16_Sm_Sn Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
1515
RAMB16_Sm_Sn
WEA ENA SSRA CLKA ADDRA [13:0] DIA [0:0]
RAMB16_S1_S1
WEA ENA DOA [0:0] SSRA CLKA ADDRA [13:0] DIA [0:0]
RAMB16_S1_S2
RAMB16_S1_S4
DOA [0:0]
WEB ENB SSRB CLKB ADDRB [13:0] DIB [0:0] DOB [0:0]
RAMB16_S1_S9
RAMB16_S1_S18
RAMB16_S1_S36
DOA [0:0]
WEB ENB SSRB CLKB ADDRB [10:0] DIB [7:0] DIPB [0:0] DOPB [0:0] DOB [7:0]
WEB ENB SSRB CLKB ADDRB [8:0] DIB [31:0] DIPB [3:0] X9466 DOPB [3:0] DOB [31:0]
RAMB16_S1_S1 through RAMB16_S1_S36 Representations
1516
RAMB16_Sm_Sn
WEA WEA ENA SSRA CLKA ADDRA [12:0] DIA [1:0] DOA [1:0] RAMB16_S2_S2 WEA ENA SSRA CLKA ADDRA [12:0] DIA [1:0] WEB WEB ENB SSRB CLKB ADDRB [12:0] DIB [1:0] DOB [1:0] WEB ENB SSRB CLKB ADDRB [11:0] DIB [3:0] DOB [3:0] ENB SSRB CLKB ADDRB [10:0] DIB [7:0] DIPB [0:0] DOA [1:0] RAMB16_S2_S4 ENA SSRA CLKA ADDRA [12:0] DIA [1:0]
RAMB16_S2_S9
DOA [1:0]
DOPB [0:0] DOB [7:0]
RAMB16_S2_S18
RAMB16_S2_S36 WEA DOA [1:0] ENA SSRA CLKA ADDRA [11:0] DIA [3:0] DOA [3:0] RAMB16_S4_S4
WEB ENB SSRB CLKB ADDRB [8:0] DIB [31:0] DIPB [3:0] DOPB [3:0] DOB [31:0] WEB ENB SSRB CLKB ADDRB [11:0] DIB [3:0] DOB [3:0]
RAMB16_S4_S9
RAMB16_S4_S18
RAMB16_S4_S36
DOA [3:0]
RAMB16_S2_S2 through RAMB16_S4_S36 Representations
1517
RAMB16_Sm_Sn
WEA ENA SSRA CLKA ADDRA [10:0] DIA [7:0] DIPA [0:0]
RAMB16_S9_S9
WEA ENA DOPA [0:0] DOA [7:0] SSRA CLKA ADDRA [10:0] DIA [7:0] DIPA [0:0]
RAMB16_S9_S18
WEA ENA DOPA [0:0] DOA [7:0] SSRA CLKA ADDRA [10:0] DIA [7:0] DIPA [0:0]
RAMB16_S9_S36
DOPA [0:0] DOA [7:0]
WEA RAMB16_S18_S18 ENA SSRA CLKA ADDRA [9:0] DIA [15:0] DIPA [1:0] DOPA [1:0] DOA [15:0]
RAMB16_S9_S9 through RAMB16_S36_S36 Representations The RAMB16_Sm_Sn components listed in the following table are dual-ported dedicated random access memory blocks with synchronous write capability. Each block RAM port has 16384 bits of data memory. Ports configured as 9, 18, or 36-bits wide have an additional 2048 bits of parity memory. Each port is independent of the other while accessing the same set of 16384 data memory cells. Each port is independently configured to a specific data width. The possible port and cell configurations are listed in the following table.
1518
RAMB16_Sm_Sn
Port A Component RAMB16_S1_ S1 RAMB16_S1_ S2 RAMB16_S1_ S4 RAMB16_S1_ S9 RAMB16_S1_ S18 RAMB16_S1_ S36 RAMB16_S2_ S2 RAMB16_S2_ S4 RAMB16_S2_ S9 RAMB16_S2_ S18 RAMB16_S2_ S36 RAMB16_S4_ S4 RAMB16_S4_ S9 RAMB16_S4_ S18 RAMB16_S4_ S36 RAMB16_S9_ S9 RAMB16_S9_ S18 RAMB16_S9_ S36 RAMB16_S18 _S18 RAMB16_S18 _S36 RAMB16_S36 _S36
aDepth x Width
Data Cellsa Parity Cellsa
Port B Data Bus (0:0) (0:0) (0:0) (0:0) (0:0) (0:0) (1:0) (1:0) (1:0) (1:0) (1:0) (3:0) (3:0) (3:0) (3:0) (7:0) (7:0) (7:0) (15:0) (15:0) (31:0) Parity Bus (0:0) (0:0) (0:0) (1:0) (1:0) (3:0)
Data Cellsa Parity Cellsa
Address Bus (13:0) (13:0) (13:0) (13:0) (13:0) (13:0) (12:0) (12:0) (12:0) (12:0) (12:0) (11:0) (11:0) (11:0) (11:0) (10:0) (10:0) (10:0) (9:0) (9:0) (8:0)
Address Bus (13:0) (12:0) (11:0) (10:0) (9:0) (8:0) (12:0) (11:0) (10:0) (9:0) (8:0) (11:0) (10:0) (9:0) (8:0) (10:0) (9:0) (8:0) (9:0) (8:0) (8:0)
Data Bus (0:0) (1:0) (3:0) (7:0) (15:0) (31:0) (1:0) (3:0) (7:0) (15:0) (31:0) (3:0) (7:0) (15:0) (31:0) (7:0) (15:0) (31:0) (15:0) (31:0) (31:0)
Parity Bus (0:0) (1:0) (3:0) (0:0) (1:0) (3:0) (0:0) (1:0) (3:0) (0:0) (1:0) (3:0) (1:0) (3:0) (3:0)
16384 x 1 16384 x 1 16384 x 1 16384 x 1 16384 x 1 16384 x 1 8192 x 2 8192 x 2 8192 x 2 8192 x 2 8192 x 2 4096 x 4 4096 x 4 4096 x 4 4096 x 4 2048 x 8 2048 x 8 2048 x 8 1024 x 16 1024 x 16 512 x 32
2048 x 1 2048 x 1 2048 x 1 1024 x 2 1024 x 2 512 x 4
16384 x 1 8192 x 2 4096 x 4 2048 x 8 1024 x 16 512 x 32 8192 x 2 4096 x 4 2048 x 8 1024 x 16 512 x 32 4096 x 4 2048 x 8 1024 x 16 512 x 32 2048 x 8 1024 x 16 512 x 32 1024 x 16 512 x 32 512 x 32
2048 x 1 1024 x 2 512 x 4 2048 x 1 1024 x 2 512 x 4 2048 x 1 1024 x 2 512 x 4 2048 x 1 1024 x 2 512 x 4 1024 x 2 512 x 4 512 x 4
1519
RAMB16_Sm_Sn
Each port is fully synchronous with independent clock pins. All port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clockto-out time referenced to the CLKA. All port B input pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out time referenced to the CLKB. The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and the outputs (DOA and DOPA) retain the last state. When ENA is High and reset (SSRA) is High, DOA and DOPA are set to SRVAL_A during the Lowto-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data at DIA and DIPA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during the Low-to-High clock transition. By default, WRITE_MODE_A=WRITE_FIRST, when ENA and WEA are High, the data on the data inputs (DIA and DIPA) is loaded into the word selected by the write address (ADDRA) during the Low-to-High clock transition and the data outputs (DOA and DOPA) reflect the selected (addressed) word. The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and the outputs (DOB and DOPB) retain the last state. When ENB is High and reset (SSRB) is High, DOB and DOPB are set to SRVAL_B during the Lowto-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data at DIB and DIPB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during the Low-to-High clock transition. By default, WRITE_MODE_B=WRITE_FIRST, when ENB and WEB are High, the data on the data inputs (DIB and PB) are loaded into the word selected by the write address (ADDRB) during the Low-to-High clock transition and the data outputs (DOB and DOPB) reflect the selected (addressed) word. The above descriptions assume active High control pins (ENA, WEA, SSRA, CLKA, ENB, WEB, SSRB, and CLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on a RAMB16 port is absorbed into the block and does not use a CLB resource. Port A Truth Table
Inputs GS R ENA SSR WE CLK ADD A A A RA DIA DIPA DOA DOPA Outputs RAM Contents Data RAM 1 0 0 0 0 X 0 1 1 1 X X 1 1 0 X X 0 1 0 X X X X X addr addr X X X data X X X X INIT_A No Chg SRVAL_A INIT_A No Chg SRVAL_A SRVAL_A RAM(addr) No Chg No Chg No Chg RAM(addr) =>data No Chg Parity RAM No Chg No Chg No Chg RAM(addr) =>pdata No Chg
pdata SRVAL_A X RAM(addr)
1520
RAMB16_Sm_Sn
Port A Truth Table

Inputs GS R 0 ENA 1 SSR WE CLK ADD A A A RA 0 1 addr DIA data DIPA DOA DOPA Outputs RAM Contents RAM(addr) =>pdata
pdata No Chg1 No Chg1 RAM(addr) RAM (addr)2 RAM(addr)2 =>data data3 pdata3
GSR=Global Set Reset INIT_A=Value specified by the INIT_A attribute for output register. Default is all zeros. SRVAL_A=register value addr=RAM address RAM(addr)=RAM contents at address ADDR data=RAM input data pdata=RAM parity data
1WRITE_MODE_A=NO_CHANGE 2WRITE_MODE_A=READ_FIRST 3WRITE_MODE_A=WRITE_FIRST
Port B Truth Table

Inputs GS R ENB SSR WE CLK ADD B B B RB DIB DIPB DOB DOPB Outputs RAM Contents Data RAM 1 0 0 0 0 0 X 0 1 1 1 1 X X 1 1 0 0 X X 0 1 0 1 X X X X X addr addr addr X X X data X data X X X INIT_B No Chg SRVAL_B INIT_B No Chg SRVAL_B SRVAL_B RAM(addr) No Chg No Chg No Chg RAM(addr) =>data No Chg Parity RAM No Chg No Chg No Chg RAM(addr) =>pdata No Chg RAM(addr) =>pdata
pdata SRVAL_B X RAM(addr)
No Chg1 RAM(addr) pdata No Chg1 RAM (addr)2 RAM(addr)2 =>data data3 pdata3
GSR=Global Set Reset INIT_B=Value specified by the INIT_B attribute for output registers. Default is all zeros. SRVAL_B=register value addr=RAM address RAM(addr)=RAM contents at address ADDR data=RAM input data pdata=RAM parity data
1WRITE_MODE_B=NO_CHANGE 2WRITE_MODE_B=READ_FIRST 3WRITE_MODE_B=WRITE_FIRST
1521
RAMB16_Sm_Sn
Address Mapping
Each port accesses the same set of 18432 memory cells using an addressing scheme that is dependent on the width of the port. For all port widths, 16384 memory cells are available for data as shown in the Port Address MappinPort Address Mapping for Data tableg for Data table Port Address MappinPort Address MappinPort Address MappinPort Address Mapping for Data tableg for Data tableg for Data tableg for Data table. For 9-, 18-, and 36-bit wide ports, 2408 parity memory cells are also available as shown in Port Address Mapping for Parity tablePort Address Mapping for Parity table. The physical RAM location that is addressed for a particular width is determined from the following formula.
Start=((ADDR port+1)*(Widthport)) -1 End=(ADDRport)*(Widthport)
The following tables shows address mapping for each port width. Port Address Mapping for Data
Data Width 1 2 4 8 16 32 Port Data Addresses 16384 <-- 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 8192 4096 2048 1024 512 <-<-<-<-<-15 07 03 01 00 14 13 06 12 11 05 02 10 09 04 08 07 03 01 00 06 05 02 04 03 01 00 02 01 00 00
Port Address Mapping for Parity

Parity Width 1 2 4 2048 1024 512 <----<----<----03 01 00 Port Parity Addresses 02 01 00 00
Initializing Memory Contents of a Dual-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory contents of a RAMB16 during device configuration. The initialization of each RAMB16_Sm_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64 hex values for a total of 16384 bits. You can use the INITP_xx attributes to specify an initial value for the parity memory during device configuration or assertion. The initialization of the parity memory for ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00 through INITP_07) of 64 hex values for a total of 2048 bits. If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial strings are padded with zeros to the left. See the Constraints Guide for more information on these attributes.
1522
RAMB16_Sm_Sn
Initializing the Output Register of a Dual-Port RAMB16

In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, each bit in an output register can be initialized at power on (when GSR is high) to either a 0 or 1. In addition, the initial state specified for power on can be different than the state that results from assertion of a set/reset. Four properties control initialization of the output register for a dual-port RAMB16: INIT_A, INIT_B, SRVAL_A, and SRVAL_B. The INIT_A attribute specifies the output register value at power on for port A and the INIT_B attribute specifies the value for port B. You can use the SRVAL_A attribute to define the state resulting from assertion of the SSR (set/reset) input on port A. You can use the SRVAL_B attribute to define the state resulting from assertion of the SSR input on port B. The INIT_A, INIT_B, SRVAL_A, and SRVAL_B attributes specify the initialization value as a hexadecimal string. The value is dependent upon the port width. For example, for a RAMB16_S1_S4 with port A width equal to 1 and port B width equal to 4, the port A output register contains 1 bit and the port B output register contains 4 bits. Therefore, the INIT_A or SRVAL_A value can only be specified as a 1 or 0. For port B, the output register contains 4 bits. In this case, you can use INIT_B or SRVAL_B to specify a hexadecimal value from 0 through F to initialize the 4 bits of the output register. For those ports that include parity bits, the parity portion of the output register is specified in the high order bit position of the INIT_A, INIT_B, SRVAL_A, or SRVAL_B value. The INIT and SRVAL attributes default to zero if they are not set by the user. See the Constraints Guide for more information on these attributes.
Write Mode Selection

The WRITE_MODE_A attribute controls the memory and output contents of port A for a dual-port RAMB16. The WRITE_MODE_B attribute does the same for port B. By default, both WRITE_MODE_A and WRITE_MODE_B are set to WRITE_FIRST. This means that input is read, written to memory, and then passed to output. You can set the write mode for port A and/or port B to READ_FIRST to read the memory contents, pass the memory contents to the outputs, and then write the input to memory. Or, you can set the write mode to NO_CHANGE to have the input written to memory without changing the output. The Port A and Port B Conflict Resolution section describes how read/write conflicts are resolved when both port A and port B are attempting to read/write to the same memory cells.
Port A and Port B Conflict Resolution

Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X block SelectRAM is True DualPort RAM that allows both ports to simultaneously access the same memory cell. When one port writes to a given memory cell, the other port must not address that memory cell (for a write or a read) within the clock-to-clock setup window. For a list of specifics of conflict resolution for port and memory cell write operations that have either a clock common to both ports or synchronous clocks on each port, see Virtex-II Handbook, Chapter 2, Design Considerations, Using BlockSelectRAM Memory, Conflict Resolution. The following tables summarize the collision detection behavior of the dual-port RAMB16 based on the WRITE_MODE_A and WRITE_MODE_B settings.
1523
RAMB16_Sm_Sn
WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=NO_CHANGE

WEA WEB CLKA CLKB 0 1 0 1 0 0 1 1 DIA DIA DIA DIA DIA DIB DIB DIB DIB DIB DIPA DIPA DIPA DIPA DIPA DIPB DIPB DIPB DIPB DIPB DOA RAM No Chg X DOB RAM X No Chg DOPA RAM No Chg X DOPB RAM X No Chg Data RAM Parity Ram
No Chg No Chg DIA DIB X DIPA DIPB X
No Chg No Chg No Chg No Chg
WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=READ_FIRST

WEA 0 1 0 1 WEB 0 0 1 1 CLKA CLKB DIA DIA DIA DIA DIA DIB DIB DIB DIB DIB DIPA DIPA DIPA DIPA DIPA DIPB DIPB DIPB DIPB DIPB DOA RAM RAM RAM RAM DOB RAM RAM RAM RAM DOPA RAM RAM RAM RAM DOPB RAM RAM RAM RAM Data RAM Parity Ram
WRITE_MODE_A= WRITE_FIRST and WRITE_MODE_B=WRITE_FIRST

WEA 0 1 0 1 WEB 0 0 1 1 CLKA CLKB DIA DIA DIA DIA DIA DIB DIB DIB DIB DIB DIPA DIPA DIPA DIPA DIPA DIPB DIPB DIPB DIPB DIPB DOA RAM DIA X X DOB RAM X DIB X DOPA RAM DIPA X X DOPB RAM X DIPB X Data RAM Parity Ram
WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=READ_FIRST

WEA 0 1 0 1 WEB 0 0 1 1 CLKA CLKB DIA DIA DIA DIA DIA DIB DIB DIB DIB DIB DIPA DIPA DIPA DIPA DIPA DIPB DIPB DIPB DIPB DIPB DOA RAM No Chg RAM No Chg DOB RAM X RAM X DOPA RAM No Chg RAM No Chg DOPB RAM X RAM X Data RAM Parity Ram
No Chg No Chg DIA DIB DIB DIPA DIPB DIPB
WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=WRITE_FIRST

WEA 0 1 WEB 0 0 CLKA CLKB DIA DIA DIA DIB DIB DIB DIPA DIPA DIPA DIPB DIPB DIPB DOA RAM No Chg DOB RAM X DOPA RAM No Chg DOPB RAM X Data RAM Parity Ram
No Chg No Chg DIA DIPA
1524
RAMB16_Sm_Sn
WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=WRITE_FIRST

WEA 0 1 WEB 1 1 CLKA CLKB DIA DIA DIA DIB DIB DIB DIPA DIPA DIPA DIPB DIPB DIPB DOA X No Chg DOB DIB X DOPA X No Chg DOPB DIPB X Data RAM DIB X Parity Ram DIPB X
WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=WRITE_FIRST

WEA 0 1 0 1 WEB 0 0 1 1 CLKA CLKB DIA DIA DIA DIA DIA DIB DIB DIB DIB DIB DIPA DIPA DIPA DIPA DIPA DIPB DIPB DIPB DIPB DIPB DOA RAM RAM X X DOB RAM RAM DIB DIB DOPA RAM RAM X X DOPB RAM RAM DIPB DIPB Data RAM Parity Ram
No Chg No Chg DIA DIB DIA DIPA DIPB DIPA
Usage
For HDL, these design elements can be inferred or instantiated. The instantiation code is shown below. For information on how to infer RAM, see the XST User Guide.
VHDL Instantiation Template for RAMB16_S1_S1, RAMB16_S1_S2, RAMB16_S1_S4, RAMB16_S2_S2, RAMB16_S2_S4, and RAMB16_S4_S4
-- Component Declaration for RAMB16_S1_{S1 | S2 | S4}, RAMB16_S2_{S2 | S4}, and -- RAMB16_S4_S4 should be placed after architecture statement but before begin keyword
-- For the following component declaration, enter RAMB16_S1_{S1 | S2 | S4}, -- RAMB16_S2_{S2 | S4}, or RAMB16_S4_S4
component RAMB16_Sm_Sn -- synthesis translate_off generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1525
RAMB16_Sm_Sn
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1526
RAMB16_Sm_Sn
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1527
RAMB16_Sm_Sn
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_A : bit_vector := X"0"; INIT_B : bit_vector := X"0"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1528
RAMB16_Sm_Sn
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL_A : bit_vector := X"0"; SRVAL_B : bit_vector := X"0"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST";
); -- synthesis translate_on
port (DOA : out STD_LOGIC_VECTOR (n downto 0); DOB : out STD_LOGIC_VECTOR (n downto 0); ADDRA : in STD_LOGIC_VECTOR (n downto 0); ADDRB : in STD_LOGIC_VECTOR (n downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (n downto 0); DIB : in STD_LOGIC_VECTOR (n downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; SSRA : in STD_ULOGIC; SSRB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC);
end component;
1529
RAMB16_Sm_Sn
-- Component Attribute Specification for design element -- should be placed after architecture declaration -- but before the begin keyword
-- Component Instantiation for design element -- Should be placed in architecture after the begin keyword
RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn -- synthesis translate_off generic map ( INIT_00 => vector_value, INIT_01 => vector_value, INIT_02 => vector_value, INIT_03 => vector_value, INIT_04 => vector_value, INIT_05 => vector_value, INIT_06 => vector_value, INIT_07 => vector_value, INIT_08 => vector_value, INIT_09 => vector_value, INIT_0A => vector_value, INIT_0B => vector_value, INIT_0C => vector_value, INIT_0D => vector_value, INIT_0E => vector_value, INIT_0F => vector_value, INIT_10 => vector_value, INIT_11 => vector_value, INIT_12 => vector_value, INIT_13 => vector_value, INIT_14 => vector_value, INIT_15 => vector_value,
1530
RAMB16_Sm_Sn
INIT_16 => vector_value, INIT_17 => vector_value, INIT_18 => vector_value, INIT_19 => vector_value, INIT_1A => vector_value, INIT_1B => vector_value, INIT_1C => vector_value, INIT_1D => vector_value, INIT_1E => vector_value, INIT_1F => vector_value, INIT_20 => vector_value, INIT_21 => vector_value, INIT_22 => vector_value, INIT_23 => vector_value, INIT_24 => vector_value, INIT_25 => vector_value, INIT_26 => vector_value, INIT_27 => vector_value, INIT_28 => vector_value, INIT_29 => vector_value, INIT_2A => vector_value, INIT_2B => vector_value, INIT_2C => vector_value, INIT_2D => vector_value, INIT_2E => vector_value, INIT_2F => vector_value, INIT_30 => vector_value, INIT_31 => vector_value, INIT_32 => vector_value, INIT_33 => vector_value, INIT_34 => vector_value, INIT_35 => vector_value, INIT_36 => vector_value, INIT_37 => vector_value, INIT_38 => vector_value,
1531
RAMB16_Sm_Sn
INIT_39 => vector_value, INIT_3A => vector_value, INIT_3B => vector_value, INIT_3C => vector_value, INIT_3D => vector_value, INIT_3E => vector_value, INIT_3F => vector_value, INIT_A => bit_value, INIT_B => bit_value, INITP_00 => vector_value, INITP_01 => vector_value, INITP_02 => vector_value, INITP_03 => vector_value, INITP_04 => vector_value, INITP_05 => vector_value, INITP_06 => vector_value, INITP_07 => vector_value, SRVAL_A => bit_value, SRVAL_B => bit_value, WRITE_MODE_A => string_value, WRITE_MODE_B => string_value) -- synopsys translate_on port map (DOA => user_DOA, DOB => user_DOB, ADDRA => user_ADDRA, ADDRB => user_ADDRB, CLKA => user_CLKA, CLKB => user_CLKB, DIA => user_DIA, DIB => user_DIB, ENA => user_ENA, ENB => user_ENB, SSRA => user_SSRA, SSRB => user_SSRB, WEA => user_WEA,
1532
RAMB16_Sm_Sn
WEB => user_WEB);
Verilog Instantiation Template for RAMB16_S1_S1, RAMB16_S1_S2, RAMB16_S1_S4, RAMB16_S2_S2, RAMB16_S2_S4, and RAMB16_S4_S4
RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA), .DOB (user_DOB), .ADDRA (user_ADDRA), .ADDRB (user_ADDRB), .CLKA (user_CLKA), .CLKB (user_CLKB), .DIA (user_DIA), .DIB (user_DIB), .ENA (user_ENA), .ENB (user_ENB), .SSRA (user_SSRA), .SSRB (user_SSRB), .WEA (user_WEA), .WEB (user_WEB));
1533
RAMB16_Sm_Sn
defparam user_instance_name.INIT_10 = 256_bit_hex_value; defparam user_instance_name.INIT_11 = 256_bit_hex_value; defparam user_instance_name.INIT_12 = 256_bit_hex_value; defparam user_instance_name.INIT_13 = 256_bit_hex_value; defparam user_instance_name.INIT_14 = 256_bit_hex_value; defparam user_instance_name.INIT_15 = 256_bit_hex_value; defparam user_instance_name.INIT_16 = 256_bit_hex_value; defparam user_instance_name.INIT_17 = 256_bit_hex_value; defparam user_instance_name.INIT_18 = 256_bit_hex_value; defparam user_instance_name.INIT_19 = 256_bit_hex_value; defparam user_instance_name.INIT_1A = 256_bit_hex_value; defparam user_instance_name.INIT_1B = 256_bit_hex_value; defparam user_instance_name.INIT_1C = 256_bit_hex_value; defparam user_instance_name.INIT_1D = 256_bit_hex_value; defparam user_instance_name.INIT_1E = 256_bit_hex_value; defparam user_instance_name.INIT_1F = 256_bit_hex_value; defparam user_instance_name.INIT_20 = 256_bit_hex_value; defparam user_instance_name.INIT_21 = 256_bit_hex_value; defparam user_instance_name.INIT_22 = 256_bit_hex_value; defparam user_instance_name.INIT_23 = 256_bit_hex_value; defparam user_instance_name.INIT_24 = 256_bit_hex_value; defparam user_instance_name.INIT_25 = 256_bit_hex_value; defparam user_instance_name.INIT_26 = 256_bit_hex_value; defparam user_instance_name.INIT_27 = 256_bit_hex_value; defparam user_instance_name.INIT_28 = 256_bit_hex_value; defparam user_instance_name.INIT_29 = 256_bit_hex_value; defparam user_instance_name.INIT_2A = 256_bit_hex_value; defparam user_instance_name.INIT_2B = 256_bit_hex_value; defparam user_instance_name.INIT_2C = 256_bit_hex_value; defparam user_instance_name.INIT_2D = 256_bit_hex_value; defparam user_instance_name.INIT_2E = 256_bit_hex_value; defparam user_instance_name.INIT_2F = 256_bit_hex_value; defparam user_instance_name.INIT_30 = 256_bit_hex_value; defparam user_instance_name.INIT_31 = 256_bit_hex_value; defparam user_instance_name.INIT_32 = 256_bit_hex_value;
1534
RAMB16_Sm_Sn
defparam user_instance_name.INIT_33 = 256_bit_hex_value; defparam user_instance_name.INIT_34 = 256_bit_hex_value; defparam user_instance_name.INIT_35 = 256_bit_hex_value; defparam user_instance_name.INIT_36 = 256_bit_hex_value; defparam user_instance_name.INIT_37 = 256_bit_hex_value; defparam user_instance_name.INIT_38 = 256_bit_hex_value; defparam user_instance_name.INIT_39 = 256_bit_hex_value; defparam user_instance_name.INIT_3A = 256_bit_hex_value; defparam user_instance_name.INIT_3B = 256_bit_hex_value; defparam user_instance_name.INIT_3C = 256_bit_hex_value; defparam user_instance_name.INIT_3D = 256_bit_hex_value; defparam user_instance_name.INIT_3E = 256_bit_hex_value; defparam user_instance_name.INIT_3F = 256_bit_hex_value; defparam user_instance_name.INIT_A = bit_value; defparam user_instance_name.INIT_B = bit_value; defparam user_instance_name.INITP_00 = 256_bit_hex_value; defparam user_instance_name.INITP_01 = 256_bit_hex_value; defparam user_instance_name.INITP_02 = 256_bit_hex_value; defparam user_instance_name.INITP_03 = 256_bit_hex_value; defparam user_instance_name.INITP_04 = 256_bit_hex_value; defparam user_instance_name.INITP_05 = 256_bit_hex_value; defparam user_instance_name.INITP_06 = 256_bit_hex_value; defparam user_instance_name.INITP_07 = 256_bit_hex_value; defparam user_instance_name.SRVAL_A = bit_value; defparam user_instance_name.SRVAL_B = bit_value; defparam user_instance_name.WRITE_MODE_A = string_value; defparam user_instance_name.WRITE_MODE_B = string_value;
VHDL Instantiation Template for RAMB16_S1_S9, RAMB16_S1_S18, RAMB16_S1_S36, RAMB16_S2_S9, RAMB16_S2_S18, RAMB16_S2_S36, RAMB16_S4_S9, RAMB16_S4_S18, and RAMB16_S4_S36
-- Component Declaration for these design elements -- should be placed after architecture statement but before begin keyword
-- For the following component declaration, enter RAMB16_S1_{S9 | S18 | S36},
1535
RAMB16_Sm_Sn
-- RAMB16_S2_{S9 | S18 | S36}, or RAMB16_S4_{S9 | S18 | S36}
component RAMB16_Sm_Sn -- synthesis translate_off generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1536
RAMB16_Sm_Sn
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1537
RAMB16_Sm_Sn
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1538
RAMB16_Sm_Sn
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_A : bit_vector := X"0"; INIT_B : bit_vector := X"0"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL_A : bit_vector := X"0"; SRVAL_B : bit_vector := X"0"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; ); -- synthesis translate_on
port (DOA : out STD_LOGIC_VECTOR (n downto 0); DOB : out STD_LOGIC_VECTOR (n downto 0); DOPB : out STD_LOGIC_VECTOR (n downto 0); ADDRA : in STD_LOGIC_VECTOR (n downto 0); ADDRB : in STD_LOGIC_VECTOR (n downto 0); CLKA : in STD_ULOGIC;
1539
RAMB16_Sm_Sn
CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (n downto 0); DIB : in STD_LOGIC_VECTOR (n downto 0); DIPB : in STD_LOGIC_VECTOR (n downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; SSRA : in STD_ULOGIC; SSRB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC);
end component;
-- Put attributes, if necessary -- Component Instantiation for design element -- Should be placed in architecture after the begin keyword
RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn -- synthesis translate_off generic map ( INIT_00 => vector_value, INIT_01 => vector_value, INIT_02 => vector_value, INIT_03 => vector_value, INIT_04 => vector_value, INIT_05 => vector_value, INIT_06 => vector_value, INIT_07 => vector_value, INIT_08 => vector_value, INIT_09 => vector_value, INIT_0A => vector_value,
1540
RAMB16_Sm_Sn
INIT_0B => vector_value, INIT_0C => vector_value, INIT_0D => vector_value, INIT_0E => vector_value, INIT_0F => vector_value, INIT_10 => vector_value, INIT_11 => vector_value, INIT_12 => vector_value, INIT_13 => vector_value, INIT_14 => vector_value, INIT_15 => vector_value, INIT_16 => vector_value, INIT_17 => vector_value, INIT_18 => vector_value, INIT_19 => vector_value, INIT_1A => vector_value, INIT_1B => vector_value, INIT_1C => vector_value, INIT_1D => vector_value, INIT_1E => vector_value, INIT_1F => vector_value, INIT_20 => vector_value, INIT_21 => vector_value, INIT_22 => vector_value, INIT_23 => vector_value, INIT_24 => vector_value, INIT_25 => vector_value, INIT_26 => vector_value, INIT_27 => vector_value, INIT_28 => vector_value, INIT_29 => vector_value, INIT_2A => vector_value, INIT_2B => vector_value, INIT_2C => vector_value, INIT_2D => vector_value,
1541
RAMB16_Sm_Sn
INIT_2E => vector_value, INIT_2F => vector_value, INIT_30 => vector_value, INIT_31 => vector_value, INIT_32 => vector_value, INIT_33 => vector_value, INIT_34 => vector_value, INIT_35 => vector_value, INIT_36 => vector_value, INIT_37 => vector_value, INIT_38 => vector_value, INIT_39 => vector_value, INIT_3A => vector_value, INIT_3B => vector_value, INIT_3C => vector_value, INIT_3D => vector_value, INIT_3E => vector_value, INIT_3F => vector_value, INIT_A => bit_value, INIT_B => bit_value, INITP_00 => vector_value, INITP_01 => vector_value, INITP_02 => vector_value, INITP_03 => vector_value, INITP_04 => vector_value, INITP_05 => vector_value, INITP_06 => vector_value, INITP_07 => vector_value, SRVAL_A => bit_value, SRVAL_B => bit_value, WRITE_MODE_A => string_value, WRITE_MODE_B => string_value) -- synopsys translate_on port map (DOA => user_DOA, DOB => user_DOB,
1542
RAMB16_Sm_Sn
DOPB => user_DOPB, ADDRA => user_ADDRA, ADDRB => user_ADDRB, CLKA => user_CLKA, CLKB => user_CLKB, DIA => user_DIA, DIB => user_DIB, DIPB => user_DIPB, ENA => user_ENA, ENB => user_ENB, SSRA => user_SSRA, SSRB => user_SSRB, WEA => user_WEA, WEB => user_WEB);
Verilog Instantiation Template for RAMB16_S1_S9, RAMB16_S1_S18, RAMB16_S1_S36, RAMB16_S2_S9, RAMB16_S2_S18, RAMB16_S2_S36, RAMB16_S4_S9, RAMB16_S4_S18, and RAMB16_S4_S36
RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA), .DOB (user_DOB), .DOPB (user_DOPB), .ADDRA (user_ADDRA), .ADDRB (user_ADDRB), .CLKA (user_CLKA), .CLKB (user_CLKB), .DIA (user_DIA), .DIB (user_DIB), .DIPB (user_DIB), .ENA (user_ENA), .ENB (user_ENB), .SSRA (user_SSRA), .SSRB (user_SSRB), .WEA (user_WEA), .WEB (user_WEB));
1543
RAMB16_Sm_Sn
defparam user_instance_name.INIT_00 = 256_bit_hex_value; defparam user_instance_name.INIT_01 = 256_bit_hex_value; defparam user_instance_name.INIT_02 = 256_bit_hex_value; defparam user_instance_name.INIT_03 = 256_bit_hex_value; defparam user_instance_name.INIT_04 = 256_bit_hex_value; defparam user_instance_name.INIT_05 = 256_bit_hex_value; defparam user_instance_name.INIT_06 = 256_bit_hex_value; defparam user_instance_name.INIT_07 = 256_bit_hex_value; defparam user_instance_name.INIT_08 = 256_bit_hex_value; defparam user_instance_name.INIT_09 = 256_bit_hex_value; defparam user_instance_name.INIT_0A = 256_bit_hex_value; defparam user_instance_name.INIT_0B = 256_bit_hex_value; defparam user_instance_name.INIT_0C = 256_bit_hex_value; defparam user_instance_name.INIT_0D = 256_bit_hex_value; defparam user_instance_name.INIT_0E = 256_bit_hex_value; defparam user_instance_name.INIT_0F = 256_bit_hex_value; defparam user_instance_name.INIT_10 = 256_bit_hex_value; defparam user_instance_name.INIT_11 = 256_bit_hex_value; defparam user_instance_name.INIT_12 = 256_bit_hex_value; defparam user_instance_name.INIT_13 = 256_bit_hex_value; defparam user_instance_name.INIT_14 = 256_bit_hex_value; defparam user_instance_name.INIT_15 = 256_bit_hex_value; defparam user_instance_name.INIT_16 = 256_bit_hex_value; defparam user_instance_name.INIT_17 = 256_bit_hex_value; defparam user_instance_name.INIT_18 = 256_bit_hex_value; defparam user_instance_name.INIT_19 = 256_bit_hex_value; defparam user_instance_name.INIT_1A = 256_bit_hex_value; defparam user_instance_name.INIT_1B = 256_bit_hex_value; defparam user_instance_name.INIT_1C = 256_bit_hex_value; defparam user_instance_name.INIT_1D = 256_bit_hex_value; defparam user_instance_name.INIT_1E = 256_bit_hex_value; defparam user_instance_name.INIT_1F = 256_bit_hex_value; defparam user_instance_name.INIT_20 = 256_bit_hex_value; defparam user_instance_name.INIT_21 = 256_bit_hex_value; defparam user_instance_name.INIT_22 = 256_bit_hex_value;
1544
RAMB16_Sm_Sn
defparam user_instance_name.INIT_23 = 256_bit_hex_value; defparam user_instance_name.INIT_24 = 256_bit_hex_value; defparam user_instance_name.INIT_25 = 256_bit_hex_value; defparam user_instance_name.INIT_26 = 256_bit_hex_value; defparam user_instance_name.INIT_27 = 256_bit_hex_value; defparam user_instance_name.INIT_28 = 256_bit_hex_value; defparam user_instance_name.INIT_29 = 256_bit_hex_value; defparam user_instance_name.INIT_2A = 256_bit_hex_value; defparam user_instance_name.INIT_2B = 256_bit_hex_value; defparam user_instance_name.INIT_2C = 256_bit_hex_value; defparam user_instance_name.INIT_2D = 256_bit_hex_value; defparam user_instance_name.INIT_2E = 256_bit_hex_value; defparam user_instance_name.INIT_2F = 256_bit_hex_value; defparam user_instance_name.INIT_30 = 256_bit_hex_value; defparam user_instance_name.INIT_31 = 256_bit_hex_value; defparam user_instance_name.INIT_32 = 256_bit_hex_value; defparam user_instance_name.INIT_33 = 256_bit_hex_value; defparam user_instance_name.INIT_34 = 256_bit_hex_value; defparam user_instance_name.INIT_35 = 256_bit_hex_value; defparam user_instance_name.INIT_36 = 256_bit_hex_value; defparam user_instance_name.INIT_37 = 256_bit_hex_value; defparam user_instance_name.INIT_38 = 256_bit_hex_value; defparam user_instance_name.INIT_39 = 256_bit_hex_value; defparam user_instance_name.INIT_3A = 256_bit_hex_value; defparam user_instance_name.INIT_3B = 256_bit_hex_value; defparam user_instance_name.INIT_3C = 256_bit_hex_value; defparam user_instance_name.INIT_3D = 256_bit_hex_value; defparam user_instance_name.INIT_3E = 256_bit_hex_value; defparam user_instance_name.INIT_3F = 256_bit_hex_value; defparam user_instance_name.INIT_A = bit_value; defparam user_instance_name.INIT_B = bit_value; defparam user_instance_name.INITP_00 = 256_bit_hex_value; defparam user_instance_name.INITP_01 = 256_bit_hex_value; defparam user_instance_name.INITP_02 = 256_bit_hex_value; defparam user_instance_name.INITP_03 = 256_bit_hex_value;
1545
RAMB16_Sm_Sn
defparam user_instance_name.INITP_04 = 256_bit_hex_value; defparam user_instance_name.INITP_05 = 256_bit_hex_value; defparam user_instance_name.INITP_06 = 256_bit_hex_value; defparam user_instance_name.INITP_07 = 256_bit_hex_value; defparam user_instance_name.SRVAL_A = bit_value; defparam user_instance_name.SRVAL_B = bit_value; defparam user_instance_name.WRITE_MODE_A = string_value; defparam user_instance_name.WRITE_MODE_B = string_value;
VHDL Instantiation Template RAMB16_S9_S9, RAMB16_S9_S18, RAMB16_S9_S36, RAMB16_S18_S18, RAMB16_S18_S36, and RAMB16_S36_S36
-- Component Declaration for these design elements -- should be placed after architecture statement but before begin keyword
-- For the following component declaration, enter RAMB16_S9_{S9 | S18 | S36}, -- RAMB16_S18_{S18 | S36}, or RAMB16_S36_S36
component RAMB16_Sm_Sn -- synthesis translate_off generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1546
RAMB16_Sm_Sn
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1547
RAMB16_Sm_Sn
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1548
RAMB16_Sm_Sn
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_A : bit_vector := X"0"; INIT_B : bit_vector := X"0"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1549
RAMB16_Sm_Sn
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL_A : bit_vector := X"0"; SRVAL_B : bit_vector := X"0"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; ); -- synthesis translate_on
port (DOA : out STD_LOGIC_VECTOR (n downto 0); DOB : out STD_LOGIC_VECTOR (n downto 0); DOPA : out STD_LOGIC_VECTOR (n downto 0); DOPB : out STD_LOGIC_VECTOR (n downto 0); ADDRA : in STD_LOGIC_VECTOR (n downto 0); ADDRB : in STD_LOGIC_VECTOR (n downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (n downto 0); DIB : in STD_LOGIC_VECTOR (n downto 0); DIPA : in STD_LOGIC_VECTOR (n downto 0); DIPB : in STD_LOGIC_VECTOR (n downto 0); ENA: in STD_ULOGIC; ENB : in STD_ULOGIC; SSRA : in STD_ULOGIC; SSRB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC);
end component;
1550
RAMB16_Sm_Sn
-- Component Instantiation for design element -- Should be placed in architecture after the begin keyword
RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn -- synthesis translate_off generic map ( INIT_00 => vector_value, INIT_01 => vector_value, INIT_02 => vector_value, INIT_03 => vector_value, INIT_04 => vector_value, INIT_05 => vector_value, INIT_06 => vector_value, INIT_07 => vector_value, INIT_08 => vector_value, INIT_09 => vector_value, INIT_0A => vector_value, INIT_0B => vector_value, INIT_0C => vector_value, INIT_0D => vector_value, INIT_0E => vector_value, INIT_0F => vector_value, INIT_10 => vector_value, INIT_11 => vector_value, INIT_12 => vector_value, INIT_13 => vector_value, INIT_14 => vector_value, INIT_15 => vector_value, INIT_16 => vector_value, INIT_17 => vector_value, INIT_18 => vector_value, INIT_19 => vector_value, INIT_1A => vector_value, INIT_1B => vector_value,
1551
RAMB16_Sm_Sn
INIT_1C => vector_value, INIT_1D => vector_value, INIT_1E => vector_value, INIT_1F => vector_value, INIT_20 => vector_value, INIT_21 => vector_value, INIT_22 => vector_value, INIT_23 => vector_value, INIT_24 => vector_value, INIT_25 => vector_value, INIT_26 => vector_value, INIT_27 => vector_value, INIT_28 => vector_value, INIT_29 => vector_value, INIT_2A => vector_value, INIT_2B => vector_value, INIT_2C => vector_value, INIT_2D => vector_value, INIT_2E => vector_value, INIT_2F => vector_value, INIT_30 => vector_value, INIT_31 => vector_value, INIT_32 => vector_value, INIT_33 => vector_value, INIT_34 => vector_value, INIT_35 => vector_value, INIT_36 => vector_value, INIT_37 => vector_value, INIT_38 => vector_value, INIT_39 => vector_value, INIT_3A => vector_value, INIT_3B => vector_value, INIT_3C => vector_value, INIT_3D => vector_value, INIT_3E => vector_value,
1552
RAMB16_Sm_Sn
INIT_3F => vector_value, INIT_A => bit_value, INIT_B => bit_value, INITP_00 => vector_value, INITP_01 => vector_value, INITP_02 => vector_value, INITP_03 => vector_value, INITP_04 => vector_value, INITP_05 => vector_value, INITP_06 => vector_value, INITP_07 => vector_value, SRVAL_A => bit_value, SRVAL_B => bit_value, WRITE_MODE_A => string_value, WRITE_MODE_B => string_value) -- synopsys translate_on port map (DOA => user_DOA, DOB => user_DOB, DOPA => user_DOPA, DOPB => user_DOPB, ADDRA => user_ADDRA, ADDRB => user_ADDRB, CLKA => user_CLKA, CLKB => user_CLKB, DIA => user_DIA, DIB => user_DIB, DIPA => user_DIPA, DIPB => user_DIPB, ENA => user_ENA, ENB => user_ENB, SSRA => user_SSRA, SSRB => user_SSRB, WEA => user_WEA, WEB => user_WEB);
1553
RAMB16_Sm_Sn
Verilog Instantiation Template for RAMB16_S9_S9, RAMB16_S9_S18, RAMB16_S9_S36, RAMB16_S18_S18, RAMB16_S18_S36, and RAMB16_S36_S36
RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA), .DOB (user_DOB), .DOPA (user_DOPA), .DOPB (user_DOPB), .ADDRA (user_ADDRA), .ADDRB (user_ADDRB), .CLKA (user_CLKA), .CLKB (user_CLKB), .DIA (user_DIA), .DIB (user_DIB), .DIPA (user_DIPA), .DIPB (user_DIB), .ENA (user_ENA), .ENB (user_ENB), .SSRA (user_SSRA), .SSRB (user_SSRB), .WEA (user_WEA), .WEB (user_WEB));
defparam user_instance_name.INIT_00 = 256_bit_hex_value; defparam user_instance_name.INIT_01 = 256_bit_hex_value; defparam user_instance_name.INIT_02 = 256_bit_hex_value; defparam user_instance_name.INIT_03 = 256_bit_hex_value; defparam user_instance_name.INIT_04 = 256_bit_hex_value; defparam user_instance_name.INIT_05 = 256_bit_hex_value; defparam user_instance_name.INIT_06 = 256_bit_hex_value; defparam user_instance_name.INIT_07 = 256_bit_hex_value; defparam user_instance_name.INIT_08 = 256_bit_hex_value; defparam user_instance_name.INIT_09 = 256_bit_hex_value; defparam user_instance_name.INIT_0A = 256_bit_hex_value; defparam user_instance_name.INIT_0B = 256_bit_hex_value; defparam user_instance_name.INIT_0C = 256_bit_hex_value; defparam user_instance_name.INIT_0D = 256_bit_hex_value;
1554
RAMB16_Sm_Sn
defparam user_instance_name.INIT_0E = 256_bit_hex_value; defparam user_instance_name.INIT_0F = 256_bit_hex_value; defparam user_instance_name.INIT_10 = 256_bit_hex_value; defparam user_instance_name.INIT_11 = 256_bit_hex_value; defparam user_instance_name.INIT_12 = 256_bit_hex_value; defparam user_instance_name.INIT_13 = 256_bit_hex_value; defparam user_instance_name.INIT_14 = 256_bit_hex_value; defparam user_instance_name.INIT_15 = 256_bit_hex_value; defparam user_instance_name.INIT_16 = 256_bit_hex_value; defparam user_instance_name.INIT_17 = 256_bit_hex_value; defparam user_instance_name.INIT_18 = 256_bit_hex_value; defparam user_instance_name.INIT_19 = 256_bit_hex_value; defparam user_instance_name.INIT_1A = 256_bit_hex_value; defparam user_instance_name.INIT_1B = 256_bit_hex_value; defparam user_instance_name.INIT_1C = 256_bit_hex_value; defparam user_instance_name.INIT_1D = 256_bit_hex_value; defparam user_instance_name.INIT_1E = 256_bit_hex_value; defparam user_instance_name.INIT_1F = 256_bit_hex_value; defparam user_instance_name.INIT_20 = 256_bit_hex_value; defparam user_instance_name.INIT_21 = 256_bit_hex_value; defparam user_instance_name.INIT_22 = 256_bit_hex_value; defparam user_instance_name.INIT_23 = 256_bit_hex_value; defparam user_instance_name.INIT_24 = 256_bit_hex_value; defparam user_instance_name.INIT_25 = 256_bit_hex_value; defparam user_instance_name.INIT_26 = 256_bit_hex_value; defparam user_instance_name.INIT_27 = 256_bit_hex_value; defparam user_instance_name.INIT_28 = 256_bit_hex_value; defparam user_instance_name.INIT_29 = 256_bit_hex_value; defparam user_instance_name.INIT_2A = 256_bit_hex_value; defparam user_instance_name.INIT_2B = 256_bit_hex_value; defparam user_instance_name.INIT_2C = 256_bit_hex_value; defparam user_instance_name.INIT_2D = 256_bit_hex_value; defparam user_instance_name.INIT_2E = 256_bit_hex_value; defparam user_instance_name.INIT_2F = 256_bit_hex_value; defparam user_instance_name.INIT_30 = 256_bit_hex_value;
1555
RAMB16_Sm_Sn
defparam user_instance_name.INIT_31 = 256_bit_hex_value; defparam user_instance_name.INIT_32 = 256_bit_hex_value; defparam user_instance_name.INIT_33 = 256_bit_hex_value; defparam user_instance_name.INIT_34 = 256_bit_hex_value; defparam user_instance_name.INIT_35 = 256_bit_hex_value; defparam user_instance_name.INIT_36 = 256_bit_hex_value; defparam user_instance_name.INIT_37 = 256_bit_hex_value; defparam user_instance_name.INIT_38 = 256_bit_hex_value; defparam user_instance_name.INIT_39 = 256_bit_hex_value; defparam user_instance_name.INIT_3A = 256_bit_hex_value; defparam user_instance_name.INIT_3B = 256_bit_hex_value; defparam user_instance_name.INIT_3C = 256_bit_hex_value; defparam user_instance_name.INIT_3D = 256_bit_hex_value; defparam user_instance_name.INIT_3E = 256_bit_hex_value; defparam user_instance_name.INIT_3F = 256_bit_hex_value; defparam user_instance_name.INIT_A = bit_value; defparam user_instance_name.INIT_B = bit_value; defparam user_instance_name.INITP_00 = 256_bit_hex_value; defparam user_instance_name.INITP_01 = 256_bit_hex_value; defparam user_instance_name.INITP_02 = 256_bit_hex_value; defparam user_instance_name.INITP_03 = 256_bit_hex_value; defparam user_instance_name.INITP_04 = 256_bit_hex_value; defparam user_instance_name.INITP_05 = 256_bit_hex_value; defparam user_instance_name.INITP_06 = 256_bit_hex_value; defparam user_instance_name.INITP_07 = 256_bit_hex_value; defparam user_instance_name.SRVAL_A = bit_value; defparam user_instance_name.SRVAL_B = bit_value; defparam user_instance_name.WRITE_MODE_A = string_value; defparam user_instance_name.WRITE_MODE_B = string_value;

INIT, INIT_xx, INIT_A, INIT_B, INTP_xx, SRVAL_A, SRVAL_B, WRITE_MODE_A, WRITE_MODE_B
1556
ROC
ROC
Reset On Configuration
ROC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
The ROC is a component used for VHDL simulation of FPGA designs. This component should not be used for Verilog or schematic entry. The ROC's function is to mimic the function of the internal reset signal during the FPGA configuration process. In order to use ROC, it must be connected to the reset/preset signal for all inferred and instantiated registers in the design. During synthesis and implementation, this reset signal will use the dedicated global set/reset network and will not use local routing resources. During simulation, ROC will emit a one-shot pulse for the amount of time specified by the WIDTH generic (default is 100 ns). This one-shot pulse is intended to reset all registers so that at the beginning of operation, all registers are at a known value as would happen in the real silicon during configuration of the device. For more information, see the Xilinx Synthesis and Verification Design Guide. Port O will be high at simulation time 0 for the amount of time specified by the WIDTH generic attribute. After that time, it will be 0. This will not affect implementation in any way.
VHDL Instantiation Code

component ROC -- synthesis translate_off generic (WIDTH : Time := 100 ns); -- synthesis translate_on port (O : out std_ulogic := '1'); end component;

For simulation, the WIDTH generic can be modified to change the amount of time the one-shot pulse is applied for. There are no supported constraints for this component for implementation.
1557
ROC
1558
ROCBUF
ROCBUF
Reset On Configuration Buffer
ROCBUF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
The ROCBUF is a component used for VHDL simulation of FPGA designs that is similar to the ROC component except that it contains an input for controlling the global set/reset function rather than a one-shot. This component should not be used for Verilog or schematic entry. The ROCBUF's function allows user control of the function of the global set/reset signal as done during the FPGA configuration process. In order to use the ROCBUF, the input should be connected to a top-level port in the design and the output must be connected to the reset/preset signal for all inferred and instantiated registers in the design. During simulation, the input to the ROCBUF can be toggled by the testbench in order to activate the global set/reset signal in the design. This should be done at the beginning of the simulation as is done in the real silicon after configuration to get the design in a known state. The signal may also be pulsed during simulation to simulate a reconfiguration (ProG pin high) of the device. During synthesis and implementation, this reset signal will use the dedicated global set/reset network and will not use local routing resources. The port connected to this component will be optimized out of the design and not use any pin resources. If you want to have the port implemented in the design, a STARTBUF_architecture should be used. In order to replace this port during back-end simulation the -gp switch should be used when invoking the netgen. If using the ISE GUI, use the "Bring Out Global Set/Reset Net as a Port" option in the Simulation Model Properties window. For more information, see the Xilinx Synthesis and Verification Design Guide. The value at port O will always be the value at port I (it is a buffer).

component ROCBUF port( I : in std_ulogic; O : out std_ulogic); end component;

None
1559
ROCBUF
1560
ROM16X1
ROM16X1
16-Deep by 1-Wide ROM
ROM16X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
A0 A1 A2 A3
ROM16X1
X4137
ROM16X1 is a 16-word by 1-bit read-only memory. The data output (O) reflects the word selected by the 4-bit address (A3 A0). The ROM is initialized to a known value during configuration with the INIT=value parameter. The value consists of four hexadecimal digits that are written into the ROM from the most-significant digit A=FH to the least-significant digit A=0H. For example, the INIT=10A7 parameter produces the data stream:
0001 0000 1010 0111
An error occurs if the INIT=value is not specified. See the appropriate CAE tool interface user guide for details.
Usage
For HDL, the ROM16X1 design element should be instantiated rather than inferred.

-- Component Declaration for ROM16X1 should be placed -- after architecture statement but before begin keyword component ROM16X1 -- synthesis translate_off generic (INIT : bit_vector := X"16"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC); end component; -- Component Attribute specification for ROM16X1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
1561
ROM16X1
-- Component Instantiation for ROM16X1 should be placed -- in architecture after the begin keyword ROM16X1_INSTANCE_NAME : ROM16X1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3);

ROM16X1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3)); defparam user_instance_name.INIT = hex_value;

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, ROM_EXTRACT, U_SET, XBLKNM
1562
ROM32X1
ROM32X1
ROM32X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
A0 A1 A2 A3 A4
ROM32X1
ROM32X1 is a 32-word by 1-bit read-only memory. The data output (O) reflects the word selected by the 5-bit address (A4 A0). The ROM is initialized to a known value during configuration with the INIT=value parameter. The value consists of eight hexadecimal digits that are written into the ROM from the most-significant digit A=1FH to the least-significant digit A=00H. For example, the INIT=10A78F39 parameter produces the data stream:
0001 0000 1010 0111 1000 1111 0011 1001
X4130
An error occurs if the INIT=value is not specified. See the appropriate CAE tool interface user guide for details.
Usage

-- Component Declaration for ROM32X1 should be placed -- after architecture statement but before begin keyword component ROM32X1 -- synthesis translate_off generic (INIT : bit_vector := X"32"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC); end component; -- Component Attribute specification for ROM32X1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
1563
ROM32X1
-- Component Instantiation for ROM32X1 should be placed -- in architecture after the begin keyword ROM32X1_INSTANCE_NAME : ROM32X1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4);

ROM32X1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4(user_A4)); defparam user_instance_name.INIT = hex_value;

1564
ROM64X1
ROM64X1
ROM64X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
A0 A1 A2 A3 A4 A5
ROM64X1
ROM64X1 is a 64-word by 1-bit read-only memory. The data output (O) reflects the word selected by the 6-bit address (A5 A0). The ROM is initialized to a known value during configuration with the INIT=value parameter. The value consists of 16 hexadecimal digits that are written into the ROM from the most-significant digit A=FH to the least-significant digit A=0H. An error occurs if the INIT=value is not specified. See the appropriate CAE tool interface user guide for details.
X9730
Usage

-- Component Declaration for ROM64X1 should be placed -- after architecture statement but before begin keyword component ROM64X1 -- synthesis translate_off generic (INIT : bit_vector := X"64"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC); end component; -- Component Attribute specification for ROM64X1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
1565
ROM64X1
-- Component Instantiation for ROM64X1 should be placed -- in architecture after the begin keyword ROM64X1_INSTANCE_NAME : ROM64X1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5);

ROM64X1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5 (user_A5)); defparam user_instance_name.INIT = hex_value;

1566
ROM128X1
ROM128X1
A0 A1 A2 A3 A4 A5 A6
ROM128X1
X9731
Usage

-- Component Declaration for ROM128X1 should be placed -- after architecture statement but before begin keyword component ROM128X1 -- synthesis translate_off generic (INIT : bit_vector := X"128"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; A6 : in STD_ULOGIC); end component; -- Component Attribute specification for ROM128X1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
1567
ROM128X1
-- Component Instantiation for ROM128X1 should be placed -- in architecture after the begin keyword ROM128X1_INSTANCE_NAME : ROM128X1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O => user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, A6 => user_A6);

ROM128X1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5 (user_A5), .A6 (user_A6)); defparam user_instance_name.INIT = hex_value;

1568
ROM256X1
ROM256X1
A0 A1 A2 A3 A4 A5 A6 A7
ROM256X1
X9732
Usage

-- Component Declaration for ROM256X1 should be placed -- after architecture statement but before begin keyword component ROM256X1 -- synthesis translate_off generic (INIT : bit_vector := X"256"); -- synthesis translate_on port (O : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; A6 : in STD_ULOGIC; A7 : in STD_ULOGIC); end component; -- Component Attribute specification for ROM256X1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
1569
ROM256X1
-- Component Instantiation for ROM256X1 should be placed -- in architecture after the begin keyword ROM256X1_INSTANCE_NAME : ROM256X1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (O=> user_O, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, A4 => user_A4, A5 => user_A5, A6 => user_A6, A7 => user_A7);

ROM256X1 instance_name (.O (user_O), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .A4 (user_A4), .A5(user_A5), .A6(user_A6), .A7(user_A7)); defparam user_instance_name.INIT = hex_value;

1570
SOP3-4
SOP3-4
Sum of Products
SOP3, SOP3B1A, SOP3B1B, SOP3B2A, SOP3B2B, SOP3B3 SOP4, SOP4B1, SOP4B2A, SOP4B2B, SOP4B3, SOP4B4 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro No No No
I3 I2 O I1 I0 SOP3 I1 I0 SOP3B2A I2 O I1 I0 SOP4 I2 O I1 I0 SOP4B2B I3 I2 O
I3 I2 O I1 I0 SOP3B1A I1 I0 SOP3B2B I2 O I1 I0 SOP4B1 I2 O
I3 I2 O I1 I0 SOP4B3
I3 I2 O I1 I0 SOP3B1B I1 I0 SOP3B3 I2 O I1 I0 SOP4B2A I2 O
I3 I2 O I1 I0 SOP4B4
X9421
SOP Gate Representations Sum Of Products (SOP) macros provide common logic functions by OR gating the outputs of two AND functions or the output of one AND function with one direct input. Variations of inverting and non-inverting inputs are available.
I2 I1 I0 AND2 I01 OR2 X8111 O
SOP3 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1571
SOP3-4
I3 I2 AND2
I2B3
O I1 I0 AND2 X8112 OR2 I0B1B
SOP4 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E
I3 I2 AND2 I1 I0 AND2 I01 OR2 X9374 I23 O
SOP4 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1572
SR4CE, SR8CE, SR16CE

4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
SR4CE, SR8CE, SR16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
SLI CE C
SR4CE
Q0 Q1 Q2 Q3
CLR X4145
SLI CE C
SR8CE
Q[7:0]
SR4CE, SR8CE, and SR16CE are 4-, 8-, and 16-bit shift registers, respectively, with a shift-left serial input (SLI), parallel outputs (Q), and clock enable (CE) and asynchronous clear (CLR) inputs. The CLR input, when High, overrides all other inputs and resets the data outputs (Q) Low. When CE is High and CLR is Low, the data on the SLI input is loaded into the first bit of the shift register during the Low-toHigh clock (C) transition and appears on the Q0 output. During subsequent Low-toHigh clock transitions, when CE is High and CLR is Low, data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). The register ignores clock transitions when CE is Low. Registers can be cascaded by connecting the last Q output (Q3 for SR4CE, Q7 for SR8CE, or Q15 for SR16CE) of one stage to the SLI input of the next stage and connecting clock, CE, and CLR in parallel.
CLR X4151
The register is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 CE X 0 1 1 SLI X X 1 0 C X X Q0 0 No Chg 1 0 Outputs Qz Q1 0 No Chg qn-1 qn-1
SLI CE C
SR16CE
Q[15:0]
CLR X4157
z = 3 for SR4CE; z = 7for SR8CE; z = 15 for SR16CE qn-1 = state of referenced output one setup time prior to active clock transition
1573
Q[7:0]
FDCE FDCE
SLI CE D CE C CLR Q0 Q Q0 Q3 D CE C CLR Q4 Q Q4
FDCE FDCE
FDCE FDCE
FDCE FDCE
C CLR X7868
SR8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of sr4ce is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C, CLR) begin if (CLR='1') then Q_INT <= (others => '0'); elsif (C'event and C='1') then if (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; end if; end if; end process; Q <= Q_INT;
1574
end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= {Q[WIDTH-2:0],SLI}; end
1575
1576
SR4CLE, SR8CLE, SR16CLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
SR4CLE, SR8CLE, SR16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
SLI D0 D1 D2 D3 L CE C
SR4CLE
Q0 Q1 Q2 Q3
CLR X4147
SR4CLE, SR8CLE, and SR16CLE are 4-, 8-, and 16-bit shift registers, respectively, with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR).The register ignores clock transitions when L and CE are Low. The asynchronous CLR, when High, overrides all other inputs and resets the data outputs (Q) Low. When L is High and CLR is Low, data on the Dn D0 inputs is loaded into the corresponding Qn Q0 bits of the register. When CE is High and L and CLR are Low, data on the SLI input is loaded into the first bit of the shift register during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and L and CLR are Low, the data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). Registers can be cascaded by connecting the last Q output (Q3 for SR4CLE, Q7 for SR8CLE, or Q15 for SR16CLE) of one stage to the SLI input of the next stage and connecting clock, CE, L, and CLR inputs in parallel. The register is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
SLI D[15:0]
SR16CLE
Inputs
Q[15:0]
Outputs SLI X X SLI Dn D0 X Dn D0 X C X Q0 0 D0 SLI Qz Q1 0 Dn qn-1
L CE C
CLR 1 0 0
L X 1 0
CE X X 1
CLR X4159
1577
Inputs CLR 0 L 0 CE 0 SLI X Dn D0 X C X Q0
Outputs Qz Q1 No Chg
No Chg
z = 3 for SR4CLE; z = 7 for SR8CLE; z = 15 for SR16CLE qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0] CE
L_OR_CE OR2
SLI D0
M2_1
D0 D1 S0 O MQ0 MD0 D
FDCE
Q Q0 D4
M2_1
FDCE
Q Q4
CE C CLR Q0
CE C CLR Q4
M2_1
D1 D0 D1 S0 O MQ1 MD1 D
FDCE
Q Q1 D5
M2_1
FDCE
Q Q5
CE C CLR Q1
CE C CLR Q5
M2_1
FDCE
Q Q2 D6
M2_1
FDCE
Q Q6
CE C CLR Q2
CE C CLR Q6
M2_1
FDCE
Q Q3 D7
M2_1
FDCE
Q Q7
CE C CLR Q3
CE C CLR Q7
CLR C D[7:0] X7869
SR8CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of sr4cle is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C, CLR) begin if (CLR='1') then Q_INT <= (others => '0'); elsif (C'event and C='1') then
1578
if (CE='1') then if (L='1') then Q_INT <= D; else Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; end if; end if; end if; end process; Q <= Q_INT; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (L) Q <= D; else Q <= {Q[WIDTH-2:0],SLI}; end
1579
1580
SR4CLED, SR8CLED, SR16CLED

4-, 8-, 16-Bit Shift Registers with Clock Enable and Asynchronous Clear
SR4CLED, SR8CLED, SR16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
SLI D0 D1 D2 D3 SRI L LEFT CE C
SR4CLED
Q0 Q1 Q2 Q3
CLR X4149
SLI SR8CLED D[7:0] SRI Q[7:0] L LEFT CE C
SR4CLED, SR8CLED, and SR16CLED are 4-, 8-, and 16-bit shift registers, respectively, with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), and asynchronous clear (CLR). The register ignores clock transitions when CE and L are Low. The asynchronous clear, when High, overrides all other inputs and resets the data outputs (Qn) Low. When L is High and CLR is Low, the data on the D inputs is loaded into the corresponding Q bits of the register. When CE is High and L and CLR are Low, data is shifted right or left, depending on the state of the LEFT input. If LEFT is High, data on the SLI is loaded into Q0 during the Low-to-High clock transition and shifted left (to Q1, Q2, and so forth) during subsequent clock transitions. If LEFT is Low, data on the SRI is loaded into the last Q output (Q3 for SR4CLED, Q7 for SR8CLED, or Q15 for SR16CLED) during the Low-to-High clock transition and shifted right (to Q2, Q1,... for SR4CLED; to Q6, Q5,... for SR8CLED; and to Q14, Q13,... for SR16CLED) during subsequent clock transitions. The truth tables for SR4CLED, SR8CLED, and SR16CLED indicate the state of the Q outputs under all input conditions for SR4CLED, SR8CLED, and SR16CLED. The register is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
CLR X4155
SLI SR16CLED D[15:0] SRI L LEFT CE C Q[15:0]
SR4CLED Truth Table

Inputs CLR 1 L X 1 0 CE X X 0 LEFT X X X SLI X X X SRI X X X D3 D0 X D3 D0 X C X X Q0 0 D0 No Chg Outputs Q3 0 D3 No Chg Q2 Q1 0 Dn No Chg
CLR X4161
0 0
1581
SR4CLED Truth Table

Inputs CLR 0 0 L 0 0 CE 1 1 LEFT 1 0 SLI SLI X SRI X SRI D3 D0 X X C Q0 SLI q1 Outputs Q3 q2 SRI Q2 Q1 qn-1 qn+1
qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition
SR8CLED Truth Table

Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 LEFT X X X 1 0 SLI X X X SLI X SRI X X X X SRI D7 D0 X D7 D0 X X X C X X Q0 0 D0 No Chg SLI q1 Outputs Q7 0 D7 No Chg q6 SRI Q6 Q1 0 Dn No Chg qn-1 qn+1
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition
SR16CLED Truth Table

Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 LEFT X X X 1 0 SLI X X X SLI X SRI X X X X SRI D15 D0 X D15 D0 X X X C X X Q0 0 D0 No Chg SLI q1 Outputs Q15 0 D15 No Chg q14 SRI Q14 Q1 0 Dn No Chg qn-1 qn+1
1582
CE OR2 SLI D0 D0 D1 S0
L_OR_CE
M2_1
O MDL0 MDL0
D0 D1 S0
M2_1
O MDR0 MDR0 D CE C
FDCE
Q Q0 Q[7:0]
CLR Q0
D1
D0 D1 S0
M2_1
O MDL1 MDL1
D0 D1 S0
M2_1
O MDR1 MDR1 D CE C
FDCE
Q Q1
CLR Q1
D2
D0 D1 S0
M2_1
O MDL2 MDL2
D0 D1 S0
M2_1
O MDR2 MDR2 D CE C
FDCE
Q Q2
CLR Q2
D3
D0 D1 S0
M2_1
O MDL3 MDL3
D0 D1 S0
M2_1
O MDR3 MDR3 D CE C
FDCE
Q Q3
CLR Q3
M2_1
D4 D0 D1 S0 O MDL4 MDL4
D0 D1 S0
M2_1
O MDR4 MDR4 D CE C
FDCE
Q Q4
CLR Q4
D5
D0 D1 S0
M2_1
O MDL5 MDL5
D0 D1 S0
M2_1
O MDR5 MDR5 D CE C
FDCE
Q Q5
CLR Q5
D0 D6 D1 S0
M2_1
O MDL6 MDL6
D0 D1 S0
M2_1
O MDR6 MDR6 D CE C
FDCE
Q Q6
CLR Q6
D[7:0] L SRI
D0 D7 D1 S0
M2_1
O MDL7 MDL7
D0 D1 S0
M2_1
O MDR7 MDR7 D CE C
FDCE
Q Q7
CLR Q7
LEFT CLR C OR2
L_LEFT
X7870
SR8CLED Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,
1583

VCC 5 CE AND2 OR2 D0 D1 S0 L_OR_CE
SLI D0
M2_1
O MDL0 MDL0
D0 D1 S0
M2_1
O MDR0 MDR0 D CE C
FDCE
Q Q0 Q[7:0]
CLR Q0
D1
D0 D1 S0
M2_1
O MDL1 MDL1
D0 D1 S0
M2_1
O MDR1 MDR1 D CE C
FDCE
Q Q1
CLR Q1
D2
D0 D1 S0
M2_1
O MDL2 MDL2
D0 D1 S0
M2_1
O MDR2 MDR2 D CE C
FDCE
Q Q2
CLR Q2
D3
D0 D1 S0
M2_1
O MDL3 MDL3
D0 D1 S0
M2_1
O MDR3 MDR3 D CE C
FDCE
Q Q3
CLR Q3
M2_1
D0 D1 S0
M2_1
O MDR4 MDR4 D CE C
FDCE
Q Q4
CLR Q4
D5
D0 D1 S0
M2_1
O MDL5 MDL5
D0 D1 S0
M2_1
O MDR5 MDR5 D CE C
FDCE
Q Q5
CLR Q5
D6
D0 D1 S0
M2_1
O MDL6 MDL6
D0 D1 S0
M2_1
O MDR6 MDR6 D CE C
FDCE
Q Q6
CLR Q6
D[7:0]
D7
D0 D1 S0
M2_1
O MDL7 MDL7
D0 D1 S0
M2_1
O MDR7 MDR7 D CE C
FDCE
Q Q7
L LEFT OR2 OR2 GND SRI CLR C OR2 L_LEFT
CLR Q7
X8108
SR8CLED Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1584
Usage
VHDL Inference Code

architecture Behavioral of sr4cled is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C, CLR) begin if (CLR='1') then Q_INT <= (others => '0'); elsif (C'event and C='1') then if (CE='1') then if (L='1') then Q_INT <= D; else if (LEFT='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; else Q_INT <= SRI & Q_INT(WIDTH-1 downto 1); end if; end if; end if; end if; end process; Q <= Q_INT; end Behavioral;

always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (L) Q <= D; else if (LEFT) Q <= {Q[WIDTH-2:0],SLI}; else Q <= {SRI, Q[WIDTH-1:1]}; end
1585
1586
SR4RE, SR8RE, SR16RE

4-, 8-, 16-Bit Serial-In Parallel-Out Shift Registers with Clock Enable and Synchronous Reset
SR4RE, SR8RE, SR16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
SLI CE C
SR4RE
Q0 Q1 Q2 Q3
R X4144
SLI CE C
SR8RE
Q[7:0]
SR4RE, SR8RE, and SR16RE are 4-, 8-, and 16-bit shift registers, respectively, with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE), and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Lowto-High clock (C) transition and resets the data outputs (Q) Low. When CE is High and R is Low, the data on the SLI is loaded into the first bit of the shift register during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent Low-to-High clock transitions, when CE is High and R is Low, data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). The register ignores clock transitions when CE is Low. Registers can be cascaded by connecting the last Q output (Q3 for SR4RE, Q7 for SR8RE, or Q15 for SR16RE) of one stage to the SLI input of the next stage and connecting clock, CE, and R in parallel.
R X4150
The register is asynchronously cleared, outputs Low, when power is applied.

SLI CE C
SR16RE
Q[15:0]
R X4156
Inputs R 1 0 0 CE X 0 1 SLI X X 1 C X Q0 0 No Chg 1 Outputs Qz Q1 0 No Chg qn-1
1587
Inputs R 0 CE 1 SLI 0 C Q0 0
Outputs Qz Q1 qn-1
z = 3 for SR4RE; z = 7 for SR8RE; z = 15 for SR16RE qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0]
FDRE FDRE
SLI CE D CE C R Q0 Q Q0 Q3 D CE C R Q4 Q Q4
FDRE FDRE
FDRE FDRE
FDRE FDRE
C R X7871
SR8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of sr4re is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if C'event and C='1' then if (R='1') then Q_INT <= (others => '0');
1588
elsif (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; end if; end if; end process; Q <= Q_INT; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (CE) Q <= {Q[WIDTH-2:0],SLI}; end
1589
1590
SR4RLE, SR8RLE, SR16RLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Synchronous Reset
SR4RLE, SR8RLE, SR16RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
SR4RLE
Q0 Q1 Q2 Q3
R X4146
SR4RLE, SR8RLE, and SR16RLE are 4-, 8-, and 16-bit shift registers, respectively, with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clock transitions when L and CE are Low. The synchronous R, when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs (Q) Low. When L is High and R is Low during the Low-to-High clock transition, data on the D inputs is loaded into the corresponding Q bits of the register. When CE is High and L and R are Low, data on the SLI input is loaded into the first bit of the shift register during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and L and R are Low, the data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). Registers can be cascaded by connecting the last Q output (Q3 for SR4RLE, Q7 for SR8RLE, or 15 for SR16RLE) of one stage to the SLI input of the next stage and connecting clock, CE, L, and R inputs in parallel. The register is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
SLI D[7:0]
SR8RLE
Q[7:0] L CE C
R X4152
Q[15:0]
SLI D[15:0]
SR16RLE
L CE C
Inputs R 1 0
X4158
Outputs SLI X X SLI Dz D0 X Dz D0 X C Q0 0 D0 SLI Qz Q1 0 Dn qn-1
L X 1 0
CE X X 1
1591
Inputs R 0 L 0 CE 0 SLI X Dz D0 X C X Q0
No Chg
z = 3 for SR4RLE; z = 7 for SR8RLE; z = 15 for SR16RLE qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0] CE
L_OR_CE OR2
SLI D0
M2_1
FDRE
Q Q0
Q3 D4
M2_1
FDRE
Q Q4
CE C R Q0
CE C R Q4
M2_1
FDRE
Q Q1 D5
M2_1
FDRE
Q Q5
CE C R Q1
CE C R Q5
M2_1
FDRE
Q Q2 D6
M2_1
FDRE
Q Q6
CE C R Q2
CE C R Q6
M2_1
FDRE
Q Q3 D7
M2_1
FDRE
Q Q7
CE C R Q3
CE C R Q7
R C D[7:0] X7872
SR8RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
Usage
VHDL Inference Code

architecture Behavioral of sr4rle is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if C'event and C='1' then if (R='1') then
1592
Q_INT <= (others => '0'); elsif (L='1') then Q_INT <= D; elsif (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; end if; end if; end if; end if; end process; Q <= Q_INT; end Behavioral;

always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) Q <= {Q[WIDTH-2:0],SLI}; end
1593
1594
SR4RLED, SR8RLED, SR16RLED

4-, 8-, 16-Bit Shift Registers with Clock Enable and Synchronous Reset
SR4RLED, SR8RLED, SR16RLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro
SR4RLED
Q0 Q1 Q2 Q3
R X4148
SLI SR8RLED D[7:0] SRI Q[7:0] L LEFT CE C
SR4RLED, SR8RLED, and SR16RLED are 4-, 8-, and 16-bit shift registers, respectively, with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), parallel outputs (Q) and four control inputs clock enable (CE), load enable (L), shift left/right (LEFT), and synchronous reset (R). The register ignores clock transitions when CE and L are Low. The synchronous R, when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs (Q) Low. When L is High and R is Low during the Low-to-High clock transition, the data on the D inputs is loaded into the corresponding Q bits of the register. When CE is High and L and R are Low, data is shifted right or left, depending on the state of the LEFT input. If LEFT is High, data on SLI is loaded into Q0 during the Low-to-High clock transition and shifted left (to Q1, Q2, and so forth) during subsequent clock transitions. If LEFT is Low, data on the SRI is loaded into the last Q output (Q3 for SR4RLED, Q7 for SR8RLED, or Q15 for SR16RLED) during the Low-to-High clock transition and shifted right (to Q2, Q1,... for SR4RLED; to Q6, Q5,... for SR8RLED; or to Q14, Q13,... for SR16RLED) during subsequent clock transitions. The truth table indicates the state of the Q outputs under all input conditions. The register is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
R X4154
SLI SR16RLED D[15:0] SRI Q[15:0] L LEFT CE C
SR4RLED Truth Table

Inputs R 1 L X 1 0 CE X X 0 LEFT X X X SLI X X X SRI X X X D3 D0 X D3 D0 X C X Q0 0 D0 No Chg Outputs Q3 0 D3 No Chg Q2 Q1 0 Dn No Chg
R X4160
0 0
1595
SR4RLED Truth Table

Inputs R 0 0 L 0 0 CE 1 1 LEFT 1 0 SLI SLI X SRI X SRI D3 D0 X X C Q0 SLI q1 Outputs Q3 q2 SRI Q2 Q1 qn-1 qn+1
SR8RLED Truth Table

Inputs R 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 LEFT X X X 1 0 SLI X X X SLI X SRI X X X X SRI D7 D0 X D7 D0 X X X C X Q0 0 D0 No Chg SLI q1 Outputs Q7 0 D7 No Chg q6 SRI Q6 Q1 0 Dn No Chg qn-1 qn+1
SR16RLED Truth Table

Inputs R 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 LEFT X X X 1 0 SLI X X X SLI X SRI X X X X SRI D15 D0 X D15 D0 X X X C X Q0 0 D0 No Chg SLI q1 Outputs Q15 0 D15 No Chg q14 SRI Q14 Q1 0 Dn No Chg qn-1 qn+1
1596
CE
L_OR_CE
OR2
SLI
M2_1
D0
M2_1
D0 O MDL0 D1 S0 O MDR0 MDR0
FDRE
D CE C R Q
Q0
Q[7:0]
D0
D1 S0
MDLO
Q0
M2_1
D0
M2_1
FDRE
D CE C R Q
Q1
D1
D1 S0
MDL1
Q1
M2_1
D0
M2_1
FDRE
D CE C R Q
Q2
D2
D1 S0
MDL2
Q2
M2_1
D0
M2_1
FDRE
D CE C R Q
Q3
D3
D1 S0
MDL3
Q3
M2_1
D0
M2_1
FDRE
D CE C R Q
Q4
D4
D1 S0
MDL4
Q4
M2_1
D0
M2_1
FDRE
D CE C R Q
Q5
D5
D1 S0
MDL5
Q5
M2_1
D0
M2_1
FDRE
D CE C R Q
Q6
D6
D1 S0
MDL6
Q6
M2_1
D[7:0] L SRI LEFT R C
OR2
L_LEFT D0
M2_1
FDRE
D CE C R Q
Q7
D7
D1 S0
MDL7
Q7
X8688
SR8RLED Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X
1597
Usage
VHDL Inference Code

architecture Behavioral of sr4rled is
begin
process(C) begin if (C'event and C='1') then if (R='1') then Q <= (others => '0'); elsif (CE='1') then if (L='1') then Q <= D; else if (LEFT='1') then Q <= Q(WIDTH-2 downto 0) & SLI; else Q <= SRI & Q(WIDTH-1 downto 1) ; end if; end if; end if; end if; end process;
end Behavioral; Verilog Inference Code always @ (posedge C) begin if (R) Q <= 0; else if (CE) if (L) Q <= D;
1598
else if (LEFT) Q <= {Q[WIDTH-2:0], SLI}; else Q <= {SRI, Q[WIDTH-1:1]}; end
1599
1600
SRD4CE, SRD8CE, SRD16CE

4-, 8-, 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Registers with Clock Enable and Asynchronous Clear
SRD4CE, SRD8CE, SRD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
SLI CE C
SRD4CE
Q0 Q1 Q2 Q3
CLR
X9700
SLI CE C
SRD8CE
Q[7:0]
SRD4CE, SRD8CE, and SRD16CE are 4-, 8-, and 16-bit dual edge triggered shift registers, respectively, with a shift-left serial input (SLI), parallel outputs (Q), clock enable (CE) and asynchronous clear (CLR) inputs. The CLR input, when High, overrides all other inputs and resets the data outputs (Q) Low. When CE is High and CLR is Low, the data on the SLI input is loaded into the first bit of the shift register during the Low-to-High (or High-to-Low) clock (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and CLR is Low, data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). The register ignores clock transitions when CE is Low. Registers can be cascaded by connecting the last Q output (Q3 for SRD4CE, Q7 for SRD8CE, or Q15 for SRD16CE) of one stage to the SLI input of the next stage and connecting clock, CE, and CLR in parallel. The register is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
CLR
X9701
SLI CE C
SRD16CE
Q[15:0]
Inputs
CLR
X9702
Outputs SLI X X 1 1 0 0 C X X Q0 0 No Chg 1 1 0 0 Qz Q1 0 No Chg qn-1 qn-1 qn-1 qn-1
CLR 1 0 0 0 0 0
CE X 0 1 1 1 1
z = 3 for SRD4CE; z = 7for SRD8CE; z = 15 for SRD16CE qn-1 = state of referenced output one setup time prior to active clock transition
1601
Q[7:0]
FDDCE FDDCE
SLI CE D CE C CLR Q0 Q Q0 Q3 D CE C CLR Q4 Q Q4
FDDCE FDDCE
FDDCE FDDCE
FDDCE FDDCE
C CLR
X9703
SRD8CE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of srd4ce is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C, CLR) begin if (CLR='1') then Q_INT <= (others => '0'); elsif (C'event) then if (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; end if; end if; end process; Q <= Q_INT;
1602
end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= {Q[WIDTH-2:0],SLI}; end
1603
1604
SRD4CLE, SRD8CLE, SRD16CLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Registers with Clock Enable and Asynchronous Clear
SRD4CLE, SRD8CLE, SRD16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
SRD4CLE
Q0 Q1 Q2 Q3
CLR
X9704
SRD4CLE, SRD8CLE, and SRD16CLE are 4-, 8-, and 16-bit dual edge triggered shift registers, respectively, with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR). The register ignores clock transitions when L and CE are Low. The asynchronous CLR, when High, overrides all other inputs and resets the data outputs (Q) Low. When L is High and CLR is Low, data on the Dn D0 inputs is loaded into the corresponding Qn Q0 bits of the register. When CE is High and L and CLR are Low, data on the SLI input is loaded into the first bit of the shift register during the Low-to-High (or High-to-Low) clock (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and L and CLR are Low, the data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). Registers can be cascaded by connecting the last Q output (Q3 for SRD4CLE, Q7 for SRD8CLE, or Q15 for SRD16CLE) of one stage to the SLI input of the next stage and connecting clock, CE, L, and CLR inputs in parallel. The register is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
SLI D[7:0]
SRD8CLE
Q[7:0] L CE C
CLR
X9705
Inputs CLR
SLI SRD16CLE D[15:0] Q[15:0] L CE C
Outputs SLI X X X SLI SLI Dn D0 X Dn D0 Dn D0 X X C X Q0 0 D0 D0 SLI SLI Qz Q1 0 Dn Dn qn-1 qn-1
L X 1 1 0 0
CE X X X 1 1
1 0 0 0 0
CLR
X9706
1605
Inputs CLR 0 L 0 CE 0 SLI X Dn D0 X C X Q0
No Chg
z = 3 for SRD4CLE; z = 7 for SRD8CLE; z = 15 for SRD16CLE qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0] CE
L_OR_CE OR2
SLI D0
M2_1
FDDCE
Q Q0 D4
M2_1
FDDCE
Q Q4
CE C CLR Q0
CE C CLR Q4
M2_1
FDDCE
Q Q1 D5
M2_1
FDDCE
Q Q5
CE C CLR Q1
CE C CLR Q5
M2_1
FDDCE
Q Q2 D6
M2_1
FDDCE
Q Q6
CE C CLR Q2
CE C CLR Q6
M2_1
FDDCE
Q Q3 D7
M2_1
FDDCE
Q Q7
CE C CLR Q3
CE C CLR Q7
CLR C D[7:0]
X9707
SRD8CLE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of srd4cle is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C, CLR) begin if (CLR='1') then Q_INT <= (others => '0'); elsif (C'event) then if (CE='1') then if (L='1') then Q_INT <= D; else Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI;
1606
end if; end if; end if; end process; Q <= Q_INT; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (L) Q <= D; else Q <= {Q[WIDTH-2:0],SLI}; end
1607
1608
SRD4CLED, SRD8CLED, SRD16CLED

4-, 8-, 16-Bit Dual Edge Triggered Shift Registers with Clock Enable and Asynchronous Clear
SRD4CLED, SRD8CLED, SRD16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro
SRD4CLED
Q0 Q1 Q2 Q3
CLR
X9708
SLI SRD8CLED D[7:0] SRI Q[7:0] L LEFT CE C
SRD4CLED, SRD8CLED, and SRD16CLED are 4-, 8-, and 16-bit dual edge triggered shift registers, respectively, with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), and asynchronous clear (CLR). The register ignores clock transitions when CE and L are Low. The asynchronous clear, when High, overrides all other inputs and resets the data outputs (Qn) Low. When L is High and CLR is Low, the data on the D inputs is loaded into the corresponding Q bits of the register. When CE is High and L and CLR are Low, data is shifted right or left, depending on the state of the LEFT input. If LEFT is High, data on the SLI is loaded into Q0 during the Low-to-High or High-to-Low clock transition and shifted left (to Q1, Q2, and so forth) during subsequent clock transitions. If LEFT is Low, data on the SRI is loaded into the last Q output (Q3 for SRD4CLED, Q7 for SRD8CLED, or Q15 for SRD16CLED) during the Low-to-High or High-to-Low clock transition and shifted right (to Q2, Q1,... for SRD4CLED; to Q6, Q5,... for SRD8CLED; and to Q14, Q13,... for SRD16CLED) during subsequent clock transitions. The truth tables for SRD4CLED, SRD8CLED, and SRD16CLED indicate the state of the Q outputs under all input conditions for SRD4CLED, SRD8CLED, and SRD16CLED. The register is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
CLR
X9709
SRD4CLED Truth Table

Inputs Outputs SRI X X X X X X D3 D0 X D3 D0 D3 D0 X X X C X X Q0 0 D0 D0 No Chg SLI SLI Q3 0 D3 D3 No Chg q2 q2 Q2 Q1 0 Dn Dn No Chg qn-1 qn-1
SLI SRD16CLED D[15:0] SRI L LEFT CE C Q[15:0]
CLR 1 0 0 0 0 0
L X 1 1 0 0 0
CE X X X 0 1 1
LEFT X X X X 1 1
SLI X X X X SLI SLI
CLR
X9710
1609

Inputs CLR 0 0 L 0 0 CE 1 1 LEFT 0 0 SLI X X SRI SRI SRI D3 D0 X X C Q0 q1 q1 Outputs Q3 SRI SRI Q2 Q1 qn+1 qn+1
qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition

Inputs CLR 1 0 0 0 0 0 0 0 L X 1 1 0 0 0 0 0 CE X X X 0 1 1 1 1 LEFT X X X X 1 1 0 0 SLI X X X X SLI SLI X X SRI X X X X X X SRI SRI D7 D0 X D7 D0 D7 D0 X X X X X C X X Q0 0 D0 D0 No Chg SLI SLI q1 q1 Outputs Q7 0 D7 D7 No Chg q6 q6 SRI SRI Q6 Q1 0 Dn Dn No Chg qn-1 qn-1 qn+1 qn+1

Inputs CLR 1 0 0 0 0 0 0 0 L X 1 1 0 0 0 0 0 CE X X X 0 1 1 1 1 LEFT X X X X 1 1 0 0 SLI X X X X SLI SLI X X SRI X X X X X X SRI SRI D15 D0 X D15 D0 D15 D0 X X X X X C X X Q0 0 D0 D0 No Chg SLI SLI q1 q1 Outputs Q15 0 D15 D15 No Chg q14 q14 SRI SRI Q14 Q1 0 Dn Dn No Chg qn-1 qn-1 qn+1 qn+1
1610
VCC 5 CE AND2 OR2 D0 D1 S0 L_OR_CE
SLI D0
M2_1
O MDL0 MDL0
D0 D1 S0
M2_1
O MDR0 MDR0 D
FDDCE
Q Q0 Q[7:0]
CE C
CLR Q0
D1
D0 D1 S0
M2_1
O MDL1 MDL1
D0 D1 S0
M2_1
O MDR1 MDR1 D
FDDCE
Q Q1
CE C
CLR Q1
D2
D0 D1 S0
M2_1
O MDL2 MDL2
D0 D1 S0
M2_1
O MDR2 MDR2 D
FDDCE
Q Q2
CE C
CLR Q2
D3
D0 D1 S0
M2_1
O MDL3 MDL3
D0 D1 S0
M2_1
O MDR3 MDR3 D
FDDCE
Q Q3
CE C
CLR Q3
M2_1
D0 D1 S0
M2_1
O MDR4 MDR4 D
FDDCE
Q Q4
CE C
CLR Q4
D5
D0 D1 S0
M2_1
O MDL5 MDL5
D0 D1 S0
M2_1
O MDR5 MDR5 D
FDDCE
Q Q5
CE C
CLR Q5
D6
D0 D1 S0
M2_1
O MDL6 MDL6
D0 D1 S0
M2_1
O MDR6 MDR6 D
FDDCE
Q Q6
CE C
CLR Q6
D[7:0]
D7
D0 D1 S0
M2_1
O MDL7 MDL7
D0 D1 S0
M2_1
O MDR7 MDR7 D
FDDCE
Q Q7
CE C
L LEFT OR2 OR2 GND SRI CLR C OR2 L_LEFT
CLR Q7
X9711
SRD8CLED Implementation CoolRunner-II
1611
Usage
VHDL Inference Code

architecture Behavioral of srd4cled is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C, CLR) begin if (CLR='1') then Q_INT <= (others => '0'); elsif (C'event) then if (CE='1') then if (L='1') then Q_INT <= D; else if (LEFT='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; else Q_INT <= SRI & Q_INT(WIDTH-1 downto 1); end if; end if; end if; end if; end process; Q <= Q_INT; end Behavioral;

always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (L) Q <= D; else if (LEFT) Q <= {Q[WIDTH-2:0],SLI}; else Q <= {SRI, Q[WIDTH-1:1]}; end
1612
SRD4RE, SRD8RE, SRD16RE

4-, 8-, 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Registers with Clock Enable and Synchronous Reset
SRD4RE, SRD8RE, SRD16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
SLI CE C
SRD4RE
Q0 Q1 Q2 Q3
R
X9712
SLI CE C
SRD8RE
Q[7:0]
SRD4RE, SRD8RE, and SRD16RE are 4-, 8-, and 16-bit dual edge triggered shift registers, respectively, with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE), and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-High or High-to-Low clock (C) transition and resets the data outputs (Q) Low. When CE is High and R is Low, the data on the SLI is loaded into the first bit of the shift register during the Low-to-High clock or High-toLow (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and R is Low, data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). The register ignores clock transitions when CE is Low. Registers can be cascaded by connecting the last Q output (Q3 for SRD4RE, Q7 for SRD8RE, or Q15 for SRD16RE) of one stage to the SLI input of the next stage and connecting clock, CE, and R in parallel. The register is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
R
X9713
SLI CE C
SRD16RE
Q[15:0]
Inputs
R
X9714
Outputs SLI X X X 1 1 0 0 C X Q0 0 0 No Chg 1 1 0 0 Qz Q1 0 0 No Chg qn-1 qn-1 qn-1 qn-1
R 1 1 0 0 0 0 0
CE X X 0 1 1 1 1
z = 3 for SRD4RE; z = 7 for SRD8RE; z = 15 for SRD16RE qn-1 = state of referenced output one setup time prior to active clock transition
1613
Q[7:0]
FDDRE FDDRE
SLI CE D CE C R Q0 Q Q0 Q3 D CE C R Q4 Q Q4
FDDRE FDDRE
FDDRE FDDRE
FDDRE FDDRE
C R
X9715
SRD8RE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of srd4re is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if C'event then if (R='1') then Q_INT <= (others => '0'); elsif (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI; end if; end if; end process; Q <= Q_INT; end Behavioral;
1614

always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (CE) Q <= {Q[WIDTH-2:0],SLI}; end
1615
1616
SRD4RLE, SRD8RLE, SRD16RLE

4-, 8-, 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Registers with Clock Enable and Synchronous Reset
SRD4RLE, SRD8RLE, SRD16RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro
SRD4RLE
Q0 Q1 Q2 Q3
R
X9716
SRD4RLE, SRD8RLE, and SRD16RLE are 4-, 8-, and 16-bit dual edge triggered shift registers, respectively, with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q), and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clock transitions when L and CE are Low. The synchronous R, when High, overrides all other inputs during the Low-to-High or High-to-Low clock (C) transition and resets the data outputs (Q) Low. When L is High and R is Low, data on the D inputs is loaded into the corresponding Q bits of the register. When CE is High and L and R are Low, data on the SLI input is loaded into the first bit of the shift register during the Low-to-High or High-to-Low clock (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and L and R are Low, the data is shifted to the next highest bit position as new data is loaded into Q0 (SLIQ0, Q0Q1, Q1Q2, and so forth). Registers can be cascaded by connecting the last Q output (Q3 for SRD4RLE, Q7 for SRD8RLE, or 15 for SRD16RLE) of one stage to the SLI input of the next stage and connecting clock, CE, L, and R inputs in parallel. The register is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs Outputs SLI X X X X SLI SLI Dz D0 X X Dz D0 Dz D0 X X C Q0 0 0 D0 D0 SLI SLI Qz Q1 0 0 Dn Dn qn-1 qn-1
SLI D[7:0]
SRD8RLE
Q[7:0] L CE C
R
X9717
R 1 1 0 0 0 0
L X X 1 1 0 0
CE X X X X 1 1
SLI D[15:0]
SRD16RLE
Q[15:0] L CE C
R
X9718
1617
Inputs R 0 L 0 CE 0 SLI X Dz D0 X C X Q0
No Chg
z = 3 for SRD4RLE; z = 7 for SRD8RLE; z = 15 for SRD16RLE qn-1 = state of referenced output one setup time prior to active clock transition
Q[7:0] CE
L_OR_CE OR2
SLI D0
M2_1
FDDRE
Q Q0
Q3 D4
M2_1
FDDRE
Q Q4
CE C R Q0
CE C R Q4
M2_1
FDDRE
Q Q1 D5
M2_1
FDDRE
Q Q5
CE C R Q1
CE C R Q5
M2_1
FDDRE
Q Q2 D6
M2_1
FDDRE
Q Q6
CE C R Q2
CE C R Q6
M2_1
FDDRE
Q Q3 D7
M2_1
FDDRE
Q Q7
CE C R Q3
CE C R Q7
R C D[7:0]
X9719
SRD8RLE Implementation CoolRunner-II
Usage
VHDL Inference Code

architecture Behavioral of srd4rle is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if (C'event) then if (R='1') then Q_INT <= (others => '0'); if (CE='1') then if (L='1') then Q_INT <= D; else Q_INT <= Q_INT(WIDTH-2 downto 0) & SLI;
1618
end if; end if; end if; end if; end process; Q <= Q_INT; end Behavioral;

always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (CE) if (L) Q <= D; else Q <= {Q[WIDTH-2:0],SLI}; end
1619
1620
SRD4RLED, SRD8RLED, SRD16RLED

4-, 8-, 16-Bit Dual Edge Triggered Shift Registers with Clock Enable and Synchronous Reset
SRD4RLED, SRD8RLED, SRD16RLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro
SLI SRD4RLED D0 D1 D2 D3 SRDI L LEFT CE C Q0 Q1 Q2 Q3
R
X9844
SLI SRD8RLED D[7:0] SRDI Q[7:0] L LEFT CE C
SRD4RLED, SRD8RLED, and SRD16RLED are 4-, 8-, and 16-bit dual edge triggered shift registers, respectively, with shift-left (SLI) and shift-right (SRDI) serial inputs, parallel inputs (D), parallel outputs (Q), and four control inputs clock enable (CE), load enable (L), shift left/right (LEFT), and synchronous reset (R). The register ignores clock transitions when CE and L are Low. The synchronous R, when High, overrides all other inputs during the Low-to-High or High-to-Low clock (C) transition and resets the data outputs (Q) Low. When L is High and R is Low, the data on the D inputs is loaded into the corresponding Q bits of the register. When CE is High and L and R are Low, data is shifted right or left, depending on the state of the LEFT input. If LEFT is High, data on SLI is loaded into Q0 during the Low-to-High or High-to-Low clock transition and shifted left (to Q1, Q2, and so forth) during subsequent clock transitions. If LEFT is Low, data on the SRDI is loaded into the last Q output (Q3 for SRD4RLED, Q7 for SRD8RLED, or Q15 for SRD16RLED) during the Low-to-High or High-to-Low clock transition and shifted right (to Q2, Q1,... for SRD4RLED; to Q6, Q5,... for SRD8RLED; or to Q14, Q13,... for SRD16RLED) during subsequent clock transitions. The truth table indicates the state of the Q outputs under all input conditions. The register is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
R
X9845
SRD4RLED Truth Table

SLI SRD16RLED D[15:0] SRDI Q[15:0] L LEFT CE C
Inputs R 1 1 0 0
X9846
Outputs SRDI X X X X X D3 D0 X X D3 D0 D3 D0 X C X Q0 0 0 D0 D0 No Chg Q3 0 0 D3 D3 No Chg Q2 Q1 0 0 Dn Dn No Chg
L X X 1 1 0
CE X X X X 0
LEFT X X X X X
SLI X X X X X
1621

Inputs R 0 0 0 0 L 0 0 0 0 CE 1 1 1 1 LEFT 1 1 0 0 SLI SLI SLI X X SRDI X X SRDI SRDI D3 D0 X X X X C Q0 SLI SLI q1 q1 Outputs Q3 q2 q2 SRDI SRDI Q2 Q1 qn-1 qn-1 qn+1 qn+1

Inputs R 1 1 0 0 0 0 0 0 0 L X X 1 1 0 0 0 0 0 CE X X X X 0 1 1 1 1 LEFT X X X X X 1 1 0 0 SLI X X X X X SLI SLI X X SRDI X X X X X X X SRDI SRDI D7 D0 X X D7 D0 D7 D0 X X X X X C X Q0 0 0 D0 D0 No Chg SLI SLI q1 q1 Outputs Q7 0 0 D7 D7 No Chg q6 q6 SRDI SRDI Q6 Q1 0 0 Dn Dn No Chg qn-1 qn-1 qn+1 qn+1

Inputs R 1 1 0 0 0 0 0 0 0 L X X 1 1 0 0 0 0 0 CE X X X X 0 1 1 1 1 LEFT X X X X X 1 1 0 0 SLI X X X X X SLI SLI X X SRDI X X X X X X X SRDI SRDI D15 D0 X X D15 D0 D15 D0 X X X X X C X Q0 0 0 D0 D0 No Chg SLI SLI q1 q1 Outputs Q15 0 0 D15 D15 No Chg q14 q14 SRDI SRDI Q14 Q1 0 0 Dn Dn No Chg qn-1 qn-1 qn+1 qn+1
1622
CE
L_OR_CE OR2
SLI D0
M2_1
D0 D1 S0 O MDL0 MDLO
M2_1
D0 D1 S0 O MDR0 MDR0
FDDRE
D CE C R Q0 Q Q0 Q[7:0]
M2_1
M2_1
FDDRE
D CE C R Q1 Q Q1
M2_1
M2_1
FDDRE
D CE C R Q2 Q Q2
M2_1
M2_1
FDDRE
D CE C R Q3 Q Q3
M2_1
M2_1
FDDRE
D CE C R Q4 Q Q4
M2_1
M2_1
FDDRE
D CE C R Q5 Q Q5
M2_1
M2_1
FDDRE
D CE C R Q6 Q Q6
M2_1
D0 D[7:0] L SRI LEFT R C OR2 L_LEFT D7 D1 S0 O MDL7 MDL7
M2_1
FDDRE
D CE C R Q7 Q Q7
X9723
SRD8RLED Implementation CoolRunner-II
1623
1624
SRL16
SRL16
16-Bit Shift Register Look-Up-Table (LUT)
SRL16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D CLK A0 A1 A2 A3
SRL16
SRL16 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or it may be dynamically adjusted. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration. The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. During subsequent Low-to-High clock transitions data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached.
X8420
Static Length Mode

To get a fixed length shift register, drive the A3 through A0 inputs with static values. The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula: Length = (8*A3) +(4*A2) + (2*A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are all ones (1111), it is 16 bits long.
Dynamic Length Mode

The length of the shift register can be changed dynamically by changing the values driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), the length of the shift register changes from 16 bits to 8 bits.
1625
SRL16
Internally, the length of the shift register is always 16 bits and the input lines A3 through A0 select which of the 16 bits reach the output.
Inputs Am Am Am
m= 0, 1, 2, 3
Output D X D Q Q(Am) Q(Am-1)
CLK X
Usage
VHDL Inference Code

architecture Behavioral of srl16 is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if (C'event and C='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (posedge C) begin Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @(Q_INT) begin Q <= Q_INT[WIDTH-1]; end

-- Component Declaration for SRL16 should be placed -- after architecture statement but before begin keyword component SRL16 -- synthesis translate_off generic ( INIT: bit_value:= X"0001"); -- synthesis translate_on port (Q : out STD_ULOGIC;
1626
SRL16
A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16 -- should be placed after architecture declaration but -- before the begin keyword
-- Enter attributes in this section
-- Component Instantiation for SRL16 should be placed -- in architecture after the begin keyword SRL16_INSTANCE_NAME : SRL16 -- synthesis translate_off generic map( INIT => hex_value) -- synthesis translate_on port map (Q => user_Q, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, CLK => user_CLK, D => user_D);

SRL16 SRL16_instance_name (.Q (user_Q), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .CLK (user_CLK), .D (user_D)); defparam SRL16_instance_name.INIT = hex_value;

BEL, U_SET, INIT
1627
SRL16
1628
SRL16_1
SRL16_1
16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock
SRL16_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D CLK A0 A1 A2 A3
SRL16_1
SRL16_1 is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or it may be dynamically adjusted. See Static Length Mode and Dynamic Length Mode in SRL16. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration. The data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK) transition. During subsequent High-to-Low clock transitions data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached.
X8422
Inputs Am Am Am
m= 0, 1, 2, 3
CLK X
Usage
VHDL Inference Code

architecture Behavioral of srl16_1 is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C)
1629
SRL16_1
begin if (C'event and C='0') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (negedge C) begin Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @ (Q_INT) begin Q <= Q_INT[WIDTH-1]; end

-- Component Declaration for SRL16_1 should be placed -- after architecture statement but before begin keyword component SRL16_1 -- synthesis translate_off generic ( INIT: bit_value:= X"0001"); -- synthesis translate_on port (Q : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16_1 -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for SRL16_1 should be placed -- in architecture after the begin keyword SRL16_1_INSTANCE_NAME : SRL16_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (Q => user_Q, A0 => user_A0,
1630
SRL16_1
A1 => user_A1, A2 => user_A2, A3 => user_A3, CLK => user_CLK, D => user_D);

SRL16_1 SRL16_1_instance_name (.Q (user_Q), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .CLK (user_CLK), .D (user_D)); defparam SRL16_1_instance_name.INIT = hex_value;

BEL U_SET INIT
1631
SRL16_1
1632
SRL16E
SRL16E
16-Bit Shift Register Look-Up-Table (LUT) with Clock Enable
SRL16E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
D CE CLK A0 A1 A2 A3
SRL16E
SRL16E is a shift register look up table (LUT). The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or dynamically adjusted. See Static Length Mode and Dynamic Length Mode in SRL16. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration. When CE is High, the data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. During subsequent Low-to-High clock transitions, when CE is High, data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached. When CE is Low, the register ignores clock transitions.
X8423
Inputs Am Am Am
m= 0, 1, 2, 3
Output CLK X D X D Q Q(Am) Q(Am-1)
CE 0 1
Usage
VHDL Inference Code

architecture Behavioral of srl16e is signal Q_INT: std_logic_vector(WIDTH-1 downto 0);
1633
SRL16E
begin process(C) begin if (C'event and C='1') then if (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (posedge C) begin if (CE) Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @(Q_INT) begin Q <= Q_INT[WIDTH-1]; end

-- Component Declaration for SRL16E should be placed -- after architecture statement but before begin keyword component SRL16E -- synthesis translate_off generic (INIT: bit_value:= X"0001"); -- synthesis translate_on port (Q : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16E -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for SRL16E should be placed -- in architecture after the begin keyword
1634
SRL16E
SRL16E_INSTANCE_NAME : SRL16E -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (Q => user_Q, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, CE => user_CE, CLK => user_CLK, D => user_D);

SRL16E SRL16E_instance_name (.Q (user_Q), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .CE (user_CE), .CLK (user_CLK), .D (user_D)); defparam SRL16E_instance_name.INIT = hex_value;

BEL U_SET INIT
1635
SRL16E
1636
SRL16E_1
SRL16E_1
16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock and Clock Enable
SRLC16E_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
SRL16E_1
SRL16E_1 is a shift register look up table (LUT) with clock enable (CE). The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or dynamically adjusted. See Static Length Mode and Dynamic Length Mode in the SRL16. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration. When CE is High, the data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK) transition. During subsequent High-to-Low clock transitions, when CE is High, data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached. When CE is Low, the register ignores clock transitions.
X8421
Inputs Am Am Am
m= 0, 1, 2, 3
Output CLK X D X D Q Q(Am) Q(Am-1)
CE 0 1
Usage
VHDL Inference Code

architecture Behavioral of srl16e_1 is signal Q_INT: std_logic_vector(WIDTH-1 downto 0);
1637
SRL16E_1
begin process(C) begin if (C'event and C='0') then if (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (negedge C) begin if (CE) Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @(Q_INT) begin Q <= Q_INT[WIDTH-1]; end

-- Component Declaration for SRL16E_1 should be placed -- after architecture statement but before begin keyword component SRL16E_1 -- synthesis translate_off generic (INIT : bit_value := X"0001"); -- synthesis translate_on port (Q : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16E_1 -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for SRL16E_1 should be placed -- in architecture after the begin keyword
1638
SRL16E_1
SRL16E_1_INSTANCE_NAME : SRL16E_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (Q => user_Q, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, CE => user_CE, CLK => user_CLK, D => user_D);

SRL16E_1 SRL16E_1_instance_name (.Q (user_Q), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .CE (user_CE), .CLK (user_CLK), .D (user_D)); defparam SRL16E_1_instance_name.INIT = hex_value;

BEL U_SET INIT
1639
SRL16E_1
1640
SRLC16
SRLC16
16-Bit Shift Register Look-Up-Table (LUT) with Carry
SRLC16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
D CLK A0 A1 A2 A3
SRLC16
Q Q15
SRLC16 is a shift register look up table (LUT) with Carry. The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length, or it may be dynamically adjusted. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration.
X9296
The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. During subsequent Low-to-High clock transitions data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached. The Q15 output is available for the user to cascade multiple shift register LUTs to create larger shift registers. For information about the static length mode, see Static Length Mode in SRL16. For information about the dynamic length mode, see Dynamic Length Mode in SRL16.
Inputs Am Am Am
m= 0, 1, 2, 3
CLK X
Usage
1641
SRLC16
VHDL Inference Code

architecture Behavioral of srlc16 is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if (C'event and C='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (posedge C) begin Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @(Q_INT) begin Q <= Q_INT[WIDTH-1]; end

-- Component Declaration for SRLC16 should be placed -- after architecture statement but before begin keyword component SRLC16 -- synthesis translate_off generic (INIT : bit_value := X"0001"); -- synthesis translate_on port (Q : out STD_ULOGIC; Q15 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRLC16 -- should be placed after architecture declaration but -- before the begin keyword
1642
SRLC16
-- Component Instantiation for SRLC16 should be placed -- in architecture after the begin keyword SRLC16_INSTANCE_NAME : SRLC16 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (Q => user_Q, Q15 => user_Q15, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, CLK => user_CLK, D => user_D);

SRLC16 SRLC16_instance_name (.Q (user_Q), .Q15 (user_Q15), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .CLK (user_CLK), .D (user_D)); defparam SRLC16_instance_name.INIT = hex_value;

INIT
1643
SRLC16
1644
SRLC16_1
SRLC16_1
16-Bit Shift Register Look-Up-Table (LUT) with Carry and NegativeEdge Clock
SRLC16_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
D CLK A0 A1 A2 A3
SRLC16_1 Q Q15
SRLC16_1 is a shift register look up table (LUT) with carry and a negative-edge clock. The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or it may be dynamically adjusted. See Static Length Mode and Dynamic Length Mode in SRL16. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration. The data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK) transition. During subsequent High-to-Low clock transitions data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached. The Q15 output is available for the user to cascade multiple shift register LUTs to create larger shift registers.
Inputs Am Am Am
m= 0, 1, 2, 3
X9297
Output D X D Q Q(Am) Q(Am-1) Q15 No Chg Q14
CLK X
Usage
For HDL, this design element can inferred.
VHDL Inference Code

architecture Behavioral of srlc16_1 is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin
1645
SRLC16_1
process(C) begin if (C'event and C='0') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (negedge C) begin Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @(Q_INT) begin Q <= Q_INT[WIDTH-1]; end
1646
SRLC16E
SRLC16E
16-Bit Shift Register Look-Up-Table (LUT) with Carry and Clock Enable
SRLC16E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
SRLC16E Q Q15
SRLC16E is a shift register look up table (LUT) with carry and clock enable. The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or it may be dynamically adjusted. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration.
X9298
The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. When CE is High, during subsequent Low-to-High clock transitions, data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached. The Q15 output is available for the user to cascade multiple shift register LUTs to create larger shift registers. For information about the static length mode, see Static Length Mode in SRL16. For information about the dynamic length mode, see Dynamic Length Mode in SRL16.
Inputs Am Am Am Am
m= 0, 1, 2, 3
Output CE 0 1 1 D X X D Q Q(Am) Q(Am) Q(Am-1) Q15 Q(15) Q(15) Q15
CLK X X
Usage
1647
SRLC16E
VHDL Inference Code

architecture Behavioral of srlc16e is signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if (C'event and C='1') then if (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (posedge C) begin if (CE) Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @ (Q_INT) begin Q <= Q_INT[WIDTH-1]; end

-- Component Declaration for SRLC16E should be placed -- after architecture statement but before begin keyword component SRLC16E -- synthesis translate_off generic (INIT : bit_value := X"0001"); -- synthesis translate_on port (Q : out STD_ULOGIC; Q15 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRLC16E -- should be placed after architecture declaration but -- before the begin keyword
1648
SRLC16E
-- Component Instantiation for SRLC16E should be placed -- in architecture after the begin keyword SRLC16E_INSTANCE_NAME : SRLC16E -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (Q => user_Q, Q15 => user_Q15, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, CE => user_CE, CLK => user_CLK, D => user_D);

SRLC16E SRLC16E_instance_name (.Q (user_Q), .Q15 (user_Q15), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .CE (user_CE), .CLK (user_CLK), .D (user_D)); defparam SRLC16E_instance_name.INIT = hex_value;

INIT
1649
SRLC16E
1650
SRLC16E_1
SRLC16E_1
16-Bit Shift Register Look-Up-Table (LUT) with Carry, Negative-Edge Clock, and Clock Enable
SRLC16E_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
SRLC16E_1 Q Q15
SRLC16E_1 is a shift register look up table (LUT) with carry, clock enable, and negative-edge clock. The inputs A3, A2, A1, and A0 select the output length of the shift register. The shift register may be of a fixed, static length or it may be dynamically adjusted. See SRLC16 and Dynamic Length Mode in SRL16. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration. When CE is High, the data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK) transition. During subsequent High-to-Low clock transitions data is shifted to the next highest bit position as new data is loaded when CE is HIgh. The data appears on the Q output when the shift register length determined by the address inputs is reached. The Q15 output is available for the user to cascade multiple shift register LUTs to create larger shift registers.
X9299
Inputs Am Am Am Am
m= 0, 1, 2, 3
Output CLK X X D X X D Q Q(Am) Q(Am) Q(Am-1) Q15 No Chg No Chg Q14
CE 0 1 1
Usage
VHDL Inference Code

architecture Behavioral of srlc16e_1 is
1651
SRLC16E_1
signal Q_INT: std_logic_vector(WIDTH-1 downto 0); begin process(C) begin if (C'event and C='0') then if (CE='1') then Q_INT <= Q_INT(WIDTH-2 downto 0) & D; end if; end if; end process; Q <= Q_INT(WIDTH-1); end Behavioral;

always @ (negedge C) begin if (CE) Q_INT <= {Q_INT[WIDTH-2:0],D}; end always @(Q_INT) begin Q <= Q_INT[WIDTH-1]; end

-- Component Declaration for SRLC16E_1 should be placed -- after architecture statement but before begin keyword component SRLC16E_1 -- synthesis translate_off generic (INIT : bit_value := X"0001"); -- synthesis translate_on port (Q : out STD_ULOGIC; Q15 : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CE : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRLC16E_1 -- should be placed after architecture declaration but -- before the begin keyword
1652
SRLC16E_1
-- Component Instantiation for SRLC16E_1 should be placed -- in architecture after the begin keyword SRLC16E_1_INSTANCE_NAME : SRLC16E_1 -- synthesis translate_off generic map (INIT => hex_value) -- synthesis translate_on port map (Q => user_Q, Q15 => user_Q15, A0 => user_A0, A1 => user_A1, A2 => user_A2, A3 => user_A3, CE => user_CE, CLK => user_CLK, D => user_D);

SRLC16E_1 SRLC16E_1_instance_name (.Q (user_Q), .Q15 (user_Q15), .A0 (user_A0), .A1 (user_A1), .A2 (user_A2), .A3 (user_A3), .CE (user_CE), .CLK (user_CLK), .D (user_D)); defparam SRLC16E_1_instance_name.INIT = hex_value;

INIT
1653
SRLC16E_1
1654
STARTBUF_architecture
VHDL Simulation of FPGA Designs
STARTBUF_architecture Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
STARTBUF_architecture is used for VHDL simulation of FPGA designs that require the use of the STARTUP block. The difference between the STARTBUF_architecture and the STARTUP block is that the STARTBUF_architecture contains output ports which may be connected to all register set/resets in the design (GSROUT) or to all I/O three-state controls (GTSOUT) so that these functions may be functionally simulated. This design element should not be used for Verilog or schematic entry. In order to use the STARTBUF_architecture, the desired input(s) should be connected to a top-level port in the design and the corresponding output(s) must be connected to either the three-state control signal for all inferred and instantiated output buffers in the design (GTSOUT) or all inferred or instantiated register set/resets in the design. During simulation, the inputs to the STARTBUF_architecture can be toggled by the testbench in order to activate the global three-state or global set/reset signal in the design. This should be done at the beginning of the simulation to simulate the behavior of the registers and I/O during configuration. It may also be applied during simulation to simulate a reconfiguration (ProG pin high) of the device. During synthesis and implementation, this component will be treated as a STARTUP block. The connected input ports to this component should remain in the design and be connected to the correct corresponding global resource. For more information, see the Xilinx Synthesis and Verification Design Guide. The value at port GSROUT will be always the be value at port GSRIN. The value at port GTSOUT will always be the value at port GTSIN. CLKIN has no effect on simulation.

Following are three examples:
component STARTBUF_SPARTAN2 port (GSROUT : out std_ulogic; GTSOUT : out std_ulogic; CLKIN : in std_ulogic; GSRIN : in std_ulogic; GTSIN : in std_ulogic); end component;
1655
component STARTBUF_VIRTEX port (GTSOUT : out std_ulogic; GSROUT : out std_ulogic; CLKIN : in std_ulogic; GSRIN : in std_ulogic; GTSIN : in std_ulogic); end component; component STARTBUF_VIRTEX2 port (GSROUT : out std_ulogic; GTSOUT : out std_ulogic; CLKIN : in std_ulogic; GSRIN : in std_ulogic; GTSIN : in std_ulogic); end component;

None
1656
STARTUP_SPARTAN2
STARTUP_SPARTAN2
Spartan-II User Interface to Global Clock, Reset, and 3-State Controls
STARTUP_SPARTAN2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No No No No No No
* Supported for Spartan-II but not for Spartan-IIE, which is supported by STARTUP_VIRTEX.
STARTUP_SPARTAN2
GSR GTS
The STARTUP_SPARTAN2 primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock. The Global Set/Reset (GSR) input, when High, sets or resets all flip-flops, all latches, and every block RAM (RAMB4) output register in the device, depending on the initialization state (S or R) of the component. Note: Block RAMB4 content, LUT RAMs, delay locked loop elements (CLKDLL, CLKDLLHF, BUFGDLL), and shift register LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1) are not set/reset. Following configuration, the global 3-state control (GTS), when Highand BSCAN is not enabled and executing an EXTEST instructionforces all the IOB outputs into high impedance mode, which isolates the device outputs from the circuit but leaves the inputs active. Note: GTS= Global 3-State Including the STARTUP_SPARTAN2 symbol in a design is optional. You must include the symbol under the following conditions. To exert external control over global set/reset, connect the GSR pin to a top level port and an IBUF, as shown here.
STARTUP_SPARTAN2
GSR GTS
CLK
X8896
CLK
X8904
To exert external control over global 3-state, connect the GTS pin to a top level port and IBUF, as shown here.
STARTUP_SPARTAN2
GSR GTS
CLK
X8905
1657
STARTUP_SPARTAN2
To synchronize startup to a user clock, connect the user clock signal to the CLK input, as shown here. Furthermore, user clock must be selected in the BitGen program.
STARTUP_SPARTAN2
GSR GTS
CLK
X8906
You can use location constraints to specify the pin from which GSR or GTS (or both) is accessed.
Usage
For HDL, this design element typically is instantiated rather than inferred.

-- Component Declaration for STARTUP_SPARTAN2 should be placed -- after architecture statement but before begin keyword component STARTUP_SPARTAN2 port (CLK : in STD_ULOGIC; GSR : in STD_ULOGIC; GTS : in STD_ULOGIC); end component; -- Component Attribute specification for STARTUP_SPARTAN2 -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for STARTUP_SPARTAN2 should be placed -- in architecture after the begin keyword STARTUP_SPARTAN2_INSTANCE_NAME : STARTUP_SPARTAN2 port map (CLK => user_CLK, GSR => user_GSR, GTS => user_GTS);

STARTUP_SPARTAN2 STARTUP_SPARTAN2_instance_name (.CLK (user_CLK), .GSR (user_GSR), .GTS (user_GTS));

None
1658
STARTUP_SPARTAN3
STARTUP_SPARTAN3
Spartan-3 User Interface to Global Clock, Reset, and 3-State Controls
STARTUP_SPARTAN3 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No
STARTUP_SPARTAN3 GSR GTS CLK
The STARTUP_SPARTAN3 primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock. The Global Set/Reset (GSR) input, when High, sets or resets all flip-flops, all latches, and every block RAMB16 output register in the device, depending on the initialization state (INIT=1 or 0) of the component.
X9932
Note: Block RAM content, LUT RAMs, the Digital Clock Manager (DCM), and shift register LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1, SRLC16, SRLC16_1, SRLC16E, and SRLC16E_1) are not set/reset. Following configuration, the global 3-state control (GTS), when Highand BSCAN is not enabled and executing an EXTEST instructionforces all the IOB outputs into high impedance mode, which isolates the device outputs from the circuit but leaves the inputs active. Note: GTS= Global 3-State Including the STARTUP_SPARTAN3 symbol in a design is optional. You must include the symbol under the following conditions. To exert external control over global set/reset, connect the GSR pin to a top level port and an IBUF, as shown here.
GSR GTS
CLK
X9391
1659
STARTUP_SPARTAN3
GSR GTS
CLK
X9392
GSR GTS
CLK
X9393
Usage

-- Component Declaration for STARTUP_SPARTAN3 should be placed -- after architecture statement but before begin keyword component STARTUP_SPARTAN3 port (CLK : in STD_ULOGIC; GSR : in STD_ULOGIC; GTS : in STD_ULOGIC); end component; -- Component Attribute specification for STARTUP_SPARTAN3 -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for STARTUP_SPARTAN3 should be placed -- in architecture after the begin keyword STARTUP_SPARTAN3_INSTANCE_NAME : STARTUP_SPARTAN3 port map (CLK => user_CLK, GSR => user_GSR, GTS => user_GTS);

STARTUP_SPARTAN3 STARTUP_SPARTAN3_instance_name (.CLK (user_CLK), GSR (user_GSR),
1660
STARTUP_SPARTAN3
GTS (user_GTS));

None.
1661
STARTUP_SPARTAN3
1662
STARTUP_VIRTEX
STARTUP_VIRTEX
Virtex and Virtex-E User Interface to Global Clock, Reset, and 3-State Controls
STARTUP_VIRTEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No Primitive No No No
* Supported for Spartan-IIE but not for Spartan-II which is supported by STARTUP_SPARTAN2..
STARTUP_VIRTEX
GSR GTS
CLK
The STARTUP_VIRTEX primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock. The Global Set/Reset (GSR) input, when High, sets or resets all flip-flops, all latches, and every block RAM (RAMB4) output register in the device, depending on the initialization state (S or R) of the component. For VirtexII, Virtex-II Pro, and Virtex-II Pro X, see STARTUP_VIRTEX2. Note: Block RAMB4 content, LUT RAMs, delay locked loop elements (CLKDLL, CLKDLLHF, BUFGDLL), and shift register LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1) are not set/reset. Following configuration, the global 3-state control (GTS), when Highand BSCAN is not enabled and executing an EXTEST instructionforces all the IOB outputs into high impedance mode, which isolates the device outputs from the circuit but leaves the inputs active. Note: GTS= Global 3-State Including the STARTUP_VIRTEX symbol in a design is optional. You must include the symbol under the following conditions. To exert external control over global set/reset, connect the GSR pin to a top level port and an IBUF, as shown here.
STARTUP_VIRTEX
GSR GTS
X8682
CLK
X8683
1663
STARTUP_VIRTEX
STARTUP_VIRTEX
GSR GTS
CLK
X8684
STARTUP_VIRTEX
GSR GTS
CLK
X8685
Usage

-- Component Declaration for STARTUP_VIRTEX should be placed -- after architecture statement but before begin keyword component STARTUP_VIRTEX port (CLK : in STD_ULOGIC; GSR : in STD_ULOGIC; GTS : in STD_ULOGIC); end component; -- Component Attribute specification for STARTUP_VIRTEX -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for STARTUP_VIRTEX should be placed -- in architecture after the begin keyword STARTUP_VIRTEX_INSTANCE_NAME : STARTUP_VIRTEX port map (CLK => user_CLK, GSR => user_GSR, GTS => user_GTS);

STARTUP_VIRTEX STARTUP_VIRTEX_instance_name (.CLK (user_CLK), .GSR (user_GSR), .GTS (user_GTS));
1664
STARTUP_VIRTEX

None
1665
STARTUP_VIRTEX
1666
STARTUP_VIRTEX2
STARTUP_VIRTEX2
Virtex-II, Virtex-II Pro, and Virtex-II Pro X User Interface to Global Clock, Reset, and 3-State Controls
STARTUP_VIRTEX2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No
STARTUP_VIRTEX2 GSR GTS CLK X9300
The STARTUP_VIRTEX2 primitive is used for Global Set/Reset, global 3-state control, and the user configuration clock. The Global Set/Reset (GSR) input, when High, sets or resets all flip-flops, all latches, and every block RAMB16 output register in the device, depending on the initialization state (INIT=1 or 0) of the component. For Virtex and Virtex-E, see STARTUP_VIRTEX. Note: Block RAM content, LUT RAMs, the Digital Clock Manager (DCM), and shift register LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1, SRLC16, SRLC16_1, SRLC16E, and SRLC16E_1) are not set/reset. Following configuration, the global 3-state control (GTS), when Highand BSCAN is not enabled and executing an EXTEST instructionforces all the IOB outputs into high impedance mode, which isolates the device outputs from the circuit but leaves the inputs active. Note: GTS= Global 3-State Including the STARTUP_VIRTEX2 symbol in a design is optional. You must include the symbol under the following conditions. To exert external control over global set/reset, connect the GSR pin to a top level port and an IBUF, as shown here.
GSR GTS
CLK
X9391
1667
STARTUP_VIRTEX2
GSR GTS
CLK
X9392
GSR GTS
CLK
X9393
Usage

-- Component Declaration for STARTUP_VIRTEX2 should be placed -- after architecture statement but before begin keyword component STARTUP_VIRTEX2 port (CLK : in STD_ULOGIC; GSR : in STD_ULOGIC; GTS : in STD_ULOGIC); end component; -- Component Attribute specification for STARTUP_VIRTEX2 -- should be placed after architecture declaration but -- before the begin keyword
-- Component Instantiation for STARTUP_VIRTEX2 should be placed -- in architecture after the begin keyword STARTUP_VIRTEX2_INSTANCE_NAME : STARTUP_VIRTEX2 port map (CLK => user_CLK, GSR => user_GSR, GTS => user_GTS);
1668
STARTUP_VIRTEX2

STARTUP_VIRTEX2 STARTUP_VIRTEX2_instance_name (.CLK (user_CLK), GSR (user_GSR), GTS (user_GTS));

None
1669
STARTUP_VIRTEX2
1670
TOC
TOC
Three-State On Configuration
TOC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
The TOC is a component used for VHDL simulation of FPGA designs. This component should not be used for Verilog or schematic entry. The TOC's function is to mimic the function of the internal three-state signal during the FPGA configuration process. In order to use TOC, it must be connected to the three-state signal for all inferred and instantiated output buffers in the design. During synthesis and implementation, this three-state signal will use the dedicated global three-state network and will not use local routing resources. During simulation, TOC will emit a one-shot pulse for the amount of time specified by the WIDTH generic (default is 100 ns). This one-shot pulse is intended to three-state all outputs so that at the beginning of operation, all outputs are not being driven as would happen in the real silicon during configuration of the device. For more information, see the Xilinx Synthesis and Verification Design Guide. Port O will be high at simulation time 0 for the amount of time specified by the WIDTH generic attribute. After that time, it will be 0. This will not affect implementation in any way.

component TOC -- synthesis translate_off generic (WIDTH : Time := 100 ns); -- synthesis translate_on port (O : out std_ulogic := '0'); end component;

For simulation, the WIDTH generic can be modified to change the amount of time the one-shot pulse is applied for. There are no supported constraints for this component for implementation.
1671
TOC
1672
TOCBUF
TOCBUF
Three-State On Configuration Buffer
TOCBUF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No
The TOCBUF is a component used for VHDL simulation of FPGA designs. It is similar to the TOC component except that it contains an input for controlling the global I/O three-state function rather than a one-shot. This component should not be used for Verilog or schematic entry. The TOCBUF's function allows user control of the function of the global I/O three-state signal as done during the FPGA configuration process. In order to use the TOCBUF, the input should be connected to a top-level port in the design and the output must be connected to the three-state control signal for all inferred and instantiated output buffers in the design. During simulation, the input to the TOCBUF can be toggled by the testbench in order to activate the global three-state signal in the design. This should be done at the beginning of the simulation to simulate the behavior of the I/O during configuration. It may also be applied during simulation to simulate a reconfiguration (ProG pin high) of the device. During synthesis and implementation, this three-state signal uses the dedicated global three-state network and does not use local routing resources. The port connected to this component is optimized out of the design and does not use any pin resources. If you want to have the port implemented in the design, a STARTBUF_architecture should be used. In order to replace this port during back-end simulation, the -tp switch should be used when invoking the NGD2VER or NGD2VHDL netlister. If using the ISE GUI, use the Bring Out Global Three-state Net as a Port option in the Simulation Model Properties window. For more information, see the Xilinx Synthesis and Verification Design Guide. The value at port O will be always be the value at port I (it is a buffer).

component TOCBUF port (I : in std_ulogic; O : out std_ulogic); end component;

None
1673
TOCBUF
1674
VCC
VCC
VCC-Connection Signal Tag
VCC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive
VCC
X8721
The VCC signal tag or parameter forces a net or input function to a logic High level. A net tied to VCC cannot have any other source. When the placement and routing software encounters a net or input function tied to VCC, it removes any logic that is disabled by the VCC signal. The VCC signal is only implemented when the disabled logic cannot be removed.
Usage
VHDL Inference Code

vcc_signal <= '1';

assign vcc_signal = 1;

-- Component Declaration for VCC should be placed -- after architecture statement but before begin keyword component VCC port (P : out STD_ULOGIC); end component; -- Component Attribute specification for VCC -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here
-- Component Instantiation for VCC should be placed -- in architecture after the begin keyword
1675
VCC
VCC_INSTANCE_NAME : VCC port map (P => user_P);

VCC instance_name (.P (user_P));

None
1676
UPAD
UPAD
Connects the I/O Node of an IOB to the Internal PLD Circuit
UPAD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
UPAD
A UPAD allows the use of any unbonded IOBs in a device. It is used the same way as an IOPAD except that the signal output is not visible on any external device pins.
X3843
1677
UPAD
1678
XNOR2-9
XNOR2-9
2- to 9-Input XNOR Gates with Non-Inverted Inputs
XNOR2, XNOR3, XNOR4 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II XNOR5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II XNOR6, XNOR7, XNOR8 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II XNOR9 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Primitive Primitive Primitive Primitive
1679
XNOR2-9
I1 I0 XNOR2 I2 I1 I0 XNOR3 I3 I2 I1 I0 XNOR4 I4 I3 I2 I1 I0 XNOR5 I5 I4 I3 I2 I1 I0 XNOR6
I6 I5 I4 I3 I2 I1 I0 XNOR7 I7 I6 I5 I4 I3 I2 I1 I0 O O
O IA I7 I6 I5 I4 O I3 I2 I1 I0
XNOR8
XNOR9 X9439
XNOR Gate Representations XNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLB resource, replace functions with unused inputs with functions having the necessary number of inputs.
I0 I1 I2
XOR3
I3 I4
XNOR2 XOR2 X7836
XNOR5 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

I0 I1 I2 XOR3 I3 I4 I5 XOR3 XNOR2 O
X7876
1680
XNOR2-9
I0 I1 I2 I3 XOR4 I4 I5 I6 XOR3 X8205 XNOR2 O

I6 I5 I4 I3 XOR4 I2 O I36
FMAP
I6 I5 I4 I3 I4 I3 I2 I1 RLOC=R0C0.S1 O I36
FMAP
XNOR4 I1 I0 I36 I2 I1 I0 X8699 I4 I3 I2 I1 RLOC=R0C0.S1 O O
XNOR7 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I6 I5 I4 I3 I2 I1 I0 XNOR4 I36 I2 I1 I0 I4 I3 I2 I1 RLOC=X0Y0 X9375 O O XOR4 O I36 I6 I5 I4 I3 I4 I3 I2 I1 RLOC=X0Y0 O I36
FMAP
XNOR7 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

I0 I1 I2 I3 I4 I5 I6 I7 XOR4 X7877 XOR4 XNOR2 O
1681
XNOR2-9
FMAP
I4 I3 S1 S2 I7 I6 I5 I4 XOR4 O XNOR2 I3 I2 I1 I0 XOR4 I3 I2 I1 I0 X8697 S0 S1 I2 I1 RLOC=R0C0.S0 O O
FMAP
FMAP

FMAP
I4 I7 I6 I5 I4 XOR4 RLOC=X0Y1 O I3 I2 I1 I0 XOR4 S0 XNOR2 S1 S1 S0 I3 I2 I1 O O
FMAP
I7 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1
FMAP

I0 I1 I2 XOR3 I3 I4 I5 XOR3 I6 I7 I8 XOR3 XNOR2 XOR2 O
X7878
1682
XNOR2-9
FMAP
I8 S1 S0 I8 I4 I3 I2 I1 O O
FMAP
I7 I6 I5 I4 XOR4 S1 XNOR3 O I7 I6 I5 I4 I4 I3 I2 I1 O S1
FMAP
I3 I2 I1 I0 XOR4 X8696 S0 I3 I2 I1 I0 I4 I3 I2 I1 O S0

FMAP
I4 S1 S0 I8 I8 I3 I2 I1 RLOC=X0Y1 O O
FMAP
I7 I6 I5 I4 I3 I2 I1 I0 XOR4 S0 I3 I2 I1 I0 XOR4 S1 XNOR3 O I7 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1
FMAP
I4 I3 I2 I1 RLOC=X0Y0 X9377 O S0
Usage
For HDL, these design elements can be inferred or instantiated.
VHDL Inference Code

architecture Behavioral of xnor2 is begin process (I0, I1) begin O <= I0 xnor I1; end process; end Behavioral;
1683
XNOR2-9

always @ (I0 or I1) begin O <= I0~^I1; end
VHDL Instantiation Template for XNOR5

Following is the VHDL code for XNOR5. To instantiate XNOR2, remove I2, I3, and I4. To instantiate XNOR3, remove I3 and I4, For XNOR4, remove I4. XNOR2B1, and XNOR2B2 have the same code as XNOR2. XNOR3B1, 3B2, and 3B3 have the same code as XNOR3 and so forth.
-- Component Declaration for XNOR5 should be placed -- after architecture statement but before begin keyword component XNOR5 port (O : out I0 : in I1 : in I2 : in I3 : in I4 : in end component;
-- Component Attribute specification for XNOR5 -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for XNOR5 should be placed -- in architecture after the begin keyword XNOR5_INSTANCE_NAME : XNOR5 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4);
Verilog Instantiation Template for XNOR5

XNOR5 XNOR5_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4));

None
1684
XOR2-9
XOR2-9
2- to 9-Input XOR Gates with Non-Inverted Inputs
XOR2, XOR3 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II XOR4 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II XOR5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II XOR6, XOR7, XOR9 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Macro Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Primitive
1685
XOR2-9
XOR8 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
XOR2 I1 I0 O I4 I3 I2 I1 XOR3 I2 I1 I0 XOR4 I3 I2 I1 I0 O O I5 I4 I3 I2 I1 I0 XOR7 I6 I5 I4 I3 I2 I1 I0 x9441 O O IA I7 I6 I5 I4 I3 I2 I1 I0 O XOR9 I0 XOR6 O XOR5 I7 I6 I5 I4 I3 I2 I1 I0 O XOR8
XOR Gate Representations XOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLB resource, replace functions with unused inputs with functions having the necessary number of inputs.
I0 I1 I2 XOR3 I3 I4 XOR2 X7882 XOR2 O
XOR5 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
1686
XOR2-9
I0 I1 I2 XOR3 I3 I4 I5 XOR3 X7883 XOR2 O

I0 I1 I2 I3 XOR4 I4 I5 I6 XOR3 X7884 XOR2 O

I0 I1 I2 I3 I4 I5 I6 I7 XOR4 X7885 XOR4 XOR2 O

FMAP
I4 I3 S1 S2 I7 I6 I5 I4 XOR4 O XOR2 I3 I2 I1 I0 XOR4 I3 I2 I1 I0 X8695 S0 S1 I2 I1 RLOC=R0C0.S0 O O
FMAP
FMAP
XOR8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E
1687
XOR2-9
FMAP
I4 I7 I6 I5 I4 XOR4 O I3 I2 I1 I0 XOR4 S0 S1 S1 S0 I3 I2 I1 RLOC=X0Y1 O O
FMAP
XOR2 I7 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1
FMAP
XOR8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

I0 I1 I2 XOR3 I3 I4 I5 XOR3 I6 I7 I8 XOR3 X7886 XOR2 XOR2 O
Usage
For HDL, these design elements can be inferred or instantiated.
VHDL Inference Code

architecture Behavioral of xor2 is begin process (I0, I1) begin O <= I0 xor I1; end process; end Behavioral;

always @ (I0 or I1) begin O <= I0^I1; end
1688
XOR2-9
VHDL Instantiation Template for XOR5

Following is the VHDL code for XOR5. To instantiate XOR2, remove I2, I3, and I4. To instantiate XOR3, remove I3 and I4, For XOR4, remove I4. XOR2B1, and XOR2B2 have the same code as XOR2. XOR3B1, 3B2, and 3B3 have the same code as XOR3 and so forth.
-- Component Declaration for XOR5 should be placed -- after architecture statement but before begin keyword component XOR5 port (O : out I0 : in I1 : in I2 : in I3 : in I4 : in end component;
-- Component Attribute specification for XOR5 -- should be placed after architecture declaration but -- before the begin keyword -- Attributes should be placed here -- Component Instantiation for XOR5 should be placed -- in architecture after the begin keyword XOR5_INSTANCE_NAME : XOR5 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4);
Verilog Instantiation Template for XOR5

XOR5 XOR5_instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4));

None
1689
XOR2-9
1690
XORCY
XORCY
XOR for Carry Logic with General Output
XORCY Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3
LI CI O X8410
CoolRunner-II
XORCY is a special XOR with general O output used for generating faster and smaller arithmetic functions. Its O output is a general interconnect. See also XORCY_D and XORCY_L.

BEL
1691
XORCY
1692
XORCY_D
XORCY_D
XOR for Carry Logic with Dual Output
XORCY_D Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
LO LI CI O X8409
XORCY_D is a special XOR used for generating faster and smaller arithmetic functions. XORCY_D has two functionally identical outputs, O and LO. The O output is a general interconnect. The LO output is used to connect to another output within the same CLB slice. See also XORCY and XORCY_L.

BEL
1693
XORCY_D
1694
XORCY_L
XORCY_L
XOR for Carry Logic with Local Output
XORCY_L Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
LO LI CI X8404
XORCY_L is a special XOR with local LO output used for generating faster and smaller arithmetic functions. The LO output is used to connect to another output within the same CLB slice. See also XORCY and XORCY_D.

BEL
1695
XORCY_L
1696

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Libraries Guide

About This Guide

Database of Xilinx solution records http://support.xilinx.com/xlnx/xil_ans_browser.jsp

Application Notes Data Book

Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm

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Whats New in This Release

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About This Guide

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Whats New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Xilinx Unified Libraries

Flip-Flop, Counter, and Register Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Architecture Specific Information

Libraries Guide ISE 6.li

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Xilinx Unified Libraries

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Xilinx Unified Libraries

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Clock Enable Bi-Directional

Combinatorial Naming Conventions

Attributes and Constraints

Spartan-II, Spartan-IIE, Virtex, and Virtex-E

Libraries Guide ISE 6.li

Xilinx Unified Libraries

Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3

Flip-Flop, Counter, and Register Performance

Libraries Guide ISE 6.li

Flip-Flop, Counter, and Register Performance

Libraries Guide ISE 6.li

Xilinx Unified Libraries

X=(CE * C2)+(CE * C1)

Y=(CE * C1)+(CE * C2)

Clock Enable Implementation Methods

Libraries Guide ISE 6.li

About Configurable Logic Blocks (CLBs)

Slice Count for FPGA Components

Number of Slices to Implement 6 10 18 3 5 9 3 5 9 5 9 17 3 5 9 3 5 9 6 10 18 3 5 9 3 5 9

Libraries Guide ISE 6.li

Slice Count for FPGA Components

Number of Slices to Implement 1 1 1 1 1 1 2 2 2 2 4 12 1 1 1 1 1 1 2 2 2 2 8 12 1 1 1 1 1 1 2 2 2 2 4 12 -

Libraries Guide ISE 6.li

Slice Count for FPGA Components

Slice Count for FPGA Components

Number of Slices to Implement 3 3 3 3 4 5 7 4 7 10 12 7 14 19 25 14 5 9 17 9 9 17 33 17 4 5 4 7 4 4 5 5 4 4 2 3 3 2 3 5 6 3 6 9 12 6 13 18 24 13 8 9 9 9 16 17 17 17 3 5 3 7 2 2 3 3 4 4 3 3 3 3 4 5 7 4 7 10 12 7 14 19 25 14 5 9 17 9 9 17 33 17 4 5 4 7 4 4 5 5 4 4 -

Libraries Guide ISE 6.li

Slice Count for FPGA Components

Number of Slices to Implement 1 2 4 9 2 5 13 32 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 4 4 4 4 8 8 1 1 1 1 1 2 3 6 1 5 11 24 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 2 2 4 4 8 8 1 1 1 1 1 2 4 9 2 5 13 32 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 4 4 4 4 8 8 1 1 1 1