9213 PSNA College of Engg. & Tech., Dindigul 624 622 ANNA UNIVERSITY - CHENNAI M.E./M.Tech.

h. DEGREE EXAMINATIONS, JAN - 2012 Regulations 2009 Semester

Date of Exam

Time 1

:First Semester : : 3 Hours

Programme : ME - VLSI Design Sub. : VL9217 VLSI DesignLab-1 Max. Mark : 100

Develop a structural VHDL model of an eight bit odd-parity checker using instances of 100 an exclusive-or gate entity. The parity checker has eight inputs, io to i7, and an output p, all of type std_ logic. The logic equation describing the parity checker is
P= (( Io+I1) + ( I2+I3)) +(( I4+I5) +( I6+I7)).

Write an entity declaration and a structural architecture body for a four bit wide 100 multiplexer, using instances of two bit multiplexer. The Input ports are a0, a1, a2,a3, b0,b1,b2,b3 and ,sel and the output ports are z0,a1,z2 and z3. When the sel is 0 , the inputs a0 to a3 ,otherwise the inputs b0 to b3 are copied to the outputs. Write a test bench for the multiplexer model, and test it using a VHDL simulator.

Write an entity declaration for a four -bit counter with a n asynchronous reset input. 100 Include a process in the entity declaration that measure the duration of each reset pulse and report the duration at the end of each pulse. Verify this logic with suitable simulator. Develop a Verilog HDL model of an averaging module that calculates the average 100 batches of 16 rel numbers. The module has clock and data inputs and a data output. The module accepts the next iput number when the clock changes to '1'. After 16 numbers have been accepted, the module places their average on the output port, then repeat the process for the next batch. Verify this logic with suitable simulator.

Write a Verilog HDL model for a counter with an output port of type natural, initially set 100 to 15. When the clk input changes to '1', the counter decrements by one. After counting down to zero, the counter wraps back to 15 on the next clock edge.

Develop a switch level model for a 3: 8 decoder and simulate the same with suitable simulator.

100

Implement the following with any one of the reprogrammable logic device.

100

An 8-bit arithmetic logic unit (ALU) adds, subtracts, bitwise ANDs, or bitwise ORs two operands and then performs an optional shift on the output. The op-code is a 3-bit value that tells the ALU what operation to perform. The most significant two bits of the op-code select the arithmetic logical operation. If the least significant bit of the op-code equals T a ] -bit left-shift operation is performed on the output. The following table shows the two most significant bits of the opcode and their cone spending functions (the leftmost bit is the most significant):
up-code (2 most significant bits) 00 01 10
]]

Function Add S u b tra ct AND OR

Develop a VHDL package of arithmetic operations for IEEE single precision floating point numbers represented as bit vectors. Your package should include addition , subtraction, multiplication, division and square-root operations, and conversion functions to convert between bit-vector and real values. Implement the logic with any suitable reprogrammable logic device.

100

Write a HDL for a digital integrator that has a clock input of type bit and data input and output each of type real. The integrator maintains the sum of successive data input values. When the clock input changes from 0 to 1, the integrator should add the current data input to the sum and provide the new sum of the output. Implement the logic with any suitable reprogrammable logic device. 10 Implement the pseudo-nMOS circuit with SPICE that provide the following logic operation h= (a+b+c).x+y.z

100

100

11

The output node of a C2MOS circuit is tri-stated with a clock signal of = 0. The output 100 capacitance at the node is cout=76fF. The leakage currents are estimated to be In=0.46UA and I p=127nA. The output voltage must be maintained above a value of 2.4 volts to be interpreted as a logic 1 stage by the next stage. Design and simulate the circuit using SPICE and find the hold time at the output node if VDD=3.3 V. 100

12 Design and implement the following logic using SPICE a four bit 4:1 MUX using transmission gate 13Model a n-channel enhancement mode MOSFET device using high level language. 14Model a p-channel enhancement mode MOSFET device using high level language. 15 Write and execute the IIR filters logic for any suitable example using available Digital signal Processor. 16 Write and Implement Butterworth filters logic for any suitable example using available Digital signal Processor. 17 Write and Implement FIR filters logic for any suitable example using available Digital signal Processor. 18 Write and Implement FFT to plot the magnitude and phase spectrum for any suitable example using available Digital signal Processor.

100 100 100

100

100

100

19 Write and execute a MATLAB program to perform linear convolution using overlap save 100 method for 2 input sequences x[n] and impulse responseh[n]. 20 Write and execute a MATLAB program to perform DFT and circular shift property of 100 finite periodic sequence. 21 Develop and Implement a behavioural model for a two stage pipelined floating point 100 multiplier using suitable reprogrammable logic device.