Design For Testability and Built-In Self-Test

Chapt er 6
Desi gn f or Test abi l i t y and

Bui l t - I n Sel f - Test
Jin- Fu Li
Advanced Reliable Syst ems ( ARES) Lab.
Depart ment of Elect rical Engineering
Nat ional Cent ral Universit y
Jungli, Taiwan
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
Basics
Design- for- Test abilit y ( DFT) Techniques
Ad Hoc DFT
St ruct ural Met hods
Scan
Part ial Scan
BI ST
Boundary Scan
Syndrome- Test able Design
C- Test able Design
Built - I n Self- Test ( BI ST) Techniques
Signat ure Analysis
Pseudorandom Pat t ern Generat or ( PRPG)
Built - I n Logic Block Observer ( BI LBO)
Summary
Out l i ne
Definit ion
A fault is t est abl e if t here exist s a well- specified
procedure t o expose it , which is implement able wit h
a reasonable cost using current t echnologies. A
circuit is t est abl e w i t h r espect t o a f aul t set
when each and every fault in t his set is t est able
Definit ion
Desi gn f or t est abi l i t y ( DFT) refers t o t hose
design t echniques t hat make t est generat ion and
t est applicat ion cost - effect ive
Elect ronic syst ems cont ain t hree t ypes of
component s: ( a) digit al logic, ( b) memory
blocks, and ( c) analog or mixed- signal circuit s
I n t his chapt er, we discuss DFT t echniques for
digit al logic
Def i ni t i ons
Part it ion large circuit s int o smaller subcircuit s
t o reduce t est generat ion cost ( using MUXed
and/ or scan chains)
Ad Hoc DFT Gui del i nes
C1
0 1
0

1
1

0
C2
1 0
T
2
T
1
T
2
T
1
Mode
0 0
0 1
1 0
Normal
Test C1
Test C2
I nsert t est point s t o enhance cont rollabilit y &
observabilit y
Test point s: cont rol point s & observat ion point s
C1
0

1
C2
CP
1
C2
CP
2
OP
CP
3
CP
4
Design circuit s t o be easily init ializable
Provide logic t o break global feedback pat hs
Part it ion large count er int o smaller ones
Avoid t he use of redundant logic
Keep analog and digit al circuit s physically
apart
Avoid t he use of asynchronous logic
Consider t est er requirement s ( pin limit at ion,
et c)
Et c
They are effect ive for circuit part it ioning
They provide cont rollabilit y and observabilit y
of int ernal st at e variables for t est ing
They t urn t he sequent ial t est problem int o a
combinat ional one
Four maj or approaches
Shift - regist er modificat ion
Scan pat h
Level- sensit ive scan design ( LSSD)
Random access
Circuit is designed using pre- specified design
rules.
Scan Desi gn Appr oaches
Consider a represent at ion of sequent ial circuit s
To make element s of st at e vect or cont rollable
and observable, we add
A TEST mode pin ( T)
A SCAN- I N pin ( SI )
A SCAN- OUT pin ( SO)
A MUX ( swit ch) in front of each FF ( M)
Scan Desi gn Appr oaches
Combi nat i onal Logi c
st at e
clk
X
Z
Y
y
( primary input s)
( primary out put s)
( next st at e)
( present st at e)
Addi ng Scan St r uct ur e
SFF
SFF
SFF
Combi nat i onal
l ogi c
PI PO
SCAN- OUT
SCAN- I N
T
Test pat t ern generat ion
Use combinat ional ATPG t o obt ain t est s for all
t est able fault s in t he combinat ional logic
Add shift regist er t est s and convert ATPG t est s int o
scan sequences for use in manufact uring t est
Scan design rules
Use only clocked D- t ype of flip- flops for all st at e
variables
At least one PI pin must be available for t est ; more
pins, if available, can be used
All clocks must be cont rolled from PI s
Clocks must not feed dat a input s of flip- flops
Scan Test Gener at i on & Desi gn Rul es
Cor r ect i ng a Rul e Vi ol at i on
All clocks must be cont rolled from PI s
Comb.
l ogi c
Comb.
l ogi c
D1
D2
CK
Q
FF
Comb.
l ogi c
D1
D2
CK
Q
FF
Comb.
l ogi c
Adding a scan FF and a mux allows a feedback loop t o
be opened for t est ing
Test ing derived clocks requires t he use of a mux t o
bypass t he division st ages
CK
FF
A B
0

1
A B
T
0

1
Test
FF
CK
FF
Freq. Divider
FF
CK
FF
Freq. Divider
0

1
Test
The AND gat es keep t he bus drivers from
being act ivat ed by t he normal logic during
t est ing
FF
FF
FF
FF
Test
St ep 1: Swit ch t o t he shift - regist er mode and
check t he SR operat ion by shift ing in an
alt ernat ing sequence of 1s and 0s, e. g. , 00110
( funct ional t est )
St ep 2: I nit ialize t he SR- - - load t he first
pat t ern
St ep 3: Ret urn t o t he normal mode and apply
t he t est pat t ern
St ep 4: Swit ch t o t he SR mode and shift out
t he final st at e while set t ing t he st art ing st at e
for t he next t est . Go t o St ep 3
Scan Test Pr ocedur e
Combi ni ng Test Vect or s
I 2 I 1
O1 O2
S2
S1
N2 N1
Combi nat i onal
l ogi c
PI
Pr esen
t
st at e
PO
Nex t
st at e
SCAN-I N
T
SCAN-OUT
Combi ni ng Test Vect or s
I 2 I 1
O1 O2
PI
PO
SCAN-I N
SCAN-OUT
S1 S2
N1 N2
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
T
Dont c ar e
or r andom
bi t s
Sequenc e l engt h = (n
c omb
+ 1) n
sf f
+ n
c omb
cl ock per i ods
n
c omb
= number of c ombi nat i onal vec t or s
n
sf f
= number of sc an f l i p-f l ops
Scan regist er must be t est ed prior t o
applicat ion of scan t est sequences
A shift sequence 00110011 . . . of lengt h
n
sff
+ 4 in scan mode ( TC= 0) produces 00, 01,
11 and 10 t ransit ions in all flip- flops and
observes t he result at SCAN- OUT out put
Tot al scan t est lengt h:
( n
comb
+ 2) n
sff
+ n
comb
+ 4 clock periods
Example: 2, 000 scan flip- flops, 500 comb.
vect ors, t ot al scan t est lengt h ~ 10
6
clocks
Mult iple scan regist ers reduce t est lengt h
Test i ng Scan Regi st er
Scan flip- flops can be dist ribut ed among any
number of shift regist ers, each having a
separat e SCAN- I N and SCAN- OUT pin
Test sequence lengt h is det ermined by t he
longest scan shift regist er
Just one t est cont rol ( TC) pin is essent ial
Mul t i pl e Scan Regi st er s
SCAN- I N1 SCAN- OUT1
T
SCAN- I N1
SCAN- I NK
SCAN- OUT2
SCAN- OUTK
Scan Regist er 1
Scan Regist er 2
Scan Regist er 3
Scan flip- flops are chained wit hin subnet works
before chaining subnet works
Advant ages:
Aut omat ic scan insert ion in net list
Circuit hierarchy preserved helps in debugging
and design changes
Disadvant age: Non- opt imum chip layout
Hi er ar chi cal Scan
SFF1
SFF2 SFF3
SFF4
SFF3 SFF1
SFF2 SFF4
Scanin Scanout
Scanin
Scanout
Hierarchical net list
Flat layout
Opt i mum Scan Lay out
I O
pad
Flip-
flop
cell
I nt erconnect s
Rout ing
channels
SFF
cell
T
SCANI N
SCAN
OUT
Y
X
Y
Act ive areas: XY and X Y
X
Aut omat ed Scan Desi gn
Behavi or, RTL, and l ogi c
Desi gn and ver i f i c at i on
Gat e-l evel
net l i st
Sc an desi gn
r ul e audi t s
Combi nat i onal
ATPG
Sc an har dwar e
i nser t i on
Chi p l ayout : Sc an-
chai n opt i mi zat i on,
t i mi ng ver i f i c at i on
Sc an sequenc e
and t est pr ogr am
gener at i on
Desi gn and t est
dat a f or
manuf ac t ur i ng
Rul e
vi ol at i ons
Sc an
net l i st
Combi nat i onal
vec t or s
Sc an chai n or der
Mask dat a
Test pr ogr am
An Ex ampl e of DFT Compi l er Fl ow
Pre-Scan
DRC
Insert Scan
Scan-
Ready
Synthesis
Post-Scan
DRC
check_t est check_t est i nser t _scan compi l e -scan
Constraints:
Scan style,
speed, area
Technology
Library:
Gates, flip-flops,
scan equivalents
Constraint-Based
Scan Synthesis:
Routing, balancing,
gate-level
optimization
HDL
Preview
Coverage
Source: H.-J. Huang, CI C
Shi f t Regi st er s
SHFT_IN
SI
SE
CLK
SHFT_OUT/ SO
DFF
DFF
DFF
CLK
SHIFT_OUT SHIFT_IN
SI
SE
DFF DFF
DFF
Scan added:
Revised:
Lock up Lat ch I nser t i on
clk1
clk2
clk1
clk2
OK!
Big Problem !!
Rearrange clock domain or
insert lockup latch
CLK_RTZ_1
CLK_RTZ_2
t
INV
F1 F2
latch
F3
Uses addressable lat ches
Provides random access t o FFs via
mult iplexingaddress select ion
Random Access Scan
L L L
C/ L X Z
SO
C
SI
L
Random access scan cell
Advant ages
Fast ; minimal impact on normal pat h
Fast for t est ingrandom access
Abilit y t o wat ch a node in normal operat ion mode
Disadvant ages
Hardware cost is large; more pins added
Random Access Scan
CK2
DI
CK1
SI
Addr
+ L
SO
C= CK1&CK2
Wire-AND
During normal operation the storage cells operate in
their parallel-load mode
To scan in a bit, the appropriate cell is addressed,
the data are applied to s
in
Random Access Ar chi t ect ur e
X decoder
Addressable
storage
elements
clocks and controls
Sout
Sin
SCK
Si
x-address
y-address
Y
decode
r
.
.
.
. . .
Combinational/Logic
1. Set test input to all test points
2.Apply the master reset signal to initialize all memory
elements
3.Set scan-in address and data, and then apply the scan
clock
4.Repeat step 3 until all internal test inputs are scanned
in
5.Clock once for normal operation
6.Check states of the output points
7.Read the scan-out states of all memory elements by
applying appropriate X-Y signals
Test Pr ocedur e
HOLD= 0Q & Q are fixed
The cont rol input HOLD keeps t he out put
st eady at previous st at e of flip- flop
Applicat ions
Reduce power dissipat ion during scan, et c.
Scan- Hol d FFs ( SHFFs)
SFF
D
SI
TC
CK
HOLD
Q
Q
SO
Trend in flip flop count wit h design size
Scan Ent er s t he Nanomet er Er a
[ Source: EE Times]
Adapt ive scan archit ect ure
Scan Ent er s t he Nanomet er Er a
[ Source: EE Times]
Definit ion
The syndrome of a Boolean funct ion is ,
where is t he number of 1s ( mint erms) in and
is t he number of independent input variables
A t ypical syndrome t est ing set - up
A circuit is syndrome t est able iff fault ,

Syndromes of logic gat es
Sy ndr ome- Test abl e Desi gn
f
n
f k
f S
2
) (
) (
k
f
1 ) ( 0 s s f S
n
Exhaust ive
pat t erns
CUT
Reference
syndrome
Syndrome
regist er
Comparat or
Go/ No- go
( Count er)
o ) ( ) (
o
f S f S =
n
2 / 1
Gat e
S
n
AND
) 2 / 1 ( 1
n
n
OR
2 / 1
n
XOR
2 / 1
NOT
Consider a circuit having 2 blocks, f and g,
wit h unshared input s
Example
Calculat e t he syndrome of t he following circuit
Sy ndr ome Comput at i on
g f g f
S S S S +
O/ P Gat e
S
OR
g f
S S
AND
g f g f
S S S S 2 +
XOR
g f
S S 1
NAND
g f g f
S S S S + 1
NOR
S
S
1
S
4
S
2
S
3
S
1
= 1-1/4 = 3/4
S
2
= 1-1/4 = 3/4
S
3
= 1/8
S
4
= 1- S
2
- S
3
+ S
2
S
3
= 7/32
S = S
1
S
4
= 21/128
Consider t he funct ion . The circuit is
syndrome unt est able
I f t he circuit has a fault , t hen t he

corresponding syndrome of t he fault y circuit is
Thus t he circuit is syndrome unt est able
A realizat ion C of a funct ion f is said t o be
syndrome- t est able if no single st uck- at fault
causes t he circuit t o have t he same syndrome
as t he fault - free circuit
Syndrome is a propert y of f unct i on, not of
i mpl ement at i on
z y xz f + =
2 / 1 =
f
S
0 / z o
2 / 1
'
=
f
S
Definit ion
A logic funct ion is unat e in a variable x
i
if it can be
represent ed as an SOP or POS expression in which
t he variable x
i
appears eit her only in an
uncomplement ed form or only in a complement ed
form
For example:
no unat e
unat e in , not unat e
in
Theorem
A 2- level irredundant circuit realizing a unat e
funct ion in all it s variables is syndrome t est able
2 1 2 1 2 1
) , ( x x x x x x f + =
3 1 3 2 2 1 3 2 1
) , , ( x x x x x x x x x f + + = 3 2
, x x
1
x
Theorem
Any 2- level irredundant circuit can be made
syndrome- t est able by adding cont rol input s t o t he
AND gat es
For example
The funct ion is syndrome unt est able
Now add a cont rol input , where
1 when in normal operat ion mode
normal i/ p when in t est mode
, and Syndrome t est able
Drawbacks
Only for combinat ional logic
Exhaust ive; modificat ion doubles t est set size
y f S =
'
=
'
o
, 8 / 3
z y xz f + =
C
z y cxz f c + =
'
S S
'
= =
'
2 / 1
o
Built - in self- t est ( BI ST) :
The capabilit y of a circuit ( chip/ board/ syst em) t o
t est it self
Advant ages of BI ST
Test pat t erns generat ed on- chip cont rollabilit y
increased
( Compressed) response evaluat ed on- chip
observabilit y increased
Test can be on- line ( concurrent ) or off- line
Test can run at circuit speed more realist ic;
short er t est t ime; easier delay t est ing
Ext ernal t est equipment great ly simplified, or even
t ot ally eliminat ed
Easily adopt ing t o engineering changes
I nt r oduct i on t o Bui l t - I n Sel f - Test
On- line BI ST
Concurrent ( EDAC, NMR, t ot ally self- checking
checkers, et c. ) :
Coding or modular redundancy t echniques ( fault
t olerance)
I nst ant aneous correct ion of errors caused by
t emporary or permanent fault s
Nonconcurrent ( diagnost ic rout ines) :
Carried out while a syst em is in an idle st at e
Module 2
Module 1
Module N
Vot er
Out put
N- Modular Redundancy ( NMR)
Off- line BI ST
A t ypical BI ST archit ect ure
Test generat ion
Prest ored TPG, e. g. , ROM or shift regist er
Exhaust ive TPG, e. g. , binary count er
Pseudo- exhaust ive TPG, e. g. , const ant - weight
count er, combined LFSR and SR
Pseudo- random pat t ern generat or, e. g. , LFSR
Funct i onal Ci r cui t
( Ci r cui t Under Test )
PG
BI ST
RA
Cont r ol l er
Go/ No- Go
Response analysis
Check- sum
Ones count ing
Transit ion count ing
Parit y checking
Syndrome analysis
Et c.
Linear feedback shift regist er ( LFSR) can be
bot h t he t est generat or and response analyzer
We need a gold unit t o generat e t he good
signat ure or a simulat or
A compression t echnique based on t he concept
of cyclic redundancy checking ( CRC) and
realized in hardware using linear feedback
shift regist ers
Definit ion
A funct ion f( x
1
, x
2
, , x
n
) is said t o be linear if it can
be expressed in t he form
where
There are 2
n+ 1
linear funct ions of n variables
Linear operat ions: modulo addit ion, module scalar
mult iplicat ion, & delay
Nonlinear operat ions: AND, OR, NAND, NOR, et c.
Si gnat ur e Anal y si s
n n
x a x a x a a f =
2 2 1 1 0
n i a
i
, , 1 , 0 } 1 , 0 { = e
Li near Feedback Shi f t Regi st er
Definit ion
A linear feedback shift regist er is a shift
regist er wit h feedback pat hs which consist
only of unit delays and XOR operat ors
Let M= fault - free circuit response, B= fault y
circuit response, and E= error syndrome
( Hamming) , where E= M Bt hus M= B E
and B= M E
We need a circuit t o t ake B as input and
compact it but st ill be able t o t ell if M! = B
LFSR is considered as a popular approach for
t est response compact ion

Two t ypes of generic st andard LFSRs
St r uct ur es of LFSR
D FF
C
1
D FF D FF
C
N
C
2
C
N-1
Y
1
Y
2
Y
N-1
Y
N
D FF
C
1
D FF D FF
C
N
C
2
C
N-1
Y
1
Y
2
Y
N-1
Y
N
As a funct ion of t ime, Y
j
can be expressed as
for
Hence
I f we denot e t he t ranslat ion operat or as X
k
,
where k is t he t ime t ranslat ion unit
On t he ot her hand, Y
0
( t ) can be expressed as
Then
for
Mat hemat i cal Foundat i on of LFSR
) 1 ( ) (
1
=

t Y t Y
j j
0 = j
) ( ) (
0
j t Y t Y
j
=
j
j
X t Y t Y ) ( ) (
0
=
=
=
N
j
j j
t Y C t Y
1
0
) ( ) (
=
=
N
j
j
j
X t Y C t Y
1
0 0
) ( ) ( N j s s 1
We can rewrit e t he Y
0
( t ) as
Also,
We can rewrit e t his expression as
For nont rivial solut ion, , we must have
where
is called t he charact erist ic polynomial of
t he LFSR
Mat hemat i cal Foundat i on of LFSR
=
=
N
j
j
j
X C t Y t Y
1
0 0
) ( ) (
0 ) 1 )( (
1
0
= +
=
N
j
j
j
X C t Y
0 ) ( ) (
0
= X P t Y
N
0 ) (
0
= t Y
0 ) ( = X P
N
=
+ =
N
j
j
j N
X C X P
1
1 ) (
) (X P
N
A serial input st ream m
n
, m
n- 1
, , m
1
, m
0
ent ering t he LFSR can be considered as t he
coefficient s of a polynomial
The LFSR is said t o have a charact erist ic polynomial

defined as follows
LFSR f or Si gnat ur e Anal y si s

m(X)
q(X)
0 1
1
1
) ( m X m X m X m X m
n
n
n
n
+ + + + =

0 1
1
1
) ( c X c X c X c X c
r
r
r
r
+ + + + =

D FF
C
1
D FF D FF
C
r
C
2
C
r-1
s
1
s
2
s
r-1
s
r
C
0
Assume t hat t he init ial st at e of t he LFSR is
D
i
= 0, i= 0,,r- 1, t hen t he LFSR effect ively
divides any m( X) by c( X) , i. e. ,
The quot ient q( X) appears serially at t he

out put of t he SR. The remainder s( X) is in t he
SR aft er n+ 1 shift s:
LFSR f or Si gnat ur e Anal y si s

) ( ) ( ) ( ) ( X s X C X q X m + - =
0 1
1
1
) ( s X s X s X s X s
r
r
r
r
+ + + + =

The following LFSR divides any m( X) by
c( X) = X
5
+ X
4
+ X
2
+ 1
Suppose m( x) = X
7
+ X
6
+ X
5
+ X
4
+ X
2
+ 1, t hen
q( X) = X
2
+ 1, and s( X) = X
4
+ X
2
An Ex ampl e
D
1
D
0
D
3
D
2
D
3
m(X) q(X)
I/P D
0
D
1
D
2
D
3
D
4
O/P
10101111
101
10
1
-
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1
0
1
1
-
-
1
01
101
Let m( X) be t he input polynomial of degree k- 1, q( X)
t he quot ient , and s( X) t he signat ure ( remainder) .
Then
m( X) = q( X) c( X) + s( X)
The error syndrome can be represent ed as a
polynomial e( X)
E. g. , le m( X) = X
4
+ X
3
+ 1( 11001) , and an erroneous
input b( X) = X
3
+ X+ 1( 01011) , t hen t he error
syndrome is 11001 01011= 10010, and is
represent ed by e( X) = X
4
+ X
I n general, an erroneous input polynomial can be
represent ed by
B( X) = m( X) + e( X)

Theorem1: I nput st reams m( X) and b( X) have t he
same signat ure iff e( X) is a mult iple of c( X)
Proof: an error is not det ect ed when m( X) and b( X) have
t he same signat ure, i. e. , b( x) = q( X) c( X) + s( X) . Since
m( X) = q( X) c( X) + s( X) , we obt ain
e( X) = m( X) + b( X) = c( X) ( q( X) - q( X) )
Theorem2: Undet ect ed errors correspond t o error
pat t erns which are mult iples of c( X)
Theorem3: I f c( X) has 2 or more nonzero
coefficient si. e. , at least 1 feedback t ermt hen it
can det ect all single- bit errors
Proof: all nonzero mult iples of c( X) must have at least 2
nonzero coefficient s. Therefore, any error wit h only 1
nonzero coefficient cannot be a mult iple of c( X) and must
be det ect able.
Theorem4: for a k- bit response sequence, if all
possible error pat t erns are equally likely, t hen t he
probabilit y of failing t o det ect an error ( i. e. , t he
aliasing probabilit y) by t he LFSR of lengt h r is
Proof: For a k- bit response, deg( m( X) ) = k- 1, and
deg( e( X) ) < = k- 1. Therefore, t he number of possible
error polynomial is represent ed by e( X) = c( X) p( X)
for some nonzero p( X) . Since deg( c( X) ) = r, t he
number of possible p( X) s is 2
k- r
- 1. Thus
For a long sequence, k> > rP
al
~ 1/ 2
r
Al i asi ng Pr obabi l i t y
1 2
1 2
=

k
r k
al
P
1 2
1 2
=

k
r k
al
P
The st ruct ure of mult iple- input signat ure regist er
( MI SR)
The mat hemat ical t heory is a direct ext ension of t he
result s shown above
For equally likely error pat t erns and long dat a
st reams, t he aliasing probabilit y for an MI SR of r
st ages also is .
Mul t i pl e- I nput Si gnat ur e Regi st er
D FF
C
1
D FF D FF
C
r
C
2
C
r-1
D
1
D
r-2
D
r-1
D
0
r
al
P 2 / 1 ~
Usually, we t hink of dat a compression as a process
t hat preserves dat a int egrit y. This is why we given
more at t ent ion here t o dat a compact ion, which may
result in some losses
There are several compact ion t est ing t echniques
Parit y t est ing
One count ing
Transit ion count ing
Syndrome calculat ion
Signat ure analysis
Response Compact i on
This is t he simplest of all t echniques but also t he
most lossy
The parit y of responses t o t he t est pat t erns is
calculat ed as
, where L is t he lengt h of t he t est and r
i
is
t he response for t he it h t est pat t ern
The response of t he circuit under t est ( CUT) t o
pat t ern i and t he part ial product P
i- 1
is illust rat ed as
below
Par i t y Test i ng
=
=
=
L i
i
i
r P
1
1 i
P
D FF CUT
i
r
Test
Patterns
The number of 1s in t he response st ream is
calculat ed and compared t o t he number of 1s in t he
fault - free responses
Consider t he circuit shown below
I f we have a t est of lengt h L and t he fault - free count
is m, t he possibilit y of aliasing is [ C( L, m) - 1] pat t erns
out of a t ot al number of possible st rings of lengt h L,
( 2
L
- 1)
One Count i ng
a
b
c
11110000
11001100
10101010
11000000
11101010
f
I n t ransit ion count ing compact ion, it is only t he
number of t ransit ion 01 and 10 t hat are count ed.
Thus t he signat ure is given by
, where t he summat ion is ordinary
addit ion and is XOR operat ion
The compact ion scheme is shown below
Tr ansi t i on Count i ng
1
1
1
+
=
=

i
L i
i
i
r r
1 i
r
D FF CUT
i
r
Test
Patterns
Logic BI ST uses most ly pseudorandom ( PR) t est s.
They are usually much longer t han det erminist ic
t est s, but are definit ely less cost ly t o generat e
PR t est s are generat ed using a LFSR or cellular
aut omat a
By means of a simple circuit called an aut onomous
linear feedback shift regist er ( ALFSR)
Definit ion: an ALFSR is a LFSR wit h no ext ernal
input s
Fault s t hat are hard t o det ect wit h PR t est s are
called random pat t ern resist ant fault s
Pseudor andom Pat t er n Gener at or
Example: t he following ALFSR generat es t he
pseudorandom sequence shown in t he t able below
The out put sequence is 000111101011001, which repeat s aft er
15( 2
n
- 1) clocks
Max period for an n- st age ALFSR= 2
n
- 1
All- 0 st at e of t he regist er cannot occur in t he max- lengt h cycle
Pseudor andom Pat t er n Gener at or ( PRPG)
Q
1
Q
2
Q
3
Q
4
output
Q
1
Q
2
Q
3
Q
4
State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15=0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
0
0
1
1
1
0
0
1
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
A generic st ruct ure of ALFSR
A sequence of bit s { a
m
} = a
0
, a
1
, , a
m
, can be associat ed
wit h a polynomialit s gener at i on f unct i on:
I n t he above figure, assume t hat t he current st at e of Q
i
is
a
m- i
, i= 1, 2, , n, and t he init ial st at e of Q
i
is a
- i
= 0,
i= 1, 2, , n, but a
- n
= 1, t hen
Mat hemat i cal Foundat i on of PRPG
=

=
n
i
i m i m
a c a
1
=
= + + + +
0
1 0
) (
m
m
m
m
m
X a X a X a a X G
Q
1
Q
2
Q
n-1
Q
n
C
1
C
n
C
2
C
n-1
C
n-2
1 m
a
m
a
n m
a

1 + n m
a
2 m
a

= =

=
0 1
) (
m
n
i
m
i m i
X a c

=
=
0
) (
m
m
m
X a X G

=
=
n
i m
i m
i m
i
i
X a X c
1 0
] [
1
1
1
=
+ + + =
n
i i m
i m
i m
i
i
i
i
X a X a X a X c
] [
1 0
1
1
=
+ + + =
n
i m
m
m
i
i
i
i
X a X a X a X c
] ) ( [
1
1
1
=
+ + + =
n
i
i
i
i
i
X G X a X a X c

= =
+ + + =
n
i
n
i
i
i
i
i
i
i
X a X a X c X G X c
1 1
1
1
) ( ) (

= =
+ + = +
n
i
n
i
i
i
i
i
i
i
X a X a X c X G X c
1 1
1
1
) ( ) ( 1
=
=

+
+ +
=
n
i
i
i
n
i
i
i
i
i
X c
X a X a X c
X G
1
1
1
1
1
) (
) (

Now is t he charact erist ic polynomial of
t he LFSR as defined above. Since a
- 1
= 0, i= 1, 2, , n- 1,
and a
- n
= 1, we have
The sequence { a
m
} is cyclic, wit h t he period assumed
t o be p
=
+ =
n
i
i
i
X c X c
1
1 ) (
=
= =
0
) (
1
) (
m
m
m
X a
X c
X G
) (
) (
1
) (
1
1 1 0
+ + + = =
p
p
X a X a a
X c
X G
) (
1
1 1 0
+ + + +
p
p
p
X a X a a X
+
) (
1
1 1 0
2
+ + + +
p
p
p
X a X a a X
) 1 )( (
2 1
1 1 0
+ + + + + + =

p p p
p
X X X a X a a
p
p
p
X
X a X a a
+ + +
=

1
) (
1
1 1 0

1
1 1 0
) (
1

+ + + =
p
p
p
X a X a a
X c
X
i.e., c(X) evenly divides into 1-X

p
Theorem: I f t he init ial st at e of an n- st age LFSR is a
- i
= 0,
i= 1, 2, , n- 1, and a
- n
= 1, t hen t he LFSR sequence { a
m
}
is periodic wit h a period t hat is t he smallest int eger p
for which c( X) divides 1- X
p
The period p< = 2
n
- 1
For a given n, we want t o find a c( X) t hat maximizes p
Definit ion: The sequences produced by max- lengt h
LFSRs are called pseudorandom sequences or m-
sequences. The charact erist ic polynomial associat ed
wit h an m- sequence is called a primit ive polynomial.
An irreducible polynomial is one t hat cannot be
fact ored
Pseudorandom sequences ( or m- sequences) are not
really random since t hey are produced by a fixed circuit .
Theor ems
Theorem: An irreducible polynomial c( X) sat isfies t he
following 2 condit ions:
I t has an odd number of t erms including t he const ant
t erm
I f it s degree n> 3, t hen c( X) must divide 1+ X
p
, where
p= 2
n
- 1
Theorem: A primit ive polynomial is irreducible if t he
smallest posit ive int eger p t hat allows t he polynomial
t o divide evenly int o 1+ X
p
occurs for p= 2
n
- 1, where n
is t he degree of t he polynomial
Theor ems
A BI LBO is a mult i- purpose t est module which serves
as a t est generat or or a signat ure analyzer. I t is
composed of a row of FFs and some addit ional gat es
for shift and feedback operat ion
Bui l t - I n- Logi c- Bl ock - Obser v er ( BI LBO)
D D D D
B1
B2
SI
0
1
Z1 Z2 Z3 Z4
B1 B2 Function
0 1
1 1
0 0
1 0
All FFs are reset
Behaves as separate latchesnormal mode
A linear shift registerSR mode
MISR/PRPGtest mode
STUMPS Ar chi t ect ur e
Logic BI ST wit h STUMPS archit ect ure
PRPG
MISR
B
S
R
CUT
PIs
POs
Test
control
signal
Design- for- t est abilit y t echniques
Ad- hoc t echniques
Scan
LSSD
Random access scan
Syndrome- t est able
C- t est abilit y
Scan is a popular DFT t echnique in modern I C
design
DFT can increase t he cont rollabilit y and
observabilit y of t he circuit under t est
Summar y
Built - in self- t est met hodology is more and
more import ant for deep submicron designs
Two key component s of BI ST
Test pat t ern generat or
E. g. , LFSR
Response evaluat or
E. g. , BI LBO
Summar y

Design For Testability and Built-In Self-Test

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Design For Testability and Built-In Self-Test

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Chapt er 6

Desi gn f or Test abi l i t y and

A circuit is syndrome t est able iff fault ,

I f t he circuit has a fault , t hen t he

The LFSR is said t o have a charact erist ic polynomial

LFSR f or Si gnat ur e Anal y si s

The quot ient q( X) appears serially at t he

LFSR f or Si gnat ur e Anal y si s

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50

i.e., c(X) evenly divides into 1-X

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