Cp

Ep
Lm
CE
Li
Ei
La
Ea
Su
Eu
Lb
Lo

T1
T2
T3
T4
T5
T6

OP0

OP1

OP2

OP3

OP4

OP5

OP6

OP7

U1:A
VCC

VCC

3
2

?
?
?
?
?
?
?
?
?
?
?
?

OFF

9
10
11
12
13
14
15
16

5
6
7
8

8
9

SW6
OPCode / Data
Switches

SW4

LOW

U1:D

Write
Memory

HIGH

13
11
12

VCC

U3:A
HLT

1
2
13

74HC00

SW2
Ep

VCC

ENmar

U2:D

ENpc

SW7
CE

12

U2:A

SW8

VCC

13
11

Manual

OEram

ENinput

Manual/Auto

U2:B

Program/Run

Auto

Program/Run

U3:B

4
6

3
4
5

HLT

VCC

U4

7
10
2
9
1

VCC
Cp
CLK
VCC
CLR

U5
14
13
12
11
15

Q0
Q1
Q2
Q3
RCO

ENP
ENT
CLK
LOAD
MR

3
4
5
6

U6

A0
A1
A2
A3

1
13

VCC
ENpc

B0
B1
B2
B3

11
10
9
8

W0
W1
W2
W3

D0
D1
D2
D3
D4
D5
D6
D7

OEA
OEB
74HC243
Program Counter

2
3
4
5
6
7
8
9

A0
A1
A2
A3
A4
A5
A6
A7

19
1

ENinput
VCC

74HC161
Program Counter

W0
W1
W2
W3
W4
W5
W6
W7

18
17
16
15
14
13
12
11

B0
B1
B2
B3
B4
B5
B6
B7

CE
AB/BA
74HC245
Data Input 3-State Buffer

U10
U7
W4
W5
W6
W7

14
13
12
11
7
1
2
9
10
15

CLK

Li
CLR

U8

D0
D1
D2
D3

Note: The 555 timer circuit has been substituted with

a virtual clock source to speed up the simulation.

U3:B(C)
INIT=LOW
START=0
COUNT=-1
CLOCK=1

D0
D1
D2
D3

CLK

12

VCC

3
4
5
6

A8
A9
A10
A11
A12
A13
A14
A15
B2[0..7]
B3[0..7]

Single Step

WEram

8
7
6
5
4
3
2
1

ON

ON

4
3
2
1

10

VCC

A0
A1
A2
A3
A4
A5
A6
A7
B0[0..7]
B1[0..7]

W7
W6
W5
W4
W3
W2
W1
W0

U1:C

D7
D6
D5
D4
D3
D2
D1
D0

ADR3
ADR2
ADR1
ADR0

?
?
?
?
?
?
?
?

74HC00

SW3
OFF

Address
Switch

CLR

VCC

SW1

D7
D6
D5
D4
D3
D2
D1
D0

U1:B
CLEAR

VCC

CLK
Cp
Ep
Lm
CE
Li
Ei
La
W[0..7]

START

Clear/Start

W7
W6
W5
W4
W3
W2
W1
W0

?
?
?
?
?
?

SW5

ADR3
ADR2
ADR1
ADR0

CLR

3
4
5
6

Q0
Q1
Q2
Q3

CLK
OE1
OE2
E1
E2
MR

W0
W1
W2
W3

I4
I5
I6
I7

14
13
12
11

D0
D1
D2
D3

7
1
2
9
10
15

CLK
Ei
Li

U9
Q0
Q1
Q2
Q3

3
4
5
6

W0
W1
W2
W3

W0
W1
W2
W3

CLK
OE1
OE2
E1
E2
MR

74HC173
Instruction Register

14
13
12
11

D0
D1
D2
D3

7
1
2
9
10
15

CLK

Lm

3
4
5
6

Q0
Q1
Q2
Q3

ADR1
ADR2

CLK
OE1
OE2
E1
E2
MR

74HC173
Instruction Register

2
3
5
6
11
10
14
13

ADR0

ADR3

1
15

ENmar

U11

1A
1B
2A
2B
3A
3B
4A
4B

1Y

10
9
8
7
6
5
4
3
25
24
21
23
2
26
1

2Y

3Y

12

4Y

A/B
E
74HC157
Memory Address Selector

74HC173
Memory Address Register

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

20
27
22

WEram
OEram

W0
W1
W2
W3
W4
W5
W6
W7

11
12
13
15
16
17
18
19

D0
D1
D2
D3
D4
D5
D6
D7

CE
WE
OE
62256
RAM

U13
W0
W1
W2
W3

14
13
12
11
7
1
2
9
10
15

CLK

La

U17

D0
D1
D2
D3

3
4
5
6

Q0
Q1
Q2
Q3

5
3
14
12

CLK
OE1
OE2
E1
E2
MR

3
2

14
13
12
11

Lb

C4

Carry

74HC283
Full Adder

5
9

D0
D1
D2
D3

7
1
2
9
10
15

CLK

C0

Su

4
1
13
10

S0
S1
S2
S3

B0
B1
B2
B3

U20
W0
W1
W2
W3

6
2
15
11

74HC173
Accumulator (LSB)

A0
A1
A2
A3

Q0
Q1
Q2
Q3

3
4
5
6

10
12
11

CLK
OE1
OE2
E1
E2
MR

13

Su

U15:D
74HC86

74HC173
B Register (LSB)

U12
W0
W1
W2
W3
W4
W5
W6
W7

2
3
4
5
6
7
8
9
19
1

Ea

U19

A0
A1
A2
A3
A4
A5
A6
A7

B0
B1
B2
B3
B4
B5
B6
B7

18
17
16
15
14
13
12
11

18
17
16
15
14
13
12
11

CE
AB/BA

14
13
12
11

La

W4
W5
W6
W7

Lb

3
4
5
6

5
3
14
12

3
2

Eu

U21

D0
D1
D2
D3

Q0
Q1
Q2
Q3

C0

Carry

4
1
13
10

S0
S1
S2
S3

B0
B1
B2
B3

4
5

A0
A1
A2
A3

6
2
15
11

74HC173
Accumulator (MSB)

7
1
2
9
10
15

CLK

Q0
Q1
Q2
Q3

CLK
OE1
OE2
E1
E2
MR

14
13
12
11

19
1

U18

D0
D1
D2
D3

7
1
2
9
10
15

W0
W1
W2
W3
W4
W5
W6
W7

2
3
4
5
6
7
8
9

74HC245

U14

CLK

A0
A1
A2
A3
A4
A5
A6
A7

CE
AB/BA
74HC245

W4
W5
W6
W7

B0
B1
B2
B3
B4
B5
B6
B7

C4

74HC283
Full Adder

3
4
5
6

10
12
11

CLK
OE1
OE2
E1
E2
MR

13

Su

U16:D
74HC86

74HC173
B Register (MSB)

U22
3
4
5
6

W0
W1
W2
W3

OP4
OP5
OP6
OP7

CLK
OE1
OE2
E1
E2
MR

14
13
12
11

D0
D1
D2
D3

7
1
2
9
10
15

CLK

Lo

I4

Ring Counter

U24:A
2

1
CLK

74HC107

12

CLK

11

CLK
6

12

CLK

CLK
6

74HC107
1

9
Q

CLK
6

12

CLK
2

11

11

10

13

10

10

5
13

U31:B

U31:A

74HC107

U24:C

U30:B

74HC107

U30:A

74HC107

U29:B

74HC107

13

U29:A

U24:B

CLR

U24:D
12

13
T6
T5
T4
T3
T2

13

T1
11

U28:E

5
4

U25:A

Control Matrix

12

Instruction Decoder

U28:D

U28:A
6

2
1

LDA
ADD
SUB

U28:B

U32:D
5
4

U26:A

U33:D

U34:D

10

12

13

10

12

13

10

12

13

10

12

13

4
9

10
9

10

OUT

U25:B

13
12

U35:D

U36:C

U28:C
6

U26:B

11

11

11

11

U37:B

U38:A

U38:B

3
4
5

1
2
13

12
13

U37:A

U39:A

U39:B

Cp Ep

Ei

La

Ea

Su

Eu

U41:B
4

U41:A
2

12

U40:D

3
1

13

11

12
Li

U40:E
10

CE

U40:F
8

Lm

U40:C
6

U40:B
4

U40:A

HLT

U27:A
6

2
1

9
10

10
9

5
4

U28:F
1
2

13
12

2
1
3

I5

74HC173
Output Register

10

I6

OP0
OP1
OP2
OP3

CLK
OE1
OE2
E1
E2
MR

74HC173
Output Register

I7

3
4
5
6

Q0
Q1
Q2
Q3

4
5

Lo

Q0
Q1
Q2
Q3

7
1
2
9
10
15

CLK

U23

D0
D1
D2
D3

14
13
12
11

W4
W5
W6
W7

Lb

Lo

Ea
Su
Eu
Lb
Lo
T1
T2
T3