You are on page 1of 1

Cp Lp Ep Lm Lrm Erm Li Ei La Ea Su Eu Lb Lo HLT NOP

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

U1:A
VCC 1 3 2 CLR VCC ADR23 ADR22 ADR21 ADR20 D7 D6 D5 D4 D3 D2 D1 D0 W7 W6 W5 W4 W3 W2 W1 W0 CLK CLK Rcs Cp Lp Ep Lm Lrm W[0..7] A0 A1 A2 A3 A4 A5 A6 A7 B0[0..7] B1[0..7] A8 A9 A10 A11 A12 A13 A14 A15 B2[0..7] B3[0..7] Erm Li Ei La Ea Eu Lb Lo

SW4
? ? ? ? ? ? ? ? ? PC3 ? PC2 ? PC1 ? PC0 ? ? FLload ? ? I6 I5 I4 I3

Start

Clear/Start

U1:B
Clear 4 6 VCC 5 74HC00 CLR

? ? ? ? ? ? ? ?

W7 W6 W5 W4 W3 W2 W1 W0

? ? ? ?

ADR23 ADR22 ADR21 ADR20

? ? ? ?

D7 D6 D5 D4 D3 D2 D1 D0

U1:C
VCC 10 8 9 VCC OPCode / Data Switches

SW1
OFF

9 10 11 12 13 14 15 16

SW2 SW5 SW3


Write Mem SWEram Single Step Low
OFF

5 6 7 8
ON

Address Switch

ON

U1:D
High 13 11 VCC 12 HLT 74HC00 1 2 13

4 3 2 1

8 7 6 5 4 3 2 1

U3:A
12

U2:A SW7
To Program Manually: Set SW6 up to manual mode. Set SW7 down to program mode. Set SW8 up to manual mode. Set addresses and data using the DIP switches. Toggle SW3 to load the data into RAM. To Program Automatically: Set SW6 up to manual mode. Set SW7 down to program mode. Set SW8 down to automatic mode. If the simulation is not running it can be started and when the loading is complete the FLload flag will equal 1. If the simulation was already started then press SW4 to clear the counters and restart the process. The debug menu can be used to view the contents of RAM. To Execute a Program: Set SW7 and SW8 up to Run mode then set SW6 to Auto. Press clear to reset the Program Counter to zero and re-execute the program. VCC ENprog VCC 1 3 2 10 8 9 12 13 11 CLK

U2:C U2:D

CLK

SW6
VCC OEDIPSWin DIPSWin Up = Run Down = Program Manual/Auto

Manual

U2:B
Auto 4 6 VCC 5 VCC 3 4 5

U3:B
6

VCC

U4:A SW8
autoDATAin Up = Manual Data Entry, Run Down = Automatic Data Entry U4:A(CLK) INIT=LOW START=0 COUNT=-1 CLOCK=10 HLT 74HC107 1 12 4 J CLK R K Q 2 Q 3

13 CLR

Note: The 555 timer circuit has been substituted with a virtual clock source to speed up the simulation.

U6
Ep VCC VCC Erm SELWEram 2 3 5 6 11 10 14 13 1 15 1A 1B 2A 2B 3A 3B 4A 4B A/B E 74HC157 Run/Program Selector 1Y 2Y 3Y 4Y 4 7 9 12 ENpc ENmar OEram WEram VCC CLK2 SWEram autoDATAin VCC VCC 2 3 5 6 11 10 14 13 1 15

U7
1A 1B 2A 2B 3A 3B 4A 4B A/B E 74HC157 Manual/Auto Data Input Selector 1Y 2Y 3Y 4Y 4 7 9 12 autoADRin DIPSWin ROMin SELWEram ADR10 ADR20 ADR11 ADR21 ADR12 ADR22 ADR13 ADR23 autoADRin 2 3 5 6 11 10 14 13 1 15

U8
1A 1B 2A 2B 3A 3B 4A 4B A/B E 74HC157 Address Input Selector 1Y 2Y 3Y 4Y 4 7 9 12 ADR00 ADR01 ADR02 ADR03

U5:A
CLK Lrm 1 3 2 74HC00

ENprog

U9
3 4 5 6 7 10 2 9 1 D0 D1 D2 D3 ENP ENT CLK LOAD MR 74HC161 Auto-Programmer CLR Q0 Q1 Q2 Q3 RCO 14 13 12 11 15 ADR10 ADR11 ADR12 ADR13 12 CLK2 11 D CLK R Q 74HC74 8 ADR10 ADR11 ADR12 ADR13 FLload 8 7 6 5 4 3 2 1 23 22 19 21 18 20

U11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 CE OE/VPP 2732 Program ROM "Auto-Programmer" Instead of manually entering data this subcircuit will load the RAM with the first 16 bytes of the linked "Program ROM.bin" file. D0 D1 D2 D3 D4 D5 D6 D7 9 10 11 13 14 15 16 17 W0 W1 W2 W3 W4 W5 W6 W7

U10:A
Q 5 CLK2

10

U10:B
Q 9

D CLK

CLK2

Q 74HC74

CLR

CLR

U4:B
74HC107 8 U4:B(CLK) INIT=LOW START=0 COUNT=-1 CLOCK=10 9 11 J CLK R K Q 6 CLK2 Q 5 CLK2

13

ROMin

CLR

U12
W4 W5 W6 W7 CLK 14 13 12 11 7 1 2 9 10 15 D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 Instruction Register Q0 Q1 Q2 Q3 3 4 5 6 I3 I4 I5 I6 CLK Ei Li Rcs W0 W1 W2 W3 14 13 12 11 7 1 2 9 10 15

10

U13
D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 Instruction Register Q0 Q1 Q2 Q3 3 4 5 6 W0 W1 W2 W3

Li Rcs

U14
3 4 5 6 VCC VCC CLK Rcs 7 10 2 9 1 D0 D1 D2 D3 ENP ENT CLK LOAD MR 74HC161 Control Sequence Counter Q0 Q1 Q2 Q3 RCO 14 I0 13 I1 12 I2 11 15 I0 10 I1 9 I2 8 7 6 5 4 3 25 24 21 23 2 20 22 27 1

U15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE OE PGM VPP 27C64 Control ROM - High D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 Ei Li Erm Lrm Lm Ep Lp Cp I0 10 I1 9 I2 8 7 6 5 4 3 25 24 21 23 2 20 22 27 1

U16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE OE PGM VPP 27C64 Control ROM - Low D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 NOP HLT Lo Lb Eu Su Ea La

I3 I4 I5 I6

I3 I4 I5 I6

Rcs

U5:B
CLR NOP 4 6 5 74HC00 9 10

U5:C
VCC 8 Rcs

VCC

74HC00

U17
W0 W1 W2 W3 VCC Cp CLK Lp CLR 3 4 5 6 7 10 2 9 1 D0 D1 D2 D3 ENP ENT CLK LOAD MR 74HC161 Program Counter Q0 Q1 Q2 Q3 RCO 14 13 12 11 15 PC0 PC1 PC2 PC3 VCC ENpc 3 4 5 6 1 13

U18
A0 A1 A2 A3 OEA OEB 74HC243 Program Counter B0 B1 B2 B3 11 10 9 8 W0 W1 W2 W3 D0 D1 D2 D3 D4 D5 D6 D7 OEDIPSWin VCC 2 3 4 5 6 7 8 9 19 1

U19
A0 A1 A2 A3 A4 A5 A6 A7 CE AB/BA 74HC245 Data Input 3-State Buffer B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 W0 W1 W2 W3 W4 W5 W6 W7

U21 U20
W0 W1 W2 W3 CLK 14 13 12 11 7 1 2 9 10 15 D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 Memory Address Register Q0 Q1 Q2 Q3 3 4 5 6 ADR00 ADR01 ADR02 ADR03 2 3 5 6 11 10 14 13 1 15 1A 1B 2A 2B 3A 3B 4A 4B A/B E 74HC157 Memory Address Selector 1Y 2Y 3Y 4Y 4 7 9 12 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 27 22

U22
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE WE OE 62256 RAM D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 W0 W1 W2 W3 W4 W5 W6 W7

ENmar

Lm Rcs

WEram OEram

U24
W0 W1 W2 W3 CLK 14 13 12 11 7 1 2 9 10 15 D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 Accumulator (LSB) Q0 Q1 Q2 Q3 3 4 5 6 5 3 14 12 6 2 15 11 7 6 5 9 Q0 Q1 Q2 Q3 3 4 5 6 Su 8 10 12 11 13 Su

U30
A0 A1 A2 A3 B0 B1 B2 B3 C0 74HC283 Full Adder C4 9 Carry S0 S1 S2 S3 4 1 13 10

1 3 2 4

La

U26
W0 W1 W2 W3 CLK 14 13 12 11 7 1 2 9 10 15 D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 B Register (LSB)

U28:D
74HC86

Lb

U23
W0 W1 W2 W3 W4 W5 W6 W7 2 3 4 5 6 7 8 9 19 1 A0 A1 A2 A3 A4 A5 A6 A7 CE AB/BA 74HC245 B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 18 17 16 15 14 13 12 11

U32
B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7 CE AB/BA 74HC245 2 3 4 5 6 7 8 9 19 1 W0 W1 W2 W3 W4 W5 W6 W7

Ea

Eu

U25
W4 W5 W6 W7 CLK 14 13 12 11 7 1 2 9 10 15 D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 Accumulator (MSB) Q0 Q1 Q2 Q3 3 4 5 6 5 3 14 12 6 2 15 11 7 6 5 9 Q0 Q1 Q2 Q3 3 4 5 6 Su 8 10 12 11 13 Carry

U31
A0 A1 A2 A3 B0 B1 B2 B3 C0 74HC283 Full Adder C4 9 S0 S1 S2 S3 4 1 13 10

1 3 2 4

La

U27
W4 W5 W6 W7 CLK 14 13 12 11 7 1 2 9 10 15 D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 B Register (MSB)

U29:D
74HC86

Lb

U33
W4 W5 W6 W7 CLK 14 13 12 11 7 1 2 9 10 15 D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 Output Register Q0 Q1 Q2 Q3 3 4 5 6 OP4 OP5 OP6 OP7 CLK W0 W1 W2 W3 14 13 12 11 7 1 2 9 10 15

U34
D0 D1 D2 D3 CLK OE1 OE2 E1 E2 MR 74HC173 Output Register Q0 Q1 Q2 Q3 3 4 5 6 OP0 OP1 OP2 OP3

Lo CLR

Lo CLR