BASICS OF VLSI LAB

REPORT II

CMOS INVERTER STATIC AND DYNAMIC CHARACTERISTICS

SUBMITTED BY Davis Oommen Abraham(M101233EC) Richu Jose Cyriac(M120128EC) AIM
To study static characteristics of CMOS inverter. To study the robustness of CMOS inverter by varying temperature and supply voltage scaling. To study the dynamic characteristics of CMOS inverter in both pre-layout and post-layout simulations.

TOOLS
CADENCE MICROSOFT EXCEL

A. STATIC CHARACTERISTICS OF CMOS INVERTER

THEORY Important terms: VOH: max output voltage when output is 1 Vin : input voltage to inverter Vout : output voltage of inverter VM : threshold voltage of inverter is defined as the point at which Vin is equal to the Vout VOL: min output voltage when output is 0 VIH : min input voltage which can be interpreted as 1 VIL : max input voltage which can be interpreted as 0

VIH and VIL are the points at which dVout 1

dVin

Threshold voltage (VM) for a non velocity saturated device is given by:

VM
Also,

VTn r (VDD VTp ) 1 r

where

kp kn

eqn(1)

N MH V OH V IH N ML V IL V OL

, where NMH is Noise margin high , where N ML is Noise margin low

eqn(2) eqn(3)

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BASICS OF VLSI LAB Region of operation: The region of operation of the nMOSFET and pMOSFET at various inputs is summarized below. VIN <VT,n VIL VM VIH >VDD + VT,p VOUT VOH Approx. VOH VM Approx.VOL VOL nMOSFET Cut-off Saturation Saturation Linear Linear pMOSFET Linear Linear Saturation Saturation Cut-off

REPORT II

Table1.1 Defining different regions of a CMOS static characteristics

OBSERVATIONS 5 2
Output Voltage(V)

0 0 -5 0.5 1 Vout Derivative Vout Vin=Vout,line Input Voltage(V) 1.5 2

Output Voltage(V)

1.5 1 0.5 0 0

Wp/Wn=1 Wp/Wn=2 Wp/Wn=3 Wp/Wn=4

-10 -15

0.5 1 1.5 Input Voltage(V)

Fig 1.1 Extraction of

V M , V IH , V IL , V OH , V OL

Fig1.2 : VTC of CMOS inverter as a function of PMOS width

INFERENCES Rail to rail voltage swing is seen Gain is maximum at VM Static CMOS inverter can be used as an analog amplifier in transition region owing to its high gain Changing the width ratio shifts the Voltage transfer curve (VTC) Increasing width of PMOS or NMOS moves VM (threshold voltage of inverter) towards VDD or GND Logic levels are not dependent upon relative device sizes ie. CMOS inverter is a ratioless logic

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BASICS OF VLSI LAB

REPORT II

B. EFFECT OF STATIC CHARACTERISTICS WITH RESPECT TO TEMPERATURE

OBSERVATIONS 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 Input Voltage(V)

3 218K 273K 300K 373K 423K 2

Output Voltage(V)

Output Voltage(V)

2.5 2 Vdd=0V Vdd=0.56V Vdd=1.39V Vdd=2.50V 1 Input Voltage(V) 2

1.5 1

0.5 0

-0.5 0

Fig 2.1 VTC of CMOS inverter as a function of Temperature

Fig 2.2 VTC of CMOS inverter as a function of supply voltages

Parameters VOH VIH VOL VIL VM NMH NML

Wp = 1 Wn 1.8 V 822.5mV 0V 501.02 mV 689 mV 977.7 mV 501.02 mV

Wp = 2 Wn 1.8 V 946.5mV 0V 594.8 mV 784.31 mV 853.5 mV 594.8 mV

Wp = 3 Wn 1.8 V 1.01V 0V 667 mV 828.62 mV 790 mV 667 mV

Wp = 4 Wn 1.8 V 1.06V 0V 727 mV 872.4 mV 740 mV 727 mV

Wp = 5.83 Wn 1.8 V 1.09V 0V 757.6 mV 900.8 mV 710 mV 757.6 mV

Table 1.2 Extracted parameters from CMOS inverter characteristcs.

INFERENCES DC characteristic of static CMOS inverter turns out to be rather insensitive to temperature variations. The effect of power supply scaling is observed by varying power supply voltages without varying transistor voltages. Characteristics observed are similar to inverter eventhough the supply voltages is not large enough to turn the transistors on. The subthreshold currents are sufficient to switch the gate between high and low levels and to provide enough gain to produce appreciable VTCs. This factor has to be considered since supply voltage is being scaled with technology.

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BASICS OF VLSI LAB

REPORT II

C. DYNAMIC CHARACTERISTICS AT PRE-LAYOUT AND POST-LAYOUT SIMULATIONS

THEORY The parasitic capacitances extracted according to how layout is designed might be critical in affecting actual performance of the device. The main difference between the pre-layout and post-layout simulation is that the delays in the interconnections are taken into account in the post-layout simulation. The materials can be different types of metal, polysilicon, and they introduce resistance and capacitance in the interconnections between the components and form a RC circuit. As a result, the interconnections require a finite charge up time and a delay is created. Post-layout simulation is important in a VLSI design as it uses a more accurate model to measure the performance of the design. Also it can be used to measure how good of the placement and routing is. If the post-layout simulation has a large difference from the pre-layout one, that means the placement and routing of layout design may not be good enough, and a greater effort should be put in the placement and routing.

DELAY PARAMETERS

PHL

2VT , n 4(VDD VT , n ) Cload ln 1 kn(VDD VT ,n ) VDD VT , n VDD

)]

...eqn(4)

PLH

2 VT , p 4(VDD VT , p ) Cload ln 1 kp (VDD VT , p ) VDD VT , p VDD

)]

eqn(5)

Pavg

PHL

PLH 2

eqn(6)

-time delay between V 50% of falling input voltage and the V 50% of rising output voltage PHL - time delay between V 50 % of rising input voltage and the V 50 % of falling output voltage Cload -Capacitance associated with CMOS
PLH

OBSERVATIONS

2.00E+00 1.50E+00
Voltage(V)

1.00E+00 5.00E-01

Vout (V)

0.00E+00 0.00E+00 5.00E+01 1.00E+02 1.50E+02 -5.00E-01 Time(s)

Fig 3.1: Variation of output from low-high when input goes from high to low

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BASICS OF VLSI LAB

REPORT II

Fig 3.2 Ringing exhibited at high frequency

Parameter

Pre Layout 0.023 ns 0.027 ns 0.025 ns

Post Layout 0.034 ns 0.029ns 0.031 ns

PLH PHL

Pavg

Table 3.1 Delay parameters of CMOS inverter at pre-layout and post-layout simulations.

INFERENCES Delay has been increased in post-layout simulation when compared to pre-layout simulation. A visible hump is present in the pre layout simulation. This could be due to the inductance in the MOSFET which has to be taken into consideration at high frequencies. Since this is a pre-layout where wire and via inductances are not being considered, the presence of inductance points to the fact that MOSFET should be modeled along with an inductor at high frequencies.

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