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10 GHz Two-stage Class A RF Power Amplier in a 0.25 m CMOS Process

Tanya Vanessa F. Abaya and Marc D. Rosales University of the Philippines in Diliman, Philippines

Abstract This report describes the methodology used in designing a CMOS Radio Frequency
(RF) power amplier (PA) operating at 10 GHz. The TSMC 0.25 m CMOS process is used for design, simulation and testing. The PA is a two-stage amplier with both driver and output stages having class-A operation supplied by a singled-ended 2.5 V source. Key specications and corresponding characteristics are presented. Important design considerations include output power, compression point, power added eciency and linearity. The amplier has a 1 dB compression point of 13.18 dBm (output referred) and 1.8 dBm (input referred). For power gain, a 17.2 dB value is achieved. Linearity is quantied by an output referred harmonic IP3 of 26.17 dBm, an intermodulation IP3 of 12.2 dBm and more importantly an IM3 at compression of 31.2 dBc. Lastly, a maximum power added eciency of 8.1% is realized. 1. INTRODUCTION

Devices of a 0.25 m CMOS process are a relatively old technology. However, this technology is cheaper compared to HBTs or shorter channel lengths CMOS and at the same time can be more easily adapted for design in ampliers operating in the low gigahertz range. The power amplier discussed is a two-stage amplier with both stages having class A operation at a 10 GHz resonant frequency. While output power is maximized and linearity is best, the eciency of the class A PA is least among all PA classes. Such design issues and trade-os complicate the design and makes it dicult for the designer to achieve all specications. In the following text, the successes and failures of the PA are described. The discussion will start with an explanation the design process, followed by a brief description of testing. Finally, the results are presented and some conclusions and recommendations are given. An appendix is also included for further reference.
2. DESIGN

The design stage consists of an initial paper design, schematic modeling and modications.
2.1. Paper Design

The basic PA topology shown in Figure 1 is implemented in this design. A single MOS transistor is used and loaded with a RF choke, which acts like an ideal current source. A largevalued blocking capacitor (set at 10 pF) is placed at the output to prevent DC dissipation in the load.
Vdd

RFC Vout Vin M0

Figure 1: Class A power amplier.

The calculations start with determining the optimal load for a given output power. Equation (1) is utilized for this purpose. Because 18 dBm (63 mW) of power must be delivered at the compression point, a maximum output power of 200 mW is assumed. Equation (1) yields an optimum load resistance of 15.625 . This high a power was also set to be able to account for other losses. The optimum load would result to a required DC drain current bias of 160 mA, which should at least be

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the maximum peak RF current. The transistor would then be designed to supply about 320 mA. Rmax =
2 VDD 2Pmax

(1)

To properly set the DC conditions, a current mirror is used as biasing circuit. A constant gate voltage biasing may be done but this would potentially cause thermal drift problems. Here, the output transistor of the current mirror is the amplier transistor M0 (refer to Figure 2). On the other hand, the biasing transistor M1 is sized smaller than the PA transistor to minimize current consumption [1]. A ratio of 100:1 is chosen for the widths. Consequently, the current ratio is the same. The width of M0 is computed from the MOS saturation drain current equation. The transistor lengths are set to the minimum 0.25 m. The width is chosen so that vgs of the mirror transistors would be about 2.5 V for maximum eective voltage [2]. As for the RFC, it should have a large enough inductance to pass through a fairly constant current [1]. Let us assume that a RFC inductance which is ten times larger than the optimum load is large enough. In this case, a value of approximately 2.5 nH will suce. At this point, no eort was made yet to match the optimum load to the required load resistance of 50 . The input matching network was also set aside rst at this stage of the design.
2.2. Schematic Simulation

The circuit schematic diagram is now set up for simulation. The inductors are rst assumed to be ideal. Also, an ideal current source is used. The DC biasing and operation of the transistor is checked. Next, the output vs. input power is plotted to see if the PA has gain and see if it has enough output power. A high enough output power is noted even at input powers greater than 0 dBm in anticipation of a driver stage. An iterative process follows consisting of changing the transistor width and nding the optimum load to achieve a high output power. To obtain the optimum load of the amplier, load-pull measurements were made [3]. The reection curves are also plotted for stability purposes. Impedance matching using the Smith chart is done. After the output matching, verication is done through another set of simulations. For maximum power transfer, input matching is applied. Again, Smith chart matching is done.
2.3. Driver Stage

Because the amplier cannot reach the requirements set for its operation, a driver stage is designed. Again, a class A amplier is designed to be cascaded before the previously designed output stage [4]. As with the output stage, paper design was done rst. An optimal load for an output power of 20 mW is now determined as the rst step of the design. Simulations and tweaking followed hand computations.
Table 1: PA key characteristics. Specication 1 dB compression point (output referred) 1 dB compression point (input referred) Gain Power Added Ecieny Linearity-Harmonic IP3 (output referred) Linearity-IMD IP3 (output referred) Linearity-IM3 at compression Stabilty Supply Inductor Q Number of Stages Obtained Value/Remark 13.18 dBm 1.8 dBm 17.2 dB 8.1% maximum 26.17 dBm 12.2 dBm 31.2 dBc Stable 2.5 (single-ended) 14 (series resistance model) 2

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After a couple of simulations and changes, the input impedance of the two-stage amplier is determined and consequently matched to the 50 -source.
3. TESTING

Useful analyses applied include biasing and power related measurements. S-parameter analysis was also useful for impedance matching. The linearity of the PA was checked by applying a second tone of 10.001 GHz. Also, operation with a 360 conduction angle and stability was ensured [5]. As with any RF circuit, the design and implementation of inductors are problematic. The inductors were modeled and the nal components used have a quality factor of 14. The nal testing (and design) of the two-stage amplier consists of inductors with a Q of 14. Also, the current sources are replaced with resistors. The iterative process described in II is repeated. The characteristics of the PA were degraded and as such needed a large amount of time for redesigning.
4. RESULTS

The nal design of the power amplier is shown in Figure 2. Table 1 presents key characteristics and considerations noted in designing and in the performance of the amplier. The non-ideal inductors (though good) have caused the drop in output power and the consequence being the diculty of bringing the power levels back up by adjusting matching networks and even biasing. The gain within the range of operation is quite high and relatively linear. Low power added eciency is expected due to the nature of class A ampliers, even more so for two series connected PAs of this type. The value obtained is comparable to other works [4]. The linearity of the amplier is quantied by the IP3 measurements for harmonic and intermodulation distortion. Lastly, the power amplier designed is guaranteed to be stable. An appendix is added to this paper to show plots supporting the values in Table 1.
2.5 V

1.7k 7.75k W = 3 um L = 0.25 um 10 pF 1.39 200 fF 6.24 299 fF 2.85 W = 300 um L = 0.25 um 10 nH 45 10 pF W = 3 um L = 0.25 um 0.6 nH 2.7

2.5 nH 11.2

10 pF 1 nH 2.22 4.5 W = 300 um L = 0.25 um

600 fF

Figure 2: Final power amplier design.

Power Output vs. Power Input and 1 dB Compression Point

Power Gain vs. Input Power

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Power Added Efficiency vs. Input Power

PIERS Proceedings, Cambridge, USA, July 26, 2008

360-degrees Conduction Angle (Class A biasing)

Third Order Intercept Point-Harmonic

Third Order Intercept Point-Intermodulation Distortion

Determining IM3 Linearity [6]

Stability (Kf)

Stability (B1f)

5. CONCLUSION

Design of the PA relied heavily on hand computations for biasing and parametric analysis to ensure the optimum values of matching network elements. The PA designed was not able to meet the required output power but has other operation characteristics comparable to other designed two-stage class A ampliers.

Progress In Electromagnetics Research Symposium, Cambridge, USA, July 26, 2008 ACKNOWLEDGMENT

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If this power amplier were to be redesigned, more output power might be set by transforming the 50-ohm resistance to a lower output impedance. Also, a class-AB power amplier should be explored for the same set of specications and performance to achieve higher eciency. APPENDIX This section contains plots supporting the acquired results. A subsection on determining IM3 linearity is also included and discussed. The plots here are from power, DC, transient, linearity and stability measurements. From the two previous plots, a comparison between the output power from the fundamental and the output power from the third IM, which is in this case 9.99 GHz (a second tone of 10.01 GHz is applied), is made. It is noted that at the 1 dB compression point ( 1.2 dBm input referred), the third order linearity is about 13.187 dBm (18 dBm) = 31.2 dBc.
REFERENCES

1. Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Ch. 13, Cambridge University Press, Cambridge, 2001. 2. Filanovsky, I., EE 671 Lecture Notes CMOS Power Ampliers in Wireless Communications Systems, University of Calgary. 3. Razavi, B., RF Microelectronics, Ch. 9, Prentice-Hall, New Jersey, 1998. 4. Aniktar, H., et al., Highly Linear Power Amplier Design, RISC Division, Aalborg University. 5. PA Design Using SpectreRF Application Note, Version 5.0 Cadence, Dec. 2003. 6. http://www.maximic. com/appnotes.cfm/appnote number/2041/