PICNODE board specs

Horcio Fernandes Joo Fortunato Leonardo Pedro Tiago Pereira Micro processor

- dsPIC30F4013 - Fcristal = 7,3728MHZ - max clock: Fcristal * 16 / 4 = 29.4912 MIPS

Interfaces

Some interfaces are pin multiplexed - Optical serial interface (Rx and Tx) - CAN - RS485 (Half Duplex) - RS232 (true RS232 from MAX232 or equivalent) - I2C - SPI - RJ11 (for ICD2, a microchip programmer)
IO

Some IO features are pin multiplexed - up to 8 power pull-down outputs (0.5A per output) - up to 6 analog inputs - up to 31 general purpose digital IO - up to 3 external interrupt sources

Board

- one push button for reset (SW2) - one push button connected to general I/O pin (SW1) - two monitoring led connected to I/O pins
Clock

- 7,3728MHZ cristal for uP clock (0% error in baud rates generation) - 32,768KHz cristal (example applications: 1s real time clock (unix time format) or 1s period timer)
Communication speed

- optical: up to 1,8Mbaud (limited by pic clock) - RS232 port: min 120kbps for HIN232CPZ (depends on RS232 converter) - RS232 standard baud rates: 9600, 19200, 38400, 115200, 460800, 921600 (with appropriate RS232 converter)
Programming

- 1st option: . use microchip ICD2 connected to RJ connector . work with MPLAB IDE . programming jumpers must be in position 1 . programming switch must connect pins 1 and 2 - 2nd option: . use serial straight through cable from PC serial port to picnode board D9 connector . compile your code in MPLAB IDE . use "WinPic - A PIC Programmer for Windows" to program the pic . programming jumpers must be in position 3 . programming switch must connect pins 2 and 3 when programming . programming switch must connect pins 1 and 2 when using the rs232 port
DIN 96 pins outputs

- Avcc: 5v used as reference for pic ADC. Maximum current out of these pins: 100mA - Vcc_unreg: vcc voltage not regulated. Maximum current: 0.9A - Vcc_5: 5v voltage supply to the pic. Maximum current: 0.8A - 5V_pwr: regulated 5v output (7805). Maximum current: 1A - Agnd: ground (0V) used as reference to the pic ADC - GND: general ground - an0, an1, ...: inputs to the several ADC channels - PwrDrv0 to PwrDrv7: power pulldown outputs - canrx and cantx: can output and input directly from the pic - can_h and can_l: differential can line from the can transceiver - rx2 and tx2: uart output and input directly from the pic - sdo: pic output to be used in rs485 - rs485_a and rs485_b: differential rs485 line from the rs485 transceiver - int0, int1 and int2: pic external interrupt pins - rc13 and rc14: pic general purpose IO

R6 1K AN4 O p tio n a l

D3

LED

AN5

R7 1K M CL R C A NR X a vcc 2 VCC_ 5 CANTX RXD U1 C2 9 1 -M C L R C2 2 A N0 / RE F + / N2 / B 0 V C R 3 A N1 / RE F -/ N3 / B 1 V C R 4 A N 2 / S 1 / V D IN / N 4 / B 2 S L C R 5 AN3 / N5 / B3 C R 6 AN4/ N6 / B4 C R an12 34 AN5 / N7 / B5 C R RX1 / DA S 33 R18 9 PG D/ M UD/ N7 / B 7 E A R 10 AN8 / B8 R R2 8 11 VDD ca n r x R24 10K 29 VS S c a n tx 28 O SC1/ L KI C r x2 27 tx 2 26 r x1 / d a s 25 EM UC1 / O S CO / 1 CK/ 1 ARX/ N0 / C1 4 S T U C R tx 1 / c l s 24 IN T 0 / A 1 1 R sd o 23 IC 2 / T 2 / D 9 IN R in t1 22 RD3 20 VS S VDD VCC_ 5 TX2 C28 VCC_ 5 100nF C1 100 nF 1 3 C22 100 nF 100 nF C27 C7 100 nF 4 5 2 6 C1 + C1 C2+ C2V+ VG ND VCC 15 C4 100 nF 16 VCC_5 21 RD2 RD2 RX_M AX 13 8 R 1 IN R 2 IN 11 10 RX2 19 IC 1 / T 1 / D 8 IN R IN T 1 U9 18 E M UC3 / CK1 / F 6 S R S DO 17 E M UD3 / 1 TX / DO 1 / CL / F 3 U S S R TX1/ CL S 100 nF VCC_ 5 RX1 / DA S TX2 14 O S C2/ LKO / C15 C R U2 TX/ N1 8 / F 5 C R U2 RX / N1 7 / F 4 C R RX2 13 C1TX/ F1 R CANTX 12 C1 RX/ F 0 R 30 C A NR X 5 G ND VCC 0R VS S 31 S DO VDD VCC_5 32 TX1/ CL S 4 DI 3 2 DE % % o RE % % o A B 8 R23 4K7 RO 6 7 0R U1 0 1 RD1 R25 4K7 R4 4 120R 8 P G C/ M UC / N6 / C F A / B 6 E A O R E M UD 2 / C 2 / D 1 O R UM UC2 / C1 / D0 O R R22 0R R D0 VCC_ 5 AN12 / B12 R 35 AN1 2 AN1 1 / B11 R 36 AN11 AN10 / B1 0 R 37 AN1 0 A N9 / B 9 R 38 AN9 AVS S 100 nF 39 AVDD 100 nF 40 M CP 2 55 1 R3 0 0R R2 120 VRE F 4 VDD 5 CANL 3 VS S 6 CAN_ L C A NH ca n _ l 7 CAN_ H ca n _ h TXD RS 1 8 R29 0R U2

D4

LED

M CL R*

AN0

an0

AN1

an1

AN2

an2

AN3

an3

AN4

an4 7

A N5

C6

C5

an5

PG C

100 nF

18pF

pgc

PG D

X1

pg d

AN8

RS 4 8 5_ A RS485_B rs3 8 5 _ a r s4 8 5 _ b

VCC_5

7 .3 7 2 8 M H Z

L TC4 8 5 C8

RC1 3 E M U D 1 / O S C I/ 2 C K / 1 A T X / N 1 / C 1 3 S T U C R U 1 R X / D I1 / D A / F 2 S S R

15

16

R1 5

in t0

3 2 ,7 6 8 K H Z

100K

IN T 2

X2

r c1 3

in t2

RD3

r c1 4

C14

C13

12 % % o R 1 O UT % % o 9 % % o R2 O UT% % o

18pF

18pF

T 1 IN T 2 IN

RX_ PC B

Schematic - Core section

14 % % oT1 O UT% % o 7 % % o T 2 O UT % % o

O p tio n a l

C1 2 100 nF R35 R3 6 R3 7 R38 AN8 AN9 AN1 0 AN11 RD0 RD1 RD2 RD3 P w r D r v7 R3 9 R40 R41 R4 2 0R 0R 0R 0R R9 R10 R11 R1 4 0R 0R 0R 0R UL N2 8 0 3 T itle C11 9 G ND CO M P w r D r v7 P w r D r v6 P w r D r v6 P w r D r v5 P w r D r v5 P w r D r v4 P w r D r v4 P w r D r v3 P w r D r v3 P w r D r v2 P w r D r v2 P w r D r v1 P w r D r v1 P w r D r v0 P w r D r v0 0R AN8 AN9 AN1 0 AN11 RD0 RD1 RD2 RD3 0R 0R 0R R31 R3 2 R3 3 R34 0R 0R 0R 0R 1 2 3 4 5 6 7 8 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 O UT1 O UT2 O UT3 O UT 4 O UT5 O UT6 O UT7 O UT 8 10 18 17 16 15 14 13 12 11 P w r D r v0 P w r D r v1 P w r D r v2 P w r D r v3 P w r D r v4 P w r D r v5 P w r D r v6 P w r D r v7 U4 VCC_ 5 C3 100 nF

M AX232A

VCC_ 5

R13

10K

VCC_ 5

M CL R*

IN T 0

R20

R8

R4

10K

1K

1K

S W1

SW2

C25

1 0 0 NF

d s p ic n o d e b o a r d - co r e

S iz e 100 nF VC C _ UNR E G D a te : 4 3 2 B

D o cu m e n t N u m b e r < D o c>

Rev 1

M o n d a y, M a r ch 0 3 , 2 0 0 8

S heet 1

of

TP8 J2 6 B AG ND J2 6 C

J2 6 A

AVCC B2 B3 B4 B5 B6 B7 B8 B9 B10 B1 1 B1 2 B1 3 B1 4 B15 B16 B1 7 B1 8 G ND C1 8 G ND ca n r x TP5 C1 7 TP10 P w r D r v7 C16 P wr D r v6 C15 P w r D r v5 VCC_5 C1 4 P wr D r v4 C1 3 P w r D r v3 C1 2 P w r D r v2 C1 1 P w r D r v1 C10 P w r D r v0 C9 C8 an5 C7 AN5 an4 C6 AN4 an3 C5 AN3 a n2 C4 AN2 an1 C3 AN1 an0 C2 A N0 an12

A1

AVCC

TP1 B1 C1 AN1 2

A2

A3

A4

A5

AVCC

A6

C2 6

A7

10 0 nF

A8

A9

A10

VCC_ UNR E G

A1 1

TP7

A1 2

A1 3

A1 4

V _ Un re g

A15

A16

A1 7

A1 8

A1 9 B20 B21 B22 B23 C23 tx2 C22 r x2 4K7 4K7 C21 ca n _ l tx1 / cl s R50 R51 C20 ca n _ h

VCC_5 B1 9 C1 9

TP6

c a n tx

r x1 / d a s

A20

A21

A22

A23

VCC

A24 B2 5 B2 6 B2 7 B28 B29 B30 B3 1 B3 2 r c1 4 C3 2 r c1 3 C3 1 in t2 C30 in t0 C29 in t1 J3 1 C28 rs3 8 5 _ a C2 7 rs4 8 5 _ b U s e o n ly w ith I2 C p r o to c o l C2 6 C2 5

B24

C24

sd o

A2 5

A2 6

A2 7

5V_PWR

A28

TP2

C J3 0 HEADER 3 HEADER 3

A29

A30

A3 1

A3 2

5V_PWR

D IN 9 6 _ A B C - R

D IN 9 6 _ A B C - R

D IN 9 6 _ A B C - R

2
PG D

PG C

P G D _ s e r ia l

P G C _ s e r ia l

TP9 TP3 PG C J2 9 VCC_ 5 1 2 VCC_5 PG D PG C HEADER 3 3 PG D TP4 C23 220 pF RX_M AX TX_ PC M CL R* B C24 220 pF

M CL R

J2 8

M CLR*

M CL R

R4 6

33 0R

R47 R4 3 100 nF 1 80

3 30R

C21

Schematic - Input/output section

HE ADE R 6

P1

U7 1 4 5 8 NC HF B R -1 4 1 2 R X 1 /S D A U11 BS17 0/ O T TX1/ CL S R4 5 0R 1 2 CATHO DE NC 3 ANO DE NC 7 ANO DE NC 6 ANO DE 2 RX_PC P G C _ s e r ia l TX_PC P G D _ s e r ia l 2 33 0R 2 330 R R49 R4 8 1 1

1 6 2 7 3 8 4 9 5

VCC_5

R21

560 R

R1 9

56 0R

CO NNE C TO R DB 9

U1 2 BS1 70/ O T A

U8

VCC

O UT

G ND

NC

C6 2

G ND

NC

10 0 nF

NC

NC

HF B R -2 4 1 2 T itle d s p icn o d e b o a r d - in p u t/ u tp u t o

S iz e B

D o cu m e n t N u m b e r < D o c>

Rev 1

D a te : 4 3 2

M o n d a y, M a r c h 0 3 , 2 0 0 8

S heet 1

of

VC C_ UNR E G VR1 LM 78 05 C/ O 22 0 T 1 IN vcc_ 5 O UT 3

VCC_ 5

VC C_ UNR E G

J2 7

R C A JA C K

D1 L 2

D1 N4 0 0 1 10 0 NF

1 0 0 UF

G ND

D C9 C1 0 1K C HO K E R5

v c c_ u n r e g

D2 LED

VC C _ UNR E G 5V_ PWR VC C _ UNR E G VR2 R1 6 LM 7 80 5C/ O 22 0 T 1 IN 5 v_ p w r 1R O UT 3 C

AVCC

R1 7

VR4

10 R

L M 7 8L 05 C/ O 9 2 T

IN

O UT

a vc c

G ND

1 0 UF

1 0 0 NF

2 2 0 0 UF

4 7 0 UF

G ND

C1 8 + 1 0 0 NF +

C1 9

C2 0

C1 6

C1 7

AG ND

Schematic - Power section

T itle d s p ic n o d e b o a r d - p o w e r

S iz e B

D o cu m e n t N u m b e r < D o c>

Rev 1

D a te : 4 3 2

M o n d a y, M a r ch 0 3 , 2 0 0 8

S heet 1

of

PCB layout - Top layer

121

122

6 1 R 48

9 5 6

J28 1 R 46 R 47

RX

TX

C 12 U9

C4

MCLR
J29

D4

D3

D2

PGD
+V
R7 R6 R5 1 J 27

PGC

G ND
SW2 S W1 C 25 R4

GND

V CC

C9 D1 1 J31 3 3 Q1 1 X2 J30

R 20
D

X1

D
R 50 R 51 U1

VR1

Q2
S

E U R ATOM / T IS C F N-IS T ds PicN ode v1.2 Outubro 2007

C 20

C 10

6.299

C 28

C 18

R 29

R 30

VR4

R 17

R 16 U2

C 16 L2

R 22

R 18

R2

C2 U 10

R 24

R 28

U4

VR2

GND_PWR

C 32 B 32 A 32

0.098 C AR D GUIDES 0.218 3.500 3.937

R 25

5V _PWR

C8

A GND

A V CC V _UNREG

J 26 C1 B1 A1

0.109

C1

C3

C 24

R 45

PCB layout - Bottom layer

C 62 C 13 R 15 C 14

R 23

C 17

3.500
C6 R 14 C5 R 11 R 10 R9 R 34 R 33 R 32 C 19 R 31

0.218
R 19 R 43 C 21 R 13

R 42

R 41

R 40

R 39

R 38

R 37

R 36

R 35

C 26

6.050

3.937
C 11
C 22 C 27

C 23

R8

C7 R 49