Let us analyse a simple Tristate inverter & a dynamic D latch and see how they respond for the

various inputs and under various circumstances.

Tristate inverter :

As we know the output just gets inverted if ENABLE =1 and if ENABLE=0 both the P & N paths are cut-off and the output is not defined.As we know ,this is called as floating node or high impedance node (dont care (x) is something that comes when we drive 2 different logic levels say a 1V and 0V into 1 node and it is difficult to say whether it is 1 or 0 logic in that node because the effective voltage level depends on the pmos & nmos sizing of the gates driving the common node).Coming back to the high Z, the o/p is not defined in logic sense but in analog sense there has to be some voltage in that right ? Let us take 3 scenarios and analyse what the voltages will be under those

1)When the above circuit is given Enable=0 and the nodes are settled well. Now this circuit will be equal to something like this

So the o/p will be vdd/2 . I just said as 1G to indicate that the resistances will be high for both P & N network but they will vary with temperature etc. The resistance can be calculated as Vdd/(2*I_leakage). In the skewed process corners (snfp and fnsp) you will see different voltages.

2)When Enable=0 and data is toggling Here still the o/p will be vdd/2 but there will be noise because of parasitic capacitances(Cgd) through top & bottom most transistors

3) When you have x-talk (cross talk) this is pretty much common in data transmission.

All chips will have clock and other data toggling at some frequency and if they are laid out closer to the tristate inverter then the layout parasitics (caused by metal interconnects) like fringe capacitance and coupling capacitance between adjacent metal lines can induce noise onto the floating node.

This effect you wont see in schematic simulations,you will see this a lot in post extracted sims.

For these reasons only we shouldnt leave any nodes floating as they are not defined properly. Also in IOs if you tristate the transmitter (no pullup or pulldown will be asserted) and then only the IO will act as receiver because then only the far end Tx can drive data into this Rx.Also in memories and some other circuits the bus will have this tristate option basically this allows the bus to be addressed by only one TX at a time,if all TX are ON then the data is not defined,here all but 1 TX are tristated and the active TX addresses the bus.

Next we see the dynamic D latch which is nothing but a tristate inverter,here the enable is controlled by clock.When clock is high the data gets latch(inverted data) and when clock is 0 the output will hold the data (for a short time only.even the tristate inverter holds the data for short time but that is not a storage circuit so we say as high Z and this is a memory element ).Even here all those above effects are seen but it is made sure that the noise spikes are less (<10% of vdd) and the data doesnt get affected.This latch is used only for high frequency as the cap discharges and data will be lost if u clock it at low frequency. When modeling this in vams you have to see it as D latch and not as tristate inverter.all depends on the functionality/place of the circuit.