Feedback amplifier >>:h parameter model representation h12:feed forward control variables v2 and i1 neglect h12 reason low

value feedback def >>:feedback to the amplifier 4 amplifier types H is the feedbackterm mixed to the input add $ sub H signal feedback -ve xi-Xf >>:overall gain Xo/Xi=G two formulas 1/2 G forward transfer parameter H is the feedback network at X0 sampling mechanism Xi mixing mechanism 4 types of feedback arragements come from these mixing mechanisms -VE FDBK gain reduces (disadvantage)gain for h<g or h>g conditions? |GH|<1 GH|>1 GAIN -VE regenerative square waves triggers GH|=1 oscillators to test + or feedback remove i/p sgl grd this terminal remove the loop at some point and apply some test segnal at one end and follow the path to the other end ratio of the otput to input sgl for one loop + to - ==> negative feedback loopgain is GH for -ve feedback formula loopgain is -GH for +e feedback formula amplifier is not bilateral observe the feedback path 1+GH = 1+loopgain

>>:Adventages +fdbk 1/(1-GH) gh<1==>

+fb>-fb -vefdbk 1)oveall voltage gain G/(1+GH) assumee G>>1,,GH>>1 ~=1/H Design H(resistor and capacitors) <1 H=Xf/Xo(can be contorlled ) ratio of r similar values indepandent of variance in forward transfer parameter G G=gm * Rc common source amplifier gm * Rd 2k(vgs-vt) H=Xf/Xo(can be contorlled ) ratio of r similar values Desensitivity of G Sensitivity(S) formula 1/GH dif amp with very high Fd transfer parameter is OP

AEC Design of currern source NC14007 with mosfet current sink LM3046with BJT,

SCD Frequency respose of CE Amplifier

4. COMMON EMITTER AMPLIFIER AIM: To find the voltage gain of a CE amplifier and to find its frequency response APPARATUS : Transistor BC107 Resistors Capacitors CRO Signal generator CIRCUIT DIAGRAM: THEORY : The CE amplifier is a small signal amplifier. This small signal amplifier accepts low voltage ac inputs and produces amplified outputs. A single stage BJT circuit may be employed as a small signal amplifier; has two cascaded stages give much more amplification. Designing for a particular voltage gain requires the use of a ac negative feedback to stabilize the gain. For good bias stability, the emitter resistor voltage drop should be much larger than the base -emitter voltage. And Re resistor will provide the required negative feedback to the circuit. C E is provided to provide necessary gain to the circuit. All bypass capacitors should be selected to have the smallest possible capacitance value, both to minimize the physical size of the circuit for economy. The coupling capacitors should have a negligible effect on the frequency response of the circuit.

PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Give l00Hz signal and 20mv p-p as Vs from the signal generator 3. Observe the output on CRO and note down the output voltage. 4. Keeping input voltage constant and by varying the frequency in steps 100Hz-1MHz, note down the corresponding output voltages. 5)Calculate gain in dB and plot the frequency response on semi log sheet

TABULAR FORM: Input voltage (Vi)= .NO FREQUENCY OUTPUT VOLTAGE(Vo) GAIN Av=Vo/Vi GAIN IN dB 20 log gain MODEL GRAPH: Precautions: 01. Wires should be checked for good continuity. 02. Transistor terminals must be identified and connected carefully. Result: