FUZZY LOGIC BASED EMBEDDED POWER MANAGER A PROJECT REPORT Submitted by S. ARUN KUMAR (41501106014) G. MAGESH (41501106054) R.

GOPALSAMY SIDDHARTH (41501106034) N. KARTHIEKEYAN (41501106040)

in partial fulfillment for the award of the degree of BACHELOR OF ENGINEERING in ELECTRONICS AND COMMUNICATION ENGINEERING

S.R.M. ENGINEERING COLLEGE, KATTANKULATHUR-603 203, KANCHEEPURAM DISTRICT.

ANNA UNIVERSITY : CHENNAI - 600 025 MAY 2005

BONAFIDE CERTIFICATE

Certified that this project report "FUZZY LOGIC BASED EMBEDDED POWER MANAGER" is the bonafide work of "S.ARUN KUMAR (41501106014), G.MAGESH(41501106054) R.GOPALSAMYSIDDHARTH(41501106034),

N.KARTHIEKEYAN (41501106040)" who carried out the project work under my supervision.

Prof. Dr. S. JAYASHRI HEAD OF THE DEPARTMENT ELECTRONICS AND COMMUNICATON ENGG. S.R.M.Engineering College Kattankulathur - 603 203 Kancheepuram District

Mr. DIWAKAR R MARUR SUPERVISOR Lecturer ELECTRONICS AND COMMUNICATON ENGG. S.R.M.Engineering College Kattankulathur - 603 203 Kancheepuram District

CHAPTER 1 1. Introduction 1.1 Energy Scenario present situation in India The socio & economic development of a country owes a lot to the development of energy resources of that country. Power development in India started at the end of 19th century with an installed power generation capacity of 1400MW which has now risen to a mammoth 1,07,972.8 MW at end of 2003, which is bound to increase in the coming years. The electric power industry in India is both a supplier and consumer of primary energy, depending on the kind of energy used to turn the generators. The various energy sources present in our country from which power is generated have been declining over a period of time causing an effective shortage of the power generated and supplied. The potential of our country to make use of these resources are always high, but due to technical and other social limitations the power generated is always low.india has a gross wind power potential of about 45,000 MW, out of which 13,000MW of power is effectively generated. Moreover the hydroelectric facilities have to be co-ordinate with other sources of electricity because of seasonal and annual variations in rainfall affect the amount of water needed to turn the generators and consequently the amount of electricity that can be produced. Similar limitations of this kind are also widely present in other energy sources like thermal and nuclear etc. the face of this growing demand, Indias electricity sector faces problems of capacity a, poor reliability and frequent blackouts. Since the public utilities developed for power generation cannot always be dependent on, due to various limitations.

Hence the effective power generation is low and there is always shortage resulting in very low per capita power consumption in the country. In this process many industrial enterprises have developed their own power generation system to remain self-sufficient. 1.2 Solution to Power management crises 1. Identification of more resources both renewable and non-renewable energy sources 2. Employ cost cutting measures likes an effective reduction in the power utilized. The above are the possible solutions for the effective utilization of power .we here choose the second option of employing cost cutting measures for optimal utilization of power. We make use of the Microcontroller to improve the effective power, utilized by them.

1.3 Power Management By Microcontrollers High-speed Microcontroller are widely used in portable equipment. With the proper use of a power management mode, the designer can optimize the life of batteries used in todays new system. This application not looks at ways to reduce power consumption by choosing efficient clock source & clock sped the use of stop mode, idle mode &burst mode. Since Prevention is better than Cure, the above solution stands to be a better one when compared to identification of more resources. This project of Fuzzy Logic Based Embedded Power Manager makes use of the basic principles of the Fuzzy Logic and the associated membership functions. Unlike the Boolean Algebra where there are only two states with no variations to be shown in the different conditions of theON state. The Fuzzy Logic principles

allow a range of conditions to be implemented between the different values of the ON state. This allows a greater user control over the available devices in terms of their better power management. This technique helps us to make use of the available power optimally, without too many hardware changes involved in the design of the product.

CHAPTER 2 2. Realization Basic Block Diagram

MICROCONTROLLER I O P O R T I O P O R T RELAY

IR SENSOR (2)

Arithmetic & Logic Unit, EEPROM, SRAM Timer

RELAY

Keypad

2.1Operating Principle This Project titled The Fuzzy Logic Based Embedded Power Manager makes use of the fundamentals of Fuzzy Logic and the power management capabilities of the ATMEGA 16L Microcontroller for the optimal utilization of the available resources.

Let us consider a room consisting of 2 bulbs, a fan, and an Air Conditioner for which the project is to be implemented. A pair of InfraRed Transmitter and Receiver is used at the entrance of the room. The Power supply circuit provides the necessary 5V and 12V supply to the Microcontroller and Relay respectively. Whenever a person enters the room the IR signal between the Tx and the Rx is cut resulting in the activation of any one of the appliances connected to the Microcontroller kit. With the increase in the no of persons entering the room more such devices are switched ON. The Pulse Width Modulation (PWM) technique is used to vary the speed of the fan (D.C motor) depending on the no of people present and the condition given. In this case the following happens 1st Light is switched ON with the entry of 1 person. The Fan is switched ON and operates at Lowest speed with the entry of 3 persons. The Fan then operates in the Medium and Highest speeds with the entry of 4 and 5 persons respectively. The 2nd Light is switched on with the entry of 6 persons.

Finally the Air Conditioner gets switched ON with the entry of 7 persons. Finally when the people exit out of the room the appliances are switched OFF one after the other till the room becomes empty. In this way the appliances are controlled and are switched ON depending on the no of people and the given conditions, thus making an optimal utilization of the power and the available energy resources. 2.2 Program Algorithm The algorithm for this project is listed as follows, 1. Include the Library files and declare the required no of variables

2.

Initialize the I/O ports along with the initialization for PWM.

After completing the above two steps the program logic is split into five different modules for an effective operation of the device. Module 1-Switch Design a) Clear the count and design a switching operation for the Infra Red sensors by clearing the bit of the corresponding to which it is connected. b) Creating appropriate loops does this and by making use of the instruction Set Bit Immediately SBI and Clear Bit Immediately CBI.

Module 2 Detection of Entry 1. 2. Every time a person enters the room, the IR sensor detects it and the details about this entry are written into the EEPROM. These details are always written into the Control Register after activating/enabling the Master Read Write Enable and the Write Enable option. 3. Making use of the instruction OUT and only after selecting the particular address into which it is written does this. Module 3- Activation of Output Devices 1. 2. Every time a new person comes in the EEPROM content is incremented. The external devices connected to the Output port now are activated switched on one after the other depending on the

number of people who have entered the room or according to the given condition. 3. Activating the Output Control Register OCR2 of the ATMEGA 16L Controller brings about the variations in the speed of the Motor. Thus enabling the Pulse Width Modulation technique.

Module 4 Activation of Trainer Option 1. The Microcontroller can be trained to operate for a given condition by activating the trainer button present in its Keypad. 2. Declaring a new variable and moving the details on the number of people does this for which the kit has to be trained into it (new variable), which is finally written into the EEPROM. Module 5- Detection of Exit 1. Every time a person exits the room, the IR sensor detects it and the details about this exit are written into the same address of the EEPROM. 2. These details are first read from the EEPROM and then the no of persons exiting is decremented and accordingly the output devices connected to the Kit are switched off, with the final value written into the EEPROM. 3. In this case both the IN and OUT instructions are used.

This completes the algorithm for the operation of the Microcontroller along with the external devices connected to it.

2.3 Individual Component Details 2.3.1Power supply circuit In this power supply circuit we have to create a +5V DC which is given to the micro controller. The below components are used to create the power supply

230V AC
Description

Step down

Bridge rectifie
Fig 1.a BlockDiagram

Filter

Regulat

230V AC supply is given to the step down transformer. It may be a 230V to 9V or 12V step down transformer. The output of the step down transformer is given to bridge rectifier. The bridge rectifier is formed with 1N4007 diodes. The bridge rectifier converts the AC Voltage into DC Voltage. But the output DC Voltage contains one AC component (ripples). So we have to use a capacitor-2200uF/25V as a filter for removing ripples. That output DC Voltage is given to the positive voltage regulator 7805. The output will be the regulated +5V DC.

F ig 1.b Circ uit diagr am

2.4 General description about microcontroller(Atmega 16L) Microcontroller ATMEGA 16L Reset circuit

Power supply

Microcontroller

Crystal oscillator
Fig 2.a Block Diagram Power supply, reset circuit and crystal (optional) are needed for activate the microcontroller 1. 2. Power supply of the microcontroller is +5V DC. It can be taken from the power supply circuit. Generally for every microcontroller has a reset pin. It may be active low or active high. Here our microcontroller is having active low reset pin. That means whenever the reset pin goes to low, the microcontroller resets. The meaning of reset is control of microcontroller is going to the starting address of the program memory. In this microcontroller the 1st pin is the RESET pin 3. The crystal oscillator circuit is used for the speed of microcontroller. Some microcontrollers are having inbuilt oscillator. So for that microcontrollers, we neednt use the crystal circuit. Here we are using 1MHz inbuilt oscillator. 2.4.1 Microcontroller Configuration(ATMEGA 16L) The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega16 provides the following features

16K bytes of In-System Programmable Flash Program memory with ReadWhile-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmels high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed insystem through an SPI serial interface, by a conventional nonvolatile memory

programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.4.2 In-System Reprogrammable Flash Program Memory The ATmega16 contains 16K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16 Program Counter (PC) is 13 bits wide, thus addressing the 8K program memory locations. 2.4.3 EEPROM Memory The ATmega16 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. 2.4.4 I/O Ports

Fig 2.b Circuit Diagram All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground. 2.4.5 External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the specification for the MCU Control Register MCUCR and MCU Control and Status Register MCUCSR. When the external interrupt is enabled and is configured as

level triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge inter-rupts on INT0 and INT1 requires the presence of an I/O clock. Low level interrupts on INT0/INT1 and the edge interrupt on INT2 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V and 25C. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt. 2.5 Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the applications requirements. To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Powerdown, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

2.5.1 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk CPU and clk FLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wakeup from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 2.5.2 ADC Noise Reduction Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk I/O , clk CPU , and clk-FLASH while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface Address Match Interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an External level interrupt on INT0 or INT1, or an external interrupt on INT2 can wake up the MCU from ADC Noise Reduction mode.

2.5.3 Power-down Mode: When the SM2.0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the External Oscillator is stopped, while the External interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, an External level interrupt on INT0 or INT1, or an External interrupt on INT2 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The same CKSEL Fuses that define the reset time-out period define the wake-up period. 2.5.4 Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Over-flow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in SREG is set. If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in theAsynchronous Timer should be considered undefined after wake-up in

Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk ASY , allowing operation only of asynchronous modules, including Timer/Counter2 if clocked asynchronously. 2.5.5 Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 2.5.6 Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 2.6 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible and the sleep mode should be selected so that as few as possible of the devices functions is operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 2.6.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. 2.6.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-erence will be enabled, independent of sleep mode. 2.6.3 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. 2.6.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brownout Detector, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. 2.6.5 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. 2.6.6 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the both the I/O clock (clk I/O ) and the ADC clock (clk ADC ) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC /2, the input buffer will use excessive power. 2.7 JTAG Interface and On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: Disable OCDEN Fuse. Disable JTAGEN Fuse. Write one to the JTD bit in MCUCSR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. 2.8 Pulse Width Modulation ( PWM) The main purpose of this PWM concept is to change the speed of any Motor connected as a peripheral to its output port . This enables user to control the ouput device more effectively according to the demands.

The main features of the Timer/Counter and the PWM options provided by the microcontroller are given as follows : Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Allows clocking from External 32 kHz Watch Crystal Independent of the I/O clock 2.8.1 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). 2.8.2 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.

2.8.3 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of when OCR2 is set to zero (0x00). The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 2.8.4 Fast PWM Mode

The

fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3)

provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the compare match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dualslope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 58. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to 3 . The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the compare match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM).

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits). A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform generated will have a maximum frequency of when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode . 2.9Infrared sensor circuit

Fig 3.a Block Diagram

Here we are using ir led as an ir transmitter, which emits Ir rays in the wavelength of 940nm. ir receiver is the phototransistor, which detects Ir rays and the

output comes in collector. If the receiver is receiving Ir rays the output will be low otherwise the output will be high. The output of the receiver is given to the comparator chip LM393, which compares the receiver output with the prefixed voltage signal. In comparator there are two terminals. One is inverting terminal (-) and the other one is non-inverting terminal (+). Conditions for comparator If + > - the output will be high If + < - the output will be low The output of the comparator is given to the Microcontroller.

Fig 3.b Circuit Diagram

2.9.1 Relay circuit

Fig 4 Circuit Diagram Relay circuit is used to activate the relay through microcontroller. In this circuit we have to use a Darlington transistor (Tip122) for switch on the relay. The relay is an electromagnetic device which energies when the supply is given. In this circuit, relay is working in the positive logic. That means when the microcontroller gives high to the relay circuit the Darlington transistor is switched on and also the relay is ON. When the microcontroller gives low to the relay circuit Darlington transistor is switched off and also the relay is OFF. The two diodes are used for protecting the microcontroller from the load due to back EMF and EMI problems. 2.9.2 Darlington Transistor This circuit is used where the large input impedances are required. The 2 transistors present in it form a composite pair, the input resistance of the second transistor constituting the emitter load for the first .It has a high input resistance and a voltage gain less close to unity than does a single-state emitter follower. The output impedance of the Darlington circuit may be greater or smaller than that of a single transistor emitter follower depending on the value of its resistance. The composite transistor pair can be used as a common -emitter amplifier. The advantage of this pair would be a very high overall hfe, nominally equal to the product of the CE shortcircuit current gains of the two transistors. 2.9.3 D.C MOTOR

The principle of operation of a dc motor can be stated in a single statement as When a current carrying conductor is placed in a magnetic field; it experiences a mechanical force. In a practical dc motor same as that we use here, field winding produces a required magnetic field while armature conductors play a role of current carrying conductors and hence armature conductors experience a force. As conductors are placed in the slots, which are on the periphery, the individual force experienced by the conductors acts as a twisting or turning force on the armature, which is, called a torque. The torque is the product of the force and radius at which this force acts.So overall armature experiences a torque and starts rotating.This is the working of a dc motor.

2.9.4 Measuring Temperature with Thermistors Thermistors are thermally sensitive resistors used in a variety of applications, including temperature measurement. This application note discusses this application of thermistors, including basic theory and how to interface thermistors to modern data acquisition systems. 2.9.4.1Thermistor Overview A thermistor is a piece of semiconductor made from metal oxides, pressed into a small bead, disk, wafer, or other shape, sintered at high temperatures, and finally coated with epoxy or glass. The resulting device exhibits an electrical resistance that varies with temperature. There are two types of thermistors negative temperature coefficient (NTC) thermistors, whose resistance decreases with increasing temperature, and positive temperature coefficient (PTC) thermistors, whose resistance increases with increasing temperature. NTC thermistors are much more commonly used than PTC thermistors, especially for temperature measurement applications.

A main advantage of thermistors for temperature measurement is their extremely high sensitivity. For example, a 2252 W thermistor has a sensitivity of -100 /C at room temperature. Higher resistance thermistors exhibit temperature coefficients of -10 K/C or more. In comparison, 100 W platinum RTD has sensitivity of only 0.4 /C. The physically small size of the thermistor bead also yields a very fast response to temperature changes. Another advantage of the thermistor is its relatively high resistance. Thermistors are available with base resistances (at 25 C) ranging from hundreds to millions of ohms. This high resistance diminishes the effect of inherent resistances in the lead wires, which can cause significant errors with low resistance devices such as RTDs. For example, while RTD measurements typically require 3-wire or 4-wire connections to reduce errors caused by lead wire resistances, 2-wire connections to thermistors are usually adequate. The major tradeoff for the high resistance and sensitivity of the thermistor is its highly nonlinear output and relatively limited operating range. Depending on the type of thermistors, upper ranges are typically limited to around 300 C. Figure 1 shows the resistance-temperature curve for a 2252 W thermistor. The curve of a 100RTD is also shown for comparison. The thermistor has been used primarily for high-resolution measurements over limited temperature ranges. The classic example of this type of application is medical thermometry. However, continuing improvements in thermistor stability, accuracy, and interchangeability have prompted increased usage of thermistors in all types of industries. 2.9.4.2 Resistance/Temperature Characteristic of Thermistors The resistance-temperature behavior of thermistors is highly dependent upon the manufacturing process. Therefore, thermistor manufacturers have not standardized thermistor curves to the extent that thermocouple or RTD curves have been standardized. Typically, thermistor manufacturers supply the resistance-versustemperature curves or tables for their particular devices. 2.9.4.3 Thermistor Measurement Circuits

Because the thermistor is a resistive device, you must pass a current through the thermistor to produce a voltage that can be sensed by a data acquisition system. The high resistance and high sensitivity of the thermistor simplify the necessary measurement circuitry and signal conditioning.Special 3-wire ,4 wire ,or the Wheatstone bridge connections are not necessary . The most common technique is to use a constant current source and measure the voltage developed across thermistor . CHAPTER 3 3. Principles Of Fuzzy Logic The basic principle that is used for the efficient operation of this power manager is Fuzzy logic .Given below are a few concepts which form a pre-requisite for an effective study about the device and its operational characteristics. Logic started as the study of language in arguments and persuasion, and it may be used to judge the correctness of a chain of reasoning, in a mathematical proof for example. In two-valued logic a proposition is either true or false, but not both. The truth or falsity which is assigned to a statement is its truth-value. In fuzzy logic a proposition may be true or false or have an intermediate truth-value, such as may be true . The sentence the level is high is an example of such a proposition in a fuzzy controller. It may be convenient to restrict the possible truth values to a discrete domain, say (0,0.5,1) for false ,may be true, and true ; in that case we are dealing with multi-valued logic. In practice a finer subdivision of the unit interval may be more appropriate. 3.1 Fuzzy sets Fuzzy sets are a further development of the mathematical concept of a set. Sets were first studied formally by the German mathematician Georg Cantor (1845-1918).

His theory of sets met much resistance during his lifetime, but nowadays most mathematicians believe it is possible to express most, if not all, of mathematics in the language of set theory. Many researchers are looking at the consequences of fuzzifying set theory, and much mathematical literature is the result. For control engineers, fuzzy logic and fuzzy relations are the most important in order to understand how fuzzy rules work. 3.2 Conventional sets A set is any collection of objects which can be treated as a whole. Cantor described a set by its members, such that an item from a given universe is either a member or not. The terms set,collection and class are synonyms, just as the terms item ,element and member. Almost anything called a set in ordinary conversation is an acceptable set in the mathematical sense. A set can be specified by its members, they characterize a set completely. The list of members A= {0,1,2,3} specifies a finite set. Nobody can list all elements of an infinite set, we must instead state some property which characterizes the elements in the set, for instance the predicate x>10. That set is defined by the elements of the universe of discourse which make the predicate true. So there are two ways to describe a set: explicitly in a list or implicitly with a predicate. 3.3 Universe Elements of a fuzzy set are taken from a universe of discourse, or universe for short. The universe contains all elements that can come into consideration. An application of the universe is to suppress faulty measurement data. In case we are dealing with a non-numerical quantity, for instance taste, which cannot be measured against a numerical scale, we cannot use a numerical universe. The elements are then said to be taken from a psychological continuum. 3.4 Membership functions

Every element in the universe of discourse is a member of the fuzzy set to some grade, maybe even zero. The set of elements that have a non-zero membership is called the support of the fuzzy set. The function that ties a number to each element x of the universe is called the membership function (x). 3.5 Continuous and Discrete Representations There are two alternative ways to represent a membership function in a computer: continuous or discrete. In the continuous form the membership function is a mathematical function, possibly a program. A membership function is for example bell-shaped , s-shaped (called an s-curve ), a reverse s-curve (called z-curve ), triangular, or trapezoidal. In the discrete form the membership function and the universe are discrete points in a list (vector). Sometimes it can be more convenient with a sampled (discrete) representation. As a very crude rule of thumb, the continuous form is more CPU intensive, but less Storage demanding than the discrete form. 3.6 Normalization A fuzzy set is normalized if its largest membership value equals 1. You normalize by dividing each membership value by the largest membership in the set, a/max(a) . CHAPTER 4 4 Testing & Observation Results We executed this project The Fuzzy Logic Based Embedded Power Manager in our college computer lab. The layout of the Lab is given below.

a) Observation Table without Microcontroller: Electrical Appliances Connected 4 Tubes , 2 Fan ,2 Air Conditioners b) Observation Table with Microcontroller: Electrical Power Consumption Tariff Power Consumption (in units) 70 Tariff (in Rs) 560

Appliances Connected 4 Tubes , Conditioners The thermistor 2 Fan ,2 Air

(in units) 56

(in Rs) 448

effectively senses the atmospheric temperature and

accordingly activates the different characteristics of the Air Conditioner. After looking at the above 2 tables we find that, the power consumption is reduced by 25-30 % from the original value. This clearly shows the effectiveness and the efficiency of our project .The practical nature of this device assimilated from the above data clearly indicates that this project can be widely employed in large shopping complexes, industrial units etc., where the power is wasted to a great extent. With a holistic view on the available resources and the shortage in the power sector, we have designed this project successfully for the optimal utilization of the limited resources. This will be an eye opener to the coming generations on how to optimally utilize the available resources. CHAPTER 5 5 Conclusion 5.1 Future Outlook This project currently makes use of a lower configuration of external devices connected to it. The feasibility of connecting it to higher order devices and employing its power management capability in larger industries and manufacturing units is always an open option. # This project can be made specific for a particular section of large complex by having an effective addition of pressure sensors which can very effectively sense the no of people present over a small area and thus provide the required.

# The use of thermistor can also help to sense the rise in the room temperature and thus provide change in the operating characteristics of Air Conditioners. # This project can also be extended into the biometrics section where the entry and exit of people are governed by a surveillance system, and depending on the numbers present the lighting and fan also be provided. # This project is also applicable for the operation of machines in

chemical and manufacturing units where depending on the quantity of raw material input the power supplied to the machinery for operation can be adjusted .This extends the industrial application of this project. Hence all these possible future additions along with the current capacity of this project can effect an optimal utilization of the available resources. This project in a way will also become an eye-opener to the international society on how to safeguard our available resources for the future generations. This will make industries to try and develop more techniques for the efficient In-house power management. APPENDIX MICROPROCESSOR DETAILS Key Features High-performance, Low-power AVR 8-bit Microcontroller Nonvolatile Program and Data Memories 16K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles. Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles

1K Byte Internal SRAM Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Four PWM Channels

Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Powerdown, Standby and Extended Standby. I/O and Packages 32 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, and 44-pad MLF. Operating Voltages 2.7 - 5.5V for ATmega16L

Power Consumption @ 1 MHz, 3V, and 25 C for ATmega16L Active: 1.1 mA Idle Mode: 0.35 mA

Power-down Mode: < 1 A

PROGRAM CODING .include"C:\Program Files\Atmel\AVR studio\Appnotes\m16def.inc" .dseg .def temp =r16 .def count =r17 .def count1 =r18 .def temp1 =r19 .def trains =r20 .def train1 =r21 .def train2 =r22 .def count2 =r23 .def ee_low =r24 .def ee_high =r25 .def del1 =r26 .def del2 =r27 .def del3 =r28 .def temp1 =r29 .def temp2 =r30 .def temp3 =r31 .cseg .org $0000 main: ldi temp,low(ramend) out spl,temp ;STACK INITIALIZATION ldi temp,high(ramend) out sph,temp ldi temp,$0f out ddra,temp out porta,temp

;LED INITIALISATION

cbi ddrd,3 cbi ddrd,4 ;IR INITIALISATION sbi ddrc,0 sbi ddrc,1 ;light1 ;light2

sbi ddrd,7 sbi ddrd,5

;motor ;motor(pwm)

ldi temp,$81 out tccr1a,temp ldi temp,$02 ;pwm init out tccr1b,temp clr temp out tcnt1l,temp out tcnt1h,temp out ocr1ah,temp ;motor off out ocr1al,temp clr count clr count1 sw1: sbic pind,3 rjmp sw1 sbic pind,4 rjmp sw2 cbi porta,0 sbi portc,0 inc count rcall per_write rcall delay sw3: sbis pind,4 rjmp sw3 rcall trano_read cpi trains,$02 brne check rcall traper_read in train1,eedr ;CLEAR THE COUNT

sw2:

;lig1 on

rcall per_read in count,eedr cp count,train1 brne check cbi porta,1 ;lig2 on sbi portc,1 check: sbis pind,3 rjmp new_entry sbis pind,4 rjmp old_exit sbis pina,4 rcall train sbis pina,5 rcall cancel rjmp check cancel: rcall delay ss: sbis pina,5 rjmp ss sbi porta,1 cbi portc,1 clr trains out eedr,trains rcall trano_write clr train1 out eedr,train1 rcall traper_write rjmp check new_entry: rcall delay

cc: sbis pind,3 rjmp cc pres: sbic pind,4 rjmp pres rcall entry rcall trano_read cpi trains,$02 brne check_sub rcall traper_read rcall per_read cp count,train1 brne check_sub cbi porta,1 sbi portc,1 check_sub: rcall delay rjmp check old_exit: rcall delay ccd: sbis pind,4 rjmp ccd pres1: sbic pind,3 rjmp pres1 rcall exit cpi trains,$02 brne check_bb rcall per_read in count2,eedr rcall traper_read in train2,eedr ;lig2 on

cp count2,train2 brcs lig2_off check_bb: rcall delay rjmp check lig2_off: cbi portc,1 sbi porta,1 rcall delay rjmp check entry: inc count cbi porta,0 sbi portc,0 rcall check1 rcall per_write ret exit: dec count rcall check2 rcall per_write ret train: rcall delay tt: sbis pina,4 rjmp tt cbi porta,1 sbi portc,1 rcall traper_read rcall per_read cp count,train1 ;lig1 on ;lig2 off

;lig2 on

brne change rcall trano_read inc trains rcall trano_write ret change: rcall per_read rcall traper_read mov train1,count rcall traper_write ldi trains,$01 rcall trano_write ret check1: cpi count,$03 breq fan_slow cpi count,$04 breq fan_med cpi count,$05 breq fan_fast cpi count,$06 brne ch cbi porta,1 ;lig2 on sbi portc,1 ch: cpi count,$07 brne retu cbi porta,3 sbi portd,7 retu: ret check2: ;ac on

cpi count,$06 breq ac_off cpi count,$05 breq lig20_off cpi count,$03 breq fan_slow cpi count,$04 breq fan_med cpi count,$02 breq fan_off cpi count,$00 breq lig1_off ret fan_slow: sbi portd,5 cbi porta,2 ;FAN_SLOW SPEED ldi temp,$7f out ocr1ah,temp ldi temp,$af out ocr1al,temp rcall delay rcall delay ret fan_med: ;FAN_MEDIUM SPEED ldi temp,$05 out ocr1ah,temp ldi temp,$cd out ocr1al,temp rcall delay rcall delay

ret fan_fast: ;FAN_FAST SPEED ldi temp,$ff out ocr1ah,temp ldi temp,$ff out ocr1al,temp rcall delay rcall delay ret lig2_on: cbi porta,1 sbi portc,1 ret lig20_off: sbi porta,1 cbi portc,1 ret fan_off: cbi portd,5 clr temp out ocr1al,temp sbi porta,2 ret lig1_off: sbi porta,0 cbi portc,0 ret ac_off: ;fan off ; lig2 on

;lig2 off

;lig1 off

sbi porta,3 cbi portd,7 ret per_write: ldi ee_low,$60 ;EEPROM WRITING out eearl,ee_low ldi ee_high,$00 out eearh,ee_high out eedr,count sbi eecr,eemwe sbi eecr,eewe wr: sbic eecr,eewe rjmp wr ret traper_write: ldi ee_low,$71 ;EEPROM WRITING out eearl,ee_low ldi ee_high,$00 out eearh,ee_high out eedr,train1 sbi eecr,eemwe sbi eecr,eewe wr1: sbic eecr,eewe rjmp wr1 ret trano_write: ldi ee_low,$70 ;EEPROM WRITING out eearl,ee_low ldi ee_high,$00 out eearh,ee_high out eedr,trains sbi eecr,eemwe sbi eecr,eewe wr2: sbic eecr,eewe rjmp wr2

ret

traper_read: ldi ee_low,$71 out eearl,ee_low ldi ee_high,$00 out eearh,ee_high sbi eecr,eere in train1,eedr ret trano_read: ldi ee_low,$70 out eearl,ee_low ldi ee_high,$00 out eearh,ee_high sbi eecr,eere in trains,eedr ret per_read : ldi ee_low,$60 out eearl,ee_low ldi ee_high,$00 out eearh,ee_high sbi eecr,eere in count,eedr ret delay: ldi del3,4 s3: ldi del2,$ff s2: ldi del1,$ff ;DELAY LOOP ;reading no of persons(count)

;reading data (no of train persons)

;reading no of trains(trains)

s1: dec del1 brne s1 dec del2 brne s2 dec del3 brne s3 ret BIBLIOGRAPHY 1. 2. 3. 4. 5. Zadeh, L. A. (1988). Fuzzy logic, IEEE Computer 21(4):83-93. Zimmermann, H.-J. (1993) Fuzzy Set Theory and its applications, second edn, Kluwer, Boston.(1. ed. 1991). Singh,M.G. (ed.) (1987). Systems and Control Encylopedia : Theory, Technology,Applications Pergamon, Oxford. Jantzen, J. (1995). Array approach to fuzzy logic,Fuzzy Sets and Systems 70: 359370. Kaufmann, A. (1975). Introduction to the theory of fuzzy sets , Academic Press, New York.