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HybridHigh-PowerRectiBerwithReducedTHDandVoItageSagRide-Through
CapabiIity
Admaryo V. Costa, Danillo B. Rodrigues, Luiz C. de Freitas, Joao B. Vieira Jr.,
Emane A. A. Coelho, Valdeir J. Farias e Luiz C. G. Freitas
Universidade Federal de Uberlfudia (UFU)
Faculdade de Engenharia Ehtrica (FEEL T)
Nucleo de Pesquisa em Eletronica de Potencia (NUPEP)
Uberlfudia, MG, Brasil 38400-902
admarco.vieira@hotmail.com, lcgfeitas@yahoo.com.br
Abstract - Temporary voltage sags are the main cause of
untimely arrest in automated systems that use adjustable
speed drives (ASDs). In this context, this paper presents an
analysis of a new hybrid three-phase rectifer designed to
correct the power factor and to promote voltage sag ride
through capability to ASDs. To prove the effectiveness of the
proposed solution, this paper presents results of simulations
for several case studies, evaluating the performance of the
proposed hybrid rectifer under the voltage sags types A, B, C,
and D. In all cases under analysis, it was proved that the
proposed solution is effective and very attractive for
retroftting applications in high power.
Inde Terms-- Adjustable Speed Drive; Harmonic
Distortion; Voltage Sag Ride-Through; Power Factor; Hybrid
Rectifer.
1. INTRODUCTION
Power supply voltage disturbances involving loss of
quality include voltage sags, whose importance is
emphasized in the specialized literature because they
represent about 92% of disturbances as reported by the
EPRl (Electric Power Research Institute) [1]. The IEEE
(institute of Electrical and Electronics Engineering)
Standard 1159-1995 defnes voltage sag as "a decrease of
0.9 to 0.1 pu in the effective nominal voltage of 0.5 cycle
to 1 minute duration" [2]. Moreover, according to the
aforementioned standard, a voltage sag with an intensity of
less than 0.1 pu is considered an interruption. The nature,
magnitude and duration, which are the main characteristics
of voltage sags, are important parameters to be considered.
Voltage sags are caused by various factors, the main one
being the occurrence of short circuits at any point of the
electric power supply, which cause an increase in the
current, leading to variations in the "rms" values of supply
voltages. In addition to short circuits, current overloads
triggered by start-up a large motor or by natural
phenomena also cause voltage sags [3].
In this context, this work focuses on the study of a
feasible solution to improve the supportability of ASD's in
the event of voltage sags and, under the system's normal
operating conditions, to mitigate the harmonic content of
AC line currents. This study is related specifcally to the
effects of these disturbances on the circuit of the proposed
rectifer, which supplies an intermediate DC link for power
electronic converters.
The proposed topology is composed by a three-phase 6-
pulse uncontrolled rectifer (Graetz Bridge), associated
with single-phase switched converters connected in parallel
in each arm of the uncontrolled rectifer. Since voltage sags
are the main reason for interruptions in ASD-controlled
processes, and in order to improve the structure of the
hybrid three-phase rectifer presented in [4]-[6], enabling it
to offer greater voltage sag ride-through capability, a Boost
converter was inserted between the conventional 6-pulse
diode bridge rectifer (Graetz Bridge) and the DC output
link. The purpose of this converter is to keep the voltage of
the DC link in a sag condition on the side of the AC power
supply until the normal supply conditions have been
reestablished. The proposed structure is illustrated in Fig.
1.
BOOST
Fig. 1. Simplifed diagram of the novel Hybrid Power Rectifer
An important feature to be highlighted in this structure
is that under normal operating conditions (imposing
sinusoidal current in the AC line), 60% of power output is
processed by the rectifer diode 6-pulse and 40% is
processed by three switching converters [4]-[6]. This
feature provides high operational reliability and robustness,
which makes it very attractive fom the standpoint of
technical and commercial applications in high power. Thus,
the proposed system is able to supply ultra-clean power and
is also immune to voltage sags, a disturbance commonly
found in electric power systems. To prove the effectiveness
of the proposed solution, this paper presents results of
simulations for several case studies evaluating the
performance of the proposed hybrid rectifer under
conditions of voltage sags of types A, B, C, and D.
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II. "VOLTAGE SAGS" AND THEIR IMPLICATIONS
As mentioned in section I, voltage sags are caused by
the starting up large motors ad by failures in electric
power systems, the latter being the most common
occurrence. Thus, depending on the type of failure and the
type of connection of the transformer and the load, voltage
sags can be classifed into seven types, denoted as A, S, C,
D, E, F and G [7]. The most common voltage sags are
types A, B, C and D, and will therefore be the focus of this
study.
The Type A sag is caused by symmetrical faults and the
others by asymmetrical faults. Table I shows the
mathematical representation of these types of sags
mentioned. The variable h (O"h"l) defnes the severity of
the magnitude and the angular opening resultant fom the
voltage sag.
TABLE I
MATHEMATICAL REPRESENTATION OF EACH TYPE OF SAG
Type A Type B
Type C Type D
Va=1 Va=h
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technique for increasing the supportability of the ASD's to
voltage sags.
i
b2
i
c'
Lil
Recl-1
. . . . . . . . . . . . '
c
', ' . . . . '0
,
'"
.
,
,
.
,
2
.
,
3
. Recl-2
. . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2. Topological structure of the proposed hybrid rectifer.
I =-
.
-j
J
h

V
b
=-
_
h-
jJ r
A.
Stead State O
p
eration
b
2 2

2 2 As illustrated in Fig. 2, the proposed converter consists
1 J . I . J
of a parallel combination of two rectifers groups. The frst
Vc=--+ j-h Vc=--h+}-
2 2
2 2 rectifer is a non-controlled six-pulse (Rect-l) and the
--------------------
The ASD's are very sensitive equipment to voltage sags.
It is noteworthy that the vast majority of outages of
adjustable speed drives are related to voltage sags with a
magnitude around 51 % to 65% of rated voltage [8] with
duration aound 3 and 30 cycles [9].
Several studies have been conducted on the behavior of
ASD's when subjected to voltage sags [10]-[12] and
different alteratives have been proposed as solutions to
increase the tolerance of ASD's under voltage sags [13]
[15].
In this context, in order to protect ASDs fom voltage
sags and thus prevent fnancial losses in industrial plants,
the authors present a new font-end hybrid rectifer
structure capable of imposing sinusoidal input line current
in the AC system and providing voltage sag ride-through
capability as well.
III. OPERATING PRINCIPLE
The operation of the proposed converter depicted in Fig.
2 and as described next, can be divided into two modes of
operation: the operation in steady state in which the
converter provides sinusoidal currents on the AC input,
providing high power factor and low harmonic distortion,
and when the rectifer is under conditions of "SAG", in
which the proposed structure is presented as an alterative
second one is composed of three SEPIC converters capable
of imposing a given input current, following the waveform
of reference imposed (Rect-2). Thus, this combination
results in the current of line A, the currents ial and ia2, being
that ial is the classical curent six-pulse uncontrolled
rectifers, while the current ia2 is imposed by the desired
reference. Therefore, it follows that the composition of the
currents ial and ia2 (ial added to ia2), takes a sinusoidal
waveform as illustrated in Fig. 3.

`
la2

la(in)
Fig. 3. Composition of theoretical waveforms - Sinusoidal input current.
B. O
p
erating under conditions of "SA
G"
Upon the occurrence of temporary voltage sags in AC
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line power supply, the Boost converter will operate as
conventional DC-DC converter used to keep the voltage of
the DC link in a suitable level during sag condition on the
side of the AC power supply until the normal supply
conditions is reestablished [14]-[16]. It is noteworthy that
during voltage sag conditions, the Boost converter is
activated and process about 80% of the total output power
in order to regulate the DC bus voltage at a predeterined
value.
IV. CONTROL STRAEGY
The theoretical block diagram showing the proposed
control strategy is illustrated in Fig. 4. The proposed
control circuit to be implemented uses a Teas
Instruments Digital Signal Processor (DSP)
TMS320F2812.
In order to make the converter operate in two modes as
outlined in the previous section, the code to be executed in
the DSP should follow an algorithm for each operation
mode. Taking the phase A as an example, the control
strategy implemented during the operation in steady state
can be described as follows: a synchronized rectifed
sinusoidal signal is multiplied by an amount corresponding
to the sampled current of the diode rectifer getting the
signal (Vref-l). This action results in a voltage signal
proportional to the load feed by the rectifer. It is added a
sign of sawtooth voltage (VT), with proper amplitude and
fequency of 20 kHz, obtaining thus the reference current
signal (Vref-2). Then, the hysteresis controller compares
Vref-2 with a sample signal of the input curent ia
(in)
, hence
obtaining the trigger signal to be applied to the switch S\.
Therefore, the current fowing in the AC input of the
converter follows the waveform of the sinusoidal imposed
reference in order to provide high power factor and low
harmonic distortion.
In the eventuality of voltage sag, by sensing the output
voltage Yo, the developed code is capable of switching the
control algorithm to the new situation. Thereby, once
detected the sag in the DC bus, the output of the voltage
controller block that consists of proportional-integral
compensator generates a control voltage (Vref-3) which
will be compared with a sawtooth voltage, obtaining as
result, the PWM signal to be applied to switch S\ to
maintain the output voltage regulated at a value of
reference pre-established and, therefore, it is able to keep
the ASD in normal operation conditions even facing the
occurrence of temporary voltage sag at the input.
Figure 5 shows the block diagram of the control code to
be implemented in the DSP TMS320F2812. To begin with,
all the variables and constants required during the
execution of the program are initialized. Afer this, all the
registers required to operate the DSP are set up. This
includes the event manager, the A/D converter and the
necessary interruptions.
The temporizer was set up to operate in continuous
conduction mode (increasing/decreasing) to generate a
signal symmetric PMW. The control action of the current
controllers is determined by the comparison registers
(TxCMP), so that while the counter's value is higher than
the comparison value, the PMW output is commutated to
the zero level, deactivating the switch in this interval.
While receiving an interrupt request, the controller stores
the content of the registers and initiates the conversion of
the monitored variables.
"SAG"
. . .... o..atio. ...
Fig. 4. Block diagram of te DSP control.
Start
Definition of vectors,
variables and constant
interruptions
DSP
Iig. 5. SimpIiLcdowchartothcprogrammingothcDSP.
Afer concluding the conversion of the process
variables, the pulses to be sent to the switches of SEPlC
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converters are determined. If there is a voltage sag in the
AC input supply and updated the error of output voltage
(Vo), the block proportional - integral voltage controller
calculates the control voltage signal ( Vref-3 ) that will be
compared with a sawtooth voltage, obtaining as result, the
PWM signal to be applied to switch SB of BOOST
converter. The previously stored records are then restored
and the device remains in stadby mode for the next
interrupti on.
V. SIMULATION RESULTS
Simulations carried out with Orcad sofware are
presented to illustrate the performance of the proposed
converter. Note the operation of the structure under normal
conditions of AC power supply, achieving high power
factor and low THOJ at the converter AC input and the
ability to maintain the supportability of the DC bus voltage
under voltage sag conditions. The design parameters used
in the simulations are shown in Table II.
TALE ll.
DESIGN PARAMETER
ProjeetSpee|eat|ons
DC Link voltage, VDC (avg) = 290 V
Line-to-neutral voltages Va, Vb, Vc (rs) = 127 V
Total output power, Pout = 5 kW
Switching fequency, fs = 20 kHz
6-Palseu|ode8r|dgeReet|er+
Boost (Reet-1j
AC inductor flter, LI-L3 - I mH
DC capacitor flter, CF - 3000 F
Sepic Converters
(Reet-2j
Input inductors, L4-L6 - 2 mH
DC capacitor flter, CF - 47 F
In order to obtain the simulations results presented in
this paper, it was made a carefl study of the SEPIC
converter according to reference [17], in that, frstly, it was
achieved the transfer fnction of the converter and then
stability studies were performed using Sisotool-Matlab.
Figs. 6 to 11 depict the main simulation results for a 5
kW converter operating under normal conditions of voltage
supply and under conditions of sag types A, B, C, and D
corresponding to the typical sag illustrated in Table I.
Figure 6 shows the line voltages, the voltage on the DC
bus under sag type A for h = 0.5 pu. Stands out the
occurrence of the voltage sag type A with a duration of
200ms in three phases starting at I50ms and the fact that
the structure presents excellent results in terms of ride
through capability, since the DC bus voltage remained
unchanged despite the occurrence of more severe sags. Fig.
7 depicts the currents for this same sag. Note the low
harmonic content during normal operation of AC mains
supply due to the imposition of sinusoidal currents.
To illustrate the effectiveness of the proposed converter
subjected to voltage sag types B, C and 0 G (h=O.I), Figs.
8 to 10 present the following simulations.
Fig. 11 shows the contributions of power processed by
the 6-pulse rectifer (Rect-I) and Se
p
ic (Rect-2) converters.
Analyzing the presented results, it can be observed that
the proposed converter provides an operation with a
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signifcant increase of the supportability to voltage sags
compared to the minimum voltage DC bus of ASD's,
established by interational organizations like the SEMI
F47 and the North American Institute EPRI, establishing,
basically for semiconductor electronics devices, the
tolerance to voltage sags to 50% for 200 ms, 70% for 500
ms and 80% for 1000 ms [14].
In order to experimentally evaluate the effectiveness of
the proposed solution, a 5 kW prototype has been
implemented in laboratory as portrayed in Figure 12. All
data efforts of current and voltage of semiconductors
devices, as well as the passive elements were used for the
specifcation of the physical components of the system and
for development of CAD design also illustrated. Currently,
the experimental setup is under analysis and the main
results will be presented in fture works.
350V
20V
OV
1
-20V
-350V
DC LINK VOTAGE
.

INPT BOOST VOTAGE

\ 1f
I I 11
!
v V I

VOTAGE SAG TE A
`INPUT LINE VOTAGES
I
1f

'VV

lOs 12 I5 175m. 20 25ms 25ms 275ms 30m 325m. 35 375ms 40s
Fig. 6. Input line voltages and DC Link type A voltage sag
70A
40A
laQn)
OA
-0A
-70A
1O 12 15. 175 20 25. 25 275 lO. 325 35 375.4O s
Fig. 7. Input currents under type A voltage sag
J:tv-
:xv
+
-:mv
L GE G
Fig. 8. Input line voltages and DC Link under type B voltage sag
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350V
DC LI VOLTAGE
. .
0l|l|
200V
OV
-200V
VOLTAGE SAG TE C
-350V
100m, 125m, 150m, 175m, 200m, 225m, 250m, 275m, 300m, 325m, 350m, 375m,400m,
35
0V
200V
OV
-20V
Fig. 9. Input line voltages and DC Link under type C voltage sag
D LI VOLTAGE
LT E G B
-
35
0V
IOms 12Sms ISOm' 17Sm, 200ms 22Sms 2S0m' 27Sm, 300m' 32Sms 3S0ms37Sm,4oms
Fig. 10. Input line voltages and DC Link under type D voltage sag
|)
|
|c)
........................... ': .................
<
--- P.re2(SGA) ,
U
-P.rel(SGA)
e 60 --- P.re.2(SB)

' -P rel(SGB)

5
0--Totl Por
P re2(S)
u
400
'
o
P rel(S)
- - .
-
0
.\
0
.\5
0
.
2
0
.25 OJ
0
.15
0
.4
tUlle (s)
Fig. I I . Power processed by Rect-I (6-pulse rectifer + Boost converter)
and the Rect-2 (switched Sepic converters)
'
Fig. 12. Prototype plant under implementation in laboratory (a)-(e) CAD Project (f Experimental setup.
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VI. CONCLUSIONS
This paper analyzed a new typology of hybrid power
rectifer that can mitigate the harmonic content of AC
currents drained by the conventional 6-pulse rectifer,
providing a high power factor and low THO] under normal
conditions of electric power supply. In addition, the
structure is able to increase the ride-through capability of
voltage sags occurring in the power supply, regulating the
voltage in the DC link.
To improve the voltage sag ride-through capability, a
Boost converter is inserted between the 6-pulse diode
rectifer and the DC link, which operates in conjunction
with switched SEPIC rectifers to regulate the output
voltage.
An analysis was made of the powers processed by the
converters involved in the structure. It was shown that
under normal conditions of operation and voltage supply,
about 40% of the power is processed by switched rectifers
while the remaining 60% is processed by 6-pulse rectifers.
In the operating condition with voltage sag, the portion of
power processed by the rectifers will depend on the type of
sag. In the presence of type A sag, the rectifer processes
the higher level of power which is about 80% (sag level of
50%).
The control strategy to be used is based on DSP, and
offers improvements such as enhanced fexibility and
greater reliability of the converters operation.
These two characteristics make the converter attractive
for high-power industrial applications. The theory put
forward here was validated by simulations for the various
types of cases. Therefore, the proposed structure appears to
be promising for industrial applications in combination
with ASDs, since ride-through capability, high power
factor, and low harmonic distortion of curent in the mains
can be achieved.
ACKNOWLEDGMENT
The authors gratefully acknowledge the fnancial
support provided by CAPES, CNPq, and F APEMIG.
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