Project Review On DESIGN & IMPLEMENTATION OF LOW POWER 32-BIT RISC PROCESSOR

ABSTRACT
The project involves design of a simple RISC processor and simulating it. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions (appx.30-40), with the aim of increasing the overall speed of the processor. The RISC concept first originated in the early 1970's when an IBM research team proved that 20% of instruction did 80% of the work. The RISC architecture follows the philosophy that one instruction should be performed every cycle Rules that has to follow for RISC architecture: 1) No of instructions should not more than 40 2) Entire operation of the instruction should be done within 1 clock cycle. 3) All the instructions should have fixed width. 4) Fixed with of time should be assigned for every instruction. 4) Pipelining concept has to be incorporated with RISC architecture. Basic theory for 32 bit RISC architecture In this project we are using 32-bit instruction word. Actually in RISC architecture we partition a single instruction into 5 parts. a) Fetch opcode. b) Decode it. c) Fetch operand.

d) Execute it. e) Write back

For each of this part, we need minimum of 1 machine cycle. So we can say that a group of machine cycles that are consumed for a single instruction is called Instruction Cycle.

Pipelining: The concept of pipelining is essential to have good performance of our processor. Pipelining is nothing but parallel processing. In the above diagram, during the decoding of 1st instruction, we can fetch the 2nd instruction. Similarly during the 3rd cycle of 1st inst, we can decode 2nd and fetch 3rd inst simultaneously.

Address and Data

As a processor has to fetch the information from memory, so in order to identify the particular location and get the data from it, we need address. So we use ADDRESS_BUS which has certain width. The width depends on the memory content.

Similarly once we identify the location and to get the data from it, we need DATA_BUS which we have width of 8 bit.

In RISC architecture we have bunch of REGISTER_FILES to preserve the data for certain manipulations. Each REGISTER_FILE has a width of DATA_BUS. One of the important REGISTER we need to define is PROGRAM COUNTER (PC). Once we have successfully completed one instruction, then we increment PC by 1. So that we can easily identify in which instruction we are.

32 bit instruction format

(3 bits unused) 5 bit OPCODE 8 bit register(RS) 8bit register(RD) 8 bit register(R)

Example: Add RS,RD,R Explanation: here add is decoded and taken as 5 bit opcode. The contents of RS and RD are fetched and the result is stored in R Control signals Control signals play a vital role. Generally we have 2 control signals. 1) Read signal 2) Write signal When read signal has asserted then the data from memory has loaded into registers. Similarly when write signal has asserted, then contents of register is stored in memory bank using address.

Dual port Ram(DPRAM)

By using this DPRAM we can read two address locations simultaneously / write one data onto register. So that, we can increase the performance of the processor by utilizing one clock cycle.