Digital Logic And Computer Organization UNIT V 5.

0) Introduction
The fact that computers are digital machines means that it is important to present data and instructions to computers in a machine-readable form, and obtain the output in a form in which it is comprehensible to the Human mind.

5.1) Objectives
This chapter will concentrate on the performance of I/O operations by programcontrolled I/O using polling, the idea of interrupts and the hardware and software needed to support them and, finally, Direct memory access.

5.2) Content
5.2.1. Input-Output Organization In most systems the Processor, memory and I/O devices are connected through one or more data paths known as buses. A typical system organization includes: Input Output Devices Mouse Keyboard Graphics Card Sound Card Disk Dives Network Interfaces Bus signals The signals on the I/O Memory Bus can be divided into three categories Address lines Data lines Control Signals Synchronous busses may also contain a clock signal. Addressing a device There are two strategies for addressing I/O devices attached to the system bus. Memory mapped IO IO mapped IO

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Memory mapped IO The address space of the machine is divided into two sections: Normal memory addresses. Addresses corresponding to IO devices. IO devices are accessed via standard load store operations. Unauthorized access is precluded by the virtual memory system. IO mapped IO IO addresses are accessed through special commands - different from standard memory access instructions (e.g. on the PC the IN and OUT instructions fulfill this role). 5.2.2. Interrupts External devices may require attention from processor at unpredictable times. CPU doesnt know when user hits a key. Very often, processor checks each device to see if it has a request. Interrupts are better if the processor has other work to do and the time to respond to events isnt absolutely critical. When interrupt is signaled, processor executes a routine called an interrupt handler to deal with the interrupt. Interrupt controller signals processor that interrupt has occurred, passes interrupt number. Processor uses interrupt number to determine which handler to start. Data structure called interrupts vector associates handlers with. Processor halts the current program. Multicycle operations may be either halted or squashed and restarted. Current program state is saved (like context switch) and the processor jumps to interrupt handler. When interrupt is completed, the program state is loaded and the program resumes. Interrupts are assigned priorities to handle simultaneous interrupts. For example, in the Interrupts on 80386EX, 80386 core has one interrupt line and one interrupt acknowledge line. The Interrupt sequence is : Interrupt controller raises INT line. 80386 core pulses INTA line low, allowing INT to go low. 80386 core pulses INTA line low again, signaling controller to put interrupt number on data bus In LINUX, OS handles interaction with the interrupt hardware. Communicating With User Programs Interrupts cannot directly read/write data in a user programs space. The two approaches are: Interrupt handler copies data from interrupting device, places it into a buffer that is mapped onto a /dev/foo entry that user program can then read. Page 131

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User program handles actual reading/writing of data to/from device. User program sleeps after each data transfer. All the interrupt handler does is wake the user program up whenever the device is ready. In this approach, the user program should clear the interrupt bit on the device, to prevent the device from overwriting data before the user program has read it. In an interrupt driven I/O scheme the I/O device can signal the processor when it needs to be serviced by asserting a special bus signal known as an interrupt request line. Interrupts are asynchronous to the operation of the user program - they can occur at any time. Interrupt Handlers Interrupt handlers are the routines that are called when an interrupt is detected. Interrupt handlers are usually short sections of code that are designed to handle the immediate needs of the device and return control to the operating system or user program. Masking Interrupts It is sometimes advantageous to disable interrupts while the processor is performing some critical operation (like handling another interrupt). On some systems there may be one or more high priority interrupts that cannot be masked. Steps in Handling an Interrupt Steps in Handling an Interrupt would include: Disable further interrupts Store current state of program Execute appropriate interrupt handling routine Restore state of program Enable interrupts Resume program execution Interrupt Handling on a PC On a PC there are 16 separate interrupt lines that can be asserted. The appropriate interrupt handler is invoked based on the interrupt number. Interrupt Handling in MIPS On a MIPS machine the Cause register is filled in with an appropriate code which allows the interrupt handler to figure out the cause of the interrupt. The interrupt mechanism has also proven to be a useful means for implementing Operating system calls and Preemptive multitasking.

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5.2.3. Interfacing Processors and Peripherals I/O Devices Input/output (I/O) devices enable processors to interact with people. For example, mouse, keyboard, monitor. They also interact with each other. For example, modem, LAN to store and retrieve data. For example, magnetic disk, magnetic tape. Every I/O device has the Data rate, which is the peak rate at which data can be transferred between I/O device and main memory (or processor). Transfer rates for modems and networks are usually specified in decimal e.g., 28.8 K bits/sec = 28800 bits/sec = 3600 Bytes/sec = 3.52 K Bytes/sec

Table 6.4: I/O Devices System Interconnection The System Interconnection is established through the bus that enables shared communication link and uses one set of wires to connect multiple devices. Buses provide electronic interconnection among I/O devices, processors and memory and also define lowest level protocol for communication, that is,how word or block of data should be communicated on wires. The Bus performance and organization depends on thelength of wires and number of connected devices limit speed of bus. The higher-level bus can be designed to be fast, while lower-level buses allow for expansion. For example, processor, memory and I/O devices might all plug into backplane bus (e.g., VME bus) or I/O buses (e.g., SCSI) might tap into processor-memory bus. I/O Modules I/O module (controller) is the hardware required to connect I/O device to backplane bus or I/O bus to processor-memory bus. For example, disk controller, SCSI-bus controller.

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I/O devices connect directly to I/O bus and provides less complex, more uniform interface to (higher-level) bus and also smooths out differences in speed containing internal buffers for temporarily holding data until it can be sent on.

Figure 6.12: I/O Controller Hardware/Software Interface Operating system has major role because multiple processes need to access I/O devices and interrupts are often used to communicate information about I/O operations and lowlevel control of I/O devices is complex. OS must therefore provide several functions: Protection - control access of users to I/O devices such as reading a file on disk requires permission. abstraction - routines that handle low-level device operations interrupt-handling scheduling - equitable access to shared I/O resources and schedule accesses to enhance system performance Three types of communication are required in order to perform these functions: OS must be able to give commands to I/O devices (e.g., read, write, disk seek ) I/O device must be able to notify OS of successful completion or error (e.g., disk has completed seek) Data must be transferred between memory and I/O device (e.g., block read from disk must be written to memory) Giving Commands to I/O Devices OS must be able to address I/O device and supply one or more command words. The two methods are used to address device:

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memory-mapped I/O - portions of memory address space assigned to I/O devices, accessible only in supervisor mode. Data written to those addresses are interpreted as commands. Dedicated I/O instructions (e.g., Intel 80x86, IBM 370) which are illegal to execute when not in supervisor mode. Communicating with the Processor Communicating with the Processor includes: programmed I/O (polling) - I/O device (e.g., mouse) puts information in "status register" and processor periodically checks register (which can waste lot of time because processors are much faster than I/O devices) interrupt-driven I/O - I/O device causes processor to be interrupted whenever it has completed operation or needs attention and to identity of device, etc., determined by "vectored interrupt" or "cause register"

5.2.4. Transferring Data between Device and Memory

Transferring Data between Device and Memory is done using programmed I/O or interrupt-driven I/O where: processor (and OS) do all the work, accessing I/O device and memory for each data item transferred which is cheap solution for low-bandwidth devices. Using direct memory access (DMA) which is the specialised controller that transfers data between I/O device and memory, independent of processor. The Processor sets up DMA by supplying identity of device, operation to perform on it, memory address that is source or destination of data and number of bytes to transfer. DMA starts operation on device and arbitrates for the bus and the data transfer can begin once DMA controller has become bus master and data is available. Upon completion of DMA transfer, the controller interrupts processor. Multiple DMA controllers are allowed. For example, one per I/O-bus controller, the processor trying to access memory is stalled while DMA controller is bus master. When virtual memory is used, either DMA transfers should be constrained to stay within one page or controller needs to know relevant page table entries. When cache memory is used, I/O activity must be routed through cache or OS must selectively flush cache where the latter is cheaper and avoids contention between DMA and processor on cache hit.

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Figure 6.13: Methods of I/O Data blocks 5.2.5. Direct Memory Access (DMA) Most modern computer systems have special purpose circuitry to relieve the processor of the tedious task of moving data back and forth between I/O devices and memory Typical DMA transaction Processor configures DMA system with target memory address, I/O address and number of bytes to be transferred. DMA unit performs operation while processor works on other tasks and informs processor when task is complete by asserting an interrupt. Data Coherency with DMA The DMA system must be made to work with the cache system and the virtual memory scheme. Addresses modified by DMA activity must be checked against the cache contents and pages in main memory that are being accessed by DMA cannot be swapped out until the DMA activity is finished. IO Processors Certain high end systems contain dedicated coprocessors for handling I/O operations. The processor can configure the IO processor to perform a sequence of I/O operations or to continually monitor the status of one or more I/O devices by polling.

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Assessing I/O performance In measuring the performance of an I/O system we are usually interested in Response Time: The time required to respond to an I/O request. Bandwidth: The amount of data delivered per second once the transfer has been initiated. Bottlenecks: Aspects of the I/O system that limit performance.

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Digital Logic And Computer Organization 5.3) Revision Points

Comparison between memory mapped I/O and I/O mapped I/O: No. 1 Memory mapped I/O Memory and I/O share the entire address space of the processor I/O mapped I/O Address space is not shared between the memory and I/O. Processor provides separate address range for memory and I/O devices Less decoding is required because the processor provides less address space I/O control signals are used to control read and write I/O operations

2 3

More decoding is required because the processor provides more address lines for accessing memory Separate memory control signals are used the control the I/O operations

No. 1

Programmed I/O Processor has to poll each I/O and so it cannot execute other instructions in sequence During polling, processor is busy and hence have serious and detrimental effect on system throughput Does not depend on the status of interrupt Does not need initialization of stack System throughput decreases as number of I/O devices connected in the system increases Implemented without interrupt hardware support.

3 4 5

Interrupt driven I/O External asynchronous input is used to tell the processor that I/O device needs its service and hence processor does not have to check if the I/O device needs service The processor is allowed to execute its instructions in sequence and only stop to service I/O device when required. This increases system throughput Interupt must be enabled to process. Because instruction execution sequence is interrupted, it needs initialization of stack. System throughput does not depend on the number of I/O devices connected in the system Implemented using interrupt hardware support

Comparison between Programmed I/O and Interrupt Driven I/O:

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Drawbacks of both programmed I/O and interrupt driven I/O: The I/O transfer rate is limited by the speed with which the CPU can test and service a device. 2. The time that the CPU spends testing I/O device status and executing a number of instructions for I/O data transfers can often be better spent on other processing tasks. To overcome these drawbacks, an alternative technique, hardware controlled data transfer used is called DMA. An external device is used to control data transfer. It generates address and control signals required to control data transfer and allows peripheral device to directly access memory. This device is called DMA controller.

5.4) Intext Questions

1. 2. 3. 4. 5. Explain the interrupts in detail. List the different types of interrupts. Explain briefly about maskable interrupt. What is meant by direct memory access? How is direct memory access used to transfer data from peripherals.

5.5) Summary
There are two strategies for addressing I/O devices attached to the system bus - Memory mapped IO and IO mapped IO. In this unit, three basic approaches to I/O transfers have been introduced. The simplest technique is programmed I/O, in which the processor performs all the necessary control functions under direct control of program instructions. The next technique is based on the use of interrupts, it makes it possible to interrupt normal execution of programs in order to service higher- priority requests that require more urgent attention. When interrupt is signaled, processor executes a routine called an interrupt handler to deal with the interrupt. The third I/O scheme involves Direct Memory Access, the DMA controller transfers data between an I/O device and the main memory without continuous processor intervention. Access to memory is shared between the DMA controller and the processor. In most systems the Processor, memory and I/O devices are connected through one or more data paths known as buses.

5.6) Terminal Exercises

1. What is meant by data coherency in the context of DMA?

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2. Explain the following data transfer schemes with necessary diagrams: 1) Interrupt driven data transfer 2) DMA data transfer. 3. Explain the Hardware and Software Interface.

5.7) Supplementary Materials

Computer Organization & Architecture, William Stallings, Pearson Education

5.8) Assignments
Find the specifications of DMA controller used in the recent processors.

5.9) Reference Books

Computer Architecture, A quantitative Approach, third edition, John L. Hennessy, David A. Patterson.

5.10) Learning Activities

What is the current maximum data transfer rate achievable in programmed I/O, DMA ?

5.11) Keywords
Memory mapped I/O, I/O mapped I/O, Programmed I/O, Interrupt driven I/O, DMA

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