INTRODUCTION TO VHDL (WITH SOME EXAMPLES)

HISTORY OF VHDL
In the mid-1980s the U.S. Department of Defense ( DoD) and the IEEE sponsored the development of the hardware description language with the goal to develop very high-speed integrated circuit, which brought result in the form of VHDL. It has become now one of industrys standard languages used to describe digital systems. The other widely used hardware description language is Verilog. Both are powerful languages that allow you to describe and simulate complex digital systems. A third HDL language is ABEL (Advanced Boolean Equation Language) which was specifically designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry.

WHATS VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. Its a hardware description language that is specifically designed to describe the organization & function of digital hardware system .In sort ,VHDL is a hardware description language that can be used to model a digital system .the digital system can be as simple as logic gate as complex as a complete electronic system.

CAPABILITIES OF VHDL
Implementation of any circuit idea like complete robot design. Microprocessor of your own configuration. Direct hardware interaction.

SPECIFIC FEATURES OF VHDL

Portability Each level of abstraction. Not technology specific. IEEE & ANSI standardized. Large projects can be easily designed.

VHDL DESIGN HIERARCHY

ENTITY DECLARATION
The entity declaration defines the NAME of the entity and lists the input and output ports. The general form is as follows, entity NAME_OF_ENTITY is [ generic generic _declarations);] port (signal _ names: mode type; signal _ names: mode type; : Signal _names: mode type); end NAME_OF_ENTITY ; An entity always starts with the keyword entity, followed by its name and the keyword is. Next are the port declarations using the keyword port. An entity declaration always ends with the keyword end.

ARCHITECTURE BODY
The architecture body specifies how the circuit operates and how it is implemented. As discussed earlier, an entity or circuit can be specified in a variety of ways, such as behavioral, structural (interconnected components), or a combination of the above. The architecture body looks as follows, Architecture architecture_name of NAME_OF_ENTITY is -- Declarations -- components declarations -- signal declarations begin

Statements; end architecture_name;

architecture Structural of fulladder is component halfadder_str_us_xor Port ( a: in STD_LOGIC; b : in STD_LOGIC;

EX:>

sum : out STD_LOGIC; carry : out STD_LOGIC); end component; //component component orgate Port ( a4: in STD_LOGIC; b4 : in STD_LOGIC; c4 : out STD_LOGIC); end component; signal s1,g,h:STD_LOGIC; //signal begin statements; end Structural;
declarations declarations

SIGNALS
Signals connect design entities together and communicate changes in values between processes.They can be interpreted as wires or busses in an actual circuit.Signals can be declared in packages , entities , architectures and blocks. The syntax is :

Signal signal_name {signal_name} :type[:=value];

DESIGN DESCRIPTION METHODS

A digital system can be represented at different levels of abstraction [1]. This keeps the description and design of complex systems manageable. Figure 1 shows different levels of abstraction.

Figure 1: Levels of abstraction: Behavioral, Structural and Physical **The highest level of abstraction is the behavioral level that describes a system in terms of what it does (or how it behaves) rather than in terms of its components and interconnection between them. A behavioral description specifies the relationship between the input and output signals. This could be a Boolean expression or a more abstract description. VHDL allows one to describe a digital system at the structural or the behavioral level. The **behavioral level can be further divided into two kinds of styles: Data flow and Algorithmic. *The dataflow representation describes how data moves through the system. This is typically done in terms of data flow between registers (Register Transfer level). The data flow model makes use of concurrent statements that are executed in parallel as soon as data arrives at the input. On the other hand , sequential statements are executed in the sequence that they are specified. VHDL allows both concurrent and sequential signal assignments that will determine the manner in which they are executed. Examples of both representations will be given later. as the Register Transfer or Algorithmic level. As an example, let us consider a simple circuit that warns car passengers when the door is open or the seatbelt is not used whenever the car key is inserted in the ignition lock, At the behavioral level this could be expressed as, Warning = Ignition_on AND ( Door_open OR Seatbelt_off)

**The structural level, on the other hand, describes a system as a collection of gates and components that are interconnected to perform a desired function. A structural description could be compared to a schematic of interconnected logic gates. It is a representation that is usually closer to the physical realization of a system. For the example above, the structural representation is shown in Figure 2 below.

Figure 2: Structural representation of a buzzer circuit.

SEQUENTIAL STATEMENTS
If Statements The if statement executes a sequence of statements whose sequence depends on one or more conditions. The syntax is as follows: if condition then sequential statements; [else if condition then sequential statements ] [else sequential statements ] end if; EX:>(if statements for xor gate)

if(a='1'and b='0')then c<='1'; else if(a='0'and b='1')then c<='1'; else c<='0'; end if; end if; ( here two end if (last two line of programme)is present due to the fact that Above we used two statements including if( those are if and else if) )

Case statements The case statement executes one of several sequences of statements, based on the value of a single expression. The syntax is as follows, case expression is when choices => sequential statements when choices => sequential statements -- branches are allowed [ when others => sequential statements ] end case; EX:> case s is when "000"=> d<="00000001";// d<="00000001";//HERE D IS THE OUTPUT OF COMBINATION OF 8BITS ="00000001"; when "001"=> d<="00000010"; when "010"=> d<="00000100"; when "011"=> d<="00001000"; when "100"=> d<="00010000"; when "101"=> d<="00100000"; when "110"=> d<="01000000"; when "111"=> d<="10000000"; when others=> //THIS STATEMENT IS MUST. null; end case; //HERE S IS THE INPUT OFCOMBINATION OFTHREE BITS

Dataflow Modeling
Concurrent Statements Behavioral modeling can be done with sequential statements using the process construct or with concurrent statements. The first method was described in the previous section and is useful to describe complex digital systems. In this section, we will use concurrent statements to describe behavior. This method is usually called dataflow modeling. The dataflow modeling describes a circuit in terms of its function and the flow of data through the circuit. This is different from the structural modeling that describes a circuit in terms of the interconnection of components. Concurrent signal assignments are event triggered and executed as soon as an event on one of the signals occurs. In the remainder of the section we will describe several concurrent constructs for use in dataflow modeling. Simple Concurrent signal assignments.(DATA FLOW MODELLING) In this section we will review the different types of concurrent signal assignments. A simple concurrent signal assignment is given in the following examples, Sum <= (A xor B) xor Cin; Carry <= (A and B); Z <= (not X) or Y ; The syntax is as follows: Target_signal <= expression; in which the value of the expression transferred to the target_signal. As soon as an event occurs on one of the signals, the expression will be evaluated. The type of the target_signal has to be the same as the type of the value of the expression. Conditional Signal assignments The syntax for the conditional signal assignment is as follows: Target_signal <= expression when Boolean_condition else expression when Boolean_condition else : expression; The target signal will receive the value of the first expression whose Boolean condition is TRUE. If no condition is found to be TRUE, the target signal will receive the value of the final expression. If more than one condition is true, the value of the first condition that is TRUE will be assigned.

Structural Modeling
A structural way of modeling describes a circuit in terms of components and its interconnection. Each component is supposed to be defined earlier (e.g. in package) and can be described as structural, a behavioral or dataflow model. At the lowest hierarchy each component is described as a behavioral model, using the basic logic operators defined in VHDL. In general structural modeling is very good to describe complex digital systems, though a set of components in a hierarchical fashion. A structural description can best be compared to a schematic block diagram that can be described by the components and the interconnections. VHDL provides a formal way to do this by Declare a list of components being used Declare signals which define the nets that interconnect components Label multiple instances of the same component so that each instance is uniquely defined.

The components and signals are declared within the architecture body, architecture architecture_name of NAME_OF_ENTITY is -- Declarations component declarations signal declarations begin -- Statements component instantiation and connections; end architecture_name; Component declaration Before components can be instantiated they need to be declared in the architecture declaration section or in the package declaration. The component declaration consists of the component name and the interface (ports). The syntax is as follows: component component_name port (port_signal_names: mode type; port_signal_names: mode type; : port_signal_names: mode type); end component ; //here not write end component_name in the last statement The component name refers to either the name of an entity defined in a library or an entity explicitly defined in the VHDL file (see example of the four bit adder).

The list of interface ports gives the name, mode and type of each port, similarly as is done in the entity declaration. A few examples of component declaration follow: component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component;

component FULLADDER

port(a, b, c: in std_logic; sum, carry: out std_logic); end component; As mentioned earlier, the component declaration has to be done either in the architecture body or in the package declaration. Generally for simplicity we used to defined component declaration in the architecture body.

CONCLUSION

VHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. It can be said that VHDL fuelled modern synthesis technology and enabled the development of ASIC semiconductor companies. From the beginning VHDL has been a powerful language with numerous language constructs that are capable of describing very complex behavior, this leadership of VHDL community has assured open and internationally accredited for the electronic design engg. community. The legacy of team work continue to benefit the design community today as the benchmark by which one measures openness.

FUTURE PROSPECTS
Each device microprocessor controlled is designed by VHDL. Future: an electronics world. International endorsement: a positive response.

SOME EXAMPLES
BEHAVIORAL MODELLING 1. XOR GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xorgate; architecture xora of xorgate is begin process(a,b) begin if(a='1'and b='0')then c<='1'; else if(a='0'and b='1')then c<='1'; else c<='0'; end if; end if; end process; end xora;

2.FULL SUBSTRACTOR
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullsubst is Port ( a : in STD_LOGIC; b : in STD_LOGIC; bi : in STD_LOGIC; d : out STD_LOGIC; bo : out STD_LOGIC); end fullsubst; architecture Behavioral of fullsubst is begin process(a,b,bi) begin if((a='0' and b='0' and bi='1')or(a='0' and b='1' and bi='0') or (a='1' and b='1' and bi='1'))then d<='1'; bo<='1'; else if(a='0' and b='1' and bi='1')then d<='0';

bo<='1'; else if(a='1' and b='0' and bi='0')then d<='1'; bo<='0'; else d<='0'; bo<='0'; end if; end if; end if; end process; end Behavioral;

3.COMPARATOR
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity compar is Port ( a : in STD_LOGIC_VECTOR (15 downto 0); b : in STD_LOGIC_VECTOR (15 downto 0); s : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC); end compar; architecture Behavioral of compar is begin process(a,b,s) begin case s is when "0000"=> if(a/=b)then --unexpected eq y<='1'; else y<='0'; end if; when "0001"=> if(a=b)then y<='1'; else y<='0'; end if; when "0010"=> if(a>b)then y<='1'; else y<='0'; end if; when "0011"=> if(a<b)then y<='1'; else y<='0'; end if; when "0100"=> if(a>=b)then y<='1'; else y<='0'; end if;

when "0101"=> if(a<=b)then y<='1'; else y<='0'; end if; when "0110"=> if(a-b=1)then y<='1'; else y<='0'; end if; when "0111"=> if(b-a=1)then y<='1'; else y<='0'; end if; when others=> null; end case; end process; end Behavioral;

4.DEMULTIPLEXER
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder is Port ( s : in STD_LOGIC_VECTOR (2 downto 0); d : out STD_LOGIC_VECTOR (7 downto 0)); end decoder; architecture Behavioral of decoder is begin process(s) begin case s is when "000"=> d<="00000001"; when "001"=> d<="00000010";

when "010"=> d<="00000100"; when "011"=> d<="00001000"; when "100"=> d<="00010000"; when "101"=> d<="00100000"; when "110"=> d<="01000000"; when "111"=> d<="10000000"; when others=> null; end case; end process; end Behavioral;

5.EVEN PARITY GENERATOR

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity evenpargen is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; p : out STD_LOGIC); end evenpargen; architecture Behavioral of evenpargen is begin process(a,b,c,d) begin if((a='0' and b='0' and c='0' and d='1') or(a='0' and b='0' and c='1' and d='0')or (a='0' and b='1' and c='0' and d='0')or (a='0' and b='1' and c='1' and d='1') or (a='1' and b='0' and c='0' and d='0')or (a='1' and b='0' and c='1' and d='1')or (a='1' and b='1' and c='0' and d='1')or (a='1' and b='1' and c='1' and d='0'))then p<='1'; else p<='0'; end if; end process; end Behavioral;

DATAFLOW MODELLING

1.BINARY TO GRAY CODE CONVERTOR

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bintogray is Port ( b3 : in STD_LOGIC; b2 : in STD_LOGIC; b1 : in STD_LOGIC; b0 : in STD_LOGIC; g3 : out STD_LOGIC; g2 : out STD_LOGIC; g1 : out STD_LOGIC; g0 : out STD_LOGIC); end bintogray; architecture dataflow of bintogray is begin g3<=(b3); g2<=(b3 xor b2); g1<=( b2 xor b1); g0<=(b1 xor b0 ); end dataflow;

2.DECIMAL TO BINARY ENCODER

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dectobcd_encoder is Port ( d0 : in STD_LOGIC; d1 : in STD_LOGIC; d2 : in STD_LOGIC; d3 : in STD_LOGIC; d4 : in STD_LOGIC; d5 : in STD_LOGIC; d6 : in STD_LOGIC; d7 : in STD_LOGIC; d8 : in STD_LOGIC; d9 : in STD_LOGIC; a3 : out STD_LOGIC; a2 : out STD_LOGIC; a1 : out STD_LOGIC; a0 : out STD_LOGIC); end dectobcd_encoder; architecture dataflow of dectobcd_encoder is

begin a3<=(d8 or d9); a2<=(d4 or d5 or d6 or d7); a1<=(d2 or d3 or d6 or d7); a0<=(d1 or d3 or d5 or d7 or d9); end dataflow;

3.BCD TO DECIMAL DECODER

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcdtodecimal is Port ( a3 : in STD_LOGIC; a2 : in STD_LOGIC; a1 : in STD_LOGIC; a0 : in STD_LOGIC;

d0 : out STD_LOGIC; d1 : out STD_LOGIC; d2 : out STD_LOGIC; d3 : out STD_LOGIC; d4 : out STD_LOGIC; d5 : out STD_LOGIC; d6 : out STD_LOGIC; d7 : out STD_LOGIC; d8 : out STD_LOGIC; d9 : out STD_LOGIC); end bcdtodecimal; architecture decoder of bcdtodecimal is begin d0<=(( not a3) and (not a2 )and (not a1)and (not a0)); d1<=(( not a3) and (not a2 )and (not a1)and ( a0)); d2<=(( not a3) and (not a2 )and ( a1)and (not a0)); d3<=(( not a3) and (not a2 )and ( a1)and ( a0)); d4<=(( not a3) and ( a2 )and (not a1)and (not a0)); d5<=(( not a3) and (a2 )and ( not a1)and ( a0)); d6<=(( not a3) and ( a2 )and ( a1)and (not a0)); d7<=(( not a3) and ( a2 )and ( a1)and (a0)); d8<=(( a3) and (not a2 )and (not a1)and (not a0)); d9<=(( a3) and (not a2 )and (not a1)and ( a0)); end decoder;

4.MULTIPLEXER
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8_1 is Port ( i0 : in STD_LOGIC; i1 : in STD_LOGIC; i2 : in STD_LOGIC; i3 : in STD_LOGIC; i4 : in STD_LOGIC; i5 : in STD_LOGIC; i6 : in STD_LOGIC; i7 : in STD_LOGIC; s2 : in STD_LOGIC; s1 : in STD_LOGIC; s0 : in STD_LOGIC; y : out STD_LOGIC);

end mux8_1; architecture dataflow of mux8_1 is begin y<=(((not s2)and (not s1) and (not s0) and i0) or((not s2)and (not s1) and ( s0) and (i1)) or ((not s2)and ( s1) and (not s0) and (i2)) or ((not s2)and ( s1) and ( s0) and (i3)) or ((s2)and (not s1) and ( s0) and (i4)) or (( s2)and (not s1) and ( s0) and (i5)) or ((not s2)and ( s1) and (not s0) and (i6)) or (( s2)and ( s1) and ( s0) and (i7))); end dataflow;

5.PRIORITY ENCODER(DECIMAL TO BINARY)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity parityen is

Port ( d1 : in STD_LOGIC; d2 : in STD_LOGIC; d3 : in STD_LOGIC; d4 : in STD_LOGIC; d5 : in STD_LOGIC; d6 : in STD_LOGIC; d7 : in STD_LOGIC; d8 : in STD_LOGIC; d9 : in STD_LOGIC; a3 : out STD_LOGIC; a2 : out STD_LOGIC; a1 : out STD_LOGIC; a0 : out STD_LOGIC); end parityen; architecture dataflow of parityen is begin a0<=((d1 and(not d2) and (not d4) and (not d6) and (not d8)) or(d3 and (not d4) and (not d6) and (not d8)) or (d5 and (not d6) and (not d8)) or (d7 and (not d8)) or d9); a1<=((d2 and (not d4) and (not d5) and (not d8) and (not d9)) or (d3 and (not d4) and (not d5) and (not d8) and (not d9)) or (d6 and (not d8) and (not d9)) or (d7 and (not d8) and (not d9))); a2<=((d4 and (not d8) and (not d9)) or (d5 and (not d8) and (not d9)) or (d6 and (not d8) and (not d9)) or (d7 and (not d8) and (not d9))); a3 <=(d8 or d9); end dataflow;

STRUCTURAL MODELLING

1.FULL ADDER

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder is Port ( k : in STD_LOGIC; l : in STD_LOGIC; cin : in STD_LOGIC; sout : out STD_LOGIC; cout : out STD_LOGIC); end fulladder; architecture Structural of fulladder is component halfadder_str_us_xor Port ( a: in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end component; component orgate Port ( a4: in STD_LOGIC; b4 : in STD_LOGIC; c4 : out STD_LOGIC); end component; signal s1,g,h:STD_LOGIC; begin L0:halfadder_str_us_xor port map(k,l,s1,g); L1:halfadder_str_us_xor port map(s1,cin,sout,h); L2:orgate port map(g,h,cout); end Structural;

PROGRAM FOR COMPONENT halfadder library IEEE; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder_str_us_xor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC;

carry : out STD_LOGIC); end halfadder_str_us_xor; architecture Structural of halfadder_str_us_xor is component xorgate Port ( a1 : in STD_LOGIC; b1 : in STD_LOGIC; c1 : out STD_LOGIC); end component; component andgate Port ( a2 : in STD_LOGIC; b2 : in STD_LOGIC; c2 : out STD_LOGIC); end component; begin L0:xorgate port map(a,b,sum); L1:andgate port map(a,b,carry); end Structural; PROGRAM FOR COMPONENT xorgate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorgate is Port ( a1 : in STD_LOGIC; b1 : in STD_LOGIC; c1 : out STD_LOGIC); end xorgate; architecture dataflow of xorgate is begin c1<=(a1 and (not b1))or(b1 and(not a1)); end dataflow; PROGRAM FOR COMPONENT andgate library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate is Port ( a2 : in STD_LOGIC; b2 : in STD_LOGIC; c2 : out STD_LOGIC);

end andgate; architecture dataflow of andgate is begin c2<= a2 and b2; end dataflow;

2.BIDIRECTIONAL SHIFT REGISTER

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BDSR is Port ( din : in STD_LOGIC; rl : in STD_LOGIC; clk : in STD_LOGIC; q1 : buffer STD_LOGIC; q2 : buffer STD_LOGIC; q3 : buffer STD_LOGIC; q4 : buffer STD_LOGIC); end BDSR; architecture Structural of BDSR is component dff Port ( clk1 : in STD_LOGIC; d : in STD_LOGIC; q : buffer STD_LOGIC); end component;

component andgate Port ( a : in STD_LOGIC; b : in STD_LOGIC; c: out STD_LOGIC); end component; component orgate Port ( a1 : in STD_LOGIC; b1 : in STD_LOGIC; c1: out STD_LOGIC); end component; component notgate Port ( a2 : in STD_LOGIC; c2: out STD_LOGIC); end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13: STD_LOGIC; begin l0:notgate port map(rl,s1); l1:andgate port map(din,rl,s2); l2:andgate port map(s1,q2,s3); l3:orgate port map(s2,s3,s4); l4:dff port map(clk,s4,q1); l5:andgate port map(rl,q1,s5); l6:andgate port map(s1,q3,s6); l7:orgate port map(s5,s6,s7); l8:dff port map(clk,s7,q2); l9:andgate port map(rl,q2,s8); l10:andgate port map(s1,q4,s9); l11:orgate port map(s8,s9,s10); l12:dff port map(clk,s10,q3); l13:andgate port map(rl,q3,s11); l14:andgate port map(s1,din,s12); l15:orgate port map(s11,s12,s13); l16:dff port map(clk,s13,q4); end Structural;

PROGRAM FOR COMPONENT dff

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is

Port ( clk1 : in STD_LOGIC; d : in STD_LOGIC; q : buffer STD_LOGIC); end dff; architecture Behavioral of dff is begin process(clk1) begin --q<='0'; if(clk1'event and clk1='1')then q<=d; else if(clk1'event and clk1='0')then q<=q; end if; end if; end process; end Behavioral;

PROGRAM FOR COMPONENT andgate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end andgate; architecture Dataflow of andgate is begin c<=(a and b); end Dataflow;

PROGRAM FOR COMPONENT orgate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is

Port ( a1 : in STD_LOGIC; b1 : in STD_LOGIC; c1 : out STD_LOGIC); end orgate; architecture Dataflow of orgate is begin c1<=( a1 or b1); end Dataflow;

PROGRAM FOR COMPONENT notgate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity notgate is Port ( a2 : in STD_LOGIC; c2 : out STD_LOGIC); end notgate; architecture Dataflow of notgate is begin c2<=( not a2); end Dataflow;

For rl=0(shift left)

For rl=1(shift right)

#EXERCISE (FULLADDER,HALF
GENERATOR,PARITY

ADDER,HALF

SUBSTRACTOR,MULTIPLEXER SUBSTRACTOR,MULTIPLEXER DIGITAL

,ALL

GATES,COUNTER,COMPLEX ,DECODER,ENCODER,KMAP UNIT))

CKTS,FLIPCKTS,FLIP-FLOP,PARITY ,DEMULTIPLEXER TO AND GRAY LOGICAL

CHECKER PROBLEMS,BINARY

CONVERSION,REGISTER,COMPARATOR,ALU(ARITHEMATIC