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1.
Introduction
The SAMA5D3 series is a member of the Atmel microprocessor family which is based on the ARM Cortex-A5 processor core. This Application Note outlines the Gigabit Ethernet function embedded on SAMA5D3 Series.
2.
Associated Documentation
Before going further into this document, please refer to the latest documentation for the corresponding SAMA5D3 devices available on the Atmel web site at http//:www.atmel.com. SAMA5D3 Series Datasheet: lit 11121 SAMA5D3-EK User Guide: lit 11180
3.
11164AATARM31-Jan-13
Support for Jumbo Frames up to 10240 Bytes Full Duplex Flow Control with Recognition of Incoming Pause Frames and Hardware Generation of Transmitted Pause Frames Half Duplex Flow Control by Forcing Collisions on Incoming Frames Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames Support for 802.1Qbb Priority-Based Flow Control Programmable Inter Packet Gap (IPG) Stretch Recognition of IEEE 1588 PTP Frames IEEE 1588 Time Stamp Unit (TSU) Support for 802.1AS Timing and Synchronization
4.
Table 4-1.
GMAC Connections in Different Modes Function Transmit Clock or Reference Clock 125 MHz input Clock 125 MHz output Clock Transmit Enable Transmit Data Transmit Coding Error Receive Clock Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output TXCK Not Used Not Used TXEN TXD[3:0] TXER RXCK RXDV RXD[3:0] RXER CRS COL MDC MDIO MII GMII Not Used 125 MHz Ref Clk TXCK TXEN TXD[7:0] TXER RXCK RXDV RXD[7:0] RXER CRS COL MDC MDIO TXCK 125 MHz Ref Clk Not Used TXCTL TXD[3:0] Not Used RXCK Not Used RXD[3:0] RXCTL/RXDV Not Used Not Used MDC MDIO RGMII
Signal Name GTXCK G125CK G125CKO GTXEN GTX[7..0] GTXER GRXCK GRXDV GRX[7..0] GRXER GCRS GCOL GMDC GMDIO
Figure 4-1. Connection between Ethernet PHY and Ethernet MAC in the MII/GMII Mode.
Figure 4-2. Connection between Ethernet PHY and Ethernet MAC in the RGMII Mode
5.
Channel
IN IN IN IN
Received clock Received data Signifies that received data is valid Signifies that received data has errors
CRS COL
IN IN
Carrier Sense (half-duplex connections only) Collision Detect (half-duplex connections only)
PHY Management
MDCK MDIO
OUT INOUT
Note:
1.
Direction is defined from the chip side: IN = PHY to MAC, OUT = MAC to PHY.
6.
Channel
IN IN IN IN
Received clock Received data (4 bits more than MII) Signifies that received data is valid Signifies that received data has errors
CRS COL
IN IN
Carrier Sense (half-duplex connections only) Collision Detect (half-duplex connections only)
PHY Management
MDCK MDIO
OUT INOUT
Note:
1.
Direction is defined from the chip side: IN = PHY to MAC, OUT = MAC to PHY.
7.
Channel Clock
Transmit clock (generated by the MAC with master clock GTXCK): 2.5 MHz for 10 Mbit/s, 25 MHz for 100 Mbit/s and 125 MHz for 1000 Mbit/s Data to be transmitted Transmitter enable / Transmitter error
IN IN IN
Received clock: 2.5 MHz for 10 Mbit/s, 25 MHz for 100 Mbit/s and 125 MHz for 1000 Mbit/s Received data Signifies that received data has errors
PHY Management
MDCK MDIO
OUT INOUT
Note:
1.
Direction is defined from the chip side: IN = PHY to MAC, OUT = MAC to PHY.
8.
Routing Considerations
The user should refer to the design and layout guidelines of the PHY provider.
8.1
SAMA5D3 Example
This example shows how SAMA5D3-EK connects to KSZ9021GN PHY. The functional mode is defined by the software. PHY is configured to operate in GMII, RGMII or MII mode, according to the chosen hardware connection.
Figure 8-1. Functional Connection.
Revision History
In the table that follows, the most recent version of the document appears first. rfo indicates changes requested during the document review and approval loop.
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