pubs.acs.

org/NanoLett

High-Performance Flexible Graphene Field Effect Transistors with Ion Gel Gate Dielectrics
Beom Joon Kim,, Houk Jang,,, Seoung-Ki Lee,, Byung Hee Hong,,| Jong-Hyun Ahn,*,, and Jeong Ho Cho*,
Department of Organic Materials and Fiber Engineering, Soongsil University, Seoul 156-743, Korea and SKKU Advanced Institute of Nanotechnology (SAINT) and Center for Human Interface Nano Technology (HINT), School of Advanced Materials Science and Engineering, and | Department of Chemistry, Sungkyunkwan University, Suwon 440-746, Korea
ABSTRACT A high-performance low-voltage graphene eld-effect transistor (FET) array was fabricated on a exible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 ( 57 and 91 ( 50 cm2/(Vs), respectively, at a drain bias of -1 V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical exibility. This method represents a signicant step in the application of graphene to exible and stretchable electronics. KEYWORDS Graphene, ion gel, exible electronics, eld effect transistor, low-voltage operation

raphene has attracted attention for a range of electronic applications, such as displays, solar cells, and sensors owing to its exceptional electronic and optoelectronic properties.1-4 Recent developments in the large area synthesis of high-quality graphene lms has created new pathways for the application of graphene to highfrequency devices.5-7 There are two general approaches for fabricating graphene devices over large areas: one that employs graphene grown directly on SiC wafers8 and another that transfers graphene lms synthesized on metal layers to other useful substrates.9,10 The latter approach is attractive because of the special attributes of graphene lms, such as exible/stretchable device fabrication and the possibility of fabrication over large areas. This approach has produced device arrays on rigid insulating wafers and is scalable to a wafer size.9 Although several studies have reported graphene eld-effect transistors (FETs) on a plastic substrate,11 there are still signicant challenges in fabricating large scale, exible graphene FETs. Exploring graphene for exible electronics requires solution-processable, high-capacitance gate dielectrics that can form at low temperature with a good interface with the graphene lms transferred to plastic sheets. Although several high-k inorganic dielectrics, such as HfO2, Al2O3, and ZrO2, have been applied to the fabrication of graphene FETs, they cannot be available for exible devices based on plastic substrates due to their high growth temperature.8,12,13

This paper reports a promising method for fabricating a low-voltage operating graphene FET array on plastic substrates using an ion gel as the gate dielectric. The ion gel consists of a room temperature ionic liquid and gelating triblock copolymer, which exhibits an extremely high capacitance of 5.17 F/cm2.14-16 The high capacitance of the ion gel gate dielectrics in the graphene FETs provides both high on-current and low voltage operation. Furthermore, ion gel gated graphene FETs fabricated on plastic substrates show very good mechanical exibility. Before the fabrication of exible graphene FETs on plastic substrate, we built typical bottom-gated graphene FETs on a SiO2/Si wafer and top-gated devices with ion gel gate dielectrics, to examine the performance of graphene lms and compare the characteristics of SiO2 and ion gel dielectrics. Figure 1a shows the transfer characteristics (ID-VG) of the graphene FETs fabricated on the SiO2 dielectrics (t 300 nm). The channel width (W) and length (L) were 10 and 20 m, respectively. The graphene lms were synthesized by a chemical vapor deposition (CVD) method;9,17 the detailed procedure will be explained later. The hole and electron mobility were calculated from the linear regime of the transfer characteristics using

ID )

W C V (V - Vth) L i D G

* Corresponding authors, jhcho94@ssu.ac.kr and ahnj@skku.edu.

B. J. Kim and H. Jang contributed equally to this work. Received for review: 05/3/2010 Published on Web: 08/12/2010
2010 American Chemical Society

where Ci is the specic capacitance of the dielectric, Vth is the threshold voltage, and is the eld-effect mobility. The calculated hole and electron mobility were 828 ( 58 and 189 ( 42 cm2/(Vs) at VD ) -1 V, respectively. In addition, electron conduction of the graphene FETs was quite weak
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DOI: 10.1021/nl101559n | Nano Lett. 2010, 10, 34643466

FIGURE 2. Schematic diagram of the steps used to fabricate the ion gel gated graphene transistor array on a plastic substrate.

FIGURE 1. Electrical properties of graphene FETs fabricated on a rigid substrate. (a) Current-voltage transfer characteristics of the bottomgated graphene FETs on SiO2/Si wafer at a drain-source bias of VD ) -1 V. The inset indicates the geometry of the graphene FETs. The channel width and length of the device were 10 and 20 m, respectively. (b) Output characteristics of the devices at ve different gate voltages. (c) Transfer characteristics of top-gated graphene FETs with ion gel gate dielectrics at ve different VD. Inset shows the geometry of ion gel gated graphene FETs. (d) Output characteristics of ion gel gated devices.

and the Dirac point was approximately +40 V. Such asymmetry in the mobility of the two carrier and the shift in the Dirac point can be explained by the different scattering cross sections for electrons and holes and the electric elds created by charged impurities on the SiO2 substrate, respectively.18-20 Figure 1b shows the output characteristics (ID-VD) of the SiO2-gated graphene FETs at ve different gate voltages (VG). The device showed a clear increase in conductance induced by the gate voltage and completely linear behavior, which is typical for metal/zero band gap semiconductor junctions. The gate dielectric is the key element of graphene devices because of its important role in determining the operating voltage range. Although HfO2 or Al2O3 formed by atomic layer deposition (ALD) are natural choices, the thermal limitation of plastic substrates has impeded the use of ALD processes. Ion gel gate dielectrics with high capacitance that can be formed at low temperatures can serve as robust gate dielectrics in graphene transistors. Ion gels provided a specic capacitance of 5.17 F/cm2 at 10 Hz, which was much larger than the typical values for 300 nm thick SiO2 dielectrics (we will explain the ion gel dielectric formation later). This extraordinary high capacitance of the ion gel is due to the formation of an electric double layer, only nanometers in thickness, at both the ion gel/
2010 American Chemical Society

graphene and ion gel/gate electrode interfaces under an electric eld. Figure 1c shows the transfer characteristics of the topgated graphene transistors fabricated using ion gel gate dielectrics at ve different VD. Characteristic V-shaped ambipolar behavior was obtained, where a positive and negative VG region represents electron and hole transport, respectively. The average hole and electron mobility were 320 ( 35 and 135 ( 26 cm2/(Vs) at VD ) -1 V, respectively. This decrease in carrier mobility of the ion gel gated graphene transistors may be due to two effects. One is the polymer residue that remains on the graphene surface after the transfer printing of graphene on the substrate. The other is the surface roughness of the graphene lms; the graphene/ion gel interfaces are rougher than the graphene/ SiO2 interfaces. Moreover, compared to SiO2 gate dielectrics, the asymmetric factor between hole and electron conduction decreased dramatically and the Dirac point shifted to almost zero because the counterions in the ion gel neutralize the charged impurities trapped on the SiO2 substrate.19,20 The output characteristics of the ion gel gated graphene transistors in the device showed reasonable drain current modulation with VG (Figure 1d). The drain current at VG ) -4 V and VD ) -1 V was approximately 2.4 mA. This is much higher than that of SiO2-gated transistors (0.4 mA at VG ) -40 V and VD ) -1 V) and is a direct result of the large capacitance of the ion gel gate dielectrics. A key advantage of graphene lies in its extremely attractive mechanical properties, which are essential for achieving exible and stretchable electronics.1,4,5 To demonstrate such attributes of graphene, an ion gel gated graphene FET array was fabricated on a exible poly(ethylene terephthalate) (PET) sheet. Figure 2 shows a schematic diagram of the fabrication steps of the ion gel gated graphene transistor array on a plastic substrate. In the rst step, large-area, high-quality graphene lms were grown on a rectangular piece of Cu foil (25 m thick) using the procedures described elsewhere.9,17 Mainly monoand bilayers of graphene were grown on the Cu foil. Poly(methyl methacrylate) (PMMA) polymer supports were coated on the graphene lms on the metal layers to allow the transfer of graphene lms from the Cu foil to the plastic substrate. The
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DOI: 10.1021/nl101559n | Nano Lett. 2010, 10, 3464-3466

FET arrays (total 50 devices) on PET. A Gaussian t indicates a hole and electron mobility of 203 ( 57 and 91 ( 50 cm2/Vs, respectively, at a drain bias of -1 V. All measurements were performed under ambient conditions. Mechanical exibility and robustness are important characteristics for the application of graphene FETs in exible electronics. A symmetric bending test was performed on the graphene FET array. Figure 3d shows the change in effective carrier mobility, normalized to the value of the graphene FETs under the unbent condition. Only 20% changes in /o were observed as the bending radius was changed from 6 to 0.6 cm. In summary, graphene lms combined with ion gel dielectrics provide an important route to mechanically exible, high-performance, and low-voltage graphene devices. Graphene technology may create opportunities for devices requiring unusual form factors, such as mechanical exibility or stretchability. Acknowledgment. This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2009-0082608, 2010-0015035, 2009-0073278, 2009-0081966) and Industrial Source Technology Development Programs from the Korea Ministry of Knowledge Economy (No. 10033309).
FIGURE 3. Electrical and mechanical properties of ion gel gated graphene FETs fabricated on a exible plastic substrate. (a) Optical images of an array of devices on a plastic substrate. (b) Transfer and output characteristics of graphene FETs on plastic substrate. In output curve, the gate voltage was varied between +2 and -3 V in steps of -1 V. (c) Distribution of the hole and electron mobility of graphene FETs. (d) Normalized effective mobility (/o) as a function of the bending radius.

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DOI: 10.1021/nl101559n | Nano Lett. 2010, 10, 3464-3466

supports adhering to the foil were then soaked with wet etchants to remove the metal layers. These lms were then delivered by transfer printing to a PET sheet containing the source and drain electrodes (Cr/Au, 10 nm/60 nm) formed by thermal evaporation. The device patterns of the graphene lms were formed by photolithography and reactive ion etching (RIE) with O2 plasma. For ion gel gate dielectric formation, poly(styrene-block-methyl methacrylate-block-styrene) (PS-PMMA-PS) triblock copolymer and 1-ethyl-3-methylimidazolium bis(triuoromethylsulfonyl)imide ([EMIM][TFSI]) ionic liquid were dissolved in methylene chloride at a 0.7:9.3:90 ratio (w/w) and then drop-casted onto a graphene pattern with an Au source and drain contact. After the solvent was removed, an ion gel lm was formed through physical association of the PS blocks in ionic liquid. The top gate electrodes (Au, 100 nm) were evaporated thermally through shadow masks. Parts a and b of Figure 3 show the exibility of the resulting device substrate as well as the transfer and output characteristics of the graphene FETs on PET. There were no signicant differences in the mobility and on-current compared to that fabricated on the Si wafer. It is evident that the device operates at low voltage (<-3 V) with a high oncurrent, and the Dirac point is almost zero. Figure 3c shows the distribution of the hole and electron mobility of graphene
2010 American Chemical Society

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