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IEEE TRANSACTIONS ON INSTRUMENTATION A N D MEASUREMENT, VOL. 44,NO. 3, JUNE 1995

647

Oversampled Interface for IC Sensors with Minimized Analog Content

Carlos Azeredo Leme, Pier0 Malcovati, and H e n r y Baltes, Member, ZEEE
Abstract-In this paper we present a new oversampled modulator architecture for A/D conversion. This modulator allows a great simplification of the analog front-end circuits at the expense of a more complex digital signal processing for the bit stream decoding. Moreover, the system can be partitioned into two blocks communicating through noise-immune signal lies. These two features are very advantageous for sensor interfaces in remote locations and where only a minimal amount of circuitry can be cointegrated with the sensor.
Fig. 1. Block diagram of the proposed circuit.

L--*F-V,

I. INTRODUCTION

ONTINUING improvements in CMOS technology have been opening new areas of application in microelectronics. Microsensor systems are an example, where the sensor is integrated together with support and interface circuits on the same chip [l], [2] An important advantage of using industrial IC processes for microsensor fabrication is that high performance and wellcharacterized IC components and libraries are readily available [3]. This makes possible the cointegration on the sensor chip, of signal conditioning and interfacing functions [4]. In a microsensor the interface circuits are an essential part of the integrated system. It is the presence of on-chip signalprocessing capability that gives the microsensor most of its advantages [5]-[7]. But, in many sensor applications, the close proximity of the sensor device may affect the performance of the IC components, more specifically in the analog circuits. Moreover, the requirements on the microsensor interface are very demanding. In certain sensor applications, it is not possible to include more than only a minimal amount of circuitry on-chip. Examples are sensors using sophisticated fabrication processes. In these cases, the process is not optimized for IC device and their parameters are not well controlled. Another example is a sensor located in a very harsh environment causing important degradation of the on-chip cointegrated IC devices. Therefore, there is a need for a novel interface architecture requiring only a minimal amount of analog circuitry. Ideally, it should provide the performance of the second-order sigmadelta modulator, but using a less complex modulator, like that of the first-order modulator.

11. SYSTEM

A F a U T E ~

The architecture we propose is illustrated with the block diagram shown in Fig. 1. It is based on the conventional second-order sigma-delta modulator [8]. The difference is that the comparator has been moved to the input of the second integrator. This allows a digital implementation of this integrator with a simple up/down counter. The analog content of the system is reduced to a single integrator and a comparator, as in the first-order modulator. But the dynamic range is comparable to that obtainable with a second-order modulator, for the same oversampling ratio. The drawback is that the feedback D/A converter is no longer an inherently linear 1-bit circuit. In order to make this architecture of practical value, an altemative implementation of the feedback loop must be found. This problem is solved with the circuit architecture shown in different D/A converter circuits are used, one Fig. 2 [9]. W O in each feedback loop. For the inner feedback loop, we employ a conventional multibit D/A converter. Any nonlinearity in this component is divided by the first integrator gain, when referred to the input. This factor is, at least, equal to the oversampling ratio. Therefore, no stringent linearity requirements are demanded on the D/A converter. On the other hand, the D/A converter in the outer feEdback loop determines the overall system linearity. It is implemented with a 1-bit D/A converter and a truncator circuit that translates the L-bit word into a 1-bit word at a higher sampling frequency, RFs. This truncator circuit consists of a digital first-order sigma-delta modulator. This arrangement makes possible the implementation of an inherently linear D/A converter at the expense of higher operating speed and Manuscript received May 10, 1994; revised February 3, 1995. i r c u i t s and Systems Group, an additional high-frequency quantization noise source. The C. Azeredo Leme is with the Integrated C Instituto Superior T&nico, DEEC, AV. Rovisco Pais, 10% Lisboa Codex, baseband component of this noise can be made sufficiently Portugal. low by increasing the secondary oversampling ratio R. P. Malcovati and H. Baltes are with the Physical Electronics Laboratory, This architecture has the propem that it can be segmented ETH-Hoenggerberg, HPT-H6, 8093 Zurich, Switzerland. IEEE Log Number 941 1493. into two separate blocks, one at the source site and the other at
0018-9456/95$04.00 0 1995 E E E

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 44, NO. 3, JUNE 1995

Sensor site

Acquisition site

P Invut

qFs :

Fig. 3. Linearized signal flow graph of modulator.

power is
Fig. 2. Block diagram of complete system

the data acquisition site. The block at the source site consists of a simple analog circuit, which can be easily cointegrated with the sensor device. The second block is the high-speed digital signal processor and is implemented at the data acquisition site. The communication between the two blocks is processed solely through two digital lines and a noncritical analog line. A high degree of immunity to interference is thus obtained which makes possible the placement of the interface front-end on a remote and noisy location. The advantages offered by this approach are as follows: The circuit at the source site can be easily cointegrated on the same chip since it requires only very simple analog components and its operation is very robust. The source site can be located at a physically remote point as the communication with the data acquisition site is carried out already in a noise-immune digital format. These properties make this interface architecture very advantageous for sensor systems in remote and harsh environments.
111. CIRCUIT ANALYSIS

which we assume to be white. The transfer function to the output is

We use a positive representation of frequency, and the power of a sampled signal is assumed to be contained in the frequency band 0 to Fs/2. The power spectrum of the quantization noise at the output is then

(3)
and the in-band power B , assuming an oversampling ratio M = Fs/2B, is
(4)

where the first three order terms in the series expansion of (3) were kept. B. Input Limits Since the first derivative of the input signal is quantized, it is the signal slope that is limited and not its amplitude. The maximum slope occurs for a sinusoid of maximum amplitude, VA,at the baseband limit, and it must satisfy the condition

The linearized signal flow graph of the circuit is shown in Fig. 3, where the comparator is modeled as an additive noise source, and the D/A converters are considered ideal. It can be immediately recognized that this structure is similar to a conventional second-order noise-shaping modulator where the quantizer has been moved to the input of the second integrator stage. Therefore, the signal transfer function is unchanged and retains unity. The main difference is that now the quantized variable is the first derivative of the input signal. As will be shown next, the signal-to-noise ratio in the baseband for this architecture is very close to that obtainable with the conventional one. The circuit analysis will be divided into three parts. First the quantization noise is calculated. Next, the input signal amplitude limits are defined. Finally, the effect of the secondary quantization noise introduced by the oversampled D/A converter is studied.

or

M VA = - A .
21r

The full-scale signal power is then given by

E O =1 - ( -M .>.
2
2T

(7)

C. Secondary Quantization Noise

The shaped quantization noise generated by the secondary modulator can be considered as an additive noise source at the system input. We consider a first-order loop with step size equal to 2 v A and running at an oversampling rate RFs. Its power spectrum is given as [8]

A. Quantization Noise
For a comparator step size A (meaning that the comparator output states are + A / 2 and - A / 2 ) , the quantization noise

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AZEREDO LEME et a l . : OVERSAMPLED INTERFACE FOR IC SENSORS WITH

ANALOG CONTENT

649

with

(9) 12 . At the input of the first integrating stage, the sample rate is reduced down to Fs by averaging all R samples. This operation is equivalent to R : 1 decimation, preceded by the filter 11-z-R TQ2(z) = - (10) R 1 - z-1.
This corresponds to the transfer function in frequency
Fig. 4. Implemented prototype.

(2VAI2 E Q= ~-

The effect of decimation is to fold back the frequency range [O; RFs] into the frequency range [O; Fs]. The transfer function from there to the output is unity. The power spectrum of the secondary quantization noise at the output is, then, given by

showing a degradation of a mere 2.2 dB relative to the conventional sigma-delta modulator. As a final remark, we note that the optimum sinc filter in the digital decimator is of order two since, from (3), the quantization noise is first-order shaped. Therefore, the complexity of the decimator filter is relaxed when compared with the conventional second-order sigma-delta modulator that requires a third-order sinc filter.

IV. EXPEWMENTAL RESULTS

-*I)%(
- R F s / 2 R [Zsin

and the power in the band is

D. Design Guidelines The design parameters for this system are the oversampling ratios, M and R, and the comparator step size, A. The system specifications are defined by the maximum input amplitude, A , desired signal-to-noise ratio, SNR, and bandwidth, B. The design equations are then

We implemented the system in a 1.2 pm CMOS technology. Extensive experimental measurements confirm the theoretical analysis [9]. The block diagram of the system is shown in Fig. 4. The system was designed for an oversampling ratio of M = 64 and a secondary oversampling ratio of R = 16. The input signal swing is ~ V = A f l V, resulting in a comparator step size equivalent to A = 0.1 V. The complete signalprocessing functions for the data acquisition site are included on the chip. This corresponds to the right side of the figure. Only the sensor site front-end need be designed for different applications. For testing we used the circuit shown in the left side of the figure. A continuous-time integrator was used as an alternative to the discrete-time one. The design equations are 1 RC=(18)

Fs

M2

32 VREF = - VA. 21

(19)

and VA = - A .
2T

A conventional second-order modulator has a signal-to-noise ratio given by [SI

2T4 As a comparison, in the case when the primary quantization noise, PQ1, is dominating, (14) simplifies to

15M5 SNR= -

A return to zero circuit, R/Z, is included at the output of the secondary sigma-delta modulator. This eliminates any nonlinearity error arising due to the nonzero waveform rise and fall times driving the 1-bit D/A converter switch. The 50% duty cycle is compensated for by doubling the value of the reference voltage, as shown in Fig. 4. The prototype output signals were acquired with a National Instruments board NB-BIO-32F into a Macintosh computer. Then the data was analyzed with the MATLAB program. Due to the limited operating speed of the board, the clock frequency was limited to FS = 16 kHz. The baseband is, then,
2M The implementation of the digital sigma-delta modulator of first order allows only the equivalent reference voltage

Fs B = - = 125Hz.

9M5 SNR= 2T4

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT. VOL. 44, NO. 3, JUNE 1995

V. CONCLUSIONS In this paper we have demonstrated a new architecture for A/D conversion. It achieves a performance close to the second-order noise-shaping modulator, but with a much lower analog content. This comes at the expense of high-speed digital processing which can be located in a different site. This allows the integration of high-performance signal conversion in application areas such as microsensor systems or remote signal acquisition where the full A/D converter cannot easily be integrated on-chip.
REFERENCES [ l ] H. Guckel and D. Bums, Fabrication techniques for integrated sensor microstructures, in Con! Rec. IEEE Electron Devices Meeting, 1986, pp. 176179. [2] K. M. Mahmoud and R. F. Wolffenbuttel, Compatibility between readout electronics and microstructures in silicon, Sensors and Actuators A, vol. 31, pp. 188-199, 1992. [3] H. Baltes, Microtransducers by industrial IC technology and micromaTokyo, Japan, May 30-31, chining, in Tech. Dig. loth Sensor Symp., .~ . . 1991, i p . 17-23, invited paper. 141 . . E. Hogenbirk, H. Verhoeven, and J. Huiising, An integrated smart sensorfor flow and temperature with 12C bus interface bas& on thermal sigma-delta modulation, in Transducers93 Cont Rec. 7th Int. Con! Solid-state Sensors and Actuators, 1993, pp. 792-795. [5] J. Huijsing, F. Riedijk, and G. van der Horn, Developments in integrated smart sensors, in Transducers93 Con! Rec. 7th Int. Con! Solid-state Sensors and Actuators, 1993, pp. 320-326. [6] C. Azeredo Leme and H. Baltes, Interfaces for microsensor systems, in Advances in Analog Circuit Design. Katholieke Universiteit Leuven, Kluwer Academic, 1993, to be published. [7] -, Multi-purpose interface for sensor systems fabricated by CMOS technology with post-processing, Sensors and Actuators, vol. A37-38, pp. 77-81, Oct. 1993. [8] J. C. Candy, A use of double integration in sigma delta modulation, IEEE Trans. Commun., vol. COM-33, pp. 249-258, Mar. 1985. 191 C. A. Leme, P. Malcovati, and H. Baltes, An oversampled modulator for A/D conversion with minimized analog content, in Proc. IEEE ISCAS94, London, UK, May 1994, pp. 381-384.

j .-

-75

-10

0.1

Frequency [Hz] Fig. 5. Measured spectrum at the modulator output.

FquenCy[Hz] Fig. 6. Measured spectrum at the decimator output.

restricted to a power of two of the LSB of the input digital fl word. Therefore, we cannot use the nominal values ~ V =A V. Instead we used VREF = f 3 2 / 2 1 V, corresponding to L = 6. This leads to an increase of 3.7 dB in the secondary quantization noise. The resulting baseband noise power levels, predicted by (4) and (13) with the referred correction, are

p1 = i o . 1 0 - v2 ~ 2OUT , =4 0 . 1 0 - ~ V
or

PI + P ~ , o u =50.10-9V2, T

-73dBV.

For the analysis, a sample length of 32768 words at the output of the modulator, before decimation, was acquired. The input signal was a sinusoid of 20 mV amplitude and frequency F~/16384.The noise spectrum was calculated by applying an FlT with a Hamming window. The result is shown in Fig. 5. The quantization noise can be isolated by subtracting the extracted sinusoid signal from the output word stream and recalculating the EFT. The resulting noise power in the band is -72.3 dBV, which differs from the theoretical value by a mere 0.7 dB. This corresponds to an equivalent conversion resolution of 11.8 bits with an oversampling ratio of 64.The spectrum at the output decimator filter is shown in Fig. 6. For large-amplitude signals near the edge of the bandwidth there is some degradation of the noise-shaping efficiency. This is not serious, and the same phenomenon happens in conventional sigma-delta modulators.

Carlos Azeredo Leme graduated in electrical engineering at IST, Lisbon, in 1986. In 1990, he received the M.Sc. degree in electronics engineering at the same university. In 1991, he joined the Physical Electronics Laboratory, at ETH Zurich, where he was involved in sensor interfaces, and received the Ph.D. degree from the same university in 1993. Since 1994, he has been with the Group of Integrated Circuits and Systems at IST Lisbon. His main interests are high-resolution A D conversion and analog interfaces for microsensors.

Piem Malcovati was bom in Milan, Italy, in 1968.

He received the Laurea degree (summa cum laude) in electronics engineering from University of Pavia, Italy, in 1992. He is currently a candidate for the Ph.D. degree at the Physical Electronics Laboratory at ETH Zurich, Switzerland, in the area of microsensor interfaces. His main research interests include the design of analog, mixed signal, and data conversion integrated circuits.

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AZEREDO LEME er al.: OVERSAMPLED INTERFACE. FOR IC SENSORS WITH MINIMlzED A N -

CONTENT

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H e n r y Baltes (M'81) received the D.Sc. degree from ETH Zurich in 1971. In the following years he was on the faculty of the Freie Universitat Berlin, the University of Dusseldorf, the University of Waterloo, Ont., Canada, and the &ole Polytechnique Federale de Lausanne (EPFL,). In 1974, he joined Landis & Gyr Zug Corporation, where he became head of the solid-state device laboratory active in microsensor research. From 1975 to 1982, he taught optics, solid state physics, and microsensors at EPFL.. From 1983 to 1988, he held the HenryMarshall Tory Chair at the University of Alberta, Edmonton, Canada, where he directed a research program in microsensors. As acting President of the Alberta Microelectronic Centre, he was in charge of the establishment of a CMOS fabrication facility. From 1986 to 1988, he also was a Director of LSI Logic Corporation of Canada. Since 1988 he has been Professor of Physical Electronics at ETH Zurich and head of ETH's Physical Electronics Laboratory active in silicon microsensors. In 1991, he joined the Board of Directors of Ascom Microelectronics and was appointed Director of the Swiss Federal Wority Program LESIT. He authored or coauthored more than 250 publications in scientific or technical journals, 15 patents, and 4 books. He is an associate editor of Sensors and Materials and the Jounuzl of Micromechanics and Micmengineering. Dr. Baltes is a member of the Optical Society of America, the Institute of Physics, the Electrochemical Society, the Swiss Information Technology Society, the Swiss Electmtechnical Association, the Swiss Society for Sensor Technology, and the Swiss Physical Society.