Self Oscillating Class-D Audio Amplier with Regulated Half Bridge Power Supply

MIT 6.100 Lab Report Michael Price Advisor: Ron Roscoe Dec. 14, 2005
Abstract In the interest of investigating more energy-ecient circuit technologies and new concepts for highdelity audio, I have designed and built a complete audio amplier system using switching electronics to accomplish accurate output with very low losses. The equipment is smaller and lighter, and the audio performance is similar, compared to well-designed linear power ampliers. This report details three circuits: a power factor correction (PFC) stage, a half-bridge DC-DC converter, and a self-oscillating Class-D audio amplier. I explain the signicance of each circuits switching converter topology, their expected behavior, construction details, and measured performance.

Contents
1 Introduction 2 Circuit Design 2.1 PFC Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Half Bridge Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Audio Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Magnetic Components 4 PCB and Mechanical Layout 5 Construction Notes and Debugging 3 4 4 5 7 11 14 16

6 Tests and Measurements 18 6.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Audio Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Conclusion 8 Appendix: Schematics and PCB Designs 9 References 23 24 29

Introduction

All ampliers deliver current to a load from their power supplies. Class-A and Class-AB ampliers accomplish this by linear amplication: transistor circuits designed to develop an output voltage proportional to input. The eciency of these ampliers is limited to a theoretical maximum of 78% for sine wave signals because the output devices (regardless of type or output stage topology) must sustain a voltage drop equal to the power supply minus output voltage. In practice, audio ampliers are operated well below their maximum power capabilities, which lowers the eciency even more: a 100W class AB amplier dissipates approximately 12W to deliver 1W. Class-D ampliers accomplish nonlinear amplication by producing a PWM output (switching between V+ and V-) with the duty cycle tightly regulated by feedback. This method is theoretically lossless, and in practice delivers much higher eciency than Class-AB ampliers at all power levels. However, Class-D audio ampliers have delivered limited delity - not only because of the large HF carrier wave in the output signal, but also because it is dicult to control the duty cycle accurately. Most Class-D ampliers, including those using standard triangle-wave PWM generation, tend to generate signicant high order (4th and higher harmonics) distortion because of timing errors. The linear power supplies used to drive ampliers incur fewer losses, but they must be large and bulky due to the 60 Hz power transformer and smoothing capacitors. Switching power supplies, which deliver energy from source to load in short impulses, require much smaller magnetic components because the peak magnetic ux in the transformer is proportional to cycle time. This report describes the design, construction and testing of a high-delity audio amplier capable of 60W into 8 and 120W into 4. For this device I designed three separate circuit boards: (1) a 500W power-factor-correction stage, to smooth the input current drawn from AC mains; (2) a 500W half-bridge converter, to produce mains-isolated 35V rails from the PFC output; and (3) a self-oscillating Class-D power amplier. I discuss the circuit designs, their implementation, and performance below.

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2.1

Circuit Design
PFC Stage

The purpose of a power-factor correction (PFC) stage is to ensure that the device draws a sinusoidal current from the AC mains. Power factor is dened as the ratio of actual load power (in W) to apparent load (in VA) which is the product of RMS current and RMS voltage. In a typical linear power supply, the rectier diodes conduct to the smoothing capacitors during short intervals at the peaks of the AC waveform. The graph below shows voltage and current waveforms for a nominal 35V DC supply delivering 41W to a 30 load. The input current has peaks of 11A and represents 3.1A RMS; the input voltage is 26.5V RMS, for an apparent load of 82VA. The power factor is 0.5. Figure 1: Voltage and current waveforms of standard linear power supply

For a power supply drawing 500 watts, these brief currents can be more than 20A from the AC power lines. This behavior causes a distortion in the mains signal and EMI radiated by mains wiring. A power supply with an ideal power factor of 1 will, in contrast, draw a sinusoidal current in phase with the mains voltage. Besides creating less interference from large current peaks, the PFC-input power supply is a less demanding load for the power company. For these reasons, IEC regulations enforced in Europe and Japan place limits on the THD of input currents, forcing manufacturers to use some form of PFC in most electronic devices. In this amplier I implemented a PFC stage as a non-isolated boost converter, delivering a nominal 390V 4

to the DC-DC converter from an input of 90V to 250V AC. This is a common method, and several varieties of control ICs are designed to provide the appropriate gate drive for a power switch. I used the NCP1653 chip from ONSemi with voltage and current feedback; the power switch is an International Rectier IRFB18N50K MOSFET. I wound the common mode choke and energy storage inductor; see section 3 for details. The converter is intended to provide 500W continuous output power at about 92% eciency. Figure 2: Concept schematic of PFC stage

The circuit directly recties the voltage between AC line and neutral, with no bulk smoothing capacitor. When the transistor is turned on, current is drawn from the AC mains, building up energy in L3. When the transistor M1 is turned o, current ows from L3 into the bulk capacitor or the load. The NCP1653 chip varies the duty cycle in phase with the AC waveform. I used a 0.1 current sense resistor to provide feedback, so the chip can compare the input current with AC voltage. A complete schematic of this stage can be found in the appendix.

2.2

Half Bridge Converter

This circuit accomplishes the task of a standard power supply: converting the high input voltage to the split power supply rails for the amplier, and providing isolation from the AC mains. It is implemented as a 50KHz half-bridge power converter controlled by an ONSemi MC34025 chip. The concept schematic is shown below. One end of the transformer primary is connected at the output of a half bridge formed by two IRFB11N50A MOSFETs. The other end of the primary is connected between two 0.22F capacitors. The capacitors are large enough to hold this node at approximately half of the input voltage. Therefore, the overall voltage across the primary switches between +Vin /2 and Vin /2, instead of +Vin and Vin . In comparison to a push5

Figure 3: Concept schematic of half bridge converter

pull converter, the VDS blocking voltage requirement of the power MOSFETs is halved from 2Vin (800V) to Vin (400V). This is important because lower-voltage MOSFETs have lower gate charge and RDS (on) (0.52 for the 500V-rated IRFB11N50A versus 3.7 for the 900V-rated IRFBF30). These characteristics reduce the switching losses in the power devices. The secondary side of the converter is a typical full-wave rectier bridge. Note that the capacitance on each output rail is only 1000F. This would be insucient for a linear power supply because of the 120Hz ripple, but these capacitors are charged at the switching frequency of 50KHz. It is very important that the supply has low output impedance at high frequencies, so I used Panasonic FC-series capacitors which have low ESR (0.043) and high ripple current capability (2.67A at 100KHz). I used an optoisolator feedback network in conjunction with the MC34025s error amplier to regulate the output to 35V. Part of this network is shown in the gure below, with V1 and V2 representing the positive and negative rail outputs. The diode side of the optoisolator is connected in series with 35k from V+ to V-. A resistor on the phototransistor side develops a voltage proportional to the current through U1. This voltage is connected to the inverting input of the MC34025s error amplier; the noninverting input is connected to an internal 5.1V reference. When the two inputs match, the supply is operating at the correct duty cycle. Therefore Vout = 5.1 35k A R2

where A is the current gain of the optoisolator. I used a 10k potentiometer for R2 to account for the variation

in A (in the PS2701-1 optoisolator, A is specied between 0.5 and 3). For A = 1 and Vout = 35V, R2 should be adjusted to the center position of 5k . Since the output LC lter functions as a 2nd-order lowpass with a corner frequency of 730Hz, much slower than the switching frequency, no extra compensation was needed to ensure stability. Figure 4: Optoisolator feedback network for DC-DC converter

The half-bridge converter needs to accomodate variations in line voltage and load-dependent losses. The conversion ratio of the buck converter is M (D) = D where D is the duty cycle; this isolated half-bridge converter also has the step-down factor from the power transformer. 1 DVin N

Vout = M (D)Vin =

where N is the turns ratio of the transformer. Given a minimum input voltage from the PFC stage of 320V, and the 90% maximum duty cycle of the MC34025, I chose a turns ratio of 4:1. At the nominal input of 390V and 70V across the output rails, the duty cycle should be around 72%. I describe the design of the transformer in more detail in section 3.

2.3

Audio Amplier

In an eort to explore the possibities for high-delity Class-D audio amplication, I designed a circuit based on the UCD self-oscillating topology proposed by Putzeys in May 2005. This circuit relies on a phase-lead compensation network to create a consistent oscillation with feedback taken after the ampliers 2nd-order output ler. The most common Class-D amplier topology compares the input (or error) to a triangle wave, generating a PWM output signal. The triangle wave must be extremely accurate in order to keep distortion low. Many

ampliers built around this topology have been criticized for their poor sound quality in comparison to Class-AB and Class-A ampliers, though some have achieved excellent measured performance: LC Audio of Denmark claims 0.002% at 1W. In any case, this topology has been built in many variations for several years. I instead focused my attention on self-oscillating ampliers, which do not generate a carrier signal. They are designed to oscillate because of positive feedback at the intended switching frequency: where the output applied to negative feedback has a 180 degree phase shift. However, it is dicult to use post-lter feedback in a standard self-oscillating amplier because the output lter introduces almost 180 degrees of phase shift. (This is because the corner frequency of the lter, 30-40KHz, is well below the switching frequencies of 200KHz or higher.) Instead, the feedback is taken from before the LC lter and the loop response is controlled by extra components in the feedback loop (possibly RC lters). The concept of the UCD amplier is shown below. E3 represents the comparator or gain block of the amplier, with the transfer function shown: a gain of 2.75 and a propagation delay of 200ns. Figure 5: Feedback network and output lter for UCD audio amplier

Putzeys derived that the Class-D power stage can be treated as a DC gain block with gain KDC =
1 2Hf b (0) .

The output lter and feedback components must be calculated to achieve the desired switching

frequency and gain given the propagation delay of the comparator. These are functions of the loop response Hloop (s); most importantly, the low-frequency gain is KDC and the switching frequency is the point at which Hloop (s) = . The transfer function is given by:

Hloop (s) = KDC Hdelay (s) Hf ilt (s) Hf b (s)

Hloop (s) = esTdelay

1
Rin 2 Rin +Rf b

1 1+
sLf ilt Rload

s2 L

f ilt Cf ilt

Rin +

Rin Rf b (1+sRpl Cpl ) 1+s(Rpl +Rf b)Cpl

The estimated propagation delay of the comparator, as simulated by LTSpice, is Tdelay = 200ns. Note the delay between the transition of the purple and tan curves in Figure 6. Figure 6: Comparator and gate drive switching waveforms

With the goal of a 400KHz switching frequency and 30KHz output lter cuto with loads from 4 to 16, I selected the following values for these components:

Rin 1.6k

Rf b 7.2k

Rpl 220

Cpl 220pF

Lf ilt 15uH

Cf ilt 1.5uF

Given these component values and a 6 load, the output and loop phase responses should be something like Figure 7. Note how the blue curve, loop phase response, has a bump caused by the phase-lead network; and it crosses -180 degrees around 400KHz. The output phase shift is mostly caused by the LC lter. The amplier section uses a dierential instrumentation amplier input stage with the AD8620 dual opamp. It is not enclosed in the feedback loop of the Class-D power stage. The dierential gain is set to 5, or 14dB; and the overall gain of the amplier is 5 2.75 = 13.75, or 23dB. The comparator is fully discrete, using a 3mA long-tailed pair as suggested by Putzeys. Comparator output signals are fed to gate drivers which provide the appropriate charging current to the IRF540Z power MOSFETs. The schematic of one gate driver is shown below in Figure 8. Each uses two 9

Figure 7: Predicted loop and output phase response

Loop and Overall Phase Response of UCD Amplifier

30

60 Phase (deg)

90

120

160

180

210 1 10

10

10

10 Frequency (Hz)

10

10

BCP53 PNP transistors, one (Q11) to conduct current into the gate at turn-on and one (Q12) to short the gate to source. The turn-o is designed to be very fast to avoid shoot-through (where both high and low MOSFETs are on, shorting V+ to V-); the turn-on speed is limited by R19 to approximately 50ns. Figure 8: Lower gate driver for UCD amplier

The gate driver circuits are supplied by a 12V linear regulator referenced to V-. I added 15V regulated supples based on the LM317 and LM337 to power the opamps. A complete schematic of this amplier can be found in the appendix.

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Magnetic Components

Since inductors and transformers for switching power electronics are not readily available in small quantities, I decided to wind my own. The PFC stage required a common mode choke and a large energy storage inductor; the half-bridge converter required a power transformer and lter inductors; and the audio amplier required a lter inductor. For simplicity I chose toroidal cores for all inductors and E-cores for the transformer. The specications for these devices are shown in the following table.

Component Common Mode Filter Energy Storage Inductor Power Transformer Supply Filter Inductors Audio Filter Inductor

Value any 470H+ 4:1 Turns 47H+ 15H

Construction Balanced toroidal Toroidal E-core Toroidal Toroidal

Power Handling 4A 2A 500W 7A 5A

All of the cores were soft ferrites purchased on Ebay. The number of turns of wire on each coil is derived from the following formula: 0 r n2 Ac (4 107 )(125)(352 )(4.84 104 ) = = 778H lm 0.1197

L=

where n is the number of turns, Ac is the cross sectional area of the core, lm is the magnetic path length (average circumference), and r is the relative permeability of the core material. (The example values are from the PFC energy storage inductor. Note the error in the actual measured value below.) I determined the necessary size of each inductor core by computing the magnetic ux corresponding to the inductance and maximum current, then dividing by the cross sectional area to nd the peak ux density. This density must be signicantly lower than the saturation ux density Bsat of the core material. For example, for the PFC energy storage inductor: (4 107 )(125)(4)(35) 0 r In = = 0.1837 T lm 0.1197

Bmax =

which is less than the saturation ux density, Bsat = 0.235 T, of the material. The core and construction specications of the inductors are summarized below. The inductance of the common mode coil was not critical, only the balancing of the two windings (so that the ux cancels out); so I wound as many turns of 20-gauge wire as would t on the core. Inductance measurements were performed 11

on a GenRad LCR meter. I checked the audio lter inductor (since its accuracy is important) with an HP 4392A impedance analyzer, with similar results. The coils maintain their inductance up to around 1MHz.
Component Common Mode Filter Energy Storage Inductor Power Transformer Supply Filter Inductors Audio Filter Inductor r 125 125 2000 10000 125 Bsat (gauss) 2350 2350 4500 4300 2350 Wire Gauge 20 16 18[p]/16[s] 18 20 Turns 26 35 60[p]/15[s] 2 11 L (H) 71.9 581.2 N/A 65.7 15.154 DCR () 0.043 0.068 N/A 0.012 0.084

I wound the power transformer on the matching plastic bobbin with 60 turns of 18-gauge wire for the primary; a layer of insulating tape; then 15 turns of 16-gauge wire for each of the two secondary windings. Similar to the inductors, the number of turns are optimized for maximum inductance while avoiding core saturation at the maximum primary current of 3A. I tested the transformer to verify that the voltages on the secondary windings were indeed both about of the primary: Measurement Primary Secondary 1 Secondary 2 Series secondaries Parallel secondaries Voltage (AC RMS) 2.187 0.562 0.562 1.202 0.562
1 4

The input-to-output voltage ratio measured here is 3.89 with no load; it will be slightly lower than that under normal operating conditions. The parallel and series measurements show that secondaries are balanced and wound in the correct orientation. These ratios were consistent at frequencies up to about 500KHz.

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Figure 9: Power transformer for 500W half-bridge converter, shown from below. The core is 2.18 square.

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PCB and Mechanical Layout

The physical implementation of switching electronics presents two challenges: to ensure that the high currents and rapid rise-times are accomodated by the PCB layout, and to allow adequate heat dissipation in the diodes and MOSFETs. I designed three double-sided PCBs and an aluminum frame to support the PFC stage, half-bridge converter, and audio amplier. The aluminum frame provides rigid support for the PCBs and heatsinking for the power devices. It consists of two pieces: a bottom plate 14 wide and 7 deep, and a mounting plate 14 wide and 3 high. Both pieces are 1 4 thick. Together they form an asymmetrical T shape supporting the PCBs. All of the power devices are lined up on one edge of the PCBs and the outside connections (AC, audio input, etc.) are along the other edge. I milled out a very at region on the mounting plate to improve heat transfer, and used Kapton tape as electrical isolation between the power devices and the frame. Figure 10: Side view showing mechanical arrangement of PCBs.

With one channel of the power amplier driving 120W into 4, the DC-DC converter must provide an average current of 2A through each supply rail, and the PFC must draw 1.3A RMS from AC mains. Assuming that each stage operates at 80% eciency, the steady-state heat demands placed on each component can be estimated as follows:

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Component PFC Rectier Diodes (4) PFC Power Switch PFC Output Diode SMPS Power Switches (2) SMPS Rectier Diodes (4) Amplier Power Switches (2)

Dissipation 1.5W 8W 1W 5W 2W 10W

The total heat dissipation is around 50W, which is reasonable for a bracket of this size and thickness. I chose not to equip the amplier with additional heatsinks, especially considering that 120W into 4 is the worst-case condition and will not be reached consistently.

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Construction Notes and Debugging

I attempted to assemble and test the amplier in several steps, to ensure that each piece worked separately and avoid unnecessarily damaging components. The audio amplier section worked as expected without any modications; see the next section for measurements. The switching power supply, in contrast, proved more dicult to test independently because my PFC board is the only readily available source for the half-bridge converters expected 390V input. The assembled frame and PCB (without the necessary connections between boards) appears in Figure 11. Figure 11: Switching amplier ready for testing.

The PFC stage presented an unusual safety risk during construction because it is not isolated from the AC mains and produces high voltages (in the 400V range) at the output. Using this circuit required me to carefully plan zones of circuit ground and mains earth connection. The PFC has a single ground which is not connected to earth (doing so would alternatively short line and neutral to earth through the rectier diodes). The PFC output and ground are connected to the inputs of the half-bridge converter. Mains earth and all other grounds are connected to the secondary side of the power transformer. After bringing the PFC stage carefully up to 120V mains using a variac, I found that the output voltage held at 160V instead of the specied 390V. This means that the power switch never turned on and the

16

bulk capacitor was being charged directly through the output diode. Preliminary checks revealed that the NCP1653 chip was receiving the correct current and voltage feedback, but its gate drive output was disabled; it may have been damaged in earlier testing. This highlights a peculiar aspect of the boost converter, which is that the conversion ratio M (D) =
1 1 D

is 1 for a duty cycle of zero.

When connected to the output of the PFC stage, the half-bridge converter experienced an unusual failure. Q6 (the upper power switch) had not been fully secured to the heatsink and heated more quickly than the other parts. The nylon screw holding Q6 began to melt, and as the plastic softened Q6 moved farther from the heatsink. This did not destroy Q6, but it did enforce a delay on any further testing because the transformer must be removed to mount or unmount transistors. Figure 12: Heatsink attachment failure of Q6 in half-bridge converter

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6
6.1

Tests and Measurements

Power Supplies

After replacing the damaged NCP1653 chip, the PFC board behaved as expected on start-up. The output was maintained at 427.3V DC, 10% higher than expected. The switching frequency, visible in the gate drive waveform, was close to 100KHz. I was unable to provide the PFC board with a suitable load (besides the half-bridge converter) for testing. With no load, when the AC power was switched on the duty cycle was close to zero - the MOSFET was only turned for very short pulses since no additional energy was required to maintain the output voltage. I noticed a slight mechanical vibration from the large inductor, which was not secured to the PCB except by its two leads. With AC power disconnected, the duty cycle increased as the NCP1653 attempted to compensate for the drooping output. The half-bridge converter regulates its output voltage by comparing a fraction of the isolated feedback voltage with an internal reference in the MC34025 chip (see section 2.2). To test the control section, I connected the output to the isolated 15V outputs of a bench power supply and viewed the gate drive signals. With the feedback adjustment potentiometer set to a minimum, the gate signals showed a square wave of approximately 45% duty cycle and period of 44.6s. This is consistent with the 90% overall duty cycle limit, 50KHz intended switching frequency and the push-pull behavior of the system (each MOSFET is on half of the time). Then, when adjusting the feedback potentiometer, there was a point at which the duty cycle fell quickly to zero. This is an indication of sucient loop gain to regulate the output. The decision point determining the duty cycle corresponds to the expected steady-state output voltage for any given amount of feedback. I tested the combination of PFC stage and half-bridge converter using a light bulb in the AC line for soft current limiting. I observed output of 7V with the input at 31V and the feedback potentiometer set to minimum (open loop) before the mechanical failure described above. This agrees with the transformer turns ratio of 4:1 and the 90% maximum duty cycle. (If the supply was totally unregulated, the output voltage would always remain proportional to the input.) Figure 13 shows the unloaded secondary voltage waveform at a very low input. Subsequent testing of the half-bridge converter revealed that a problem in the upper gate drive circuit prevents the upper MOSFET from ever switching o. When I connected it to the output of the PFC stage, the NCP1653 engaged its over-current protection. The cause of the problem is shown in Figure 14. Notice how the upper gate drive switches at the correct times, but never drops below 7.2V (the threshold voltage

18

Figure 13: Half-bridge converter voltage before rectication

Vt of the IRF540Z MOSFET is between 2V and 4V). Hence the power switches are both on 45% of the time, creating an intermittent short-circuit from the input to ground. This explains the over-heating of the upper MOSFET described above. I went on to test the audio amplier with a separate linear power supply.

6.2

Audio Amplier

When connected to a 18V bench supply, the audio amplier section works almost as expected. I veried its self-oscillation behavior by measuring the gate drive signals, as well as the pre- and post-lter output voltages. The gain is a little over 8, or 18dB. The input stage has a very high bandwidth, limited only by the AD8620s slew rate (50V /s); so the ampliers frequency response closely follows that of the output lter, which is a 2nd-order rollo at 33.5KHz. A close-up of the output residual (Figure 16) indicates that it is mostly a sine wave with an amplitude of 230mV RMS. The amplier switches at about 280KHz, signicantly lower than anticipated. The pre-lter output waveform is shown below in Figure 17. The output impedance of the 18V bench supply and its connection leads interacted with the rapidly changing current demands of the amplier, creating signicant voltage ripple. After the addition of two 0.47F bypass capacitors, the MOSFET gates (Figure 18) and output 19

Figure 14: Gate drive waveforms for half-bridge converter with input disconnected.
Upper and Lower Gate Drive Waveforms 16

14

12

10 Signal Amplitude (V)

4 Lower Gate 2 Upper Gate

0.1

0.2

0.3

0.4

0.5 Time (sec)

0.6

0.7

0.8

0.9 x 10

1
4

Figure 15: Response of amplier to 1KHz, 1V RMS input.

Amplifier Input and Output with 1KHz Input 15

10

5 Signal Amplitude (V)

10

15

0.2

0.4

0.6

0.8

1 Time (sec)

1.2

1.4

1.6

1.8 x 10

2
3

switched more cleanly. Overall, the UCD audio ampliers performance met my expectations. It appears to oscillate reliably at a reasonable frequency (though lower than expected) and provide clean output switching. I look forward to increasing the input stage gain and testing it with the switching power supplies working at 35V. With the 20

Figure 16: Amplier output residual.

Switching Ripple and Noise on Output 0.4

0.3

0.2

Signal Amplitude (V)

0.1

0.1

0.2

0.3

0.4

0.2

0.4

0.6

0.8

1 Time (sec)

1.2

1.4

1.6

1.8 x 10

2
5

Figure 17: Output switching with and without bypass capacitors.

Comparison of PreFilter Output with and without Bypass Capacitors 25 With Bypass Without Bypass

20

15

10 Signal Amplitude (V)

10

15

20

25

0.5

1 Time (sec)

1.5

2 x 10

2.5
6

current input stage, single-ended input of 3V RMS (slightly higher than usual) would be required to drive the amplier to clipping.

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Figure 18: Gate drive waveforms for lower MOSFET (non-oating).

Lower Gate Drive Waveforms for UCD Amplifier 8 Without Bypass With Bypass 10

12 Signal Amplitude (V)

14

16

18

20

0.5

1.5

2.5 Time (sec)

3.5

4.5 x 10

5
6

22

Conclusion

Designing switching electronics requires a dierent technique from linear ampliers. As opposed to nding a bias point and linearizing the device characteristics to predict small-signal behavior, I had to understand the behavior of each circuit in terms of two wildly dierent states. The primary output control for each stage of this amplier, instead of a continuous input voltage such as the audio signal, was a duty cycle describing the percentage of time the circuit was on. In the half-bridge converter, the duty cycle denes the on-time of two power MOSFETs, and hence the magnitude of the impulse (in volt-seconds) applied to the primary of the transformer. This corresponds linearly to the rectied output voltage on the other side. In the audio amplier the duty cycle is also directly proportional to ltered output voltage, but the output tracks an input with 20KHz bandwidth. Finally, the PFC stage (as a boost converter) builds up energy in the large inductor during the on state and delivers it to the load during the o state. Controlling the duty cycle remains one of the most dicult tasks in switching electronics. Very complex circuits have been devised so the circuits can handle a wide range of operating conditions: the PFC stage is intended to produce 390V DC from 90V to 250V AC at either 50Hz or 60Hz, without any part substitutions. To take advantage of this exibility provided by switching circuits and oer several modes of protection, most forms of duty-cycle control have been implemented as integrated circuits (such as the NCP1653 and MC34025 I used in my power supplies). Even when using an integrated circuit, proper operation is still not foolproof. I needed to design and debug the half-bridge converters gate drive and feedback networks discrete circuits made specically for the MC34025s expected mode of operation. The comparatively simple self-oscillating amplier allowed me the opportunity to use a high-performance discrete control circuit. I am impressed by the simplicity and functionality of Putzeys UCD design concept; the design is straightforward given the transfer function model, and the circuit is capable of excellent audio quality. I look forward to exploring other applications, such as a dierential ampliverter that converts AC mains voltage directly into audio. The switching power topologies I used in this project are useful for reducing the power consumption and heat dissipation of devices that would otherwise have been linear circuits, such as 60 Hz power supplies and Class-AB ampliers. More importantly, they are capable of similar performance. By exploring an application of switched power conversion and Class-D amplication, I have learned a lot about high-power analog circuit design.

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Appendix: Schematics and PCB Designs

Figure 19: Complete schematic of PFC stage

24

Figure 20: Complete schematic of DC-DC converter

25

Figure 21: Complete schematic of Class-D amplier stage

26

Figure 22: PCB layout of PFC stage

27

Figure 23: PCB layout of DC-DC converter

Figure 24: PCB layout of Class-D amplier stage

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References

I consulted many online datasheets and application notes from ON Semiconductor, NEC, and International Rectier for the design and construction of this switching amplier. I used LTSpice for circuit simulation; schematics and layouts were done in EAGLE.

Chryssis, George, High-frequency Switching Power Supplies: Theory and Design. New York: McGrawHill, 1989.

Hancock, Jon M., Simplifying Power-factor Correction in SMPS. Power Electronics Technology, October 2004. http://powerelectronics.com/mag/410pet21.pdf

Putzeys, Bruno, Simple Self-Oscillating Class D Amplier With Full Output Filter Control. Audio Engineering Society (118th Convention), May 28, 2005.

[Multiple contributors], My DIY UCD, online forum discussion started April 14, 2005. http://www.diyaudio.com/forums/showthread.php?threadid=55385.

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