Appendix B

VHDL Syntax

In this appendix we present the full set of syntax rules for VHDL using the EBNF notation introduced in Chapter 1. The form of EBNF used in this book differs from that of the VHDL Language Reference Manual (LRM) in order to make the syntax rules more intelligible to the VHDL user. The LRM includes a separate syntax rule for each minor syntactic category. In this book, we condense the grammar into a smaller number of rules, each of which defines a larger part of the grammar. We introduce the EBNF symbols (, ) and as part of this simplification. Our aim is to avoid the large amount of searching required when using the LRM rules to resolve a question of grammar. Those parts of the syntax rules that were introduced in VHDL-2008 are underlined in this appendix. A model written using earlier versions of the language may not use these features. In addition, there are some entirely new rules introduced in VHDL-2008 that have no predecessors in earlier versions. We identify these rules by underlining the rule name on the left-hand side of the symbol. Some of the rules refer to the syntax rules for the PSL. Such references are identified by the italicized prefix PSL_. The PSL syntax rules are not included here. The interested reader should refer to the PSL standard or to books on PSL for details.

Index to Syntax Rules

absolute_pathname 858 access_type_definition 848 actual_part 856 aggregate 858 alias_declaration 847 architecture_body 844 array_type_definition 848 assertion_statement 853 association_list 856 attribute_declaration 847 attribute_name 857 attribute_specification 847 based_integer 858 based_literal 858 binding_indication 848 bit_string_literal 858 block_configuration 844 block_declarative_item 850 block_statement 850 case_generate_statement 852 case_statement 855 character_literal 858 choices 858 component_configuration 844

841

842

Appendix B VHDL Syntax

component_declaration 847 component_instantiation_statement 852 component_specification 847 concurrent_assertion_statement 851 concurrent_conditional_signal_assignment 851 concurrent_procedure_call_statement 851 concurrent_selected_signal_assignment 851 concurrent_signal_assignment_statement 851 concurrent_simple_signal_assignment 851 concurrent_statement 850 condition 856 conditional_force_assignment 853 conditional_signal_assignment 853 conditional_variable_assignment 854 conditional_waveform_assignment 853 configuration_declaration 844 configuration_specification 847 constant_declaration 846 context_declaration 844 context_reference 843 decimal_literal 858 delay_mechanism 854 design_file 843 design_unit 843 disconnection_specification 848 discrete_range 850 entity_class 847 entity_declaration 843 entity_declarative_item 844 entity_name_list 847 enumeration_type_definition 848 exit_statement 855 expression 856 external_name 857 external_pathname 857 factor 857 file_declaration 847 file_type_definition 848 floating_type_definition 848 for_generate_statement 852 formal_part 856 function_call 857 function_specification 846 generate_statement 852 generate_statement_body 852 group_declaration 848 group_template_declaration 848 identifier 858 if_generate_statement 852 if_statement 854 integer 858 integer_type_definition 848

interface_constant_declaration 855 interface_file_declaration 855 interface_list 855 interface_package_declaration 856 interface_signal_declaration 855 interface_subprogram_declaration 856 interface_type_declaration 855 interface_variable_declaration 855 label 858 library_clause 843 library_unit 843 literal 858 logical_expression 856 loop_statement 855 mode 855 name 857 next_statement 855 null_statement 855 operator_symbol 857 package_body 845 package_body_declarative_item 845 package_declaration 845 package_declarative_item 845 package_instantiation_declaration 845 package_pathname 858 pathname_element 858 physical_literal 858 physical_type_definition 848 primary 857 procedure_call_statement 854 procedure_specification 846 process_declarative_item 851 process_statement 851 protected_type_body 849 protected_type_body_declarative_item 849 protected_type_declaration 849 protected_type_declarative_item 849 qualified_expression 857 record_type_definition 848 relation 856 relative_pathname 858 report_statement 853 return_statement 855 selected_name 857 selected_signal_assignment 853, 854 selected_variable_assignment 854 selected_waveform_assignment 853 sequential_statement 852 shift_expression 856 signal_assignment_statement 853

B.1 Design File

843

signal_declaration 847 signature 857 simple_expression 857 simple_signal_assignment 853 simple_variable_assignment 854 string_literal 858 subprogram_body 846 subprogram_declaration 846 subprogram_declarative_item 846 subprogram_instantiation_declaration 846 subprogram_specification 845 subtype_declaration 849 subtype_indication 849

term 857 tool_directive 858 type_declaration 846 type_definition 846 type_mark 850 use_clause 848 variable_assignment_statement 854 variable_declaration 847 wait_statement 853 waveform 854

B.1

Design File
design_file design_unit { } design_unit { library_clause I use_clause I context_reference } library_unit library_unit entity_declaration I package_declaration I package_instantiation_declaration I configuration_declaration I PSL_Verification_Unit I architecture_body I package_body I context_declaration

library_clause library identifier { , } ; context_reference context selected_name { , } ;

B.2

Library Unit Declarations

entity_declaration entity identifier is [ generic ( generic_interface_list ) ; ] [ port ( port_interface_list ) ; ] { entity_declarative_item } [ begin { concurrent_assertion_statement I passive_concurrent_procedure_call_statement I passive_process_statement } ] I PSL_PSL_Directive end [ entity ] [ identifier ] ;

844 entity_declarative_item subprogram_declaration I subprogram_instantiation_declaration I package_declaration I package_instantiation_declaration I type_declaration I constant_declaration I shared_variable_declaration I alias_declaration I attribute_declaration I disconnection_specification I group_template_declaration I PSL_Property_Declaration I PSL_Clock_Declaration

Appendix B VHDL Syntax

I subprogram_body I package_body I subtype_declaration I signal_declaration I file_declaration I I I I attribute_specification use_clause group_declaration PSL_Sequence_Declaration

architecture_body architecture identifier of entity_name is { block_declarative_item }

begin

{ concurrent_statement }
end [ architecture ] [ identifier ] ;

configuration_declaration configuration identifier of entity_name is { use_clause I attribute_specification I group_declaration } { use vunit verification_unit_name { , } ; } block_configuration end [ configuration ] [ identifier ] ; block_configuration for ( architecture_name I block_statement_label I generate_statement_label [ ( ( static_discrete_range I static_expression I alternative_label ) ) ] ) { use_clause } { block_configuration I component_configuration }
end for ;

component_configuration for component_specification [ binding_indication ; ] { use vunit verification_unit_name { , } ; } [ block_configuration ]

end for ;

context_declaration context identifier is { library_clause I use_clause I context_reference } end [ context ] [ identifier ] ;

B.3 Declarations and Specifications

845

B.3

Declarations and Specifications

package_declaration package identifier is [ generic ( generic_interface_list ) ; [ generic map ( generic_association_list ) ; ] ] { package_declarative_item } end [ package ] [ identifier ] ; package_declarative_item subprogram_declaration I subprogram_instantiation_declaration I package_declaration I package_instantiation_declaration I type_declaration I constant_declaration I variable_declaration I alias_declaration I attribute_declaration I disconnection_specification I group_template_declaration I PSL_Property_Declaration package_body
package body identifier is

I I I I I I I I

subtype_declaration signal_declaration file_declaration component_declaration attribute_specification use_clause group_declaration PSL_Sequence_Declaration

{ package_body_declarative_item }
end [ package body ] [ identifier ] ;

package_body_declarative_item subprogram_declaration I subprogram_instantiation_declaration I package_declaration I package_instantiation_declaration I type_declaration I constant_declaration I file_declaration I attribute_declaration I use_clause I group_template_declaration

I subprogram_body I package_body I I I I subtype_declaration variable_declaration alias_declaration attribute_specification

I group_declaration

package_instantiation_declaration package identifier is new uninstantiated_package_name [ generic map ( generic_association_list ) ] ; subprogram_specification procedure_specification I function_specification

846 procedure_specification procedure identifier [ generic ( generic_interface_list ) [ generic map ( generic_association_list ) ] ] [ [ parameter ] ( parameter_interface_list ) ]

Appendix B VHDL Syntax

function_specification [ pure I impure ] function ( identifier I operator_symbol ) [ generic ( generic_interface_list ) [ generic map ( generic_association_list ) ] ] [ [ parameter ] ( parameter_interface_list ) ] return type_mark subprogram_declaration subprogram_specification ; subprogram_body subprogram_specification is { subprogram_declarative_item }
begin

{ sequential_statement }
end [ procedure I function ] [ identifier I operator_symbol ] ;

subprogram_declarative_item subprogram_declaration I subprogram_instantiation_declaration I package_declaration I package_instantiation_declaration I type_declaration I constant_declaration I file_declaration I attribute_declaration I use_clause I group_template_declaration

I subprogram_body I package_body I I I I subtype_declaration variable_declaration alias_declaration attribute_specification

I group_declaration

subprogram_instantiation_declaration ( procedure I function ) identifier is new uninstantiated_subprogram_name [ signature ] [ generic map ( generic_association_list ) ] ; type_declaration type identifier is type_definition ; I type identifier ; type_definition enumeration_type_definition I floating_type_definition I array_type_definition I access_type_definition I protected_type_declaration I I I I I integer_type_definition physical_type_definition record_type_definition file_type_definition protected_type_body

constant_declaration constant identifier { , } : subtype_indication [ := expression ] ;

B.3 Declarations and Specifications signal_declaration signal identifier { , } : subtype_indication [ register I bus ] [ := expression ] ;

847

variable_declaration [ shared ] variable identifier { , } : subtype_indication [ := expression ] ; file_declaration file identifier { , } : subtype_indication [ [ open file_open_kind_expression ] is string_expression ] ; alias_declaration alias ( identifier I character_literal I operator_symbol ) [ : subtype_indication] is name [ signature ] ; component_declaration component identifier [ is ] [ generic ( generic_interface_list ) ; ] [ port ( port_interface_list ) ; ] end component [ identifier ] ; attribute_declaration attribute identifier : type_mark ; attribute_specification attribute identifier of entity_name_list : entity_class is expression ; entity_name_list ( ( identifier I character_literal I operator_symbol ) [ signature ] ) { , } I others I all entity_class
entity I procedure I constant I component I group

I I I I I

architecture function signal label property

I I I I I

configuration type variable literal sequence

I I I I

package subtype file units

configuration_specification for component_specification binding_indication ; { use vunit verification_unit_name { , } ; } [ end for ; ] component_specification ( instantiation_label { , } I others I all ) : component_name

848

Appendix B VHDL Syntax binding_indication use ( entity entity_name [ ( architecture_identifier ) ] I configuration configuration_name I open ) [ generic map ( generic_association_list ) ] [ port map ( port_association_list ) ] disconnection_specification disconnect ( signal_name { , } I others I all ) : type_mark after time_expression ; group_template_declaration group identifier is ( ( entity_class [ <> ] ) { , } ) ; group_declaration group identifier : group_template_name ( ( name I character_literal ) { , } ) ; use_clause use selected_name { , } ;

B.4

Type Definitions
enumeration_type_definition ( ( identifier I character_literal ) { , } ) integer_type_definition range ( range_attribute_name I simple_expression ( to I downto ) simple_expression ) floating_type_definition range ( range_attribute_name I simple_expression ( to I downto ) simple_expression ) physical_type_definition range ( range_attribute_name I simple_expression ( to I downto ) simple_expression )
units

identifier ; { identifier = physical_literal ; } end units [ identifier ] array_type_definition array ( ( type_mark range <> ) { , } ) of element_subtype_indication I array ( discrete_range { , } ) of element_subtype_indication record_type_definition
record

( identifier { , } : subtype_indication ; ) {} end record [ identifier ] access_type_definition access subtype_indication file_type_definition file of type_mark

B.4 Type Definitions protected_type_declaration

protected

849

{ protected_type_declarative_item }
end protected [ identifier ]

protected_type_declarative_item subprogram_declaration I subprogram_instantiation_declaration I attribute_specification I use_clause protected_type_body

protected body

{ protected_type_body_declarative_item }
end protected body [ identifier ]

protected_type_body_declarative_item subprogram_declaration I subprogram_instantiation_declaration I package_declaration I package_instantiation_declaration I type_declaration I constant_declaration I file_declaration I attribute_declaration I use_clause I group_template_declaration

I subprogram_body I package_body I I I I subtype_declaration variable_declaration alias_declaration attribute_specification

I group_declaration

subtype_declaration subtype identifier is subtype_indication ; subtype_indication [ resolution_indication ] type_mark [ constraint ] resolution_indication resolution_function_name I ( resolution_indication I ( record_element_identifier resolution_indication ) { , } ) constraint range ( range_attribute_name I simple_expression ( to I downto ) simple_expression ) I array_constraint I record_constraint array_constraint ( discrete_range { , } ) [ array_constraint I record_constraint ] I ( open ) [ array_constraint I record_constraint ] record_constraint ( ( record_element_identifier ( array_constraint I record_constraint ) ) { , } )

850

Appendix B VHDL Syntax discrete_range discrete_subtype_indication I range_attribute_name I simple_expression ( to I downto ) simple_expression type_mark type_name I subtype_name

B.5

Concurrent Statements
concurrent_statement block_statement I process_statement I concurrent_procedure_call_statement I concurrent_assertion_statement I concurrent_signal_assignment_statement I component_instantiation_statement I generate_statement I PSL_PSL_Directive block_statement block_label : block [ ( guard_expression ) ] [ is ] [ generic ( generic_interface_list ) ; [ generic map ( generic_association_list ) ; ] ] [ port ( port_interface_list ) ; [ port map ( port_association_list ) ; ] ] { block_declarative_item }
begin

{ concurrent_statement }
end block [ block_label ] ;

block_declarative_item subprogram_declaration I subprogram_instantiation_declaration I package_declaration I package_instantiation_declaration I type_declaration I constant_declaration I shared_variable_declaration I alias_declaration I attribute_declaration I configuration_specification I use_clause I group_template_declaration I PSL_Property_Declaration I PSL_Clock_Declaration

I subprogram_body I package_body I I I I I I subtype_declaration signal_declaration file_declaration component_declaration attribute_specification disconnection_specification

I group_declaration I PSL_Sequence_Declaration

B.5 Concurrent Statements process_statement [ process_label : ] [ postponed ] process [ ( ( signal_name { , } ) I all ) ] [ is ] { process_declarative_item }
begin

851

{ sequential_statement }
end [ postponed ] process [ process_label ] ;

process_declarative_item subprogram_declaration I subprogram_body I subprogram_instantiation_declaration I package_declaration I package_body I package_instantiation_declaration I type_declaration I subtype_declaration I constant_declaration I variable_declaration I file_declaration I alias_declaration I attribute_declaration I attribute_specification I use_clause I group_template_declaration I group_declaration concurrent_procedure_call_statement [ label : ] [ postponed ] procedure_name [ ( parameter_association_list ) ] ; concurrent_assertion_statement [ label : ] [ postponed ] assert condition [ report expression ] [ severity expression ] ; concurrent_signal_assignment_statement [ label : ] [ postponed ] concurrent_simple_signal_assignment I [ label : ] [ postponed ] concurrent_conditional_signal_assignment I [ label : ] [ postponed ] concurrent_selected_signal_assignment concurrent_simple_signal_assignment target <= [ guarded ] [ delay_mechanism ] waveform ; concurrent_conditional_signal_assignment target <= [ guarded ] [ delay_mechanism ] waveform when condition { else waveform when condition } [ else waveform ] ; concurrent_selected_signal_assignment with expression select [ ? ] target <= [ guarded ] [ delay_mechanism ] { waveform when choices , } waveform when choices ;

852

Appendix B VHDL Syntax component_instantiation_statement instantiation_label : ( [ component ] component_name I entity entity_name [ ( architecture_identifier ) ] I configuration configuration_name ) [ generic map ( generic_association_list ) ] [ port map ( port_association_list ) ] ; generate_statement for_generate_statement I if_generate_statement I case_generate_statement for_generate_statement generate_label : for identifier in discrete_range generate generate_statement_body end generate [ generate_label ] ; if_generate_statement generate_label : if [ alternative_label : ] condition generate generate_statement_body { elsif [ alternative_label : ] condition generate generate_statement_body } [ else [ alternative_label : ] generate generate_statement_body ] end generate [ generate_label ] ; case_generate_statement generate_label : case expression generate ( when [ alternative_label : ] choices => generate_statement_body ) {} end generate [ generate_label ] ; generate_statement_body [ { block_declarative_item } begin ] { concurrent_statement } [ end [ alternative_label ] ; ]

B.6

Sequential Statements
sequential_statement wait_statement I report_statement I variable_assignment_statement I if_statement I loop_statement I I I I I assertion_statement signal_assignment_statement procedure_call_statement case_statement next_statement

B.6 Sequential Statements I exit_statement I null_statement I return_statement

853

wait_statement [ label : ] wait [ on signal_name { , } ] [ until condition ] [ for time_expression ] ; assertion_statement [ label : ] assert condition [ report expression ] [ severity expression ] ; report_statement [ label : ] report expression [ severity expression ] ; signal_assignment_statement [ label : ] simple_signal_assignment I [ label : ] conditional_signal_assignment I [ label : ] selected_signal_assignment simple_signal_assignment ( name I aggregate ) <= [ delay_mechanism ] waveform ; I name <= force [ in I out ] expression ; I name <= release [ in I out ] ; conditional_signal_assignment conditional_waveform_assignment I conditional_force_assignment conditional_waveform_assignment [ label : ] ( name I aggregate ) <= [ delay_mechanism ] waveform when condition { else waveform when condition } [ else waveform ] ; conditional_force_assignment [ label : ] name <= force [ in I out ] expression when condition { else expression when condition } [ else expression ] ; selected_signal_assignment selected_waveform_assignment I selected_force_assignment selected_waveform_assignment [ label : ] with expression select [ ? ] ( name I aggregate ) <= [ delay_mechanism ] { waveform when choices , } waveform when choices ;

854 selected_signal_assignment [ label : ] with expression select [ ? ] name <= force [ in I out ] { expression when choices , } expression when choices ;

Appendix B VHDL Syntax

delay_mechanism transport I [ reject time_expression ] inertial waveform ( value_expression [ after time_expression ] I null [ after time_expression ] ) { , } I unaffected variable_assignment_statement [ label : ] simple_variable_assignment I [ label : ] conditional_variable_assignment I [ label : ] selected_variable_assignment simple_variable_assignment ( name I aggregate ) := expression ; conditional_variable_assignment ( name I aggregate ) := expression when condition { else expression when condition } [ else expression ] ; selected_variable_assignment with expression select [ ? ] ( name I aggregate ) := { expression when choices , } expression when choices ; procedure_call_statement [ label : ] procedure_name [ ( parameter_association_list ) ] ; if_statement [ if_label : ] if condition then { sequential_statement } { elsif condition then { sequential_statement } } [ else { sequential_statement } ] end if [ if_label ] ;

B.7 Interfaces and Associations case_statement [ case_label : ] case [ ? ] expression is ( when choices => { sequential_statement } ) {} end case [ ? ] [ case_label ] ; loop_statement [ loop_label : ] [ while condition I for identifier in discrete_range ] loop { sequential_statement } end loop [ loop_label ] ; next_statement [ label : ] next [ loop_label ] [ when condition ] ; exit_statement [ label : ] exit [ loop_label ] [ when condition ] ; return_statement [ label : ] return [ expression ] ; null_statement [ label : ] null ;

855

B.7

Interfaces and Associations

interface_list ( interface_constant_declaration I interface_signal_declaration I interface_variable_declaration I interface_file_declaration I interface_type_declaration I interface_subprogram_declaration I interface_package_declaration ) { ; } interface_constant_declaration [ constant ] identifier { , } : [ in ] subtype_indication [ := static_expression ] interface_signal_declaration [ signal ] identifier { , } : [ mode ] subtype_indication [ bus ] [ := static_expression ] interface_variable_declaration [ variable ] identifier { , } : [ mode ] subtype_indication [ := static_expression ] mode in I out I inout I buffer I linkage interface_file_declaration file identifier { , } : subtype_indication interface_type_declaration type identifier

856

Appendix B VHDL Syntax interface_subprogram_declaration ( procedure identifier [ [ parameter ] ( parameter_interface_list ) ] I [ pure I impure ] function ( identifier I operator_symbol ) [ [ parameter ] ( parameter_interface_list ) ] return type_mark ) [ is ( subprogram_name I <> ) ] interface_package_declaration package identifier is new uninstantiated_package_name generic map ( ( generic_association_list I <> I default ) ) association_list ( [ formal_part => ] actual_part ) { , } formal_part generic_name I port_name I parameter_name I function_name ( ( generic_name I port_name I parameter_name ) ) I type_mark ( ( generic_name I port_name I parameter_name ) ) actual_part [ inertial ] expression I signal_name I variable_name I file_name I subtype_indication I subprogram_name I package_name I open I function_name ( ( signal_name I variable_name ) ) I type_mark ( ( signal_name I variable_name ) )

B.8

Expressions and Names

condition expression expression ( ?? primary ) I logical_expression logical_expression relation { and relation } I relation { or relation } I relation { xor relation }

I relation [ nand relation ] I relation [ nor relation ] I relation { xnor relation }

relation shift_expression [ ( = I /= I < I <= I > I >= I ?= I ?/= I ?< I ?<= I ?> I ?>= ) shift_expression ] shift_expression simple_expression [ ( sll I srl I sla I sra I rol I ror ) simple_expression ]

B.8 Expressions and Names simple_expression [ + I ] term { ( + I I & ) term } term factor { ( * I / I mod I rem ) factor } factor primary [ ** primary ] I abs primary I not primary I and primary I nand primary I or primary I nor primary I xor primary I xnor primary primary name I aggregate I qualified_expression I new subtype_indication I ( expression ) I I I I literal function_call type_mark ( expression ) new qualified_expression

857

function_call function_name [ ( parameter_association_list ) ] qualified_expression type_mark ' ( expression ) I type_mark ' aggregate name identifier I operator_symbol I character_literal I selected_name I ( name I function_call ) ( expression { , } ) I ( name I function_call ) ( discrete_range ) I attribute_name I external_name selected_name ( name I function_call ) . ( identifier I character_literal I operator_symbol I all ) operator_symbol " { graphic_character } " attribute_name ( name I function_call ) [ signature ] ' identifier [ ( expression ) ] signature [ [ type_mark { , } ] [ return type_mark ] ] external_name
<< constant external_pathname : subtype_indication >> I << signal external_pathname : subtype_indication >> I << variable external_pathname : subtype_indication >>

external_pathname absolute_pathname I relative_pathname I package_pathname

858

Appendix B VHDL Syntax absolute_pathname . { pathname_element . } object_identifier relative_pathname { ^ . } { pathname_element . } object_identifier pathname_element ::= entity_identifier I component_instantiation_label I block_label I generate_statement_label [ ( static_expression ) ] I package_identifier package_pathname @ library_identifier . { package_identifier . } object_identifier literal decimal_literal I physical_literal I character_literal I bit_string_literal I I I I based_literal identifier string_literal
null

physical_literal [ decimal_literal I based_literal ] unit_name decimal_literal integer [ . integer ] [ E [ + ] integer I E integer ] based_literal integer # based_integer [ . based_integer ] # [ E [ + ] integer I E integer ] integer digit { [ _ ] } based_integer ( digit I letter ) { [ _ ] } character_literal ' graphic_character ' string_literal " { graphic_character } " bit_string_literal [ integer ] ( B I O I X I UB I UO I UX I SB I SO I SX I D ) " [ graphic_character { [ _ ] } ] " aggregate ( ( [ choices => ] expression ) { , } ) choices ( simple_expression I discrete_range I identifier I others ) { | } label identifier identifier letter { [ _ ] ( letter I digit ) } I \ graphic_character { } \ tool_directive ` identifier { graphic_character }