library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.

ALL; entity simple_alu is port( Clk : in std_logic; --clock signal A,B : in signed(7 downto 0); --input operands Op : in unsigned(2 downto 0); --Operation to be performed R : out signed(7 downto 0) --output of ALU ); end simple_alu; architecture Behavioral of simple_alu is --temporary signal declaration. signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0'); begin Reg1 <= A; Reg2 <= B; R <= Reg3; process(Clk) begin if(rising_edge(Clk)) then --Do the calculation at the positive edge of clock cycle. case Op is when "000" => Reg3 <= Reg1 + Reg2; --addition when "001" => Reg3 <= Reg1 - Reg2; --subtraction when "010" => Reg3 <= not Reg1; --NOT gate when "011" => Reg3 <= Reg1 nand Reg2; --NAND gate when "100" => Reg3 <= Reg1 nor Reg2; --NOR gate when "101" => Reg3 <= Reg1 and Reg2; --AND gate when "110" => Reg3 <= Reg1 or Reg2; --OR gate when "111" => Reg3 <= Reg1 xor Reg2; --XOR gate when others => NULL; end case; end if;

end process; end Behavioral;

Test bench

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS signal Clk : std_logic := '0'; signal A,B,R : signed(7 downto 0) := (others => '0'); signal Op : unsigned(2 downto 0) := (others => '0'); constant Clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.simple_alu PORT MAP ( Clk => Clk, A => A, B => B, Op => Op, R => R ); -- Clock process definitions Clk_process :process begin Clk <= '0'; wait for Clk_period/2; Clk <= '1'; wait for Clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for Clk_period*1; A <= "00010010"; --18 in decimal B <= "00001010"; --10 in decimal Op <= "000"; wait for Clk_period; Op <= "001"; wait for Clk_period; Op <= "010"; wait for Clk_period; Op <= "011"; wait for Clk_period; Op <= "100"; wait for Clk_period; Op <= "101"; wait for Clk_period; Op <= "110"; wait for Clk_period; Op <= "111"; wait for Clk_period;

--add A and B --subtract B from A. --Bitwise NOT of A --Bitwise NAND of A and B --Bitwise NOR of A and B --Bitwise AND of A and B --Bitwise OR of A and B --Bitwise XOR of A and B

wait; end process;

library ieee ; use ieee.std_logic_1164.all; --------------------------------------------------entity shift_reg is port( I: clock: shift: Q: ); end shift_reg; in std_logic; in std_logic; in std_logic; out std_logic

--------------------------------------------------architecture behv of shift_reg is -- initialize the declared signal signal S: std_logic_vector(2 downto 0):="111"; begin process(I, clock, shift, S) begin -- everything happens upon the clock changing if clock'event and clock='1' then if shift = '1' then S <= I & S(2 downto 1); end if; end if; end process; -- concurrent assignment Q <= S(0); end behv; ----------------------------------------------------

--------------------------------------------------------------- Test Bench for 3-bit shift register (ESD figure 2.6) -- by Weijun Zhang, 04/2001 --- please note usually the processes within testbench do -- not have sesitive list. -------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity shifter_TB is end shifter_TB; architecture TB of shifter_TB is component shift_reg port( I: in std_logic; clock: in std_logic; shift: in std_logic; Q: out std_logic ); end component; signal signal signal signal begin U_shifter: shift_reg port map (T_I, T_clock, T_shift, T_Q); -- concurrent process of clock process begin T_clock<= '0'; wait for 5 ns; T_clock<= '1'; wait for 5 ns; end process; -- concurrent process of test process variable err_cnt: integer := 0; begin T_shift<= '1'; T_I <= '0'; wait for 20 ns; T_I <= '1'; wait for 20 ns; T_I <= '0'; wait for 10 ns; T_I <= '1'; wait; end process; -- start shifting -- 1st/2nd bit input -- 3rd bit input -- 4th bit input T_I: T_clock: T_shift: T_Q: std_logic; std_logic; std_logic; std_logic; -- entity declaration

process variable err_cnt: integer :=0; begin -- case 1 wait for 30 ns; assert(T_Q='0') report "Test1 Failed !" severity error; if (T_Q/='0') then err_cnt:=err_cnt+1; end if; -- case 2 wait for 10 ns; assert(T_Q='0') report "Test2 Failed !" severity error; if (T_Q/='0') then err_cnt:=err_cnt+1; end if; -- case 3 wait for 10 ns; assert(T_Q='1') report "Test3 Failed !" severity error; if (T_Q/='1') then err_cnt:=err_cnt+1; end if; -- case 4 wait for 10 ns; assert(T_Q='1') report "Test4 Failed !" severity error; if (T_Q/='1') then err_cnt:=err_cnt+1; end if; -- summary of all the tests if (err_cnt=0) then assert (false) report "Testbench of Shifter completed successfully!" severity note; else assert (true) report "Something wrong, try again!" severity error; end if; wait; end process; end TB; ---------------------------------------------------------------configuration CFG_TB of shifter_TB is for TB end for; end CFG_TB; -----------------------------------------------------------------

ENTITAS MOV library ieee; use ieee.std_logic_1164.all;

entity mov is port ( en : in std_logic; a : in std_logic_vector(7 downto 0); b : out std_logic_vector(7 downto 0)); end mov;

architecture movarch of mov is begin process(a,en) begin if en = '0' then null; else b <= a; end if; end process; end movarch;

Test Bench library ieee; use ieee.std_logic_1164.all;

entity movtb is end movtb;

architecture movtbarch of movtb is signal en : std_logic; signal a : std_logic_vector(7 downto 0); signal b : std_logic_vector(7 downto 0); begin blok : entity work.mov port map ( en => en, a => a, b => b); tb : process is begin en <= '0', '1' after 200ns; a <= "01100110"; wait for 1000ns; wait; end process; end movtbarch;