27413 Analog Integrated Circuits

Lab Manual
Francesc Serra Graells
http://www.cnm.es/~pserra/uab/cia paco.serra@imb-cnm.csic.es

Contents
1 Objectives and Installation 2 My 2.1 2.2 2.3 CMOS Operational Amplier Datasheet Extraction . . . . . . . . . . . . . . . . . . . . . . . Circuit Optimization . . . . . . . . . . . . . . . . . . . . . . . . Physical CMOS Design . . . . . . . . . . . . . . . . . . . . . . 2 3 6 14 16 21 21

3 Glossary References

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual

Objectives and Installation

The aim of these lab exercises is to supply an introduction to the Computer Aided Design (CAD) of CMOS analog integrated circuits. After their completion, the student should feel familiar with the standard Electronic Design Automation (EDA) methodology for numerical simulation, mask edition and physical verication of any analog full-custom Very Large Scale Integration (VLSI) design, from a single MOS transistor to a complete Application Specic Integrated Circuit (ASIC). The proposed lab exercises are almost self guided so they can easily be done at home. Also, the required EDA tools are freely available for both MSWindows and Linux operative systems:

SPICEOPUS (SPICE with integrated OPtimization UtilitieS) by the CACD Group at University of Ljubljana is a port of the SPICE3F5 from Berkeley, together with the XSPICE from Georgia Tech Research Institute and a custom optimization tool, all performing native mixed-mode circuit simulation and optimization. Download and install the latest version from http://fides.fe.uni-lj.si/spice.

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Avoid spaced names for the installation directory! Optionally, download the ocial SPICE3 manual from the syllabus website.

GLADE (GDS, LEF And DEF Editor) by Keith Morris is a mask layout editor, Design Rule Checker (DRC), device extractor, place & route tool and format converter for Integrated Circuit (IC) design. Download and install the latest version from http://www.peardrop.co.uk/glade. For MS Windows, create a glade.bat le in the same directory containing:
set GLADE_USE_OPENGL=NO "C:\ ...path-to-glade... \glade.exe"

The Design Kit contains all the specic les needed for the 2.5m 2-polySi 2-metal CMOS technology from the Centre Nacional de Microelectrnica (CNM25). Download aickit.zip from the syllabus website.

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Contents:

aickit/doc /spiceopus /glade

This manual. . . SPICEOPUS simulation les GLADE design les

F. Serra-Graells

Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual

My CMOS Operational Amplier

Basically, these lab exercise are conceived to illustrate the general EDA methodology of Figure 1 for fullcustom integrated circuits with a simple but interesting enough design case. For such a purpose, an Operational Amplier (OpAmp) block is selected.
Synthesis

Specs

Schematic capture

Foundry
Available Devices

Extraction+ERC
M1 D G S MODN W= L= M=

Pre layout simulation Process and mismatching model parameters Phyisical edition Table of layers DRC Design rules Extraction+ERC
M1 D G S MODN W= L= M= CPAR D S

Physical device rules

LVS
==?

Post layout simulation Parasitic model parameters Codification Conversion tables

Foundry processing Prototype

Figure 1: General EDA ow for full-custom integrated circuits.

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual The CMOS implementation chosen for the OpAmp is the classic two-stage Miller-compensated single-ended output topology of Figure 2, consisting on: a current reference M8-M9, which biases the two cascaded amplication stages, a PMOS dierential input M1-M2 with active loads M3-M4 and current source M7, an inverting stage M6 with its corresponding current source M5, and nally the nested compensation capacitance Ccomp . The initial OpAmp design parameters are given in Table 1, while the equivalent SPICE2 subcircuit can be found in spiceopus/opamp.sub.
VDD M7

M8 Vin-

M5 VDD Vout Ccomp Vin+ VinM6

M1

M2

Vout
-

M9

M3

M4

VSS

Vin+

VSS

Figure 2: OpAmp schematic (left) and symbol (right). = = = =

W L W L

1,2

12 6 12 6

W L W L

3,4

12 12 12 6

W L W L

48 6 12 6

5 W L

=8 =
3 24

=2

Ccomp = 100 100 (4pF)

Table 1: OpAmp physical device dimensions in m.

spiceopus/opamp.sub * PMOS-input two-stage Miller operational amplifier .subckt opamp vinn vinp vout vdd vss m1 vload vinn vcomm vdd modp w=12u l=6u m=1 m2 vinter vinp vcomm vdd modp w=12u l=6u m=1 m3 vload vload vss vss modn w=12u l=12u m=1 m4 vinter vload vss vss modn w=12u l=12u m=1 m5 vout vbias vdd vdd modp w=12u l=6u m=8 m6 vout vinter vss vss modn w=48u l=6u m=1 m7 vcomm vbias vdd vdd modp w=12u l=6u m=2 m8 vbias vbias vdd vdd modp w=12u l=6u m=1 m9 vbias vbias vss vss modn w=3u l=24u m=1 ccomp vout vinter cpoly w=100u l=100u m=1 .ends spiceopus/opamp.sub

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Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual Concerning the target CMOS technology, the electrical models for both the P/NMOS devices and the polySi capacitor are supplied in spiceopus/cnm25typ.mod, while the process design rules are listed in Table 2.
spiceopus/cnm25typ.mod * ****************** WARNING *********************** * These SPICE3 LEVEL 2 MOSFET model parameters for * * the 2.5um VLSI CMOS 2M 2P technology (CNM25) are * * supplied by the CNM without any warranty. * * For CAD support, please contact scad@cnm.es * **************************************************** .model modp pmos LEVEL = 2 + TOX = 380E-10 VTO = -1.139 + UCRIT = 1E4 UEXP = 1.16E-1 + DELTA = 1.82 RS = 134.9 + VMAX = 1.20E5 NEFF = 6.67E-2 + CJSW = 7.38E-10 MJSW = .39 + AF =1.330e+00 KF =1.010e-26 .model modn nmos LEVEL = 2 + TOX = 380E-10 VTO = .942 + UCRIT = 1E4 UEXP = 6.86E-2 + DELTA = 2.20 RS = 93.8 + VMAX = 5.96E4 NEFF = 1.48 + CJSW = 5.95E-10 MJSW = .29 + AF =1.290e+00 KF =3.900e-28 .model cpoly c CJ= 4.227E-4

NSUB = 1.36E16 NFS = 6.62E11 LD = 8.10E-7 CJ = 3.82E-4 PB = .56

UO = 213 XJ = 2.78E-9 MJ = .35

NSUB = 2.64E16 NFS = 7.11E11 LD = 9.13E-7 CJ = 3.50E-4 PB = .65

UO = 648 XJ = 8.24E-8 MJ = .40

CJSW=0.0 spiceopus/cnm25typ.mod

Ref. 1.1 1.2 2.1 2.2 2.3 2.4 3.1 3.2 3.3 4.1.a 4.1.b 4.2 4.3 4.4 4.5 4.6 5.1 5.2 5.3 5.4

Description N-well width >= 8um N-well spacing >= 8um GASAD width >= 2um GASAD spacing >= 4um N-well overlap to P-plus active >= 5um N-well spacing to N-plus active >= 5um Poly0 width >= 2.5um Poly0 spacing >= 6um Poly0 spacing to GASAD >= 6um Poly1 width inside GASAD >= 3um Poly1 width outside GASAD >= 2.5um Poly1 spacing >= 3um Poly1 overlap of GASAD >= 3um Poly1 overlap to GASAD >= 2.5um Poly1 spacing to GASAD >= 1.25um Poly1 overlap to Poly0 >= 3um N-plus overlap to GASAD >= 2.5um N-plus active spacing to P-plus active >= 2.5um N-plus spacing to Poly1 inside P-plus active >= 2um N-plus overlap to Poly1 inside N-plus active >= 1.5um

Ref. 6.1 6.2 6.3 6.4 6.6 6.9 6.10 7.1 7.2 7.3 8.1 8.2 8.3 8.4 8.5 8.6 9.1 9.2 10.1

Description Exact contact size = 2.5um x 2.5um Contact spacing >= 3um Contact overlap of GASAD >= 1um Contact overlap of Poly1 >= 1.25um Contact spacing to Poly1 inside GASAD >= 2um 6.9 Contact overlap of Poly0 >= 4um 6.10a Contact spacing to Poly1 & Poly0 >= 4um Metal1 width >= 2.5um Metal1 spacing >= 3um Contact overlap of Metal1 >= 1.25um Exact via size = 3um x 3um Via spacing >= 3.5um Via overlap of Metal1 >= 1.25um Via overlap of Metal2 >= 1.25um Via spacing to contact >= 2.5um Via spacing to Poly1 >= 2.5um Metal2 width >= 3.5um Metal2 spacing >= 3.5um Exact passivation window size = 100um x 100um

Table 2: Kit design rules for CNM25

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual

2.1

Datasheet Extraction

The analog behavior of the OpAmp can be fully described by the performance parameters listed in Table 3, so the internal topology of the circuit is hidden (i.e. black box) and easily incorporated into the design ow of a larger and complex integrated system. Static Large Signal Range: Dierential input (IR) Common mode input (CM R) Output (OR) Equivalent input oset (Vof f ) Quiescent power (Pd ) Dynamic

Slew rate (SR) Settling time (ts ) Maximum frequency (fmax ) Harmonic distortion (T HD)

Small Signal

Open loop dierential gain (GDC ) Common mode rejection (CM RRDC ) Power supply rejection (P SRRDC )

Bandwidth (BW ) GDC BW product (GBW ) Phase margin (m ) Impedance (Zin,out ) Equivalent input noise (Vneq )

Table 3: OpAmp main performance parameters. In practice, these performance values are commonly specied by the datasheet of Table 4. For the particular case of the Area parameter, it is somehow dicult to predict the nal value from the schematic view. Hence, only the sum of device silicon areas based on (1) will be taken into account before mask design, where Dcont stands for the minimum depth to open a contact window in each case according to the CNM25 design rules of Table 2. Area WCcomp LCcomp +
Mj

(WM j + Wcont )(LM j + Lcont )

(1)

In order to extract all the required parameters of Table 4, exhaustive electrical simulations of the OpAmp subcircuit must be performed with the suitable stimulus and boundary conditions. In this sense, the complete set of test circuits of Figure 3 is selected under the following congurations: openloop.cir: open-loop conguration. qopenloop{n}.cir: quasi open-loop {for noise} topology. follower{ac,mc,pulse,sin}.cir: follower scheme {for AC, MonteCarlo, delta, harmonic analysis}. cmrr.cir: specic CM RR measurement setup.

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Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual

Parameter IR CM R OR Vof f Pd GDC CM RRDC P SRRDC SR ts (1%) fmax T HD BW GBW m Vnieq Area

Comments + Mismatching ( ) Vin = 2.5V

Typical

Units mVpp V Vpp mV mW dB dB dB V/s ns KHz % Hz MHz

+ + Vout = 2 3V Vout = 3 2V Vout = OR Vout = OR/2@10KHz 3dB 1kHz to 1MHz According to (1)

mVrms mm2

VDD = +5V, VSS = 0V and Cload =10pF. Table 4: Typical OpAmp datasheet.

Vout Cload

Vdiff/2
+

Vin
+

Vout Cload
1F 1MOhm

Vcom

Ref: man.pdf

Vdiff/2
openloop.cir qopenloop{n}.cir

Vac
+

Vout
+

Vout Cload

Vin

Cload

Vcom

Vac

follower{ac,mc,pulse,sin}.cir

cmrr.cir

Figure 3: Test congurations for the OpAmp included in spiceopus/.

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Analog Integrated Circuits (27413) Lab Manual

spiceopus/openloop.cir openloop.cir * OpAmp configuration in open-loop .include cnm25typ.mod .include opamp.sub .options gmin=1e-15 cload vout 0 10p vcommon vcom 0 dc=2.5v xopamp vinn vinp vout vdd vss opamp vss vss 0 dc=0v vdd vdd 0 dc=5v vdiffp vinp vcom dc=0v ac=0.5 ediffn vcom vinn vinp vcom 1 .end spiceopus/openloop.cir spiceopus/qopenloop.cir qopenloop.cir * OpAmp configuration in quasi open-loop .include cnm25typ.mod .include opamp.sub .options gmin=1e-15 cload vout 0 10p vinput vin 0 dc=2.5v ac=1 xopamp vfb vin vout vdd vss opamp vss vss 0 dc=0v vdd vdd 0 dc=5v cdc vfb 0 1 rdc vfb vout 1000k .end spiceopus/qopenloop.cir

spiceopus/followerac.cir followerac.cir * OpAmp in follower configuration * for AC analysis .include cnm25typ.mod .include opamp.sub .options gmin=1e-15 cload vout 0 10p vinput vin 0 dc=2.5v ac=1 xopamp vout vin vout vdd vss opamp vss vss 0 dc=0v vdd vdd 0 dc=5v .end spiceopus/followerac.cir spiceopus/cmrr.cir cmrr.cir * OpAmp configuration for CMRR test .include cnm25typ.mod .include opamp.sub .options gmin=1e-15 cload vout 0 10p vcommon vcom 0 dc=2.5v xopamp vinn vinp vout vdd vss opamp vss vss 0 dc=0v vdd vdd 0 dc=5v vdiffp vinp vcom dc=0v ac=1 ediffn vinn vout vinp vcom 1 .end spiceopus/cmrr.cir

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Have a look to the rest of *.cir les in spiceopus/. Answer the following questions: What are the dierences between follower{ac,pulse,sin}.cir? Can you guess the purpose of followermc.cir? See opampmc.sub and cnm25mc.mod les. . . Why is qopenloopn.cir needed for?

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Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual Based on the previous test conguration circuits, a complete set of SPICE3 scripts are supplied for the electrical simulation and the numerical extraction of all the OpAmp parameters of Table 4:
spiceopus/test01.sp3 test01.sp3 * Differential mode input range .control destroy all delete all source openloop.cir save all dc vdiffp -2.5 2.5 5m let vdin=v(vinp)-v(vinn) let vout=v(vout) plot vout vs vdin xlabel Diff. Input ... dc vdiffp -2.5m 2.5m 5u let vdin=v(vinp)-v(vinn) let vout=v(vout) plot vout vs vdin xlabel Diff. Input ... .endc .end spiceopus/test01.sp3 spiceopus/test03.sp3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

spiceopus/test02.sp3 test02.sp3 * Common mode input range .control destroy all delete all source followerac.cir save all dc vinput 0 5 5m let vin=v(vin) let vout=v(vout) plot vin vout xlabel Input Voltage ... .endc .end

spiceopus/test02.sp3

test03.sp3 * Technology mismatching offset .control destroy all delete all source followermc.cir set appendwrite * Define an aproximation for a Gaussian random distribution * m = mean * s = std deviation * r = resolution define inv(r) 1/r define uniform(r) r*rnd(inv(r))-1/2 define gaussian(m,s,r) s*uniform(r)+2*s*uniform(r)+3*s*uniform(r)+m save all op let voff=v(vin)-v(vout) * CNM25 Mismatching parameters * Avto(NMOS,PMOS)=30mVum let Avto=30e-3*1e-6*unitvec(vector(1)) let mvtoA=@@modp1[vto] let mvtoB=@@modn3[vto] let mvtoC=@@modp8[vto] let mvtoD=@@modn9[vto] let mvtoE=@@modn6[vto] let svtoA=Avto/sqrt(@m1:xopamp[l]*@m1:xopamp[w]*@m1:xopamp[m]) let svtoB=Avto/sqrt(@m3:xopamp[l]*@m3:xopamp[w]*@m3:xopamp[m]) let svtoC=Avto/sqrt(@m8:xopamp[l]*@m8:xopamp[w]*@m8:xopamp[m])

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

let svtoD=Avto/sqrt(@m9:xopamp[l]*@m9:xopamp[w]*@m9:xopamp[m]) let svtoE=Avto/sqrt(@m6:xopamp[l]*@m6:xopamp[w]*@m6:xopamp[m]) repeat 100 let @@modp1[vto] = gaussian(op1.mvtoA,op1.svtoA,0.001) let @@modp2[vto] = gaussian(op1.mvtoA,op1.svtoA,0.001) let @@modn3[vto] = gaussian(op1.mvtoB,op1.svtoB,0.001) let @@modn4[vto] = gaussian(op1.mvtoB,op1.svtoB,0.001) let @@modp8[vto] = gaussian(op1.mvtoC,op1.svtoC,0.001) let @@modp7[vto] = gaussian(op1.mvtoC,op1.svtoC,0.001) let @@modp5[vto] = gaussian(op1.mvtoC,op1.svtoC,0.001) let @@modn9[vto] = gaussian(op1.mvtoD,op1.svtoD,0.001) let @@modn6[vto] = gaussian(op1.mvtoE,op1.svtoE,0.001) save v(vin) v(vout) op let op1.voff=(op1.voff;v(vin)-v(vout)) end let op1.voff = op1.voff[1, length(op1.voff) - 1] let mn=mean(op1.voff)*1e3 let std=sqrt(mean((op1.voff-mean(op1.voff))^2))*1e3 echo Systematic +/- random input offset = $(&mn) mV +/- $(&std) mV set nobreak set noprintheader set noprintindex set width = 32 print op1.voff > test03.dat .endc .end spiceopus/test03.sp3 spiceopus/test04.sp3 test04.sp3 * Queiscent power .control destroy all delete all save all source followerac.cir op let iddq=-i(vdd) let pd=iddq*v(vdd)*1e6 echo Quiescent power consumption = $(&pd)uW .endc .end spiceopus/test05.sp3 test05.sp3 * Bode plot .control destroy all delete all save all set units=degrees source openloop.cir ac dec 50 1 1e7 let Gmag=20*log10(mag(v(vout))) let Gph=phase(v(vout)) source qopenloop.cir ac dec 50 1 1e7 let Gmag=20*log10(mag(v(vout))) let Gph=phase(v(vout)) plot ac1.Gmag ac2.Gmag ac1.Gph ac2.Gph xlog ... .endc .end spiceopus/test04.sp3 spiceopus/test05.sp3

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Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual

spiceopus/test06.sp3 test06.sp3 * Common mode rejection ratio .control destroy all delete all save all source cmrr.cir ac dec 50 1 1e7 let CMRR=-20*log10(mag(v(vout))) plot CMRR xlog xlabel Frequency [Hz] ... .endc .end

spiceopus/test08.sp3 test08.sp3 * Slew-rate +/.control destroy all delete all save all source followerpulse.cir tran 1n 5u let vout=v(vout) plot vout xlabel Time [s] ylabel Output ... .endc .end spiceopus/test08.sp3 spiceopus/test09.sp3 test09.sp3 * Spectral noise analysis

spiceopus/test06.sp3 .control destroy all delete all save all source qopenloopn.cir op noise v(vout) vinput dec 100 1k 1000k plot sqrt(noise1.inoise_spectrum) vs ... let vnin=sqrt(noise2.inoise_total)*1e3 echo Equivalent input noise (1kHz to 1MHz) = ... .endc .end spiceopus/test09.sp3 spiceopus/test10.sp3 test10.sp3 * Harmonic distortion analysis .control destroy all delete all save all source followersin.cir tran 1u 2m 1m 1u let vout=tran1.v(vout) plot vout xlabel Time [s] ylabel Output ... fourier 10k vout .endc .end spiceopus/test07.sp3 spiceopus/test10.sp3

spiceopus/test07.sp3 test07.sp3 * Power supply rejection ratio +/.control destroy all delete all save all source followerac.cir let @vinput[acmag]=0 let @vdd[acmag]=1 ac dec 50 1 1e7 let PSRRP=-20*log10(mag(v(vout))) let @vdd[acmag]=0 let @vss[acmag]=1 ac dec 50 1 1e7 let PSRRN=-20*log10(mag(v(vout))) plot ac1.PSRRP ac2.PSRRN xlog xlabel ... .endc .end

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual In our context, the EDA tool used to perform all these circuit analysis is SPICEOPUS, an interactive electrical simulator based on SPICE3, as depicted in Figure 4. Its main Nutmeg commands are listed in Table 5, and they can be either scripted in les or called interactively from the shell.

Figure 4: SPICEOPUS interface.

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For the initial OpAmp dimensions of Table 1, ll the datasheet of Table 4: From SPICEOPUS shell type cd C:/cia...path/spiceopus/ Call test scripts simply by invoking its name, e.g. test01.sp3 Measure the parameters graphically or annotate the results from the shell Answer the following questions: test03.sp3: What is the meaning of systematic vs random oset? Compare with test01.sp3. test05.sp3: Why openloop.cir and qopenloop.cir show dierent results? Which one is correct? test06.sp3: How is the CM RRDC calculated? test07.sp3: How are the P SRRDC obtained? The report for this section must include the complete datasheet of Table 4 and the required simulation plots to extract the parameters, as well as the answers to all the in-line questions.

F. Serra-Graells

Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual

Group

Name alias bug cd help history quit rusage shell tutorial unalias version where set shift unset define diff let linearize reshape settype spec transpose undefine ac alter dc fourier ic nodeset noise op reset run resume save sens setcirc status step stop tf trace tran delete destroy display nameplot show showmod setplot asciiplot cursor echo hardcopy iplot listing plot print edit load source write

Description Create an alias for a command Mail a bug report Change directory Print summaries of Nutmeg commands Review previous commands Leave SPICE3 Resource usage Call the command interpreter Display hypertext help Retract an alias Print the version of SPICE3 Identify troublesome node or device Set the value of a variable Alter a list variable Clear a variable Dene a function Compare vectors Assign a value to a vector Interpolate to a linear scale Alter the dimensionality or dimensions of a vector Set the type of a vector Generate a Fourier transform vector Swap the elements in a multi-dimensional data set Retract a denition Perform an AC frequency response analysis Change a device or model parameter Perform a DC-sweep analysis Perform a fourier transform Set initial condition Set temptative DC solution Perform a noise analysis Perform an operating point analysis Reset an analysis Run analysis from the input le Continue a simulation after a stop Save a set of output vectors Run a sensitivity analysis Change the current circuit Display breakpoint and trace information Run a xed number of time points Set a breakpoint Run a Transfer Function analysis Trace nodes Perform a transient analysis Remove a trace or breakpoint Delete a data analysis List data in selected analysis Rename selected data analysis List device state List model parameter values Select data analysis Plot values using old-style character plots Move cursors Print text Save a plot to a le for printing Incremental plot Print a listing of the current circuit Plot values on the display Print values Edit the current circuit Load rawle data Read an SPICE3 input le Write data to a le

Ref: man.pdf

I/O

Graphics

Results

Simulation

Vectors

Vars.

General

Table 5: Summary of SPICE3 Nutmeg commands.

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Analog Integrated Circuits (27413) Lab Manual

2.2

Circuit Optimization

The main objective of this second section is to apply the analytical equations from theory to the optimization of the OpAmp. This design stage is based on sizing the MOSFET and capacitor devices only, without changing the internal architecture of Figure 2. The optimization process is organized in two steps: Initial solution. A starting point is asked to verify the relaxed specications listed in the Spec. column of Table 6. This initial solution can be easily derived from the dimensions of Table 1. Simulation results must be listed in the Initial column of the same datasheet. Optimization. Starting from the above Initial solution, a single parameter is chosen for the circuit optimization, while maintaining the rest of parameters within the specication range. Such circuit resizing must be based on the analytical equations given in theory [1]. After nishing this optimization process, performance results will be then displayed in the Optim. column of Table 6. As already said, the rest of rows must still fulll the requirements given in the Spec. column.

Ask the professor before choosing the optimization parameter! Possible alternatives are: GDC , GBW or SR.

Parameter IR CM R OR Vof f Pd GDC CM RRDC P SRRDC SR ts (1%) fmax T HD BW GBW m Vnieq Area

Comments + Mismatching ( ) Vin = 2.5V

Spec. >4 <1 >3 <30 <1.5 >60 >50 >50 >50 >1.5 >1.5 <1500 <1500 <1 >1 >50 <5 <0.025

Initial

Optim.

Units mVpp V Vpp mV mW dB dB dB V/s ns KHz % Hz MHz

+ + Vout = 2 3V Vout = 3 2V Vout = OR Vout = OR/2@10KHz 3dB 1kHz to 1MHz According to (1)

mVrms mm2

VDD = +5V, VSS = 0V and Cload =10pF. Table 6: OpAmp design datasheet. 14/21
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Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual

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The report for this second part includes both the initial and optimized device dimensions, together with the datasheet of Table 6 and all the required graphs to demonstrate the performance of the OpAmp. For each optimization iteration, it is advised to carefully check the following key parameters: GDC , GBW , SR, m , Area and PD . Students are encouraged to develop their own test script (datasheet.sp3) in order to extract these 6 paremeters automatically. For such a purpose, some useful SPICE3 code examples are given below. The comprehensive explanation of the optimization strategy is of major importance, including geometry and biasing approaches, as well as the second order eects that have limited the nal values!

SPICE3 receipts * Working with multiple circuits source file1.cir source file2.cir setcirc ckt1 * Reporting results echo G(DC)=$(&GDC)dB

* Cleaning results destroy ac2 * Interfacing with circuits let w1=@m1:xopamp[w] let @m2:xopamp[w]=w1

* Working with multiple analysis ac dec 50 1 10meg let G=20*log10(mag(v(vout))) setcirc ckt2 ac dec 50 1 10meg let G=20*log10(mag(v(vout))) plot ac1.G ac2.G xlog xlabel Frequency... setplot ac1

* Parametric analysis foreach w6 10u 20u 30u let @m6:xopamp[w]=$w6 ac dec 50 1 10meg let GDC=20*log10(mag(v(vout)[0])) let ac1.GDC=(ac1.GDC;GDC) end let mydata=ac1.GDC

* Automatic calculus let GDC=G[0] let GBW=frequency[sum(G ge 0)]

* Exporting results set nobreak set noprintheader set noprint index set width=132 print mydata > fileout.txt SPICE3 receipts

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual

2.3

Physical CMOS Design

Once the optimal dimensions for all devices of the OpAmp schematic have been obtained, the physical design of the CMOS circuit begins with the GLADE tool. Geometrical mask edition is performed interactively in the main drawing window of Figure 5, where commands can be called from the header menu and buttons, typed at the bottom console, or invoked through the bindkeys dened in EditEdit Bindkeys. The meaning of the physical layers of the CNM25 are listed in Table 7. GDS num. 1 2 4 3 5 6 7 9 10 8 Name NTUB GASAD POLY1 POLY0 NPLUS WINDOW METAL METAL2 VIA CAPS Explanation N-well GASAD PolySi for MOS gate PolySi for capacitors only N-plus implant Contact window Metal 1 Metal 2 Metal 1 to 2 via Passivation window

Table 7: CNM25 kit layer table.

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For MS Windows, start GLADE by double-click on glade.bat. Set the grid parameters as shown in Figure 5!!! Open the design library located in glade/OpAmpLib. Build the optimized OpAmp from the template cell opamp-layout and the recommended layout analog techniques of Table 8. The cell can be stretched horizontally only, so their top and bottom power rails can be aligned with other cells. Also, input and output pins must be accessible from North and/or South. Finally, the N-well template may be modied in order to allocate the PMOS devices from the schematic, but the lateral structures must be preserved to allow adjacent cells.

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Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual

pop-up menus

layer selection window

(Tools!LSW)

merge (shift+m)

selected

library browser

(Tools!Library Browser) object properties (q)

stretch (s)

non-selectable non-visible

ruler (k) clear rulers (shift+k)

chop (shift+c)

console window

(Tools!Message Window)

copy (c)

move (m) (e) (shift+e) Full for move, ... Edge for strech

other useful functions:

add to selection (shift) remove from selection (ctrl) deselect all (ctrl+d) redraw (ctrl+d) undo (u)

boxed zoom-in

boxed zoom-out

Grid parameters for CNM25

Figure 5: GLADE main window.

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual Once the OpAmp layout is drawn, some physical verication steps must be executed: DRC: The main purpose of this checker is to verify the fabrication feasibility from the geometrical viewpoint only. For such a purpose, the technological le cnm25drc.py is included in the glade/ directory with the main CNM25 design rules listed in Table 2.
# Get raw nwell active polygate polycap nimp cont metal1 via12 metal2 pad glade/cnm25drc.py (abstract) layers = geomGetShapes("NTUB", "drawing") = geomGetShapes("GASAD", "drawing") = geomGetShapes("POLY1", "drawing") = geomGetShapes("POLY0", "drawing") = geomGetShapes("NPLUS", "drawing") = geomGetShapes("WINDOW", "drawing") = geomGetShapes("METAL", "drawing") = geomGetShapes("VIA", "drawing") = geomGetShapes("METAL2", "drawing") = geomGetShapes("CAPS", "drawing")

# Form derived layers gate = geomAnd(polygate, active) ngate = geomAnd(gate, nimp) pgate = geomAndNot(gate, ngate) cpoly = geomAnd(polygate, polycap) polygatecont= geomAnd(polygate, cont) polycapcont = geomAnd(polycap, cont) activecont = geomAnd(active, cont) allcon = geomOr(geomOr(polygatecont, polycapcont),activecont) badcon = geomAndNot(allcon, metal1) metal1via = geomAnd(metal1, via12) badvia = geomAndNot(metal1via, metal2) diff = geomAndNot(active, gate) ndiff = geomAnd(diff, nimp) pdiff = geomAndNot(diff, nimp) ntap = geomAnd(ndiff, nwell) ptap = geomAndNot(pdiff, nwell) # Form connectivity geomConnect( [ [ntap, nwell, ndiff], [cont, ndiff, metal1], [cont, pdiff, metal1], [cont, polygate, metal1], [cont, polycap, metal1], [via12, metal1, metal2] ] ) # Start design rule checking print "4.X. Checking Poly1..." geomWidth(gate, 3, "4.1.a. Poly1 width inside GASAD >= 3um") geomWidth(geomAndNot(polygate, gate), 2.5, "4.1.b. Poly1 width outside GASAD >= 2.5um") geomSpace(polygate, 3, diffnet, "4.2. Poly1 spacing (different net) >= 3um") geomNotch(polygate, 3, "4.2. Poly1 notch >= 3um") geomOverlap(active, polygate, 3 , "4.3. Poly1 overlap of GASAD >= 3um") geomOverlap(polygate, active, 2.5, "4.4. Poly1 overlap to GASAD >= 2.5um") geomSpace(polygate, active, 1.25, samenet, "4.5. Poly1 spacing to GASAD (same net) >= 1.25um") geomSpace(polygate, active, 1.25, diffnet, "4.5. Poly1 spacing to GASAD (different net) >= ... geomExtension(polygate, polycap, 3, "4.6. Poly1 overlap to Poly0 >= 3um") ... glade/cnm25drc.py (abstract)

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Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual

Layout Rule Unitary Elements Large Area

Bad

Good

Process Resolution

Same Orientation

Minimum Distance

(W/L)>>1

Interleaved (W/L)<<1

Same Sorround
Dummy Dummy

Same Symmetry

Iso Therms

Common Centroid

Table 8: Analog layout style guide for MOS device matching.

Ref: man.pdf

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Analog Integrated Circuits (27413) Lab Manual Starting the rule checker (VerifyDRCRun) is as simple as specifying the location of the cnm25drc.py le, as shown in Figure 6. In order to play with this DRC tool, the sample cell drctest-layout is also included in the design library OpAmpLib. Following again the example Figure 6, the resulting DRC errors (VerifyDRCView Errors) can be easily browsed by category or individually.

specify the full path!

object properties (q)

Figure 6: Browsing the DRC errors with GLADE for the drctest-layout cell.

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Apply the same DRC method to correct any error in opamp-layout.

F. Serra-Graells

Ref: man.pdf

Analog Integrated Circuits (27413) Lab Manual Circuit Extraction: Not implemented yet! Layout Versus Schematic (LVS): Not implemented yet! Post-layout Simulation: Not implemented yet!

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The main results for this third and last section of the lab exercise are: 1. The CMOS layout of the OpAmp block as a GDS le to be sent to the IC foundry (FileExportExport GDS2). 2. The overall dimensions of the OpAmp cell.

Glossary

ASIC Application Specic Integrated Circuit CAD Computer Aided Design CNM25 2.5m 2-polySi 2-metal CMOS technology from the Centre Nacional de Microelectrnica DRC Design Rule Checker EDA Electronic Design Automation IC Integrated Circuit LVS Layout Versus Schematic OpAmp Operational Amplier VLSI Very Large Scale Integration

References
[1] P. E. Allen and D. R. Holberg. CMOS Analog Circuit Design. Oxford University Press, 1987.

Ref: man.pdf

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