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Logic families
Bipolar Uses bipolar junction transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density MOS - Uses nMOS and pMOS Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration
Transistor Evolution
Transistor Bipolar
First
First First TTL ECL
Bipolar
TTL (Transistor-transistor logic) had been used for many years . ECL (Emitter Coupled Logic) : basic element is the differential BJT pair. BiCMOS : combines the high speed of BJTs with low power dissipation of CMOS . GaAs : for very high speed due to the high carrier mobility . Has not demonstrated its potential commercially .
CMOS
Replaced NMOS (much lower power dissipation) Small size, ease of fabrication Channel length has decreased significantly (as short as 0.06 m or shorter) Low power dissipation than bipolar logic circuits ( can pack more) . High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar) High levels of integration for both logic (chapter 10) and memory circuits. Dynamic logic to further reduce power dissipation and to increase speed performance .
Features to be Considered
Interface circuits for different families Logic flexibility Speed Complex functions Noise immunity Temperature Power dissipation Co$t
MODULE
+ GATE
CIRCUIT
DEVICE G S n+ D n+
MOS Structure
NMOS
Metal: the gate of the transistor was made of aluminum metal in the early days, but is made of polysilicon today (for the past 25 years or more). Oxide: silicon dioxide is the material between the gate and the channel Semiconductor: the semiconductor material is silicon, a type IV element in the periodic chart. Each silicon atom bonds to four other silicon atoms in a tetrahedral crystal structure.
gate
N+ N N+ P+
oxide
gate
P+
source
P substrate
drain
source
N well
drain
N channel device
P channel device
N channel device: built directly in the P substrate with N-doped source and drain junctions and normally N-doped gate conductor
Requires positive voltage applied to gate and drain (with respect to source) for electrons to flow from source to drain (thought of as positive drain current)
P channel device: built in an N-well (a deep N-type junction diffused into the P substrate) with P-doped source and drain junctions and N or P-doped gate
Requires negative voltage applied to gate and drain (with respect to source) for electrons to flow from drain to source (thought of as negative drain current)
oxide
N+ N
source
gate
N+
drain
P substrate
gate
PMOS Device:
Negative voltage (0 or low) on gate relative to source turns device ON and allows (negative) current to flow from drain to source (closes switch) Zero volts on gate relative to source (1 or high) turns device OFF (closes switch) source (vs drain) is the most positive terminal
oxide gate
source
P+
N well
P+
drain
gate
polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9)
Symbols
NMOS
Vg + Vgs Vs + Vgd Vds + Vd
Operation
Three regions of operation Cutoff Linear Saturation
Cut-Off Mode
Vgs = 0
+ s n+
+ d n+
Vgd
=0
p-type body b
No channel formed
Operation
Linear Mode
Vgs > Vt
+ s n+
+ d n+
Vgd = Vgs
Vds = 0
p-type body b
Vgs > Vt
+ s n+
+ d n+
p-type body b
Operation
Saturation Mode
Vgs > Vt
+ -
+ -
Vgd < Vt
n+ p-type body b
n+
The voltage drop at the induced channel (from the pinch-off point to the source remains fixed at Vgs Vt
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
Source Polysilicon SiO2 Gate Drain
p+ n
p+ bulk Si
Transistors as Switches
We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain
g=0 d nMOS g s s d ON s s s d OFF s d OFF g=1 d ON
d pMOS g
MOS Transistors
Voltage-controlled resistance
PMOS
NMOS
MOSFET as Switches
MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor nFET: an n-channel MOSFET that uses negatively charged electrons for electrical current flow pFET: a p-channel MOSFET that uses positive charges for current flow In many ways, MOSFETs behave like the idealized switches introduced in the previous section
(a) nFET symbol
The voltage applied to the gate determines the current flow between the source and drain terminals
(b) pFET symbol Figure 1 Symbols used for nFETs and pFETs
MOSFET as Switches
Early generations of silicon MOS logic circuits used both positive and negative supply voltages as Figure 2 showing In modern designs require only a single positive voltage VDD and the ground connection, e.g. VDD = 5 V and 3.3 V or lower The relationship between logic variables x and its voltages Vx
0 Vx VDD 0V VDD
(1)
(2)
(a) Power supply connection (b) Logic definitions Figure 3 Single voltage power supply
In general,
Low voltages correspond to logic 0 values High voltages correspond to logic 1 values
(a) Open
(b) Closed
nFET
y x A which is valid iff A 1
(3)
pFET
y x A which is valid iff A 0
(4)
(a) Open (b) Closed
An nFET is characterized by a threshold voltage VTn that is positive, typical is around VTn = 0.5 V to 0.7 V If VGSn VTn , then the transistor acts like an open (off) circuit and there is no current flow between the drain and source If VGSn VTn , then the nFET drain and source are connected and the equivalent switch is closed (on)
Thus, to define the voltage VA that is associated with the binary variable A
VA VGSn
(5)
(b) Logic translation Figure 6 Threshold voltage of an nFET
An pFET is characterized by a threshold voltage VTp that is negative, typical is around VTp = 0.5 V to 0.8 V
If VSGp VTp , then the transistor acts like an open (off)
switch and there is no current flow between the drain and source
(a) Source-gate voltage
VA
0V
VA VDD VSGp
VDD VTp
VA VDD
(9)
(b) Logic translation Figure 7 pFET threshold voltage
(8) Note that the transition between a logic 0 and a logic 1 is at (8) !
An ideal electrical switch can pass any voltage applied to it As Figure 8 (b), the output voltage Vy is reduced to a value
V1 VDD VTn
(10)
since
VGSn VTn
Thus, we say that the nFET can only pass a weak logic 1; in other word, the nFET is said to pass a strong logic 0 can pass a voltage in the range [0, V1]
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
Static CMOS
VDD In1 In2 In3
PUN
PMOS Only
F=G
PDN
NMOS Only
VSS
Vdd
Inverter Schematic
PMOS source
P-MOS
PMOS drain Vin Vout
NMOS drain
N-MOS
NMOS source
Operation:
If Vin is down (0 volts), NMOS is OFF and PMOS is ON pulling Vout to Vdd (high = 1) If Vin is up (at Vdd), NMOS is ON hard and PMOS is OFF pulling Vout low to Gnd (0) With Vin at 0 or Vdd, no dc current flows in inverter
Gnd
Inverter Symbol
CMOS Inverter
A 0 1 Y
VDD A Y
GND
CMOS Inverter
A 0 1 Y
0
A=1
VDD OFF
Y=0
ON
A Y
GND
CMOS Inverter
A 0 1 Y 1 0
A=0
VDD ON
Y=1
OFF
A Y
GND
a g1 g2
a g1 b (c) g2 0
a 0 b OFF 0
a 1 b ON 1
a 0 b ON 1
a 1 b ON
a g1 b (d) g2 0
a 0 b ON 0
a 1 b ON 1
a 0 b ON 1
a 1 b OFF
A B C
Pulldown GND
Y A B
A B Y
Logic Identities
If a closed path exists in PDN, then the output is pulled low. Thus the logic function realized is the complement (inverted) version of the Boolean expression. output
A B C
Pulldown GND
B A
Observe: take the expression for PDN and use DeMorgans Law to write it in terms of complemented input variables. Complemented variables are true when the input level is low. Thus, this gives exactly the form of C the PUN
In this case: not A or ( not B and not C)
VDD
OUT = D + A (B+C)
A D B C
OUT = D + A (B+C)
A D B C
VDD B A C D
OUT = D + A (B+C)
A D B C
Vcc
Gnd
Vcc C E D
D Vcc
F A B F Gnd A
C
D E
Gnd
83
Two Versions of C (A + B)
A
VDD
C
VDD
GND
GND
AOI Logic Function (OR) Design of XOR gate using CMOS logic.
AND-OR-INVERT logic function(AOI) implements operation in the order AND,OR,NOT. For example , Let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR (C AND D))
Step 3:
Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw parallel connection. So, A.B series connected in parallel with C.D as shown in figure.
Step 5: Take output at the point in between nMOS and pMOS networks.
Example: x = ab+cd
OAI Logic Function (OR) Design of XNOR gate using CMOS logic. OR-AND-INVERT logic function(AOI) implements operation in the order OR,AND,NOT. For example , Let us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR B)AND (C OR D))
A B C D
(b) pFET OAI circuit (b) Series-connected pFETs Figure 2.46 pFET logic formation Figure 2.47 pFET arrays for AOI and OAI gates
Bubble Pushing
(b) NOR - AND Figure 2.52 Bubble pushing using DeMorgan rules (b) Series-connected pFETs Figure 2.51 Assert-low models for pFETs
An important example of using an AOI circuit is constructing Exclusive-OR (XOR) and Exclusive-NOR circuits
a b a b a b a b a b a b
a
a
b (a
b) a b a b
b a b a b
(a) AOI22
(b) AOI321
(c) AOI221
E Vcc
Gnd
Half-Adder
Logic Equations
Truth Table
x 0 0 1 1
y 0 1 0 1
C 0 0 0 1
S 0 1 1 0
C = x y S = x y
Schematic
Full Adder
Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit.
Inputs Outputs
Sum S
XY C-in 0
00 0
1 3
01
2
11
6
10
4
1
7 5
1 1
Y C-in
Carry C-out
XY C-in 0
00 0
1 3
01
2
11
6
10
4
1
7
5
1
Y
C-in
ai
bi
Cout
Full Adder
Cin
si
The sum and carry outputs are described as:
si
ci 1 ai bi ci ai bi ci ai bi ci ai bi ci ai bi ai ci bi ci
XYC-in
Sum S
C-in
XYC-in
X Y
XY
C-out
Full Adder
S
C-in
X C-in Y C-in
XC-in
C-out
YC-in
Cont..
Outputs
ci+1 0 0 0 1 0 1 1 1
Propagate Generate
Propagate
Generate
PGK
G=AB P=A B
Propagate: Cout = C
K = ~A ~B
Full-Adder Implementation
Full Adder operations is defined by equations:
si
ai
bi
ci
pi
ci
gi
bi
pici
ai bi
ai
gi
ai bi
cout
One-bit adder could be implemented as shown
cin
si
High-Speed Addition
ci
ai
1
gi
pi ci
pi ai bi
bi
gi
ai bi
0
cout
si
pi
ci
s 1
cin
si
Multiplexers
S
S 0 0 1 D1 X X 0 D0 0 1 X Y
D0 D1
0 Y 1
Multiplexers
S
S 0 0 1 D1 X X 0 D0 0 1 X Y 0 1 0
D0 D1
0 Y 1
D1 S D0
4 2 4
2 4 2 2
Inverting Mux
Inverting multiplexer
Use compound AOI22 Or pair of tristate inverters Essentially the same thing
D0 S S
S D1 Y S D1 1 D0
S 0 Y
Tristate Inverter
A EN Y EN
Tristate Inverter
A A EN Y EN Y
EN = 0 Y = 'Z'
EN = 1 Y=A
D0 S S
D1 S Y S D1 1
S D0 0 Y
Inverting Mux
Inverting multiplexer
Use compound AOI22 Or pair of tristate inverters Essentially the same thing
X
A
Ci
Ci A B
S
Ci
VDD
A Co B Ci A
28 Transistors
24 transistors
and 2 inverter Total 24+4 =28 Transistors
Mirror Adder
Stick Diagram
VDD
Ci Co
A Ci
Co
Ci
S GND
139
OAI/AOI duality
A B C OUT
Vdd B C
A B C OUT
A
Out B C Gnd A
A
B
Series Transistors
increases effective L
Parallel Transistors
increases effective W
1
W
1
R
W W
R R
0
0
Designing a CMOS gate: Find pulldown NMOS network from logic function or by inspection Find pullup PMOS network - By inspection - Using logic function - Using dual network approach Size transistors using equivalent inverter - Find worst-case pullup and pulldown paths - Size to meet rise/fall or threshold requirements
For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.
For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased.
.
Exercise: Design and compare two input NAND and NOR gates
Assume K'n=2K'p
1.
2. 3.
4.
F or an inverter the (W/L) of the NMOS is (W/L)n and that for the PMOS is (W/L)p for Fall time = Rise Time. For the worst case design of the NAND gate, you should set the W/L ratio of the NMOS transistors to 2*(W/L)n (i.e. twice that of the inverter) and that of the PMOS to (W/L)p (i.e. equal to that of the inverter)
A
B
Parallel transistors: assume the worst case, i.e. only one of the parallel transistor is ON.
Assumption: Equal rise delay and fall delay Consideration: Effective Resistance
Trade-Off
Increase W to reduce the effective Resistance for the pull down network. The area is increased.
i input CMOS NAND i WP /LP =2.5 WN /LN Two input CMOS NAND 2 WP /LP =2.5 WN /LN
Total area of the NMOS and PMOS channels is seen as L=2u w=4u ratio 2.5 times CMOS NAND 2 input gate 2( 8u)(2u) + 2 (10u)(2u) = 72um2 CMOS INVERTER gate ( 4u)(2u) + (10u)(2u) = 28um2
WN LN + WP LP
Example
WN LN + WP LP
L=2u w=4u ratio 2.5 time CMOS NAND gate -2 input gate 2( 8u)(2u) + 2 (10u)(2u) = 72um2
A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance of the transistor The latter is achieved by increasing the W/L ratio of the device
Rp A Rn A Rn B B
Rp
CL
Cint
A=B=1 0
Input Data Delay (psec) 69 62 50 35 76 57
Voltage, V
A=1
0, B=1
Rp A Rn A Cint B CL Rp
A=1, B=1 0
300
400
time, psec
Conclusions: Estimates of delay can be fairly Rn complex have to consider internal node B capacitances and the data patterns
B A 4 3
8 6
C
D 4 6
8 6
OUT = D + A (B + C)
A
D 1 B 2C
2
2
Red sizing assuming Rp = Rn Follow short path first; note PMOS for C and B 4 rather than 3 average in pull-up chain of three (4+4+2)/3 = 3 Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where Rn = 3 Rp) Sizing rules of thumb PMOS = 3 * NMOS 1 in series = 1 2 in series = 2 3 in series = 3 etc.
Tutorial on Transistor Sizing Problem #1 (Static CMOS logic): Design a 3-input CMOS NAND gate (PUN/PDN) with fan-out of 3. Total output load of the NAND gate is equal to 15fF and n/p = 2.5. For 0.35m process technology tox = 7.6*10-9m, ox = 35*10-12F/m. Compare the above design with that of a 3-input NOR (PUN/PDN) gate. State any benefits of one implementation over the other. For the sake of simplicity assume all capacitance is lumped and gate capacitance neglecting diffusion and wiring capacitance. Solution: Cox = oxWL/ tox = 15fF. So W = 9.2m. Leff = 0.35m. Assuming output load is all gate capacitance. This is a simplifying assumption made for this problem. A more realistic approach would be to calculate the diffusion and wiring capacitances as well. Equivalent inverter for fan-out of 3 and n/p = 2.5 would result in: Wp = 2.5*Wn for equal rise and fall times. Also, Wp + Wn = 9.2/3 = 3.16m for fan-out of 3. Solving the above equations we have, Wp = 2.23m and Wn = 0.89m.
A 2.23 B 2.23 C 2.23
A B C
NAND implementation NAND implementation: Therefore, for the 3-ip NAND gate implementation, each PDN n-MOS transistor will be: 3*0.89m = 2.67m
and each p-MOS transistor in the PUN network will be: 2.23m NOR implementation: For a 3-ip NOR gate implementation, each PDN n-MOS transistor will be: 0.89m Each PUN p-MOS transistor will be 3*2.23m = 6.69m Area comparison: Total gate area of NAND gate is: 3*(2.67+2.23)m = 14.7m Total gate area of NOR gate is: 3*(6.69+0.89) m = 22.7m
A 0.89
6.69
6.69
6.69 C
0.89
0.89
NOR implementation
Thus we infer that the NAND gate has less area and power compared to the NOR gate for identical loading and fan-out conditions and is the preferred implementation.