ULN2003 Datasheet

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A
www.ti.com SLRS027K DECEMBER 1976 REVISED AUGUST 2011
HIGH-VOLTAGE, HIGH-CURRENT DARLINGTON TRANSISTOR ARRAYS

Check for Samples: ULN2002A, ULN2003A, ULN2003AI, ULN2004A, ULQ2003A, ULQ2004A
1
FEATURES
500-mA-Rated Collector Current (Single Output) High-Voltage Outputs: 50 V Output Clamp Diodes Inputs Compatible With Various Types of Logic Relay-Driver Applications
ULN2002A . . . N PACKAGE ULN2003A . . . D, N, NS, OR PW PACKAGE ULN2004A . . . D, N, OR NS PACKAGE ULQ2003A, ULQ2004A . . . D OR N PACKAGE (TOP VIEW)
1B 2B 3B 4B 5B 6B 7B E
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1C 2C 3C 4C 5C 6C 7C COM
DESCRIPTION
The ULN2002A, ULN2003A, ULN2003AI, ULN2004A, ULQ2003A, and ULQ2004A are high-voltage high-current Darlington transistor arrays. Each consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of a single Darlington pair is 500 mA. The Darlington pairs can be paralleled for higher current capability. Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line drivers, and logic buffers. For 100-V (otherwise interchangeable) versions of the ULN2003A and ULN2004A, see the SN75468 and SN75469, respectively. The ULN2001A is a general-purpose array and can be used with TTL and CMOS technologies. The ULN2002A is designed specifically for use with 14-V to 25-V PMOS devices. Each input of this device has a Zener diode and resistor in series to control the input current to a safe limit. The ULN2003A and ULQ2003A have a 2.7-k series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. The ULN2004A and ULQ2004A have a 10.5-k series base resistor to allow operation directly from CMOS devices that use supply voltages of 6 V to 15 V. The required input current of the ULN/ULQ2004A is below that of the ULN/ULQ2003A, and the required voltage is less than that required by the ULN2002A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 19762011, Texas Instruments Incorporated

SLRS027K DECEMBER 1976 REVISED AUGUST 2011 www.ti.com
ORDERING INFORMATION (1)

TA PDIP N PACKAGE (2) Tube of 25 Tube of 40 Reel of 2500 20C to 70C SOIC D Reel of 2500 Tube of 40 Reel of 2500 SOP NS TSSOP PW PDIP N Reel of 2000 Tube of 90 Reel of 2000 Tube of 25 Tube of 40 40C to 85C SOIC D Reel of 2500 Tube of 40 Reel of 2500 SOP NS PDIP N 40C to 105C SOIC D TSSOP PW (1) (2) Reel of 2000 Tube of 425 Tube of 40 Reel of 2500 Reel of 2500 ORDERABLE PART NUMBER ULN2002AN ULN2003AN ULN2004AN ULN2003AD ULN2003ADR ULN2003ADRG3 ULN2004AD ULN2004ADRG3 ULN2003ANSR ULN2004ANSR ULN2003APW ULN2003APWR ULQ2003AN ULQ2004AN ULQ2003AD ULQ2003ADR ULQ2004AD ULQ2004ADR ULN2003AINSR ULN2003AIN ULN2003AID ULN2003AIDR ULN2003AIPWR ULN2004A ULN2003A ULN2004A UN2003A ULQ2003A ULQ2004AN ULQ2003A ULQ2004A ULN2003AI ULN2003AIN ULN2003AI UN2003AI ULN2003A TOP-SIDE MARKING ULN2002AN ULN2003AN ULN2004AN
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
LOGIC DIAGRAM
9 COM 1 1B 2 2B 3 3B 4 4B 5 5B 6 6B 7 7B 10 7C 11 6C 12 5C 13 4C 14 3C 15 2C 16 1C

SCHEMATICS (EACH DARLINGTON PAIR)
10.5 kW 7.2 kW 3 kW
ULN2002A
RB
ULN/ULQ2003A: RB = 2.7 kW ULN2003AI: RB = 2.7 kW ULN/ULQ2004A: RB = 10.5 kW 7.2 kW 3 kW
ULN2003A, ULN2003AI, ULN2004A, ULQ2003A, ULQ2004A
All resistor values shown are nominal. The collector-emitter diode is a parasitic structure and should not be used to conduct current. If the collector(s) go below ground an external Schottky diode should be added to clamp negative undershoots.

ABSOLUTE MAXIMUM RATINGS (1)

at 25C free-air temperature (unless otherwise noted)
MIN VCC VI Collector-emitter voltage Clamp diode reverse voltage (2) Input voltage (2) Peak collector current IOK Output clamp current Total emitter-terminal current ULN200xA TA Operating free-air temperature range ULN200xAI ULQ200xA ULQ200xAT D package JA Package thermal impedance (3)
(4)
MAX 50 50 30
UNIT V V V mA mA A
See Figure 14 and Figure 15
500 500 2.5 20 40 40 40 70 105 85 105 73 67 64 108 36 54 150 260 65 150
N package NS package PW package D package N package
C/W
JC TJ Tstg (1) (2) (3) (4) (5) (6)
Package thermal impedance (5)
(6)
Operating virtual junction temperature Lead temperature for 1.6 mm (1/16 inch) from case for 10 seconds Storage temperature range
C C C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Maximum power dissipation is a function of TJ(max), JC, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/JC. Operating at the absolute maximum TJ of 150C can affect reliability. The package thermal impedance is calculated in accordance with MIL-STD-883.
ELECTRICAL CHARACTERISTICS
TA = 25C
PARAMETER VI(on) VCE(sat) VF ICEX II(off) II IR Ci On-state input voltage Collector-emitter saturation voltage Clamp forward voltage Collector cutoff current Off-state input current Input current Clamp reverse current Input capacitance TEST FIGURE Figure 6 Figure 4 Figure 7 Figure 1 Figure 2 Figure 2 Figure 3 Figure 6 TEST CONDITIONS VCE = 2 V, II = 250 A, II = 350 A, II = 500 A, IF = 350 mA VCE = 50 V, VCE = 50 V, TA = 70C VCE = 50 V, VI = 17 V VR = 50 V VI = 0, TA = 70C f = 1 MHz II = 0 II = 0 VI = 6 V IC = 500 A 50 65 0.82 1.25 100 50 25 IC = 300 mA IC = 100 mA IC = 200 mA IC = 350 mA 0.9 1 1.2 1.7 ULN2002A MIN TYP MAX 13 1.1 1.3 1.6 2 50 100 500 A mA A pF A V V UNIT V

TA = 25C
PARAMETER TEST FIGURE TEST CONDITIONS IC = 125 mA IC = 200 mA VI(on) On-state input voltage Figure 6 VCE = 2 V IC = 250 mA IC = 275 mA IC = 300 mA IC = 350 mA II = 250 A, VCE(sat) Collector-emitter saturation voltage Figure 5 Figure 1 ICEX VF II(off) Collector cutoff current Clamp forward voltage Off-state input current Figure 2 Figure 8 Figure 3 II = 350 A, II = 500 A, VCE = 50 V, VCE = 50 V, TA = 70C IF = 350 mA VCE = 50 V, TA = 70C, VI = 3.85 V II Input current Figure 4 VI = 5 V VI = 12 V IR Ci Clamp reverse current Input capacitance Figure 7 VR = 50 V VI = 0, 50 TA = 70C f = 1 MHz 15 100 25 15 IC = 500 A 50 IC = 100 mA IC = 200 mA IC = 350 mA II = 0 II = 0 VI = 6 V 1.7 65 0.93 1.35 0.35 1 0.5 1.45 50 100 25 A pF mA 2 50 1.7 65 0.9 1 1.2 1.1 1.3 1.6 50 100 0.9 1 1.2 3 8 1.1 1.3 1.6 50 100 500 2 V A A V 2.4 2.7 7 ULN2003A MIN TYP MAX ULN2004A MIN TYP MAX 5 6 V UNIT
TA = 25C
PARAMETER TEST FIGURE TEST CONDITIONS IC = 200 mA VI(on) On-state input voltage Figure 6 VCE = 2 V II = 250 A, VCE(sat) ICEX VF II(off) II IR Ci Collector-emitter saturation voltage Collector cutoff current Clamp forward voltage Off-state input current Input current Clamp reverse current Input capacitance Figure 5 Figure 1 Figure 8 Figure 3 Figure 4 Figure 7 II = 350 A, II = 500 A, VCE = 50 V, IF = 350 mA VCE = 50 V, VI = 3.85 V VR = 50 V VI = 0, f = 1 MHz 15 IC = 500 A 50 IC = 250 mA IC = 300 mA IC = 100 mA IC = 200 mA IC = 350 mA II = 0 1.7 65 0.93 1.35 50 25 0.9 1 1.2 ULN2003AI MIN TYP MAX 2.4 2.7 3 1.1 1.3 1.6 50 2 A V A mA A pF V V UNIT

TA = 40C to 105C
PARAMETER TEST FIGURE TEST CONDITIONS IC = 200 mA VI(on) On-state input voltage Figure 6 VCE = 2 V II = 250 A, VCE(sat) ICEX VF II(off) II IR Ci Collector-emitter saturation voltage Collector cutoff current Clamp forward voltage Off-state input current Input current Clamp reverse current Input capacitance Figure 5 Figure 1 Figure 8 Figure 3 Figure 4 Figure 7 II = 350 A, II = 500 A, VCE = 50 V, IF = 350 mA VCE = 50 V, VI = 3.85 V VR = 50 V VI = 0, f = 1 MHz 15 IC = 500 A 30 IC = 250 mA IC = 300 mA IC = 100 mA IC = 200 mA IC = 350 mA II = 0 1.7 65 0.93 1.35 100 25 0.9 1 1.2 ULN2003AI MIN TYP MAX 2.7 2.9 3 1.2 1.4 1.7 100 2.2 A V A mA A pF V V UNIT
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST FIGURE TEST CONDITIONS IC = 125 mA IC = 200 mA VI(on) On-state input voltage Figure 6 VCE = 2 V IC = 250 mA IC = 275 mA IC = 300 mA IC = 350 mA II = 250 A, VCE(sat) Collector-emitter saturation voltage Figure 5 Figure 1 ICEX VF II(off) Collector cutoff current Clamp forward voltage Off-state input current Figure 2 Figure 8 Figure 3 II = 350 A, II = 500 A, VCE = 50 V, VCE = 50 V, TA = 70C IF = 350 mA VCE = 50 V, TA = 70C, VI = 3.85 V II Input current Figure 4 VI = 5 V VI = 12 V IR Ci Clamp reverse current Input capacitance Figure 7 VR = 50 V VI = 0, TA = 25C f = 1 MHz 15 100 100 25 15 IC = 500 A IC = 100 mA IC = 200 mA IC = 350 mA II = 0 II = 0 VI = 6 V 1.7 65 0.93 1.35 0.35 1 0.5 1.45 50 100 25 A pF mA 2.3 50 1.7 65 0.9 1 1.2 1.2 1.4 1.7 100 0.9 1 1.2 3 8 1.1 1.3 1.6 50 100 500 2 V A A V 2.7 2.9 7 ULQ2003A MIN TYP MAX ULQ2004A MIN TYP MAX 5 6 V UNIT

SWITCHING CHARACTERISTICS
TA = 25C
PARAMETER tPLH tPHL VOH Propagation delay time, low- to high-level output Propagation delay time, high- to low-level output High-level output voltage after switching TEST CONDITIONS See Figure 9 See Figure 9 VS = 50 V, IO = 300 mA, See Figure 10 VS 20 ULN2002A, ULN2003A, ULN2004A MIN TYP 0.25 0.25 MAX 1 1 s s mV UNIT
TA = 25C
PARAMETER tPLH tPHL VOH Propagation delay time, low- to high-level output Propagation delay time, high- to low-level output High-level output voltage after switching TEST CONDITIONS See Figure 9 See Figure 9 VS = 50 V, IO 300 mA, See Figure 10 VS 20 ULN2003AI MIN TYP 0.25 0.25 MAX 1 1 UNIT s s mV
TA = 40C to 105C
PARAMETER tPLH tPHL VOH Propagation delay time, low- to high-level output Propagation delay time, high- to low-level output High-level output voltage after switching TEST CONDITIONS See Figure 9 See Figure 9 VS = 50 V, IO 300 mA, See Figure 10 VS 50 ULN2003AI MIN TYP 1 1 MAX 10 10 UNIT s s mV
over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL VOH Propagation delay time, low- to high-level output Propagation delay time, high- to low-level output High-level output voltage after switching TEST CONDITIONS See Figure 9 See Figure 9 VS = 50 V, IO = 300 mA, See Figure 10 VS 20 ULQ2003A, ULQ2004A MIN TYP 1 1 MAX 10 10 UNIT s s mV

PARAMETER MEASUREMENT INFORMATION

Open VCE ICEX Open
Open
VCE ICEX
VI
Figure 1. ICEX Test Circuit

Open II(off) VCE IC
Figure 2. ICEX Test Circuit

Open II(on) VI Open
Figure 3. II(off) Test Circuit

A. II is fixed for measuring VCE(sat), variable for measuring hFE. Open
hFE = IC II
Figure 4. II Test Circuit

Open
II
VCE
IC
VI(on)
VCE
IC
Figure 5. hFE, VCE(sat) Test Circuit

VR IR
Figure 6. VI(on) Test Circuit

VF Open
IF
Open
Figure 7. IR Test Circuit
Figure 8. VF Test Circuit
Figure 9. Propagation Delay-Time Waveforms

PARAMETER MEASUREMENT INFORMATION (continued)
200 W
5 ns Input 10% 40 s 90% 1.5 V 90% 1.5 V
10 ns VIH (see Note C) 10% 0V VOH
Output VOL VOLTAGE WAVEFORMS
A. B. C.
The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 . CL includes probe and jig capacitance. For testing the ULN2003A, ULN2003AI, and ULQ2003A, VIH = 3 V; for the ULN2002A, VIH = 13 V; for the ULN2004A and the ULQ2004A, VIH = 8 V.
Figure 10. Latch-Up Test Circuit and Voltage Waveforms

TYPICAL CHARACTERISTICS
COLLECTOR-EMITTER SATURATION VOLTAGE vs COLLECTOR CURRENT (ONE DARLINGTON)
VCE(sat) VCE(sat) - Collector-Emitter Saturation Voltage - V
VCE(sat) VCE(sat) - Collector-Emitter Saturation Voltage - V
COLLECTOR-EMITTER SATURATION VOLTAGE vs TOTAL COLLECTOR CURRENT (TWO DARLINGTONS IN PARALLEL)

2.5 TA = 25C 2 II = 350 A 1.5 II = 500 A 1 II = 250 A
2.5 TA = 25C 2 II = 250 A 1.5 II = 350 A II = 500 A
0.5
0.5
0 0 100 200 300 400 500 600 700 800 IC - Collector Current - mA
0 0 100 200 300 400 500 600 700 800 IC(tot) - Total Collector Current - mA
Figure 11.
Figure 12. D PACKAGE MAXIMUM COLLECTOR CURRENT vs DUTY CYCLE

600
COLLECTOR CURRENT vs INPUT CURRENT

500
IC I C - Maximum Collector Current - mA
450
RL = 10 TA = 25C VS = 10 V VS = 8 V
IC IC - Collector Current - mA
400 350 300 250 200 150 100 50 0 0 25 50 75 100 125 150 175 200 II - Input Current - A
500 N=1 N=4 N=3 300 N=6 200 N = 7 N=5 100 TA = 70C N = Number of Outputs Conducting Simultaneously 0 10 20 30 40 50 60 70 80 90 100 N=2
400
0 Duty Cycle - %
Figure 13.
Figure 14.
10

TYPICAL CHARACTERISTICS (continued)

N PACKAGE MAXIMUM COLLECTOR CURRENT vs DUTY CYCLE
600
2000 TJ = -40C to 105C 1800
MAXIMUM AND TYPICAL INPUT CURRENT vs INPUT VOLTAGE
IC I C - Maximum Collector Current - mA
500 N=2 400

Input Current A
1600
N=1 N=3 N=4
1400 1200 1000 800 600 400 Maximum
300
N=5 N=6 N=7
200
100
TA = 85C N = Number of Outputs Conducting Simultaneously 0 10 20 30 40 50 60 70 80 90 100
Typical 200 0 2 2.5 3 3.5 4 Input Voltage V 4.5 5
Duty Cycle - %
Figure 15. MAXIMUM AND TYPICAL SATURATED VCE vs OUTPUT CURRENT

2.1 TJ = -40C to 105C 450 1.9 500
Figure 16. MINIMUM OUTPUT CURRENT vs INPUT CURRENT

V CE = 2 V TJ = -40C to 105C
Maximum VCE(sat) Voltage V
400 1.7
Output Current mA
350 300 250 Minimum 200
1.5
Maximum
1.3
1.1 Typical 0.9 100
150 100 250
200
300 Output Current mA
400
500
350
450 Input Current A
550
650
Figure 17.
Figure 18.
11

APPLICATION INFORMATION
VSS ULN2002A V
VCC ULQ2003A V
1 2 3 4 5 6 7 P-MOS Output 8
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 Lam Test
TTL Output
Figure 19. P-MOS to Load

VDD ULN2004A ULQ2004A V
Figure 20. TTL to Load

VCC ULQ2003A V
1 2 3 4 5 6 7 8 CMOS Output
16 15 14 13 12 11 10 9
1 2 RP 3 4 5 6 7 8
16 15 14 13 12 11 10 9
TTL Output
Figure 21. Buffer for Higher Current Loads
Figure 22. Use of Pullup Resistors to Increase Drive Current
12

REVISION HISTORY
Changes from Revision J (September 2010) to Revision K Page
Added SOP NS Package to the 40C to 85C TA range in the Ordering Information table. ........................................... 2 Added Input Current (II) parameters ..................................................................................................................................... 5 Added Input Current (II) parameters ..................................................................................................................................... 6
13
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
PACKAGING INFORMATION
Orderable Device ULN2001AD ULN2001ADR ULN2001AN ULN2002AD ULN2002AN ULN2002ANE4 ULN2003AD ULN2003ADE4 ULN2003ADG4 ULN2003ADR ULN2003ADRE4 ULN2003ADRG3 ULN2003ADRG4 ULN2003AID ULN2003AIDE4 ULN2003AIDG4 ULN2003AIDR ULN2003AIDRE4 ULN2003AIDRG4 ULN2003AIN Status
(1)
Package Type Package Drawing SOIC SOIC PDIP SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP D D N D N N D D D D D D D D D D D D D N
Pins 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Package Qty
Eco Plan TBD TBD TBD TBD
(2)
Lead/ Ball Finish Call TI Call TI Call TI Call TI
MSL Peak Temp Call TI Call TI Call TI Call TI
(3)
Samples (Requires Login)
OBSOLETE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
25 25 40 40 40 2500 2500 2500 2500 40 40 40 2500 2500 2500 25
Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU SN Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type
Addendum-Page 1
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20-Aug-2011
Orderable Device ULN2003AINE4 ULN2003AINSR ULN2003AIPW ULN2003AIPWE4 ULN2003AIPWG4 ULN2003AIPWR ULN2003AIPWRE4 ULN2003AIPWRG4 ULN2003AJ ULN2003AN ULN2003ANE3 ULN2003ANE4 ULN2003ANSR ULN2003ANSRE4 ULN2003ANSRG4 ULN2003APW ULN2003APWE4 ULN2003APWG4 ULN2003APWR ULN2003APWRE4
Status
(1)
Package Type Package Drawing PDIP SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP CDIP PDIP PDIP PDIP SO SO SO TSSOP TSSOP TSSOP TSSOP TSSOP N NS PW PW PW PW PW PW J N N N NS NS NS PW PW PW PW PW
Pins 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Package Qty 25 2000 90 90 90 2000 2000 2000
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE PREVIEW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD Pb-Free (RoHS) TBD Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM Call TI Call TI Call TI Call TI
25 25 25 2000 2000 2000 90 90 90 2000 2000
CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 2
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20-Aug-2011
Orderable Device ULN2003APWRG4 ULN2004AD ULN2004ADE4 ULN2004ADG4 ULN2004ADR ULN2004ADRE4 ULN2004ADRG4 ULN2004AN ULN2004ANE4 ULN2004ANSR ULN2004ANSRG4 ULQ2003AD ULQ2003ADG4 ULQ2003ADR ULQ2003ADRG4 ULQ2003AN ULQ2004AD ULQ2004ADG4 ULQ2004ADR
Status
(1)
Package Type Package Drawing TSSOP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO SOIC SOIC SOIC SOIC PDIP SOIC SOIC SOIC PW D D D D D D N N NS NS D D D D N D D D
Pins 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Package Qty 2000 40 40 40 2500 2500 2500 25 25 2000 2000 40 40 2500 2500 25 40 40 2500
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 3
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20-Aug-2011
Orderable Device ULQ2004ADRG4 ULQ2004AN

(1)
Status
(1)
Package Type Package Drawing SOIC PDIP D N
Pins 16 16
Package Qty 2500 25
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ULQ2003A, ULQ2004A :
Automotive: ULQ2003A-Q1, ULQ2004A-Q1

NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 4
PACKAGE MATERIALS INFORMATION

www.ti.com 27-Aug-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing SOIC SO TSSOP TSSOP SO TSSOP TSSOP SO SOIC D NS PW PW NS PW PW NS D 16 16 16 16 16 16 16 16 16
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 16.4 16.4 12.4 12.4 16.4 12.4 12.4 16.4 16.4 6.5 8.2 6.9 7.0 8.2 6.9 7.0 8.2 6.5
B0 (mm) 10.3 10.5 5.6 5.6 10.5 5.6 5.6 10.5 10.3
K0 (mm) 2.1 2.5 1.6 1.6 2.5 1.6 1.6 2.5 2.1
P1 (mm) 8.0 12.0 8.0 8.0 12.0 8.0 8.0 12.0 8.0
W Pin1 (mm) Quadrant 16.0 16.0 12.0 12.0 16.0 12.0 12.0 16.0 16.0 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1
ULN2003ADR ULN2003AINSR ULN2003AIPWR ULN2003AIPWR ULN2003ANSR ULN2003APWR ULN2003APWR ULN2004ANSR ULQ2003ADR
2500 2000 2000 2000 2000 2000 2000 2000 2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 27-Aug-2011
*All dimensions are nominal
Device ULN2003ADR ULN2003AINSR ULN2003AIPWR ULN2003AIPWR ULN2003ANSR ULN2003APWR ULN2003APWR ULN2004ANSR ULQ2003ADR
Package Type SOIC SO TSSOP TSSOP SO TSSOP TSSOP SO SOIC
Package Drawing D NS PW PW NS PW PW NS D
Pins 16 16 16 16 16 16 16 16 16
SPQ 2500 2000 2000 2000 2000 2000 2000 2000 2500
Length (mm) 346.0 346.0 346.0 364.0 346.0 346.0 364.0 346.0 333.2
Width (mm) 346.0 346.0 346.0 364.0 346.0 346.0 364.0 346.0 345.9
Height (mm) 33.0 33.0 29.0 27.0 33.0 29.0 27.0 33.0 28.6
Pack Materials-Page 2
IMPORTANT NOTICE
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ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

www.ti.com SLRS027K DECEMBER 1976 REVISED AUGUST 2011

HIGH-VOLTAGE, HIGH-CURRENT DARLINGTON TRANSISTOR ARRAYS

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

ORDERING INFORMATION (1)

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

SCHEMATICS (EACH DARLINGTON PAIR)

ULN/ULQ2003A: RB = 2.7 kW ULN2003AI: RB = 2.7 kW ULN/ULQ2004A: RB = 10.5 kW 7.2 kW 3 kW

ULN2003A, ULN2003AI, ULN2004A, ULQ2003A, ULQ2004A

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

ABSOLUTE MAXIMUM RATINGS (1)

See Figure 14 and Figure 15

500 500 2.5 20 40 40 40 70 105 85 105 73 67 64 108 36 54 150 260 65 150

N package NS package PW package D package N package

JC TJ Tstg (1) (2) (3) (4) (5) (6)

Package thermal impedance (5)

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

PARAMETER MEASUREMENT INFORMATION

Figure 1. ICEX Test Circuit

Figure 2. ICEX Test Circuit

Figure 3. II(off) Test Circuit

Figure 4. II Test Circuit

Figure 5. hFE, VCE(sat) Test Circuit

Figure 6. VI(on) Test Circuit

Figure 7. IR Test Circuit

Figure 8. VF Test Circuit

Figure 9. Propagation Delay-Time Waveforms

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

PARAMETER MEASUREMENT INFORMATION (continued)

5 ns Input 10% 40 s 90% 1.5 V 90% 1.5 V

10 ns VIH (see Note C) 10% 0V VOH

Output VOL VOLTAGE WAVEFORMS

Figure 10. Latch-Up Test Circuit and Voltage Waveforms

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

COLLECTOR-EMITTER SATURATION VOLTAGE vs TOTAL COLLECTOR CURRENT (TWO DARLINGTONS IN PARALLEL)

2.5 TA = 25C 2 II = 250 A 1.5 II = 350 A II = 500 A

Figure 12. D PACKAGE MAXIMUM COLLECTOR CURRENT vs DUTY CYCLE

COLLECTOR CURRENT vs INPUT CURRENT

Copyright 19762011, Texas Instruments Incorporated

ULN2002A, ULN2003A, ULN2003AI, ULN2004A ULQ2003A, ULQ2004A

TYPICAL CHARACTERISTICS (continued)

MAXIMUM AND TYPICAL INPUT CURRENT vs INPUT VOLTAGE

IC I C - Maximum Collector Current - mA

500 N=2 400

N=1 N=3 N=4

1400 1200 1000 800 600 400 Maximum

N=5 N=6 N=7

TA = 85C N = Number of Outputs Conducting Simultaneously 0 10 20 30 40 50 60 70 80 90 100

Typical 200 0 2 2.5 3 3.5 4 Input Voltage V 4.5 5

Figure 15. MAXIMUM AND TYPICAL SATURATED VCE vs OUTPUT CURRENT

Figure 16. MINIMUM OUTPUT CURRENT vs INPUT CURRENT