Muhammad Syazwan bin Mohd Jaafar

1092701374

Muhammad Syazwan bin Mohd Jaafar

1092701374

Pipelining incerases concurrency by dividing a computation into a number of steps

Parallelism is the use of multiple resources to increase concurrency

Muhammad Syazwan bin Mohd Jaafar PIPELINING Key implementation technique used to build fast processors that be seen in RISCs architecture. It allows the execution of multiple instructions to overlap in time Entire processing flow is broken up into multiple stages, and new data/instructions is processed by a stage potentially as soon as it is done with the current data/instruction, which then goes onto the next stage for further processing.

1092701374 NON-PIPELINING By contrast, the next data/instruction is processed after the entire processing of the previous data/instruction is complete

Non-pipelined
Processing path
Data/instruction Delay = D

Non-pipelined processing, new data/instruction, inputted every seconds. A new data/instruction is done every seconds

Pipelined

Data/instruction

k stages delay

Pipelined processing, new data/instruction is inputted every D/k seconds. After initial fill, a data/instruction is done every D/k seconds.
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Muhammad Syazwan bin Mohd Jaafar

1092701374

Typical instruction execution sequences : fetch,decode,read,execute,write In a non-pipelined CPU, instructions are performed one at a time before an instruction is begun, the preceding instruction is completed.

Fetch

Decode

Execute

Fetch

Decode

Execute

Fetch

Decode

In a pipelined CPU, the execution of instructions is performed stages. Separate hardware is provided to handle each of these satges. Instructions proceed through the CPU stages :

Fetch

Decode Fetch

Execute Decode Fetch

Fetch Execute Decode

Decode Fetch Execute

Execute Decode Fetch

Execute Decode Execute

To implement instruction pipelining, desirable features of (instruction set): All instructions same length Registers specified in same place in instructions Memory operands only in load or stores, i.e. RISC

But, it is not always the case in reality

Muhammad Syazwan bin Mohd Jaafar

1092701374

Two Stage Instruction Pipeline

Instruction

Fetch

Instruction

Execute

Result

a) Simplified view

Wait Instruction

New address Instruction

Wait

Fetch

Execute

Result

Observation
Performance usually shorter than execution Pipeline should have more stages to improve the performance An ideal pipeline divides a task into k independent sequential subtasks: o Each subtask requires 1 time unit to complete o The task itself then requires k time units to complete

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1092701374

Pipelining of Unequal Stages

Important for pipelining where stages are unequal o Always taje the largest of the stage delay to be the cycle time o No stage overlaps and latency must be constant o Ensure that instruction overlap is the same as the cycle time else get timing diagram is wrong

Pipeline Performance
n : number of instructions k : stages of pipelines : total time for pipelining : total time without pipelining : cycletime

TOTAL TIME

Pipelining = nk

Non-pipelining = (k + (n-1))

Muhammad Syazwan bin Mohd Jaafar

1092701374

Total Time For Unequal Stage

No pipelining :

Pipelining

= Fill time + (n-1) . max {ti} = sum ti + (n-1) . max {ti}

Speedup

S= =
))

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1092701374

Throughput
Pipeline throughput = (n) (n)

Non-pipeline throughput =

Where n = total number of instances. Pipelining,

(n) is the Total Time for Non-

(n) is the Total Time for Pipelining.

Both Throughputs is in instructions/per unit time (s)

Pipelined Throughput > Non-Pipelined Throughput

Limits to Pipelining
Factors that limits performance enhancement: Unequal duration/delay of stages Conditional branch instruction or interrupts

Muhammad Syazwan bin Mohd Jaafar

1092701374

Hazards as Limitations to Pipelining

Resources hazards : HW cannot support this combination of instruction. Data hazards : Instruction depends on result of prior instruction in still in the pipeline Control hazards : Caused by delay between the fetching of instructions and decision about changes in control flow

RISC: Reduced Instruction Set Computers

Major advance in computer : The family concept o Separate architecture from implementation Microprogrammed control unit Cache memory Solid state RAM Microprocessor Pipelining o Introduces parallelism into fetch execute cycle Multiple processors

Muhammad Syazwan bin Mohd Jaafar

1092701374

CISC and RISC

The next step : RISC in processor architecture Key features of CISC : o Large number of predefined instructions making high level programming languages easy to design and implement o Support microprogramming to simplify computer architecture Key features of RISC : o Limited and simple instruction set o Large number of general purpose registers or use of compiler technology to optimize register use o Emphasis on optimizing the instruction pipeline

Arguements of CISC
A rich instruction set should simplify the compiler by having instructions which match the high-level language instructions. o This work fine if the number of HL languages is very small Since the programs are smaller in size, they have better performances o They take up less memory space and need fewer instruction fetch cycles o Fewer number of instructions are executed, which may lead to smaller execution time

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Muhammad Syazwan bin Mohd Jaafar

1092701374

Drawbacks for CISC

CPU complexity The control unit design (mainly instruction decoding) becomes complex since the instruction set is large with heavily encoded instructions System size and cost There is a lot of hardware circuitry due to complexity of the CPU. This increases the hardware cost of the system and also the power requirement Complex machine instructions may not high-level languages statements exactly in which case they may be of little use This will be a major problem the number of languages getting bigger

CHARACTERISTICS of CISC AND RISC

CISC Varying number of instructions per cycle Small number of general purpose registers More addressing modes More instruction formats : fewer instructions can be used to implement a given task Use microcode Variable length instruction Simplified compiler: microprogram instructions could be written to match constructs of high level languages RISC One instruction per cycle Register to register operations Few, simple addressing modes Few, simple instruction formats Hardwired design (no microcode) Fixed instruction format More compile time/effort

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Muhammad Syazwan bin Mohd Jaafar

1092701374

CISC vs RISC

CISC
Emphasis on hardware Multiple instruction sizes and formats Less registers More adressing modes Extnsive use of microprogramming Instructions take a varying amount of cycle time Pipelining is difficult

RISC
Emphasis on software Instructions of same set with few formats Uses more registers Fewer addressing modes Complexity in compiler Instructions take one cycle time Pipelining is easy

Summary
Pipelining is a fundamental concept Instruction Pipelining and concepts How to improve performance Hazards are limitations of pipelining- data, structural, control RISC has a simple architecture and can be highly pipelined , CISC has a more complex architecture. Today, designers are producing a hybrid of the two design philosophies known as a complex/reduced instruction set computer. These computers combine characteristics such as variable-length instructions, few generalpurpose registers, pipelining, and floating-point units. RISC and CISC controversy results in the consideration of several factors before deciding on the architecture.
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