ECE 453 Integrated Circuit Design

Lab #2 Cadence Set-up and Analysis of a Single-Stage Amplifier

Date: Week beginning September 20, 2004. Due: October 4, 2004.

1 Objective :
Following lab 1, this lab will provide you with more exposure to Cadence simulation environment. It is a good idea to review Lab 1 on basic Cadence set-up and layout skills, especially on what you did to pass DRC(Design Rule Check) and LVS(Layout Vs. Schematic). Even though you wont need layout in this lab, summarizing what you learned from Lab 1 will be invaluable for future labs and the final project.

2 Circuit :
A common source amplifier with an output buffer and bias network will be entered as a schematic and dc and frequency domain simulation will be performed. This will give you the ability to do almost all of the simulations required to analyze and understand the main performance metrics of a single stage amplifier.

3 Lab Instructions:
3.1 Schematic Generation and Entry:
Enter the schematic shown on the last page of the instructions in your labs design library The components in the schematic will be found in the analogLib and sigehp libraries. The nFET and the pFET transistors for the amplifier and bias circuit as well as the subc substrate contact come from the sigehp library, the rest of the components are in analogLib. Be sure to set ALL of the component parameters correctly. Be sure to select, Add nw and dt to pcell in the pFET properties window when you instance it. Not doing so will lead to errors at the layout stage and although there is no layout for this lab, it is useful to always remember to select this whenever a pFET is instanced. When the schematic entry is complete, click on Check and Save (the check mark box in the top left hand corner). Be sure that your design is error and warning free (or that all warnings are acceptable and understood) before proceeding.

3.2 Simulation:
If your design has no errors or significant warnings, then you may begin simulations to assess the circuits overall performance. From the schematic window select Tools-Analog Environment to launch the analog environment window

*3.2.1 File Set-up:

Note: You can load state Lab_1_setup from Lab 1 and skip to 3.3.1. Make
sure you check that the following entries are correct:

Select Setup-Simulator/Directory/Host Set Simulator = spectre; Project Directory = ~/Cadence/simulation; Host Mode = local. Select Setup-Model Libraries and enter the following model libraries (They must appear in this order in the window!) /opt/cadence-designkits/AMS/sigehp/V2.6.2.1/models/spectre/design.scs /opt/cadence-designkits/AMS/sigehp/V2.6.2.1/models/spectre/process.scs Select Setup-Temperature and set Temperature=25. Select Setup-Simulation Files Include Path = /opt/cadence-designkits/AMS/sigehp/V2.6.2.1/models/spectre Definition Files = /opt/cadencedesignkits/AMS/sigehp/V2.6.2.1/models/spectre/definitions.scs Select Setup-Environment Set Switch View List = spectre cmos_sch cmos.sch schematic veriloga ahdl Set View List = spectre Select Automatic Output Log

3.3.1 Transient Analysis:

In this section we will look at the small signal performance of the amplifier in the time domain. As seen in the schematic, the circuit consists of a simple common source amplifier stage with a voltage follower at the output to yield a low output resistance. We will input a 10 mV, 10 MHz small signal at the input and look at the waveforms at the output of the common source stage and the voltage follower stage. Select Analyses-Choose Select tran Set the Stop time to 20ns. Set the Accuracy to Moderate Enable the analysis and click OK. Select Simulation - Netlist and Run. Select Results-Direct Plot-Transient Signal In the schematic window that pops up, select the input wire from Vsin, the wire connecting the two stages and the wire connecting the output to the capacitor. (You have to click on the wires and not on the nets). Press ESC when finished and the three waveforms will pop up. Print this plot. From the plot estimate the gain of the common source and the follower stages. Repeat the above simulation changing the small signal frequency to 30 MHz, 60 MHz, 100 MHz and 500 MHz (and correspondingly changing the stop time) and attach the plots to your report. What does the gain of the follower stage depend on?

You can save the state before proceeding to facilitate an easy check of the results later.

3.3.2 Bias Current Sweep:

Select Analyses-Choose Select dc Select Save DC Operating Point In Sweep variable select Component parameter. Click Select component and go to the schematic window and select the current source (idc). In the window that pops up select dc idc DC Current. Set the following dc Sweep range : Start = 1e-6, Stop = 1e-3, sweep type = automatic. Select Outputs-To be Plotted When the schematic pops up, select the drain node on the 10/1 pFET and hit ESC. Select Simulation - Netlist and Run. Reduce the plot to a smaller range by selecting Axes-X Axes and then setting the Min-Max range from 10uA to 300uA. Print the resulting plot. Estimate the mirrors current gain and the useful range of operation.

3.3.3 Voltage Supply Sweep:

Select Analyses-Choose Select dc Select Save DC Operating Point In Sweep variable select Component parameter. Clear Component Name and Parameter Name fields. Click Select Component Select Vdc in the schematic window. In the window that pops up, select dc vdc DC voltage and click OK Enter 2.5-3.5 V as the sweep range and click OK. Select Outputs-To be Plotted On the schematic, select the Vdc node in the Vdd definition path to measure current through the circuit and hit ESC. Select Simulation Netlist and Run (or alternately the green traffic light) Print the resulting plot. Estimate the power consumed at 2.5 V, 3.0 V and 3.3 V and include it in your report.

3.3.4 AC Analysis:
Before starting on this part, on the schematic select the Vsin source. On the parameter window enter, AC Magnitude - 50 mV AC Phase - 0

In the Analog Environment, Select Analyses-Choose Select ac. Enable the analysis and disable all other analyses. Set the following : Sweep Variable - Frequency Sweep Range - 1e6 to 1e9 Sweep Type - Automatic Select Outputs - To be Plotted - Select on Schematic On the schematic window, select the wire between the two stages and the output wire. Select Simulation - Netlist and Run. Print the resulting plot. Using a marker, determine the gains of the output buffer at 1 MHz, 10 MHz, 100 MHz and 500 MHz and bandwidth at each output and include the values in your report.

4 Report:
A short (individual) lab write-up showing your schematic, simulation plots and the required results should be handed in. The report should be brief (perhaps 1-2 pages of writing plus simulation results and schematic attached), but include a summary of the insights you gained from the lab and any suggestions you may have for future labs.

Questions ?
Contact your TA : Venkat Narayanan vn23@cornell.edu