Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 1 oI 12

Rail to Rail Folded Cascode Opamp Employing Class AB Output Stage

Imre Knausz, Analog IC Design, EE726




Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 2 oI 12

Table of Contents

Table oI Contents ........................................................................................................................................... 2
Introduction .................................................................................................................................................... 3
Opamp Topology............................................................................................................................................ 3
First Stage................................................................................................................................................... 4
Class AB Output Stage............................................................................................................................... 4
Opamp Gain ............................................................................................................................................... 7
Compensation................................................................................................................................................. 7
OIIset Calculations ......................................................................................................................................... 9
Implementation............................................................................................................................................. 10
ReIerences: ................................................................................................................................................... 12

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Introduction

This paper will describe a high perIormance opamp architecture suitable Ior driving moderate oII
chip capacitances. This opamp is suitable Ior driving LCD panels. Below is a high level model oI the
opamp and it`s load.

Figure 1: Ideal view oI opamp and load.

Because the circuit can be used to drive LCDs, this ampliIier has to be as low power as possible to enable
eIIicient use oI the battery in a portable application. The opamp will be designed towards the Iollowing
speciIications and simulated to veriIy adequate circuit operation.

- Power Consumption 50A (250W across supply voltage)
- Power Supply 3.3 to 5V
- Low oIIset +2mV (1o)
- Settling time (1 oI Iinal value) 250ns
- Slew rate 25 V/s (C
L
100pF, RS 500O)
- Rail to rail input
- Rail to rail output (actually +200mV Irom any rail)

Opamp Topology

The Iollowing is a schematic diagram oI the opamp that was constructed:

Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 4 oI 12


Figure 2: SimpliIied opamp schematic

First Stage
The Iirst stage oI the opamp is a Iolded cascode with a dual polarity Iront end. The Iolded cascode
is conIigured the same as a standard Iolded cascode with a PMOS input, except this opamp has an extra
NMOS input pair pulling current out oI current mirror M11 and M12. The output oI this stage is the drain
oI the M10 device and the drain oI M8. Mt1 and Mt2 provide a Iunction Ior the output stage as will be
described later. These two devices Iorm a low impedance path Irom the drain oI M10 to M8. This is a low
impedance path because we can consider Mt1 & Mt2 as common gate ampliIiers and the input impedance
(i.e. impedance looking into the source) oI such a conIiguration is 1/g
m
.
A downside oI using such a conIiguration is that the g
m
oI the input stage is not constant through
the operating range. The input circuitry can be separated into three diIIerent operating ranges. While the
common mode range is in or near the center, both diIIerential pairs are active and the eIIective g
m
oI the
input stage is g
m-n
g
m-p
. II the input common mode voltage drops below V
GS-N
2*V
ON-N
, the NMOS
diIIerential pair is oII and only the PMOS input pair is active and thus the total g
m
equals g
m-p
. Similarly,
the PMOS diIIerential pair turns oII with high common mode voltages and the g
m
once again drops to about
halI oI it`s maximum value (assuming the NMOS and PMOS devices were sized to have the same g
m
). The
main problem this variation oI g
m
causes is that it can move the unity gain Irequency around and this makes
it diIIicult to optimally compensate the opamp. In this application, we will not employ a constant g
m
circuit
because the load will cause diIIiculties in compensating the opamp which we will solve later in the
compensation section.
For completeness, I will mention an eIIective method Ior correcting this g
m
variation. The easiest
method is to boost the current though the active diIIerential pair (when the other diIIerential pair is oII). To
double the g
m
oI remaining diIIerential pair, we need to quadruple the tail current since g
m
is proportional to
D
I . We can do this by injecting an additional 3*I
tail
into the active pair. This assumes the input pair is
in saturation, iI the input pair is operating in subthreshold (weak inversion) region to save power, then only
1x extra tail current needs to be injected because in this mode oI operation, the transistor`s g
m
is directly
proportional to it`s drain current.
Class AB Output Stage
Three basic choices are available Ior output stages class A, class B and class AB. Class A
output stages are normally used in classic 7 transistor` opamps. Their problem is that they waste power
and the output slew rates are asymmetric. Slewing in one direction is done by the output device (usually a
common source device), but slewing in the other direction is perIormed by an active load which is just a
Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 5 oI 12

current source. The current source device`s gate is tied to a constant bias voltage, so the current output oI
the device is limited. The second choice is a class B output stage which is basically two common source
output stages with the output oI one stage Iunctioning as a load Ior the other and vice-versa. The gates oI
the output devices are driven by the Iirst stage oI the opamp. The problem with this approach is that PMOS
and NMOS devices require a diIIerent DC bias voltage on the gate. Because oI this, class B output stages
require some kind oI Ieedback to avoid this unacceptable crossover distortion.
The third option is to employ a class AB output stage |1, p. 150|. A diagram below details
operation.

Figure 3: SimpliIied view oI class AB output stage.

Voltage source V1 represents the Iloating voltage source which is required to properly bias the
output devices. This scheme is called class AB because it is a cross oI class A and B. The output devices
are biased with a current, just like class A, but when the ampliIier needs to sink or source a large amount oI
current, it can drive the gate oI the NMOS or PMOS to either rail to overdrive the NMOS or PMOS device.
Because oI the Iloating voltage source, even when one device iI being overdriven, the other device still has
it`s quiescent current Ilowing through it. The advantage oI this is that neither device is completely turned
oII and the ampliIier can respond quicker to transients, reducing crossover distortion. The simulation result
below illustrates the biasing scheme:

Figure 4: Output current versus output device currents

The Iollowing is a zoomed in view oI our implementation:
Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 6 oI 12


Figure 5: Zoomed in view oI the class AB implementation.

Mt1 & Mt2 create the Iloating voltage source. Their bias voltages are created by the diode stacked devices
Moutnb & Mt1b and Moutpb & Mt2b respectively. This conIiguration Iorms a translinear loop. The
NMOS side oI the loop is Iormed by diode stacked devices connecting to the gate oI Mt1 down to the gate
oI Moutn. In terms oI quiescent biasing, we can write a voltage loop equation to obtain:

outn gs t gs b t gs outnb gs
J J J J

+ = +
1 1

(1)

The threshold voltages all cancel out oI the equation and we are leIt with:

outn ON t ON b t ON outnb ON
J J J J

+ = +
1 1

(2)

which reduces to:

outn
outn D
t
t D
b t
b t D
outnb
outnb D
L
W
I
L
W
I
L
W
I
L
W
I
|
.
|

\
|
+
|
.
|

\
|
=
|
.
|

\
|
+
|
.
|

\
|

1
1
1
1

(3)

We will use equation 3 to size the devices because we will likely have larger currents in the output than in
the Iolded cascode devices. We might also want to minimize the bias currents through Mt1b & Moutnb.
To understand how the 'Iloating voltage source Iunction oI this biasing scheme works, we will
examine the large signal characteristics oI the output stage |2, p. 1507|. Consider M5 as one current source
and M12 as the other. In-phase input signals coming Irom the diIIerential pairs into the drains oI M5 &
M12 will control the Iloating voltage source. Consider the case where current AI is pulled. Mt1`s current
in increased by AI whereas Mt2`s drain current decreases by the same amount. This will cause the gate
voltages oI the output devices to move down. This is because the gate to source voltages Mt1 & Mt2
increase due to the increased current, but their gate voltages remain constant. This will start to reduce the
current through Moutn and increase the current though Moutp, causing the opamp to source current. This
Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 7 oI 12

trend will continue until all oI the current Ilows through Mt1. At this point some minimum current will
Ilow through Moutn which is set up by the sizes oI the devices in our translinear loop.
Also important to note is the Iact that this output stage has some component oI quiescent power
that is supply voltage dependent. This is mainly due to the Iact that the output devices don`t have the same
drain to source voltages as their diode connected bias counterparts. This will result in channel length
modulation and one can expect 10-20 more current in the output stage than calculated.
Opamp Gain
The gain expression is relatively easy to Iind since we can consider each stag individually. The
gain oI the Iirst stage can be Iound using the standard Iolded cascode gain expression, the only diIIerence
being that we have two sets oI input devices. We can combine the eIIects oI both by using superposition
resulting in:

( ) ( ) ( ) ( ) | |
12 10 10 3 6 8 8 4 , 3 2 , 1 1
,, ,,
o o m o o o m m m J
r r g r r r g g g A + =
(4)

Next, we can Iind the gain oI the output stage using superposition. II we consider the output stage
as two common source ampliIiers (using each other as their load), then it is easy to see that their gain is:

( ) ( )
outp o outn o outp m outn m J
r r g g A

+ = ,,
2

(5)

Thus the total gain is:

( )( ) ( ) ( ) ( ) | |( )
outp o outn o o o m o o o m outp m outn m m m J
r r r r g r r r g g g g g A

+ + = ,, ,, ,,
12 10 10 3 6 8 8 4 , 3 2 , 1 1

(6)

Compensation

This ampliIier makes use oI cascoded Miller compensation. This variation oI Miller
compensation allows us to use a smaller compensation capacitor since our load capacitor is relatively large.
Normal Miller compensation give us an output pole oI:
L
m
out
C
g
0
= e
(7)

The schematic below shows how to use cascode Miller compensation:


Figure 6: Cascode Miller compensation schematic.
Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 8 oI 12


Above we can see the class AB devices Mt1 & Mt2 and the current mirror M5-8. To employ cascode
Miller compensation, we hook up one end oI the compensation capacitor to the output and the other end oI
the capacitor to the drain oI the current mirror device M6. To see what this does Ior us, we can write this
simpliIied small signal model oI halI oI the output stage:


Figure 7: Small signal model oI output stage

r
nd
represents the total resistance at the V
ndrive
node and r
out
represents the resistance at the output node.
Current source M6 is represented by current source I6 and the cascode device M8 is driven by it`s gate to
source voltage, V
cn
. We consider I6 to be the input signal current. Also, since V1 is such a comparatively
low impedance node, we can consider it to be a virtual AC ground. ThereIore, we will write an expression
Ior Vout:
( )
( )
out
L
out
L
nd outn m out nd outn m out
r
C C s
r
C C s
J g Z J g J
+
+
+
= =

1
1

(8)
Which then simpliIies to:
( )
L out
out
nd outn m out
C C r s
r
J g J
+ +
=

1

(9)

to Iind an expression Ior V
nd,
we can write a node equation at node V1:

0 ) (
1 6 8
= + + sC J J I J g
out cn m

(10)

since the AC current through M8 is the same as that through rnd & Cnd,

0 ) (
1 6
= + + sC J J I
:
J
out
nd
nd

(11)

Since V1 is at a virtual ground, the above becomes:

0
6
= + sC J I
:
J
out
nd
nd

(12)

substituting Ior z1 and solving Ior Vcn we get:
( )
nd nd
nd
out nd
r sC
r
sC J I J
+
+ =
1
6

(13)

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Plugging this expression into (9) and multiplying through we get:

( ) ( )
L out nd nd L o nd nd
out outn m nd M out out outn m nd
out
C C r r C s C C sr r sC
r g r sC J r g r I
J
+ + + + +

=

2
6
1

(14)

Now we rearrange to solve Ior the transIer Iunction:

( ) ( ) ( )
L out nd nd out outn m nd M L o nd nd
out outn m nd out
C C r r C s r g r C C C r r C s
r g r
I
J
+ + + + + +
=

2
6
1

(15)

Assuming the poles are Iar apart, i.e. p1 ~~ p2, we can write them as |3, p. 618|:

( )
out outn m nd M out outn m nd M L o nd nd
r g r C r g r C C C r r C
p

~
+ + +

~
1 1
1

(16)
( )
( )
L
outn m
nd
M
L out nd nd
out outn m nd M L o nd nd
C
g
C
C
C C r r C
r g r C C C r r C
p

~
+
+ + +
~
2

(17)

This is a very positive result. P
2
has bee increased by a Iactor oI C
M
/C
nd
which pushes out the unity gain
Irequency oI the opamp and increases it`s perIormance. Alternately, to save space or to increase the slew
rate, we can decrease C
M
and still maintain the same unity gain Irequency we would get with conventional
Miller compensation. Another very positive result oI this analysis is that no RHP zero results Irom this
Iorm oI compensation!

Offset Calculations

The majority oI the oIIset oI this ampliIier results Irom 4 main components the oIIset oI each
diIIerential input pair, the oIIset oI the current source (M
9-12
Iigure 1) and the current mirror (M
5-8
Iigure 1).
The standard deviation is equal to the square root oI the sums oI the variances oI the components:

2 2 2 2
cm os cs os thp os thn os OS
+ + + = o o o o o
(18)

The standard deviations oI threshold voltages are normally available Ior each process, however, we don`t
have access to this AMI 0.5u data. I will take a guess at what the Iab data might look like based on other
similar processes. Threshold voltage is linearly proportional to the inverse oI the square root oI the gate
area |4|. The Iollowing chart illustrates the concept.
Figure 8: Sample matching data
NMOS matching (imaginary data)
y = 20x - 0.05
0
5
10
15
20
25
30
35
40
45
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
1/SQRT(W*L) (1/um)
S
t
a
n
d
a
r
d

D
e
v
i
a
t
i
o
n

(
m
V
)
Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 10 oI 12


For this paper we will use a slope oI 20mV Ior NMOS devices and a slope oI 25mV Ior PMOS devices.
Next we will calculate the input reIerred oIIset voltages oI the current source. Let`s deIine AI I
1

I
2
which is the diIIerence in current Irom one leg oI the current source (or mirror) to the other. In the
current mirror,

th m
J g I A = A
(19)

In a Ieedback conIiguration, the opamp will try to oIIset this current mirror mismatch and this action will
maniIest itselI as an input reIerred oIIset. The amp will have an oIIset voltage proportional to the current
oIIset that it must account Ior and this constant oI proportionality is g
m
. ThereIore,

2
2 , 1
cs os th
m
cs m
os
J
g
g
J

= A = o
(20)

The variance oI the current mirror input reIerred oIIset voltage is Iound in the same way.
A very important observation is that the opamp`s oIIset is not constant over the input common
mode range. A the input common mode goes down, the NMOS diIIerential pair will turn oII and it`s oIIset
will no longer contribute to the total. Also, the g
m
`s oI the current source and the current mirror will
evaluate to diIIerent values since those devices now have diIIerent current. The converse is also true Ior
high input common modes when the PMOS diIIerential pair is oII.

Implementation

The Iirst thing that will be done is to Iind the amount oI current we need in the Iolded cascode
stage to slew the input oI the second stage. We will assume that the output stage loads the Iirst stage with
about 0.25pF oI capacitance. The slew rate is deIined by the Iollowing expression:

C
I
SR
b
=
(21)

Our total slew rate budget is 250ns, so we will assume we can use halI oI the budget Ior internal slewing.
We only need to slew about 3V in any direction beIore the output devices are turned on hard, thereIore our
internal slew rate spec should be 3/125ns 24V/us. Given this, I
b
comes out to be 6uA.
Device sizes in the Iolded cascode are not critical in this application (in terms oI gain), we can
pick devices as large as possible (but making sure devices are still in the inversion region). We will use a
V
ON
oI 200mV to pick original sizes and increase the sizes iI need be. The diIIerential pair needs to be
sizeable Ior matching.
The output stage needs to be sized to slew the load capacitance. The output stage has to slew 5V
in 125ns, thereIore, its required slew rate is 40V/us, and this will require a current oI 4mA. Since the
output devices are in the triode region, the devices can be sized using:

( )
DS th GS
D
J J J K
I
L
W

=
|
.
|

\
|
'

(21)

Using this equation (with V
GS
4V and with V
DS
equal to 200mV, to make sure we can slew quickly across
our Iull range), (W/L)
outn
comes out to be 55. Tripling this gives us 165 Ior the PMOS device.
Equations 16 & 17 show that the poles are independent (with respect to each other, i.e. they both
move by the same amount due to a change in bias current) oI the bias current in the output stage. The
devices will respond Iaster iI they are biased in the active region.


Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 11 oI 12

Simulation Results
Rail to Rail Opamp with Class AB Output Imre Knausz - 2/18/2004 Page 12 oI 12

References:

1. Roubik Gregorian, Introduction to CMOS Opamps and Comparators. John Wiley & Sons, Inc.,
New York, 1999
2. Hogervorst et al., 'A Compact Power eIIicient 3V CMOS Rail-to-Rail Input/Output Operational
AmpliIier Ior VSLI Cell Libraries, IEEE J. Solid-State Circ., vol. 29, pp. 1505-1512, Dec. 1990.
3. Paul R. Gray and Robert G. Meyer, Analvsis and Design of Analog Integrated Circuits. John
Wiley & Sons, Inc., New York, Third Edition, 1993
4. Marcel J. M. Pelgrom, 'Matching Properties oI MOS Transistors, IEEE J. Solid-State Circ., vol.
24, No. 5, pp. 1433-1440, Oct. 1990.