The code is composed of four data bits (A,B,C,D) and one parity bit (P).

the code format is ABCDP The parity bit generator and the error detector must agree with what parity bit adding system to be used, add 1 to make data bits even or add 1 to make data bits odd. The parity bit makes the number of ones in a code either even or odd by simply having a value of 1 if a 1 is needed to comply with the parity bit adding system used. eg. A B C D P 1 0 1 0 0 ( if using even system) 1 (if using odd system) Errors in the code may take place because of the degradation of the signal while traveling through long transmission lines. The bits (data or parity) maybe changed from 0 to 1 or vice versa. The error detector detects errors by simply counting the number of 1s and checking if it complies with the parity bit adding system in use (if bits are altered at once, the error is cancelled out and the error detector fails. However, for digital signals, this is very unlikely to happen.).

Circuit operation example: (refer to the colors) 1)Data bit code 0101 enters the parity bit generator

Transmitting Digital system

Receiving digital system

Parity bit generator

Error detector alar m

2) Using even parity bit adding system, the 5 bit code is 01010 with P=0. The data bits and parity bit are then transmitted toward the receiving where the error detector checks for any errors by counting the number of ones and checking if it complies with the parity bit adding system in use

Transmitting Digital system

Receiving digital system

Parity bit generator

Error detector alar m

Assuming no error occurred, the error detector counts two 1s

3) If an error occurred (notice the first bit changed its color from red to brown to signify an error)

Transmitting Digital system

Receiving digital system

Parity bit generator

Error detector alar m

the transmitted code would be 11010. The detector counts three 1s and the alarm sounds (ENNNGGKKK!). A request for resending the code would be sent to the transmitting digital system.

A code having seven bits; four of which are data bits (7th, 6th, 5th, 3rd bit) and three others are parity bits. Format: D7 D6 D5 P4 D3 P2 P1 The parity bits serve the same purpose as of the error detecting circuit. However, for the error correcting circuit, each parity bit only handles the parity bit addition of a combination of three data bits. 7 6 5 3 P4 1 1 1 0 P2 1 1 0 1 P1 1 0 1 1

The table above shows the binary number equivalent of n of the nth data bit. Taking a look at the P columns, the nth data bit, which holds a bit value of 1 under that column means that that data bit will be handled by that parity bit. Therefore, P4 handles D7 D6 D5, P2 handles D7 D6 D3, and P1 handles D7 D5 D3. eg. D7 = 0 D6 = 1 D5 = 0 D3 = 1 Using even parity bit adding system, P4 = 1 to make even number of 1s for its 3 data bit combination, P2 = 0 for its 3 data bit combination, and P1 = 1 for its 3 data bit combination.

The resulting code is :0101101 The error-correcting code circuit consists of three parity bit generators, which handle their corresponding three data bit combination, and three error detectors which are partnered with their corresponding parity bit generator. Again, the generators and the detectors must use the same parity bit adding system. The error detectors detect errors the same way as the previous circuit and receive codes from their corresponding parity bit generators but this time they have outputs. If an error is detected by an error detector, it automatically outputs a 1 and 0 otherwise. The outputs of the three detectors are arranged in the following manner: [ouput of P4 detector] [ouput of P2 detector] [ouput of P1 detector]. The arranged output forms a binary number equivalent of the hamming code bit the experienced an error. Therefore, and output of 000 means the code is error free. If an error did occur, the error corrector simply inverts the value of the bit in error from 0 to 1 or vice versa to correct it. If multiple errors occur, the error detectors will fail to correctly give the code of the erroneous bits. Again this situation is very unlikely.

Circuit operation example: (refer to the colors) 1) the data bits 0101 enter their corresponding parity bit generators

Transmitting Digital System

Error corrector

Receiving digital system

P4 generator

P4 detect or

P2 Generator

P2 detect or

P1 generator

P1 detect or

2) The parity bit generators perform their function using the even parity bit adding system. The transmitted signal is now 0101101. The code enters the error detectors where each detector counts the number of 1s and sees if the 4 bit combination complies with the parity bit adding system in use.

Transmitting Digital System

Error corrector

Receiving digital system

P4 generator

P4 detect or

P2 Generator

P2 detect or

P1 generator

P1 detect or

3) If no error occurred, the detectors will ouput zeroes and the error corrector simply lets the codes pass to the receiver.

Transmitting Digital System

Error corrector

Receiving digital system

P4 generator

P4 detect or

P2 Generator

P2 detect or

P1 generator

P1 detect or

4) If an error occurred, for example in D 5 (refer to the change in color of the blue arrows in the previous figure to signify error), then the P 4 and P1 detectors will output a 1. Since D 5 is not handled P2 detector it outpus a 0. The output binary code would be 101 which is equal to 5. This tells the error corrector that hamming code bit 5 is in error and the corrector simply inverts its erroneous value of 0 to a correct value of 1. The corrected code is then allowed to pass to the receiver.

Transmitting Digital System

Error corrector

Receiving digital system

P4 generator

P4 detect or

P2 Generator

P2 detect or

P1 generator

P1 detect or